drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34 #include "psp_v11_0.h"
  35
  36 static void psp_set_funcs(struct amdgpu_device *adev);
  37
  38 static int psp_early_init(void *handle)
  39 {
  40         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  41
  42         psp_set_funcs(adev);
  43
  44         return 0;
  45 }
  46
  47 static int psp_sw_init(void *handle)
  48 {
  49         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  50         struct psp_context *psp = &adev->psp;
  51         int ret;
  52
  53         switch (adev->asic_type) {
  54         case CHIP_VEGA10:
  55         case CHIP_VEGA12:
  56                 psp_v3_1_set_psp_funcs(psp);
  57                 break;
  58         case CHIP_RAVEN:
  59                 psp_v10_0_set_psp_funcs(psp);
  60                 break;
  61         case CHIP_VEGA20:
  62                 psp_v11_0_set_psp_funcs(psp);
  63                 break;
  64         default:
  65                 return -EINVAL;
  66         }
  67
  68         psp->adev = adev;
  69
  70         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  71                 return 0;
  72
  73         ret = psp_init_microcode(psp);
  74         if (ret) {
  75                 DRM_ERROR("Failed to load psp firmware!\n");
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 static int psp_sw_fini(void *handle)
  83 {
  84         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85
  86         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  87                 return 0;
  88
  89         release_firmware(adev->psp.sos_fw);
  90         adev->psp.sos_fw = NULL;
  91         release_firmware(adev->psp.asd_fw);
  92         adev->psp.asd_fw = NULL;
  93         if (adev->psp.ta_fw) {
  94                 release_firmware(adev->psp.ta_fw);
  95                 adev->psp.ta_fw = NULL;
  96         }
  97         return 0;
  98 }
  99
 100 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 101                  uint32_t reg_val, uint32_t mask, bool check_changed)
 102 {
 103         uint32_t val;
 104         int i;
 105         struct amdgpu_device *adev = psp->adev;
 106
 107         for (i = 0; i < adev->usec_timeout; i++) {
 108                 val = RREG32(reg_index);
 109                 if (check_changed) {
 110                         if (val != reg_val)
 111                                 return 0;
 112                 } else {
 113                         if ((val & mask) == reg_val)
 114                                 return 0;
 115                 }
 116                 udelay(1);
 117         }
 118
 119         return -ETIME;
 120 }
 121
 122 static int
 123 psp_cmd_submit_buf(struct psp_context *psp,
 124                    struct amdgpu_firmware_info *ucode,
 125                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 126 {
 127         int ret;
 128         int index;
 129
 130         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 131
 132         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 133
 134         index = atomic_inc_return(&psp->fence_value);
 135         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 136                              fence_mc_addr, index);
 137         if (ret) {
 138                 atomic_dec(&psp->fence_value);
 139                 return ret;
 140         }
 141
 142         while (*((unsigned int *)psp->fence_buf) != index)
 143                 msleep(1);
 144
 145         /* the status field must be 0 after FW is loaded */
 146         if (ucode && psp->cmd_buf_mem->resp.status) {
 147                 DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n",
 148                           psp->cmd_buf_mem->resp.status, ucode->ucode_id);
 149                 return -EINVAL;
 150         }
 151
 152         if (ucode) {
 153                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 154                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 155         }
 156
 157         return ret;
 158 }
 159
 160 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 161                                  struct psp_gfx_cmd_resp *cmd,
 162                                  uint64_t tmr_mc, uint32_t size)
 163 {
 164         if (psp_support_vmr_ring(psp))
 165                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 166         else
 167                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 168         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 169         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 170         cmd->cmd.cmd_setup_tmr.buf_size = size;
 171 }
 172
 173 /* Set up Trusted Memory Region */
 174 static int psp_tmr_init(struct psp_context *psp)
 175 {
 176         int ret;
 177
 178         /*
 179          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 180          * physical).
 181          *
 182          * Note: this memory need be reserved till the driver
 183          * uninitializes.
 184          */
 185         ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000,
 186                                       AMDGPU_GEM_DOMAIN_VRAM,
 187                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 188
 189         return ret;
 190 }
 191
 192 static int psp_tmr_load(struct psp_context *psp)
 193 {
 194         int ret;
 195         struct psp_gfx_cmd_resp *cmd;
 196
 197         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 198         if (!cmd)
 199                 return -ENOMEM;
 200
 201         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, PSP_TMR_SIZE);
 202         DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
 203                         PSP_TMR_SIZE, psp->tmr_mc_addr);
 204
 205         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 206                                  psp->fence_buf_mc_addr);
 207         if (ret)
 208                 goto failed;
 209
 210         kfree(cmd);
 211
 212         return 0;
 213
 214 failed:
 215         kfree(cmd);
 216         return ret;
 217 }
 218
 219 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 220                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 221                                  uint32_t size, uint32_t shared_size)
 222 {
 223         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 224         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 225         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 226         cmd->cmd.cmd_load_ta.app_len = size;
 227
 228         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 229         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 230         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 231 }
 232
 233 static int psp_asd_init(struct psp_context *psp)
 234 {
 235         int ret;
 236
 237         /*
 238          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 239          * physical) for shared ASD <-> Driver
 240          */
 241         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 242                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 243                                       &psp->asd_shared_bo,
 244                                       &psp->asd_shared_mc_addr,
 245                                       &psp->asd_shared_buf);
 246
 247         return ret;
 248 }
 249
 250 static int psp_asd_load(struct psp_context *psp)
 251 {
 252         int ret;
 253         struct psp_gfx_cmd_resp *cmd;
 254
 255         /* If PSP version doesn't match ASD version, asd loading will be failed.
 256          * add workaround to bypass it for sriov now.
 257          * TODO: add version check to make it common
 258          */
 259         if (amdgpu_sriov_vf(psp->adev))
 260                 return 0;
 261
 262         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 263         if (!cmd)
 264                 return -ENOMEM;
 265
 266         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 267         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 268
 269         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 270                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 271
 272         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 273                                  psp->fence_buf_mc_addr);
 274
 275         kfree(cmd);
 276
 277         return ret;
 278 }
 279
 280 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 281                                           uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
 282                                           uint32_t xgmi_ta_size, uint32_t shared_size)
 283 {
 284         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 285         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
 286         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
 287         cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
 288
 289         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
 290         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
 291         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 292 }
 293
 294 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 295 {
 296         int ret;
 297
 298         /*
 299          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 300          * physical) for xgmi ta <-> Driver
 301          */
 302         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 303                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 304                                       &psp->xgmi_context.xgmi_shared_bo,
 305                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 306                                       &psp->xgmi_context.xgmi_shared_buf);
 307
 308         return ret;
 309 }
 310
 311 static int psp_xgmi_load(struct psp_context *psp)
 312 {
 313         int ret;
 314         struct psp_gfx_cmd_resp *cmd;
 315
 316         /*
 317          * TODO: bypass the loading in sriov for now
 318          */
 319         if (amdgpu_sriov_vf(psp->adev))
 320                 return 0;
 321
 322         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 323         if (!cmd)
 324                 return -ENOMEM;
 325
 326         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 327         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 328
 329         psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 330                                       psp->xgmi_context.xgmi_shared_mc_addr,
 331                                       psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
 332
 333         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 334                                  psp->fence_buf_mc_addr);
 335
 336         if (!ret) {
 337                 psp->xgmi_context.initialized = 1;
 338                 psp->xgmi_context.session_id = cmd->resp.session_id;
 339         }
 340
 341         kfree(cmd);
 342
 343         return ret;
 344 }
 345
 346 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 347                                             uint32_t xgmi_session_id)
 348 {
 349         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 350         cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
 351 }
 352
 353 static int psp_xgmi_unload(struct psp_context *psp)
 354 {
 355         int ret;
 356         struct psp_gfx_cmd_resp *cmd;
 357
 358         /*
 359          * TODO: bypass the unloading in sriov for now
 360          */
 361         if (amdgpu_sriov_vf(psp->adev))
 362                 return 0;
 363
 364         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 365         if (!cmd)
 366                 return -ENOMEM;
 367
 368         psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 369
 370         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 371                                  psp->fence_buf_mc_addr);
 372
 373         kfree(cmd);
 374
 375         return ret;
 376 }
 377
 378 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 379                                             uint32_t ta_cmd_id,
 380                                             uint32_t xgmi_session_id)
 381 {
 382         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 383         cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
 384         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 385         /* Note: cmd_invoke_cmd.buf is not used for now */
 386 }
 387
 388 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 389 {
 390         int ret;
 391         struct psp_gfx_cmd_resp *cmd;
 392
 393         /*
 394          * TODO: bypass the loading in sriov for now
 395         */
 396         if (amdgpu_sriov_vf(psp->adev))
 397                 return 0;
 398
 399         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 400         if (!cmd)
 401                 return -ENOMEM;
 402
 403         psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 404                                         psp->xgmi_context.session_id);
 405
 406         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 407                                  psp->fence_buf_mc_addr);
 408
 409         kfree(cmd);
 410
 411         return ret;
 412 }
 413
 414 static int psp_xgmi_terminate(struct psp_context *psp)
 415 {
 416         int ret;
 417
 418         if (!psp->xgmi_context.initialized)
 419                 return 0;
 420
 421         ret = psp_xgmi_unload(psp);
 422         if (ret)
 423                 return ret;
 424
 425         psp->xgmi_context.initialized = 0;
 426
 427         /* free xgmi shared memory */
 428         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 429                         &psp->xgmi_context.xgmi_shared_mc_addr,
 430                         &psp->xgmi_context.xgmi_shared_buf);
 431
 432         return 0;
 433 }
 434
 435 static int psp_xgmi_initialize(struct psp_context *psp)
 436 {
 437         struct ta_xgmi_shared_memory *xgmi_cmd;
 438         int ret;
 439
 440         if (!psp->adev->psp.ta_fw)
 441                 return -ENOENT;
 442
 443         if (!psp->xgmi_context.initialized) {
 444                 ret = psp_xgmi_init_shared_buf(psp);
 445                 if (ret)
 446                         return ret;
 447         }
 448
 449         /* Load XGMI TA */
 450         ret = psp_xgmi_load(psp);
 451         if (ret)
 452                 return ret;
 453
 454         /* Initialize XGMI session */
 455         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 456         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 457         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 458
 459         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 460
 461         return ret;
 462 }
 463
 464 static int psp_hw_start(struct psp_context *psp)
 465 {
 466         struct amdgpu_device *adev = psp->adev;
 467         int ret;
 468
 469         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
 470                 ret = psp_bootloader_load_sysdrv(psp);
 471                 if (ret)
 472                         return ret;
 473
 474                 ret = psp_bootloader_load_sos(psp);
 475                 if (ret)
 476                         return ret;
 477         }
 478
 479         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 480         if (ret)
 481                 return ret;
 482
 483         ret = psp_tmr_load(psp);
 484         if (ret)
 485                 return ret;
 486
 487         ret = psp_asd_load(psp);
 488         if (ret)
 489                 return ret;
 490
 491         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 492                 ret = psp_xgmi_initialize(psp);
 493                 /* Warning the XGMI seesion initialize failure
 494                  * Instead of stop driver initialization
 495                  */
 496                 if (ret)
 497                         dev_err(psp->adev->dev,
 498                                 "XGMI: Failed to initialize XGMI session\n");
 499         }
 500         return 0;
 501 }
 502
 503 static int psp_np_fw_load(struct psp_context *psp)
 504 {
 505         int i, ret;
 506         struct amdgpu_firmware_info *ucode;
 507         struct amdgpu_device* adev = psp->adev;
 508
 509         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 510                 ucode = &adev->firmware.ucode[i];
 511                 if (!ucode->fw)
 512                         continue;
 513
 514                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 515                     psp_smu_reload_quirk(psp))
 516                         continue;
 517                 if (amdgpu_sriov_vf(adev) &&
 518                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 519                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 520                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 521                         /*skip ucode loading in SRIOV VF */
 522                         continue;
 523
 524                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 525                 if (ret)
 526                         return ret;
 527
 528                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 529                                          psp->fence_buf_mc_addr);
 530                 if (ret)
 531                         return ret;
 532
 533 #if 0
 534                 /* check if firmware loaded sucessfully */
 535                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 536                         return -EINVAL;
 537 #endif
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int psp_load_fw(struct amdgpu_device *adev)
 544 {
 545         int ret;
 546         struct psp_context *psp = &adev->psp;
 547
 548         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
 549                 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 550                 goto skip_memalloc;
 551         }
 552
 553         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 554         if (!psp->cmd)
 555                 return -ENOMEM;
 556
 557         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 558                                         AMDGPU_GEM_DOMAIN_GTT,
 559                                         &psp->fw_pri_bo,
 560                                         &psp->fw_pri_mc_addr,
 561                                         &psp->fw_pri_buf);
 562         if (ret)
 563                 goto failed;
 564
 565         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 566                                         AMDGPU_GEM_DOMAIN_VRAM,
 567                                         &psp->fence_buf_bo,
 568                                         &psp->fence_buf_mc_addr,
 569                                         &psp->fence_buf);
 570         if (ret)
 571                 goto failed_mem2;
 572
 573         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 574                                       AMDGPU_GEM_DOMAIN_VRAM,
 575                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 576                                       (void **)&psp->cmd_buf_mem);
 577         if (ret)
 578                 goto failed_mem1;
 579
 580         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 581
 582         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 583         if (ret)
 584                 goto failed_mem;
 585
 586         ret = psp_tmr_init(psp);
 587         if (ret)
 588                 goto failed_mem;
 589
 590         ret = psp_asd_init(psp);
 591         if (ret)
 592                 goto failed_mem;
 593
 594 skip_memalloc:
 595         ret = psp_hw_start(psp);
 596         if (ret)
 597                 goto failed_mem;
 598
 599         ret = psp_np_fw_load(psp);
 600         if (ret)
 601                 goto failed_mem;
 602
 603         return 0;
 604
 605 failed_mem:
 606         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 607                               &psp->cmd_buf_mc_addr,
 608                               (void **)&psp->cmd_buf_mem);
 609 failed_mem1:
 610         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 611                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 612 failed_mem2:
 613         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 614                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 615 failed:
 616         kfree(psp->cmd);
 617         psp->cmd = NULL;
 618         return ret;
 619 }
 620
 621 static int psp_hw_init(void *handle)
 622 {
 623         int ret;
 624         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 625
 626
 627         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 628                 return 0;
 629
 630         mutex_lock(&adev->firmware.mutex);
 631         /*
 632          * This sequence is just used on hw_init only once, no need on
 633          * resume.
 634          */
 635         ret = amdgpu_ucode_init_bo(adev);
 636         if (ret)
 637                 goto failed;
 638
 639         ret = psp_load_fw(adev);
 640         if (ret) {
 641                 DRM_ERROR("PSP firmware loading failed\n");
 642                 goto failed;
 643         }
 644
 645         mutex_unlock(&adev->firmware.mutex);
 646         return 0;
 647
 648 failed:
 649         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 650         mutex_unlock(&adev->firmware.mutex);
 651         return -EINVAL;
 652 }
 653
 654 static int psp_hw_fini(void *handle)
 655 {
 656         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 657         struct psp_context *psp = &adev->psp;
 658
 659         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 660                 return 0;
 661
 662         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
 663             psp->xgmi_context.initialized == 1)
 664                 psp_xgmi_terminate(psp);
 665
 666         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 667
 668         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 669         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 670                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 671         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 672                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 673         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 674                               &psp->asd_shared_buf);
 675         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 676                               (void **)&psp->cmd_buf_mem);
 677
 678         kfree(psp->cmd);
 679         psp->cmd = NULL;
 680
 681         return 0;
 682 }
 683
 684 static int psp_suspend(void *handle)
 685 {
 686         int ret;
 687         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 688         struct psp_context *psp = &adev->psp;
 689
 690         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 691                 return 0;
 692
 693         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
 694             psp->xgmi_context.initialized == 1) {
 695                 ret = psp_xgmi_terminate(psp);
 696                 if (ret) {
 697                         DRM_ERROR("Failed to terminate xgmi ta\n");
 698                         return ret;
 699                 }
 700         }
 701
 702         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
 703         if (ret) {
 704                 DRM_ERROR("PSP ring stop failed\n");
 705                 return ret;
 706         }
 707
 708         return 0;
 709 }
 710
 711 static int psp_resume(void *handle)
 712 {
 713         int ret;
 714         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 715         struct psp_context *psp = &adev->psp;
 716
 717         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 718                 return 0;
 719
 720         DRM_INFO("PSP is resuming...\n");
 721
 722         mutex_lock(&adev->firmware.mutex);
 723
 724         ret = psp_hw_start(psp);
 725         if (ret)
 726                 goto failed;
 727
 728         ret = psp_np_fw_load(psp);
 729         if (ret)
 730                 goto failed;
 731
 732         mutex_unlock(&adev->firmware.mutex);
 733
 734         return 0;
 735
 736 failed:
 737         DRM_ERROR("PSP resume failed\n");
 738         mutex_unlock(&adev->firmware.mutex);
 739         return ret;
 740 }
 741
 742 int psp_gpu_reset(struct amdgpu_device *adev)
 743 {
 744         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 745                 return 0;
 746
 747         return psp_mode1_reset(&adev->psp);
 748 }
 749
 750 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 751                                         enum AMDGPU_UCODE_ID ucode_type)
 752 {
 753         struct amdgpu_firmware_info *ucode = NULL;
 754
 755         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 756                 DRM_INFO("firmware is not loaded by PSP\n");
 757                 return true;
 758         }
 759
 760         if (!adev->firmware.fw_size)
 761                 return false;
 762
 763         ucode = &adev->firmware.ucode[ucode_type];
 764         if (!ucode->fw || !ucode->ucode_size)
 765                 return false;
 766
 767         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 768 }
 769
 770 static int psp_set_clockgating_state(void *handle,
 771                                      enum amd_clockgating_state state)
 772 {
 773         return 0;
 774 }
 775
 776 static int psp_set_powergating_state(void *handle,
 777                                      enum amd_powergating_state state)
 778 {
 779         return 0;
 780 }
 781
 782 const struct amd_ip_funcs psp_ip_funcs = {
 783         .name = "psp",
 784         .early_init = psp_early_init,
 785         .late_init = NULL,
 786         .sw_init = psp_sw_init,
 787         .sw_fini = psp_sw_fini,
 788         .hw_init = psp_hw_init,
 789         .hw_fini = psp_hw_fini,
 790         .suspend = psp_suspend,
 791         .resume = psp_resume,
 792         .is_idle = NULL,
 793         .check_soft_reset = NULL,
 794         .wait_for_idle = NULL,
 795         .soft_reset = NULL,
 796         .set_clockgating_state = psp_set_clockgating_state,
 797         .set_powergating_state = psp_set_powergating_state,
 798 };
 799
 800 static const struct amdgpu_psp_funcs psp_funcs = {
 801         .check_fw_loading_status = psp_check_fw_loading_status,
 802 };
 803
 804 static void psp_set_funcs(struct amdgpu_device *adev)
 805 {
 806         if (NULL == adev->firmware.funcs)
 807                 adev->firmware.funcs = &psp_funcs;
 808 }
 809
 810 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 811 {
 812         .type = AMD_IP_BLOCK_TYPE_PSP,
 813         .major = 3,
 814         .minor = 1,
 815         .rev = 0,
 816         .funcs = &psp_ip_funcs,
 817 };
 818
 819 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 820 {
 821         .type = AMD_IP_BLOCK_TYPE_PSP,
 822         .major = 10,
 823         .minor = 0,
 824         .rev = 0,
 825         .funcs = &psp_ip_funcs,
 826 };
 827
 828 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
 829 {
 830         .type = AMD_IP_BLOCK_TYPE_PSP,
 831         .major = 11,
 832         .minor = 0,
 833         .rev = 0,
 834         .funcs = &psp_ip_funcs,
 835 };