drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/pagemap.h>
  30 #include <drm/drmP.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33
  34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  35 {
  36         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  37
  38         if (robj) {
  39                 if (robj->gem_base.import_attach)
  40                         drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
  41                 amdgpu_mn_unregister(robj);
  42                 amdgpu_bo_unref(&robj);
  43         }
  44 }
  45
  46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  47                                 int alignment, u32 initial_domain,
  48                                 u64 flags, bool kernel,
  49                                 struct drm_gem_object **obj)
  50 {
  51         struct amdgpu_bo *robj;
  52         unsigned long max_size;
  53         int r;
  54
  55         *obj = NULL;
  56         /* At least align on page size */
  57         if (alignment < PAGE_SIZE) {
  58                 alignment = PAGE_SIZE;
  59         }
  60
  61         if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
  62                 /* Maximum bo size is the unpinned gtt size since we use the gtt to
  63                  * handle vram to system pool migrations.
  64                  */
  65                 max_size = adev->mc.gtt_size - adev->gart_pin_size;
  66                 if (size > max_size) {
  67                         DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
  68                                   size >> 20, max_size >> 20);
  69                         return -ENOMEM;
  70                 }
  71         }
  72 retry:
  73         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
  74                              flags, NULL, NULL, &robj);
  75         if (r) {
  76                 if (r != -ERESTARTSYS) {
  77                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  78                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  79                                 goto retry;
  80                         }
  81                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  82                                   size, initial_domain, alignment, r);
  83                 }
  84                 return r;
  85         }
  86         *obj = &robj->gem_base;
  87
  88         return 0;
  89 }
  90
  91 void amdgpu_gem_force_release(struct amdgpu_device *adev)
  92 {
  93         struct drm_device *ddev = adev->ddev;
  94         struct drm_file *file;
  95
  96         mutex_lock(&ddev->filelist_mutex);
  97
  98         list_for_each_entry(file, &ddev->filelist, lhead) {
  99                 struct drm_gem_object *gobj;
 100                 int handle;
 101
 102                 WARN_ONCE(1, "Still active user space clients!\n");
 103                 spin_lock(&file->table_lock);
 104                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 105                         WARN_ONCE(1, "And also active allocations!\n");
 106                         drm_gem_object_unreference_unlocked(gobj);
 107                 }
 108                 idr_destroy(&file->object_idr);
 109                 spin_unlock(&file->table_lock);
 110         }
 111
 112         mutex_unlock(&ddev->filelist_mutex);
 113 }
 114
 115 /*
 116  * Call from drm_gem_handle_create which appear in both new and open ioctl
 117  * case.
 118  */
 119 int amdgpu_gem_object_open(struct drm_gem_object *obj,
 120                            struct drm_file *file_priv)
 121 {
 122         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 123         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 124         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 125         struct amdgpu_vm *vm = &fpriv->vm;
 126         struct amdgpu_bo_va *bo_va;
 127         int r;
 128         r = amdgpu_bo_reserve(abo, false);
 129         if (r)
 130                 return r;
 131
 132         bo_va = amdgpu_vm_bo_find(vm, abo);
 133         if (!bo_va) {
 134                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 135         } else {
 136                 ++bo_va->ref_count;
 137         }
 138         amdgpu_bo_unreserve(abo);
 139         return 0;
 140 }
 141
 142 static int amdgpu_gem_vm_check(void *param, struct amdgpu_bo *bo)
 143 {
 144         /* if anything is swapped out don't swap it in here,
 145            just abort and wait for the next CS */
 146         if (!amdgpu_bo_gpu_accessible(bo))
 147                 return -ERESTARTSYS;
 148
 149         if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
 150                 return -ERESTARTSYS;
 151
 152         return 0;
 153 }
 154
 155 static bool amdgpu_gem_vm_ready(struct amdgpu_device *adev,
 156                                 struct amdgpu_vm *vm,
 157                                 struct list_head *list)
 158 {
 159         struct ttm_validate_buffer *entry;
 160
 161         list_for_each_entry(entry, list, head) {
 162                 struct amdgpu_bo *bo =
 163                         container_of(entry->bo, struct amdgpu_bo, tbo);
 164                 if (amdgpu_gem_vm_check(NULL, bo))
 165                         return false;
 166         }
 167
 168         return !amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_vm_check, NULL);
 169 }
 170
 171 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 172                              struct drm_file *file_priv)
 173 {
 174         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 175         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 176         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 177         struct amdgpu_vm *vm = &fpriv->vm;
 178
 179         struct amdgpu_bo_list_entry vm_pd;
 180         struct list_head list;
 181         struct ttm_validate_buffer tv;
 182         struct ww_acquire_ctx ticket;
 183         struct amdgpu_bo_va *bo_va;
 184         int r;
 185
 186         INIT_LIST_HEAD(&list);
 187
 188         tv.bo = &bo->tbo;
 189         tv.shared = true;
 190         list_add(&tv.head, &list);
 191
 192         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 193
 194         r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
 195         if (r) {
 196                 dev_err(adev->dev, "leaking bo va because "
 197                         "we fail to reserve bo (%d)\n", r);
 198                 return;
 199         }
 200         bo_va = amdgpu_vm_bo_find(vm, bo);
 201         if (bo_va && --bo_va->ref_count == 0) {
 202                 amdgpu_vm_bo_rmv(adev, bo_va);
 203
 204                 if (amdgpu_gem_vm_ready(adev, vm, &list)) {
 205                         struct dma_fence *fence = NULL;
 206
 207                         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 208                         if (unlikely(r)) {
 209                                 dev_err(adev->dev, "failed to clear page "
 210                                         "tables on GEM object close (%d)\n", r);
 211                         }
 212
 213                         if (fence) {
 214                                 amdgpu_bo_fence(bo, fence, true);
 215                                 dma_fence_put(fence);
 216                         }
 217                 }
 218         }
 219         ttm_eu_backoff_reservation(&ticket, &list);
 220 }
 221
 222 /*
 223  * GEM ioctls.
 224  */
 225 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 226                             struct drm_file *filp)
 227 {
 228         struct amdgpu_device *adev = dev->dev_private;
 229         union drm_amdgpu_gem_create *args = data;
 230         uint64_t size = args->in.bo_size;
 231         struct drm_gem_object *gobj;
 232         uint32_t handle;
 233         bool kernel = false;
 234         int r;
 235
 236         /* reject invalid gem flags */
 237         if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 238                                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 239                                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 240                                       AMDGPU_GEM_CREATE_VRAM_CLEARED|
 241                                       AMDGPU_GEM_CREATE_SHADOW |
 242                                       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS))
 243                 return -EINVAL;
 244
 245         /* reject invalid gem domains */
 246         if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
 247                                  AMDGPU_GEM_DOMAIN_GTT |
 248                                  AMDGPU_GEM_DOMAIN_VRAM |
 249                                  AMDGPU_GEM_DOMAIN_GDS |
 250                                  AMDGPU_GEM_DOMAIN_GWS |
 251                                  AMDGPU_GEM_DOMAIN_OA))
 252                 return -EINVAL;
 253
 254         /* create a gem object to contain this object in */
 255         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 256             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 257                 kernel = true;
 258                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 259                         size = size << AMDGPU_GDS_SHIFT;
 260                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 261                         size = size << AMDGPU_GWS_SHIFT;
 262                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 263                         size = size << AMDGPU_OA_SHIFT;
 264                 else
 265                         return -EINVAL;
 266         }
 267         size = roundup(size, PAGE_SIZE);
 268
 269         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 270                                      (u32)(0xffffffff & args->in.domains),
 271                                      args->in.domain_flags,
 272                                      kernel, &gobj);
 273         if (r)
 274                 return r;
 275
 276         r = drm_gem_handle_create(filp, gobj, &handle);
 277         /* drop reference from allocate - handle holds it now */
 278         drm_gem_object_unreference_unlocked(gobj);
 279         if (r)
 280                 return r;
 281
 282         memset(args, 0, sizeof(*args));
 283         args->out.handle = handle;
 284         return 0;
 285 }
 286
 287 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 288                              struct drm_file *filp)
 289 {
 290         struct amdgpu_device *adev = dev->dev_private;
 291         struct drm_amdgpu_gem_userptr *args = data;
 292         struct drm_gem_object *gobj;
 293         struct amdgpu_bo *bo;
 294         uint32_t handle;
 295         int r;
 296
 297         if (offset_in_page(args->addr | args->size))
 298                 return -EINVAL;
 299
 300         /* reject unknown flag values */
 301         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 302             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 303             AMDGPU_GEM_USERPTR_REGISTER))
 304                 return -EINVAL;
 305
 306         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 307              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 308
 309                 /* if we want to write to it we must install a MMU notifier */
 310                 return -EACCES;
 311         }
 312
 313         /* create a gem object to contain this object in */
 314         r = amdgpu_gem_object_create(adev, args->size, 0,
 315                                      AMDGPU_GEM_DOMAIN_CPU, 0,
 316                                      0, &gobj);
 317         if (r)
 318                 return r;
 319
 320         bo = gem_to_amdgpu_bo(gobj);
 321         bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
 322         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 323         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 324         if (r)
 325                 goto release_object;
 326
 327         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
 328                 r = amdgpu_mn_register(bo, args->addr);
 329                 if (r)
 330                         goto release_object;
 331         }
 332
 333         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 334                 down_read(&current->mm->mmap_sem);
 335
 336                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
 337                                                  bo->tbo.ttm->pages);
 338                 if (r)
 339                         goto unlock_mmap_sem;
 340
 341                 r = amdgpu_bo_reserve(bo, true);
 342                 if (r)
 343                         goto free_pages;
 344
 345                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 346                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 347                 amdgpu_bo_unreserve(bo);
 348                 if (r)
 349                         goto free_pages;
 350
 351                 up_read(&current->mm->mmap_sem);
 352         }
 353
 354         r = drm_gem_handle_create(filp, gobj, &handle);
 355         /* drop reference from allocate - handle holds it now */
 356         drm_gem_object_unreference_unlocked(gobj);
 357         if (r)
 358                 return r;
 359
 360         args->handle = handle;
 361         return 0;
 362
 363 free_pages:
 364         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
 365
 366 unlock_mmap_sem:
 367         up_read(&current->mm->mmap_sem);
 368
 369 release_object:
 370         drm_gem_object_unreference_unlocked(gobj);
 371
 372         return r;
 373 }
 374
 375 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 376                           struct drm_device *dev,
 377                           uint32_t handle, uint64_t *offset_p)
 378 {
 379         struct drm_gem_object *gobj;
 380         struct amdgpu_bo *robj;
 381
 382         gobj = drm_gem_object_lookup(filp, handle);
 383         if (gobj == NULL) {
 384                 return -ENOENT;
 385         }
 386         robj = gem_to_amdgpu_bo(gobj);
 387         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 388             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 389                 drm_gem_object_unreference_unlocked(gobj);
 390                 return -EPERM;
 391         }
 392         *offset_p = amdgpu_bo_mmap_offset(robj);
 393         drm_gem_object_unreference_unlocked(gobj);
 394         return 0;
 395 }
 396
 397 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 398                           struct drm_file *filp)
 399 {
 400         union drm_amdgpu_gem_mmap *args = data;
 401         uint32_t handle = args->in.handle;
 402         memset(args, 0, sizeof(*args));
 403         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 404 }
 405
 406 /**
 407  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 408  *
 409  * @timeout_ns: timeout in ns
 410  *
 411  * Calculate the timeout in jiffies from an absolute timeout in ns.
 412  */
 413 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 414 {
 415         unsigned long timeout_jiffies;
 416         ktime_t timeout;
 417
 418         /* clamp timeout if it's to large */
 419         if (((int64_t)timeout_ns) < 0)
 420                 return MAX_SCHEDULE_TIMEOUT;
 421
 422         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 423         if (ktime_to_ns(timeout) < 0)
 424                 return 0;
 425
 426         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 427         /*  clamp timeout to avoid unsigned-> signed overflow */
 428         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 429                 return MAX_SCHEDULE_TIMEOUT - 1;
 430
 431         return timeout_jiffies;
 432 }
 433
 434 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 435                               struct drm_file *filp)
 436 {
 437         union drm_amdgpu_gem_wait_idle *args = data;
 438         struct drm_gem_object *gobj;
 439         struct amdgpu_bo *robj;
 440         uint32_t handle = args->in.handle;
 441         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 442         int r = 0;
 443         long ret;
 444
 445         gobj = drm_gem_object_lookup(filp, handle);
 446         if (gobj == NULL) {
 447                 return -ENOENT;
 448         }
 449         robj = gem_to_amdgpu_bo(gobj);
 450         ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
 451                                                   timeout);
 452
 453         /* ret == 0 means not signaled,
 454          * ret > 0 means signaled
 455          * ret < 0 means interrupted before timeout
 456          */
 457         if (ret >= 0) {
 458                 memset(args, 0, sizeof(*args));
 459                 args->out.status = (ret == 0);
 460         } else
 461                 r = ret;
 462
 463         drm_gem_object_unreference_unlocked(gobj);
 464         return r;
 465 }
 466
 467 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 468                                 struct drm_file *filp)
 469 {
 470         struct drm_amdgpu_gem_metadata *args = data;
 471         struct drm_gem_object *gobj;
 472         struct amdgpu_bo *robj;
 473         int r = -1;
 474
 475         DRM_DEBUG("%d \n", args->handle);
 476         gobj = drm_gem_object_lookup(filp, args->handle);
 477         if (gobj == NULL)
 478                 return -ENOENT;
 479         robj = gem_to_amdgpu_bo(gobj);
 480
 481         r = amdgpu_bo_reserve(robj, false);
 482         if (unlikely(r != 0))
 483                 goto out;
 484
 485         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 486                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 487                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 488                                            sizeof(args->data.data),
 489                                            &args->data.data_size_bytes,
 490                                            &args->data.flags);
 491         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 492                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 493                         r = -EINVAL;
 494                         goto unreserve;
 495                 }
 496                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 497                 if (!r)
 498                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 499                                                    args->data.data_size_bytes,
 500                                                    args->data.flags);
 501         }
 502
 503 unreserve:
 504         amdgpu_bo_unreserve(robj);
 505 out:
 506         drm_gem_object_unreference_unlocked(gobj);
 507         return r;
 508 }
 509
 510 /**
 511  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 512  *
 513  * @adev: amdgpu_device pointer
 514  * @vm: vm to update
 515  * @bo_va: bo_va to update
 516  * @list: validation list
 517  * @operation: map, unmap or clear
 518  *
 519  * Update the bo_va directly after setting its address. Errors are not
 520  * vital here, so they are not reported back to userspace.
 521  */
 522 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 523                                     struct amdgpu_vm *vm,
 524                                     struct amdgpu_bo_va *bo_va,
 525                                     struct list_head *list,
 526                                     uint32_t operation)
 527 {
 528         int r = -ERESTARTSYS;
 529
 530         if (!amdgpu_gem_vm_ready(adev, vm, list))
 531                 goto error;
 532
 533         r = amdgpu_vm_update_directories(adev, vm);
 534         if (r)
 535                 goto error;
 536
 537         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 538         if (r)
 539                 goto error;
 540
 541         if (operation == AMDGPU_VA_OP_MAP ||
 542             operation == AMDGPU_VA_OP_REPLACE)
 543                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 544
 545 error:
 546         if (r && r != -ERESTARTSYS)
 547                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 548 }
 549
 550 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 551                           struct drm_file *filp)
 552 {
 553         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 554                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 555                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
 556         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 557                 AMDGPU_VM_PAGE_PRT;
 558
 559         struct drm_amdgpu_gem_va *args = data;
 560         struct drm_gem_object *gobj;
 561         struct amdgpu_device *adev = dev->dev_private;
 562         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 563         struct amdgpu_bo *abo;
 564         struct amdgpu_bo_va *bo_va;
 565         struct amdgpu_bo_list_entry vm_pd;
 566         struct ttm_validate_buffer tv;
 567         struct ww_acquire_ctx ticket;
 568         struct list_head list;
 569         uint64_t va_flags;
 570         int r = 0;
 571
 572         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 573                 dev_err(&dev->pdev->dev,
 574                         "va_address 0x%lX is in reserved area 0x%X\n",
 575                         (unsigned long)args->va_address,
 576                         AMDGPU_VA_RESERVED_SIZE);
 577                 return -EINVAL;
 578         }
 579
 580         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 581                 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
 582                         args->flags);
 583                 return -EINVAL;
 584         }
 585
 586         switch (args->operation) {
 587         case AMDGPU_VA_OP_MAP:
 588         case AMDGPU_VA_OP_UNMAP:
 589         case AMDGPU_VA_OP_CLEAR:
 590         case AMDGPU_VA_OP_REPLACE:
 591                 break;
 592         default:
 593                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
 594                         args->operation);
 595                 return -EINVAL;
 596         }
 597         if ((args->operation == AMDGPU_VA_OP_MAP) ||
 598             (args->operation == AMDGPU_VA_OP_REPLACE)) {
 599                 if (amdgpu_kms_vram_lost(adev, fpriv))
 600                         return -ENODEV;
 601         }
 602
 603         INIT_LIST_HEAD(&list);
 604         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 605             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 606                 gobj = drm_gem_object_lookup(filp, args->handle);
 607                 if (gobj == NULL)
 608                         return -ENOENT;
 609                 abo = gem_to_amdgpu_bo(gobj);
 610                 tv.bo = &abo->tbo;
 611                 tv.shared = false;
 612                 list_add(&tv.head, &list);
 613         } else {
 614                 gobj = NULL;
 615                 abo = NULL;
 616         }
 617
 618         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 619
 620         r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
 621         if (r)
 622                 goto error_unref;
 623
 624         if (abo) {
 625                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 626                 if (!bo_va) {
 627                         r = -ENOENT;
 628                         goto error_backoff;
 629                 }
 630         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 631                 bo_va = fpriv->prt_va;
 632         } else {
 633                 bo_va = NULL;
 634         }
 635
 636         switch (args->operation) {
 637         case AMDGPU_VA_OP_MAP:
 638                 r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address,
 639                                         args->map_size);
 640                 if (r)
 641                         goto error_backoff;
 642
 643                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
 644                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 645                                      args->offset_in_bo, args->map_size,
 646                                      va_flags);
 647                 break;
 648         case AMDGPU_VA_OP_UNMAP:
 649                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 650                 break;
 651
 652         case AMDGPU_VA_OP_CLEAR:
 653                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 654                                                 args->va_address,
 655                                                 args->map_size);
 656                 break;
 657         case AMDGPU_VA_OP_REPLACE:
 658                 r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address,
 659                                         args->map_size);
 660                 if (r)
 661                         goto error_backoff;
 662
 663                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
 664                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 665                                              args->offset_in_bo, args->map_size,
 666                                              va_flags);
 667                 break;
 668         default:
 669                 break;
 670         }
 671         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
 672                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
 673                                         args->operation);
 674
 675 error_backoff:
 676         ttm_eu_backoff_reservation(&ticket, &list);
 677
 678 error_unref:
 679         drm_gem_object_unreference_unlocked(gobj);
 680         return r;
 681 }
 682
 683 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 684                         struct drm_file *filp)
 685 {
 686         struct drm_amdgpu_gem_op *args = data;
 687         struct drm_gem_object *gobj;
 688         struct amdgpu_bo *robj;
 689         int r;
 690
 691         gobj = drm_gem_object_lookup(filp, args->handle);
 692         if (gobj == NULL) {
 693                 return -ENOENT;
 694         }
 695         robj = gem_to_amdgpu_bo(gobj);
 696
 697         r = amdgpu_bo_reserve(robj, false);
 698         if (unlikely(r))
 699                 goto out;
 700
 701         switch (args->op) {
 702         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 703                 struct drm_amdgpu_gem_create_in info;
 704                 void __user *out = (void __user *)(uintptr_t)args->value;
 705
 706                 info.bo_size = robj->gem_base.size;
 707                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 708                 info.domains = robj->prefered_domains;
 709                 info.domain_flags = robj->flags;
 710                 amdgpu_bo_unreserve(robj);
 711                 if (copy_to_user(out, &info, sizeof(info)))
 712                         r = -EFAULT;
 713                 break;
 714         }
 715         case AMDGPU_GEM_OP_SET_PLACEMENT:
 716                 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
 717                         r = -EINVAL;
 718                         amdgpu_bo_unreserve(robj);
 719                         break;
 720                 }
 721                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 722                         r = -EPERM;
 723                         amdgpu_bo_unreserve(robj);
 724                         break;
 725                 }
 726                 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 727                                                         AMDGPU_GEM_DOMAIN_GTT |
 728                                                         AMDGPU_GEM_DOMAIN_CPU);
 729                 robj->allowed_domains = robj->prefered_domains;
 730                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 731                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 732
 733                 amdgpu_bo_unreserve(robj);
 734                 break;
 735         default:
 736                 amdgpu_bo_unreserve(robj);
 737                 r = -EINVAL;
 738         }
 739
 740 out:
 741         drm_gem_object_unreference_unlocked(gobj);
 742         return r;
 743 }
 744
 745 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 746                             struct drm_device *dev,
 747                             struct drm_mode_create_dumb *args)
 748 {
 749         struct amdgpu_device *adev = dev->dev_private;
 750         struct drm_gem_object *gobj;
 751         uint32_t handle;
 752         int r;
 753
 754         args->pitch = amdgpu_align_pitch(adev, args->width,
 755                                          DIV_ROUND_UP(args->bpp, 8), 0);
 756         args->size = (u64)args->pitch * args->height;
 757         args->size = ALIGN(args->size, PAGE_SIZE);
 758
 759         r = amdgpu_gem_object_create(adev, args->size, 0,
 760                                      AMDGPU_GEM_DOMAIN_VRAM,
 761                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 762                                      ttm_bo_type_device,
 763                                      &gobj);
 764         if (r)
 765                 return -ENOMEM;
 766
 767         r = drm_gem_handle_create(file_priv, gobj, &handle);
 768         /* drop reference from allocate - handle holds it now */
 769         drm_gem_object_unreference_unlocked(gobj);
 770         if (r) {
 771                 return r;
 772         }
 773         args->handle = handle;
 774         return 0;
 775 }
 776
 777 #if defined(CONFIG_DEBUG_FS)
 778 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 779 {
 780         struct drm_gem_object *gobj = ptr;
 781         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 782         struct seq_file *m = data;
 783
 784         unsigned domain;
 785         const char *placement;
 786         unsigned pin_count;
 787
 788         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 789         switch (domain) {
 790         case AMDGPU_GEM_DOMAIN_VRAM:
 791                 placement = "VRAM";
 792                 break;
 793         case AMDGPU_GEM_DOMAIN_GTT:
 794                 placement = " GTT";
 795                 break;
 796         case AMDGPU_GEM_DOMAIN_CPU:
 797         default:
 798                 placement = " CPU";
 799                 break;
 800         }
 801         seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
 802                    id, amdgpu_bo_size(bo), placement,
 803                    amdgpu_bo_gpu_offset(bo));
 804
 805         pin_count = ACCESS_ONCE(bo->pin_count);
 806         if (pin_count)
 807                 seq_printf(m, " pin count %d", pin_count);
 808         seq_printf(m, "\n");
 809
 810         return 0;
 811 }
 812
 813 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 814 {
 815         struct drm_info_node *node = (struct drm_info_node *)m->private;
 816         struct drm_device *dev = node->minor->dev;
 817         struct drm_file *file;
 818         int r;
 819
 820         r = mutex_lock_interruptible(&dev->filelist_mutex);
 821         if (r)
 822                 return r;
 823
 824         list_for_each_entry(file, &dev->filelist, lhead) {
 825                 struct task_struct *task;
 826
 827                 /*
 828                  * Although we have a valid reference on file->pid, that does
 829                  * not guarantee that the task_struct who called get_pid() is
 830                  * still alive (e.g. get_pid(current) => fork() => exit()).
 831                  * Therefore, we need to protect this ->comm access using RCU.
 832                  */
 833                 rcu_read_lock();
 834                 task = pid_task(file->pid, PIDTYPE_PID);
 835                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 836                            task ? task->comm : "<unknown>");
 837                 rcu_read_unlock();
 838
 839                 spin_lock(&file->table_lock);
 840                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
 841                 spin_unlock(&file->table_lock);
 842         }
 843
 844         mutex_unlock(&dev->filelist_mutex);
 845         return 0;
 846 }
 847
 848 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
 849         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 850 };
 851 #endif
 852
 853 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
 854 {
 855 #if defined(CONFIG_DEBUG_FS)
 856         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 857 #endif
 858         return 0;
 859 }