5 * \author Gareth Hughes <gareth@valinux.com>
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_gem.h>
35 #include "amdgpu_drv.h"
37 #include <drm/drm_pciids.h>
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/vga_switcheroo.h>
42 #include "drm_crtc_helper.h"
45 #include "amdgpu_irq.h"
47 #include "amdgpu_amdkfd.h"
51 * - 3.0.0 - initial driver
52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
55 * - 3.3.0 - Add VM support for UVD on supported hardware.
56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
57 * - 3.5.0 - Add support for new UVD_NO_OP register.
58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
59 * - 3.7.0 - Add support for VCE clock list packet
60 * - 3.8.0 - Add support raster config init in the kernel
61 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
64 * - 3.12.0 - Add query for double offchip LDS buffers
65 * - 3.13.0 - Add PRT support
67 #define KMS_DRIVER_MAJOR 3
68 #define KMS_DRIVER_MINOR 13
69 #define KMS_DRIVER_PATCHLEVEL 0
71 int amdgpu_vram_limit = 0;
72 int amdgpu_gart_size = -1; /* auto */
73 int amdgpu_moverate = -1; /* auto */
74 int amdgpu_benchmarking = 0;
75 int amdgpu_testing = 0;
76 int amdgpu_audio = -1;
77 int amdgpu_disp_priority = 0;
78 int amdgpu_hw_i2c = 0;
79 int amdgpu_pcie_gen2 = -1;
81 int amdgpu_lockup_timeout = 0;
83 int amdgpu_fw_load_type = -1;
85 int amdgpu_runtime_pm = -1;
86 unsigned amdgpu_ip_block_mask = 0xffffffff;
88 int amdgpu_deep_color = 0;
89 int amdgpu_vm_size = -1;
90 int amdgpu_vm_block_size = -1;
91 int amdgpu_vm_fault_stop = 0;
92 int amdgpu_vm_debug = 0;
93 int amdgpu_vram_page_split = 1024;
94 int amdgpu_exp_hw_support = 0;
95 int amdgpu_sched_jobs = 32;
96 int amdgpu_sched_hw_submission = 2;
97 int amdgpu_no_evict = 0;
98 int amdgpu_direct_gma_size = 0;
99 unsigned amdgpu_pcie_gen_cap = 0;
100 unsigned amdgpu_pcie_lane_cap = 0;
101 unsigned amdgpu_cg_mask = 0xffffffff;
102 unsigned amdgpu_pg_mask = 0xffffffff;
103 char *amdgpu_disable_cu = NULL;
104 char *amdgpu_virtual_display = NULL;
105 unsigned amdgpu_pp_feature_mask = 0xffffffff;
107 int amdgpu_prim_buf_per_se = 0;
108 int amdgpu_pos_buf_per_se = 0;
109 int amdgpu_cntl_sb_buf_per_se = 0;
110 int amdgpu_param_buf_per_se = 0;
112 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
113 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
115 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
116 module_param_named(gartsize, amdgpu_gart_size, int, 0600);
118 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
119 module_param_named(moverate, amdgpu_moverate, int, 0600);
121 MODULE_PARM_DESC(benchmark, "Run benchmark");
122 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
124 MODULE_PARM_DESC(test, "Run tests");
125 module_param_named(test, amdgpu_testing, int, 0444);
127 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
128 module_param_named(audio, amdgpu_audio, int, 0444);
130 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
131 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
133 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
134 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
136 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
137 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
139 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
140 module_param_named(msi, amdgpu_msi, int, 0444);
142 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
143 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
145 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
146 module_param_named(dpm, amdgpu_dpm, int, 0444);
148 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
149 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
151 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
152 module_param_named(aspm, amdgpu_aspm, int, 0444);
154 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
155 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
157 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
158 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
160 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
161 module_param_named(bapm, amdgpu_bapm, int, 0444);
163 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
164 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
166 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
167 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
169 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
170 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
172 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
173 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
175 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
176 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
178 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)");
179 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
181 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
182 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
184 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
185 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
187 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
188 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
190 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
191 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);
193 MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
194 module_param_named(no_evict, amdgpu_no_evict, int, 0444);
196 MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
197 module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
199 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
200 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
202 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
203 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
205 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
206 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
208 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
209 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
211 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
212 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
214 MODULE_PARM_DESC(virtual_display,
215 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
216 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
218 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
219 module_param_named(ngg, amdgpu_ngg, int, 0444);
221 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
222 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
224 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
225 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
227 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
228 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
230 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
231 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
234 static const struct pci_device_id pciidlist[] = {
235 #ifdef CONFIG_DRM_AMDGPU_SI
236 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
237 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
238 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
239 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
240 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
241 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
242 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
243 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
244 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
245 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
246 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
247 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
248 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
249 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
250 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
251 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
252 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
253 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
254 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
255 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
256 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
257 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
258 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
259 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
260 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
261 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
262 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
263 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
264 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
265 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
266 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
267 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
268 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
269 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
270 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
271 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
272 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
273 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
274 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
275 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
276 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
277 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
278 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
279 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
280 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
281 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
282 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
283 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
284 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
285 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
286 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
287 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
288 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
289 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
290 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
291 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
292 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
293 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
294 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
295 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
296 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
297 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
298 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
299 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
300 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
301 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
302 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
303 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
304 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
305 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
306 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
307 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
309 #ifdef CONFIG_DRM_AMDGPU_CIK
311 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
312 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
313 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
314 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
315 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
316 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
317 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
318 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
319 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
320 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
321 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
322 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
323 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
324 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
325 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
326 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
327 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
328 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
329 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
330 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
331 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
332 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
334 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
335 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
336 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
337 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
338 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
339 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
340 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
341 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
342 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
343 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
344 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
346 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
347 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
348 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
349 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
350 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
351 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
352 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
353 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
354 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
355 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
356 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
357 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
359 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
360 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
361 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
362 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
363 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
364 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
365 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
366 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
367 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
368 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
369 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
370 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
371 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
372 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
373 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
374 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
376 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
377 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
378 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
379 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
380 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
381 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
382 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
383 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
384 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
385 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
386 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
387 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
388 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
389 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
390 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
391 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
394 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
395 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
396 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
397 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
398 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
400 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
401 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
402 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
403 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
404 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
405 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
406 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
407 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
408 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
410 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
411 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
413 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
414 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
415 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
416 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
417 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
419 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
421 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
422 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
423 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
424 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
425 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
426 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
427 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
428 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
429 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
431 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
432 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
433 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
434 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
435 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
436 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
437 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
438 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
439 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
440 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
441 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
442 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
444 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
445 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
446 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
447 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
448 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
449 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
450 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
452 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
453 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
454 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
455 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
456 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
457 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
458 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
462 MODULE_DEVICE_TABLE(pci, pciidlist);
464 static struct drm_driver kms_driver;
466 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
468 struct apertures_struct *ap;
469 bool primary = false;
471 ap = alloc_apertures(1);
475 ap->ranges[0].base = pci_resource_start(pdev, 0);
476 ap->ranges[0].size = pci_resource_len(pdev, 0);
479 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
481 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
487 static int amdgpu_pci_probe(struct pci_dev *pdev,
488 const struct pci_device_id *ent)
490 unsigned long flags = ent->driver_data;
493 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
494 DRM_INFO("This hardware requires experimental hardware support.\n"
495 "See modparam exp_hw_support\n");
500 * Initialize amdkfd before starting radeon. If it was not loaded yet,
501 * defer radeon probing
503 ret = amdgpu_amdkfd_init();
504 if (ret == -EPROBE_DEFER)
507 /* Get rid of things like offb */
508 ret = amdgpu_kick_out_firmware_fb(pdev);
512 return drm_get_pci_dev(pdev, ent, &kms_driver);
516 amdgpu_pci_remove(struct pci_dev *pdev)
518 struct drm_device *dev = pci_get_drvdata(pdev);
524 amdgpu_pci_shutdown(struct pci_dev *pdev)
526 struct drm_device *dev = pci_get_drvdata(pdev);
527 struct amdgpu_device *adev = dev->dev_private;
529 /* if we are running in a VM, make sure the device
530 * torn down properly on reboot/shutdown.
531 * unfortunately we can't detect certain
532 * hypervisors so just do this all the time.
534 amdgpu_suspend(adev);
537 static int amdgpu_pmops_suspend(struct device *dev)
539 struct pci_dev *pdev = to_pci_dev(dev);
541 struct drm_device *drm_dev = pci_get_drvdata(pdev);
542 return amdgpu_device_suspend(drm_dev, true, true);
545 static int amdgpu_pmops_resume(struct device *dev)
547 struct pci_dev *pdev = to_pci_dev(dev);
548 struct drm_device *drm_dev = pci_get_drvdata(pdev);
550 /* GPU comes up enabled by the bios on resume */
551 if (amdgpu_device_is_px(drm_dev)) {
552 pm_runtime_disable(dev);
553 pm_runtime_set_active(dev);
554 pm_runtime_enable(dev);
557 return amdgpu_device_resume(drm_dev, true, true);
560 static int amdgpu_pmops_freeze(struct device *dev)
562 struct pci_dev *pdev = to_pci_dev(dev);
564 struct drm_device *drm_dev = pci_get_drvdata(pdev);
565 return amdgpu_device_suspend(drm_dev, false, true);
568 static int amdgpu_pmops_thaw(struct device *dev)
570 struct pci_dev *pdev = to_pci_dev(dev);
572 struct drm_device *drm_dev = pci_get_drvdata(pdev);
573 return amdgpu_device_resume(drm_dev, false, true);
576 static int amdgpu_pmops_poweroff(struct device *dev)
578 struct pci_dev *pdev = to_pci_dev(dev);
580 struct drm_device *drm_dev = pci_get_drvdata(pdev);
581 return amdgpu_device_suspend(drm_dev, true, true);
584 static int amdgpu_pmops_restore(struct device *dev)
586 struct pci_dev *pdev = to_pci_dev(dev);
588 struct drm_device *drm_dev = pci_get_drvdata(pdev);
589 return amdgpu_device_resume(drm_dev, false, true);
592 static int amdgpu_pmops_runtime_suspend(struct device *dev)
594 struct pci_dev *pdev = to_pci_dev(dev);
595 struct drm_device *drm_dev = pci_get_drvdata(pdev);
598 if (!amdgpu_device_is_px(drm_dev)) {
599 pm_runtime_forbid(dev);
603 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
604 drm_kms_helper_poll_disable(drm_dev);
605 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
607 ret = amdgpu_device_suspend(drm_dev, false, false);
608 pci_save_state(pdev);
609 pci_disable_device(pdev);
610 pci_ignore_hotplug(pdev);
611 if (amdgpu_is_atpx_hybrid())
612 pci_set_power_state(pdev, PCI_D3cold);
613 else if (!amdgpu_has_atpx_dgpu_power_cntl())
614 pci_set_power_state(pdev, PCI_D3hot);
615 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
620 static int amdgpu_pmops_runtime_resume(struct device *dev)
622 struct pci_dev *pdev = to_pci_dev(dev);
623 struct drm_device *drm_dev = pci_get_drvdata(pdev);
626 if (!amdgpu_device_is_px(drm_dev))
629 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
631 if (amdgpu_is_atpx_hybrid() ||
632 !amdgpu_has_atpx_dgpu_power_cntl())
633 pci_set_power_state(pdev, PCI_D0);
634 pci_restore_state(pdev);
635 ret = pci_enable_device(pdev);
638 pci_set_master(pdev);
640 ret = amdgpu_device_resume(drm_dev, false, false);
641 drm_kms_helper_poll_enable(drm_dev);
642 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
643 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
647 static int amdgpu_pmops_runtime_idle(struct device *dev)
649 struct pci_dev *pdev = to_pci_dev(dev);
650 struct drm_device *drm_dev = pci_get_drvdata(pdev);
651 struct drm_crtc *crtc;
653 if (!amdgpu_device_is_px(drm_dev)) {
654 pm_runtime_forbid(dev);
658 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
660 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
665 pm_runtime_mark_last_busy(dev);
666 pm_runtime_autosuspend(dev);
667 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
671 long amdgpu_drm_ioctl(struct file *filp,
672 unsigned int cmd, unsigned long arg)
674 struct drm_file *file_priv = filp->private_data;
675 struct drm_device *dev;
677 dev = file_priv->minor->dev;
678 ret = pm_runtime_get_sync(dev->dev);
682 ret = drm_ioctl(filp, cmd, arg);
684 pm_runtime_mark_last_busy(dev->dev);
685 pm_runtime_put_autosuspend(dev->dev);
689 static const struct dev_pm_ops amdgpu_pm_ops = {
690 .suspend = amdgpu_pmops_suspend,
691 .resume = amdgpu_pmops_resume,
692 .freeze = amdgpu_pmops_freeze,
693 .thaw = amdgpu_pmops_thaw,
694 .poweroff = amdgpu_pmops_poweroff,
695 .restore = amdgpu_pmops_restore,
696 .runtime_suspend = amdgpu_pmops_runtime_suspend,
697 .runtime_resume = amdgpu_pmops_runtime_resume,
698 .runtime_idle = amdgpu_pmops_runtime_idle,
701 static const struct file_operations amdgpu_driver_kms_fops = {
702 .owner = THIS_MODULE,
704 .release = drm_release,
705 .unlocked_ioctl = amdgpu_drm_ioctl,
710 .compat_ioctl = amdgpu_kms_compat_ioctl,
714 static struct drm_driver kms_driver = {
717 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
718 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET,
719 .load = amdgpu_driver_load_kms,
720 .open = amdgpu_driver_open_kms,
721 .postclose = amdgpu_driver_postclose_kms,
722 .lastclose = amdgpu_driver_lastclose_kms,
723 .set_busid = drm_pci_set_busid,
724 .unload = amdgpu_driver_unload_kms,
725 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
726 .enable_vblank = amdgpu_enable_vblank_kms,
727 .disable_vblank = amdgpu_disable_vblank_kms,
728 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
729 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
730 #if defined(CONFIG_DEBUG_FS)
731 .debugfs_init = amdgpu_debugfs_init,
733 .irq_preinstall = amdgpu_irq_preinstall,
734 .irq_postinstall = amdgpu_irq_postinstall,
735 .irq_uninstall = amdgpu_irq_uninstall,
736 .irq_handler = amdgpu_irq_handler,
737 .ioctls = amdgpu_ioctls_kms,
738 .gem_free_object_unlocked = amdgpu_gem_object_free,
739 .gem_open_object = amdgpu_gem_object_open,
740 .gem_close_object = amdgpu_gem_object_close,
741 .dumb_create = amdgpu_mode_dumb_create,
742 .dumb_map_offset = amdgpu_mode_dumb_mmap,
743 .dumb_destroy = drm_gem_dumb_destroy,
744 .fops = &amdgpu_driver_kms_fops,
746 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
747 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
748 .gem_prime_export = amdgpu_gem_prime_export,
749 .gem_prime_import = drm_gem_prime_import,
750 .gem_prime_pin = amdgpu_gem_prime_pin,
751 .gem_prime_unpin = amdgpu_gem_prime_unpin,
752 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
753 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
754 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
755 .gem_prime_vmap = amdgpu_gem_prime_vmap,
756 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
761 .major = KMS_DRIVER_MAJOR,
762 .minor = KMS_DRIVER_MINOR,
763 .patchlevel = KMS_DRIVER_PATCHLEVEL,
766 static struct drm_driver *driver;
767 static struct pci_driver *pdriver;
769 static struct pci_driver amdgpu_kms_pci_driver = {
771 .id_table = pciidlist,
772 .probe = amdgpu_pci_probe,
773 .remove = amdgpu_pci_remove,
774 .shutdown = amdgpu_pci_shutdown,
775 .driver.pm = &amdgpu_pm_ops,
780 static int __init amdgpu_init(void)
784 r = amdgpu_sync_init();
788 r = amdgpu_fence_slab_init();
792 r = amd_sched_fence_slab_init();
796 if (vgacon_text_force()) {
797 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
800 DRM_INFO("amdgpu kernel modesetting enabled.\n");
801 driver = &kms_driver;
802 pdriver = &amdgpu_kms_pci_driver;
803 driver->num_ioctls = amdgpu_max_kms_ioctl;
804 amdgpu_register_atpx_handler();
805 /* let modprobe override vga console setting */
806 return drm_pci_init(driver, pdriver);
809 amdgpu_fence_slab_fini();
818 static void __exit amdgpu_exit(void)
820 amdgpu_amdkfd_fini();
821 drm_pci_exit(driver, pdriver);
822 amdgpu_unregister_atpx_handler();
824 amd_sched_fence_slab_fini();
825 amdgpu_fence_slab_fini();
828 module_init(amdgpu_init);
829 module_exit(amdgpu_exit);
831 MODULE_AUTHOR(DRIVER_AUTHOR);
832 MODULE_DESCRIPTION(DRIVER_DESC);
833 MODULE_LICENSE("GPL and additional rights");