drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __AMDGPU_DPM_H__
  24 #define __AMDGPU_DPM_H__
  25
  26 enum amdgpu_int_thermal_type {
  27         THERMAL_TYPE_NONE,
  28         THERMAL_TYPE_EXTERNAL,
  29         THERMAL_TYPE_EXTERNAL_GPIO,
  30         THERMAL_TYPE_RV6XX,
  31         THERMAL_TYPE_RV770,
  32         THERMAL_TYPE_ADT7473_WITH_INTERNAL,
  33         THERMAL_TYPE_EVERGREEN,
  34         THERMAL_TYPE_SUMO,
  35         THERMAL_TYPE_NI,
  36         THERMAL_TYPE_SI,
  37         THERMAL_TYPE_EMC2103_WITH_INTERNAL,
  38         THERMAL_TYPE_CI,
  39         THERMAL_TYPE_KV,
  40 };
  41
  42 enum amdgpu_dpm_auto_throttle_src {
  43         AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
  44         AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
  45 };
  46
  47 enum amdgpu_dpm_event_src {
  48         AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
  49         AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
  50         AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
  51         AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
  52         AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
  53 };
  54
  55 #define SCLK_DEEP_SLEEP_MASK 0x8
  56
  57 struct amdgpu_ps {
  58         u32 caps; /* vbios flags */
  59         u32 class; /* vbios flags */
  60         u32 class2; /* vbios flags */
  61         /* UVD clocks */
  62         u32 vclk;
  63         u32 dclk;
  64         /* VCE clocks */
  65         u32 evclk;
  66         u32 ecclk;
  67         bool vce_active;
  68         enum amd_vce_level vce_level;
  69         /* asic priv */
  70         void *ps_priv;
  71 };
  72
  73 struct amdgpu_dpm_thermal {
  74         /* thermal interrupt work */
  75         struct work_struct work;
  76         /* low temperature threshold */
  77         int                min_temp;
  78         /* high temperature threshold */
  79         int                max_temp;
  80         /* was last interrupt low to high or high to low */
  81         bool               high_to_low;
  82         /* interrupt source */
  83         struct amdgpu_irq_src   irq;
  84 };
  85
  86 enum amdgpu_clk_action
  87 {
  88         AMDGPU_SCLK_UP = 1,
  89         AMDGPU_SCLK_DOWN
  90 };
  91
  92 struct amdgpu_blacklist_clocks
  93 {
  94         u32 sclk;
  95         u32 mclk;
  96         enum amdgpu_clk_action action;
  97 };
  98
  99 struct amdgpu_clock_and_voltage_limits {
 100         u32 sclk;
 101         u32 mclk;
 102         u16 vddc;
 103         u16 vddci;
 104 };
 105
 106 struct amdgpu_clock_array {
 107         u32 count;
 108         u32 *values;
 109 };
 110
 111 struct amdgpu_clock_voltage_dependency_entry {
 112         u32 clk;
 113         u16 v;
 114 };
 115
 116 struct amdgpu_clock_voltage_dependency_table {
 117         u32 count;
 118         struct amdgpu_clock_voltage_dependency_entry *entries;
 119 };
 120
 121 union amdgpu_cac_leakage_entry {
 122         struct {
 123                 u16 vddc;
 124                 u32 leakage;
 125         };
 126         struct {
 127                 u16 vddc1;
 128                 u16 vddc2;
 129                 u16 vddc3;
 130         };
 131 };
 132
 133 struct amdgpu_cac_leakage_table {
 134         u32 count;
 135         union amdgpu_cac_leakage_entry *entries;
 136 };
 137
 138 struct amdgpu_phase_shedding_limits_entry {
 139         u16 voltage;
 140         u32 sclk;
 141         u32 mclk;
 142 };
 143
 144 struct amdgpu_phase_shedding_limits_table {
 145         u32 count;
 146         struct amdgpu_phase_shedding_limits_entry *entries;
 147 };
 148
 149 struct amdgpu_uvd_clock_voltage_dependency_entry {
 150         u32 vclk;
 151         u32 dclk;
 152         u16 v;
 153 };
 154
 155 struct amdgpu_uvd_clock_voltage_dependency_table {
 156         u8 count;
 157         struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
 158 };
 159
 160 struct amdgpu_vce_clock_voltage_dependency_entry {
 161         u32 ecclk;
 162         u32 evclk;
 163         u16 v;
 164 };
 165
 166 struct amdgpu_vce_clock_voltage_dependency_table {
 167         u8 count;
 168         struct amdgpu_vce_clock_voltage_dependency_entry *entries;
 169 };
 170
 171 struct amdgpu_ppm_table {
 172         u8 ppm_design;
 173         u16 cpu_core_number;
 174         u32 platform_tdp;
 175         u32 small_ac_platform_tdp;
 176         u32 platform_tdc;
 177         u32 small_ac_platform_tdc;
 178         u32 apu_tdp;
 179         u32 dgpu_tdp;
 180         u32 dgpu_ulv_power;
 181         u32 tj_max;
 182 };
 183
 184 struct amdgpu_cac_tdp_table {
 185         u16 tdp;
 186         u16 configurable_tdp;
 187         u16 tdc;
 188         u16 battery_power_limit;
 189         u16 small_power_limit;
 190         u16 low_cac_leakage;
 191         u16 high_cac_leakage;
 192         u16 maximum_power_delivery_limit;
 193 };
 194
 195 struct amdgpu_dpm_dynamic_state {
 196         struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
 197         struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
 198         struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
 199         struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
 200         struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
 201         struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
 202         struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
 203         struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
 204         struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
 205         struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
 206         struct amdgpu_clock_array valid_sclk_values;
 207         struct amdgpu_clock_array valid_mclk_values;
 208         struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
 209         struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
 210         u32 mclk_sclk_ratio;
 211         u32 sclk_mclk_delta;
 212         u16 vddc_vddci_delta;
 213         u16 min_vddc_for_pcie_gen2;
 214         struct amdgpu_cac_leakage_table cac_leakage_table;
 215         struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
 216         struct amdgpu_ppm_table *ppm_table;
 217         struct amdgpu_cac_tdp_table *cac_tdp_table;
 218 };
 219
 220 struct amdgpu_dpm_fan {
 221         u16 t_min;
 222         u16 t_med;
 223         u16 t_high;
 224         u16 pwm_min;
 225         u16 pwm_med;
 226         u16 pwm_high;
 227         u8 t_hyst;
 228         u32 cycle_delay;
 229         u16 t_max;
 230         u8 control_mode;
 231         u16 default_max_fan_pwm;
 232         u16 default_fan_output_sensitivity;
 233         u16 fan_output_sensitivity;
 234         bool ucode_fan_control;
 235 };
 236
 237 enum amdgpu_pcie_gen {
 238         AMDGPU_PCIE_GEN1 = 0,
 239         AMDGPU_PCIE_GEN2 = 1,
 240         AMDGPU_PCIE_GEN3 = 2,
 241         AMDGPU_PCIE_GEN_INVALID = 0xffff
 242 };
 243
 244 #define amdgpu_dpm_pre_set_power_state(adev) \
 245                 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
 246
 247 #define amdgpu_dpm_set_power_state(adev) \
 248                 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
 249
 250 #define amdgpu_dpm_post_set_power_state(adev) \
 251                 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
 252
 253 #define amdgpu_dpm_display_configuration_changed(adev) \
 254                 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
 255
 256 #define amdgpu_dpm_print_power_state(adev, ps) \
 257                 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
 258
 259 #define amdgpu_dpm_vblank_too_short(adev) \
 260                 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
 261
 262 #define amdgpu_dpm_enable_bapm(adev, e) \
 263                 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
 264
 265 #define amdgpu_dpm_read_sensor(adev, idx, value, size) \
 266                 ((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))
 267
 268 #define amdgpu_dpm_get_temperature(adev) \
 269                 ((adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle))
 270
 271 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
 272                 ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
 273
 274 #define amdgpu_dpm_get_fan_control_mode(adev) \
 275                 ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
 276
 277 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
 278                 ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
 279
 280 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
 281                 ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
 282
 283 #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
 284                 ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
 285
 286 #define amdgpu_dpm_get_sclk(adev, l) \
 287                 ((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
 288
 289 #define amdgpu_dpm_get_mclk(adev, l)  \
 290                 ((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))
 291
 292 #define amdgpu_dpm_force_performance_level(adev, l) \
 293                 ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
 294
 295 #define amdgpu_dpm_powergate_uvd(adev, g) \
 296                 ((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
 297
 298 #define amdgpu_dpm_powergate_vce(adev, g) \
 299                 ((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
 300
 301 #define amdgpu_dpm_get_current_power_state(adev) \
 302                 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
 303
 304 #define amdgpu_dpm_get_pp_num_states(adev, data) \
 305                 ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
 306
 307 #define amdgpu_dpm_get_pp_table(adev, table) \
 308                 ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
 309
 310 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
 311                 ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
 312
 313 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
 314                 ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
 315
 316 #define amdgpu_dpm_force_clock_level(adev, type, level) \
 317                 ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
 318
 319 #define amdgpu_dpm_get_sclk_od(adev) \
 320                 ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
 321
 322 #define amdgpu_dpm_set_sclk_od(adev, value) \
 323                 ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
 324
 325 #define amdgpu_dpm_get_mclk_od(adev) \
 326                 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
 327
 328 #define amdgpu_dpm_set_mclk_od(adev, value) \
 329                 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
 330
 331 #define amdgpu_dpm_dispatch_task(adev, task_id, input, output)          \
 332                 ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output))
 333
 334 #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
 335                 ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
 336
 337 #define amdgpu_dpm_get_vce_clock_state(adev, i)                         \
 338                 ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
 339
 340 #define amdgpu_dpm_get_performance_level(adev)                          \
 341                 ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
 342
 343 #define amdgpu_dpm_reset_power_profile_state(adev, request) \
 344                 ((adev)->powerplay.pp_funcs->reset_power_profile_state(\
 345                         (adev)->powerplay.pp_handle, request))
 346
 347 #define amdgpu_dpm_get_power_profile_state(adev, query) \
 348                 ((adev)->powerplay.pp_funcs->get_power_profile_state(\
 349                         (adev)->powerplay.pp_handle, query))
 350
 351 #define amdgpu_dpm_set_power_profile_state(adev, request) \
 352                 ((adev)->powerplay.pp_funcs->set_power_profile_state(\
 353                         (adev)->powerplay.pp_handle, request))
 354
 355 #define amdgpu_dpm_switch_power_profile(adev, type) \
 356                 ((adev)->powerplay.pp_funcs->switch_power_profile(\
 357                         (adev)->powerplay.pp_handle, type))
 358
 359 #define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
 360                 ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
 361                         (adev)->powerplay.pp_handle, msg_id))
 362
 363 struct amdgpu_dpm {
 364         struct amdgpu_ps        *ps;
 365         /* number of valid power states */
 366         int                     num_ps;
 367         /* current power state that is active */
 368         struct amdgpu_ps        *current_ps;
 369         /* requested power state */
 370         struct amdgpu_ps        *requested_ps;
 371         /* boot up power state */
 372         struct amdgpu_ps        *boot_ps;
 373         /* default uvd power state */
 374         struct amdgpu_ps        *uvd_ps;
 375         /* vce requirements */
 376         u32                  num_of_vce_states;
 377         struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
 378         enum amd_vce_level vce_level;
 379         enum amd_pm_state_type state;
 380         enum amd_pm_state_type user_state;
 381         enum amd_pm_state_type last_state;
 382         enum amd_pm_state_type last_user_state;
 383         u32                     platform_caps;
 384         u32                     voltage_response_time;
 385         u32                     backbias_response_time;
 386         void                    *priv;
 387         u32                     new_active_crtcs;
 388         int                     new_active_crtc_count;
 389         u32                     current_active_crtcs;
 390         int                     current_active_crtc_count;
 391         struct amdgpu_dpm_dynamic_state dyn_state;
 392         struct amdgpu_dpm_fan fan;
 393         u32 tdp_limit;
 394         u32 near_tdp_limit;
 395         u32 near_tdp_limit_adjusted;
 396         u32 sq_ramping_threshold;
 397         u32 cac_leakage;
 398         u16 tdp_od_limit;
 399         u32 tdp_adjustment;
 400         u16 load_line_slope;
 401         bool power_control;
 402         bool ac_power;
 403         /* special states active */
 404         bool                    thermal_active;
 405         bool                    uvd_active;
 406         bool                    vce_active;
 407         /* thermal handling */
 408         struct amdgpu_dpm_thermal thermal;
 409         /* forced levels */
 410         enum amd_dpm_forced_level forced_level;
 411 };
 412
 413 struct amdgpu_pm {
 414         struct mutex            mutex;
 415         u32                     current_sclk;
 416         u32                     current_mclk;
 417         u32                     default_sclk;
 418         u32                     default_mclk;
 419         struct amdgpu_i2c_chan *i2c_bus;
 420         /* internal thermal controller on rv6xx+ */
 421         enum amdgpu_int_thermal_type int_thermal_type;
 422         struct device           *int_hwmon_dev;
 423         /* fan control parameters */
 424         bool                    no_fan;
 425         u8                      fan_pulses_per_revolution;
 426         u8                      fan_min_rpm;
 427         u8                      fan_max_rpm;
 428         /* dpm */
 429         bool                    dpm_enabled;
 430         bool                    sysfs_initialized;
 431         struct amdgpu_dpm       dpm;
 432         const struct firmware   *fw;    /* SMC firmware */
 433         uint32_t                fw_version;
 434         uint32_t                pcie_gen_mask;
 435         uint32_t                pcie_mlw_mask;
 436         struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
 437 };
 438
 439 #define R600_SSTU_DFLT                               0
 440 #define R600_SST_DFLT                                0x00C8
 441
 442 /* XXX are these ok? */
 443 #define R600_TEMP_RANGE_MIN (90 * 1000)
 444 #define R600_TEMP_RANGE_MAX (120 * 1000)
 445
 446 #define FDO_PWM_MODE_STATIC  1
 447 #define FDO_PWM_MODE_STATIC_RPM 5
 448
 449 enum amdgpu_td {
 450         AMDGPU_TD_AUTO,
 451         AMDGPU_TD_UP,
 452         AMDGPU_TD_DOWN,
 453 };
 454
 455 enum amdgpu_display_watermark {
 456         AMDGPU_DISPLAY_WATERMARK_LOW = 0,
 457         AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
 458 };
 459
 460 enum amdgpu_display_gap
 461 {
 462     AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
 463     AMDGPU_PM_DISPLAY_GAP_VBLANK       = 1,
 464     AMDGPU_PM_DISPLAY_GAP_WATERMARK    = 2,
 465     AMDGPU_PM_DISPLAY_GAP_IGNORE       = 3,
 466 };
 467
 468 void amdgpu_dpm_print_class_info(u32 class, u32 class2);
 469 void amdgpu_dpm_print_cap_info(u32 caps);
 470 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
 471                                 struct amdgpu_ps *rps);
 472 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
 473 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
 474 bool amdgpu_is_uvd_state(u32 class, u32 class2);
 475 void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
 476                               u32 *p, u32 *u);
 477 int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
 478
 479 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
 480
 481 int amdgpu_get_platform_caps(struct amdgpu_device *adev);
 482
 483 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
 484 void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
 485
 486 void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
 487
 488 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
 489                                                  u32 sys_mask,
 490                                                  enum amdgpu_pcie_gen asic_gen,
 491                                                  enum amdgpu_pcie_gen default_gen);
 492
 493 u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
 494                                  u16 asic_lanes,
 495                                  u16 default_lanes);
 496 u8 amdgpu_encode_pci_lane_width(u32 lanes);
 497
 498 struct amd_vce_state*
 499 amdgpu_get_vce_clock_state(void *handle, u32 idx);
 500
 501 #endif