drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30
  31 #define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
  32
  33 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
  34 {
  35         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  36                                                 firmwareinfo);
  37         uint16_t data_offset;
  38
  39         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  40                                           NULL, NULL, &data_offset)) {
  41                 struct atom_firmware_info_v3_1 *firmware_info =
  42                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  43                                                            data_offset);
  44
  45                 if (le32_to_cpu(firmware_info->firmware_capability) &
  46                     ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
  47                         return true;
  48         }
  49         return false;
  50 }
  51
  52 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  53 {
  54         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  55                                                 firmwareinfo);
  56         uint16_t data_offset;
  57
  58         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  59                                           NULL, NULL, &data_offset)) {
  60                 struct atom_firmware_info_v3_1 *firmware_info =
  61                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  62                                                            data_offset);
  63
  64                 adev->bios_scratch_reg_offset =
  65                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
  66         }
  67 }
  68
  69 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
  70 {
  71         struct atom_context *ctx = adev->mode_info.atom_context;
  72         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  73                                                 vram_usagebyfirmware);
  74         uint16_t data_offset;
  75         int usage_bytes = 0;
  76
  77         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
  78                 struct vram_usagebyfirmware_v2_1 *firmware_usage =
  79                         (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
  80
  81                 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
  82                           le32_to_cpu(firmware_usage->start_address_in_kb),
  83                           le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
  84                           le16_to_cpu(firmware_usage->used_by_driver_in_kb));
  85
  86                 usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) * 1024;
  87         }
  88         ctx->scratch_size_bytes = 0;
  89         if (usage_bytes == 0)
  90                 usage_bytes = 20 * 1024;
  91         /* allocate some scratch memory */
  92         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
  93         if (!ctx->scratch)
  94                 return -ENOMEM;
  95         ctx->scratch_size_bytes = usage_bytes;
  96         return 0;
  97 }
  98
  99 union igp_info {
 100         struct atom_integrated_system_info_v1_11 v11;
 101 };
 102
 103 /*
 104  * Return vram width from integrated system info table, if available,
 105  * or 0 if not.
 106  */
 107 int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
 108 {
 109         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 110         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 111                                                 integratedsysteminfo);
 112         u16 data_offset, size;
 113         union igp_info *igp_info;
 114         u8 frev, crev;
 115
 116         /* get any igp specific overrides */
 117         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 118                                    &frev, &crev, &data_offset)) {
 119                 igp_info = (union igp_info *)
 120                         (mode_info->atom_context->bios + data_offset);
 121                 switch (crev) {
 122                 case 11:
 123                         return igp_info->v11.umachannelnumber * 64;
 124                 default:
 125                         return 0;
 126                 }
 127         }
 128
 129         return 0;
 130 }
 131
 132 union firmware_info {
 133         struct atom_firmware_info_v3_1 v31;
 134 };
 135
 136 union smu_info {
 137         struct atom_smu_info_v3_1 v31;
 138 };
 139
 140 union umc_info {
 141         struct atom_umc_info_v3_1 v31;
 142 };
 143
 144 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 145 {
 146         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 147         struct amdgpu_pll *spll = &adev->clock.spll;
 148         struct amdgpu_pll *mpll = &adev->clock.mpll;
 149         uint8_t frev, crev;
 150         uint16_t data_offset;
 151         int ret = -EINVAL, index;
 152
 153         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 154                                             firmwareinfo);
 155         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 156                                    &frev, &crev, &data_offset)) {
 157                 union firmware_info *firmware_info =
 158                         (union firmware_info *)(mode_info->atom_context->bios +
 159                                                 data_offset);
 160
 161                 adev->clock.default_sclk =
 162                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 163                 adev->clock.default_mclk =
 164                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 165
 166                 adev->pm.current_sclk = adev->clock.default_sclk;
 167                 adev->pm.current_mclk = adev->clock.default_mclk;
 168
 169                 /* not technically a clock, but... */
 170                 adev->mode_info.firmware_flags =
 171                         le32_to_cpu(firmware_info->v31.firmware_capability);
 172
 173                 ret = 0;
 174         }
 175
 176         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 177                                             smu_info);
 178         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 179                                    &frev, &crev, &data_offset)) {
 180                 union smu_info *smu_info =
 181                         (union smu_info *)(mode_info->atom_context->bios +
 182                                            data_offset);
 183
 184                 /* system clock */
 185                 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 186
 187                 spll->reference_div = 0;
 188                 spll->min_post_div = 1;
 189                 spll->max_post_div = 1;
 190                 spll->min_ref_div = 2;
 191                 spll->max_ref_div = 0xff;
 192                 spll->min_feedback_div = 4;
 193                 spll->max_feedback_div = 0xff;
 194                 spll->best_vco = 0;
 195
 196                 ret = 0;
 197         }
 198
 199         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 200                                             umc_info);
 201         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 202                                    &frev, &crev, &data_offset)) {
 203                 union umc_info *umc_info =
 204                         (union umc_info *)(mode_info->atom_context->bios +
 205                                            data_offset);
 206
 207                 /* memory clock */
 208                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 209
 210                 mpll->reference_div = 0;
 211                 mpll->min_post_div = 1;
 212                 mpll->max_post_div = 1;
 213                 mpll->min_ref_div = 2;
 214                 mpll->max_ref_div = 0xff;
 215                 mpll->min_feedback_div = 4;
 216                 mpll->max_feedback_div = 0xff;
 217                 mpll->best_vco = 0;
 218
 219                 ret = 0;
 220         }
 221
 222         return ret;
 223 }