drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "amdgpu_amdkfd.h"
  24 #include "amd_shared.h"
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include <linux/module.h>
  29
  30 const struct kgd2kfd_calls *kgd2kfd;
  31
  32 static const unsigned int compute_vmid_bitmap = 0xFF00;
  33
  34 int amdgpu_amdkfd_init(void)
  35 {
  36         int ret;
  37
  38 #ifdef CONFIG_HSA_AMD
  39         ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
  40         if (ret)
  41                 kgd2kfd = NULL;
  42         amdgpu_amdkfd_gpuvm_init_mem_limits();
  43 #else
  44         kgd2kfd = NULL;
  45         ret = -ENOENT;
  46 #endif
  47
  48         return ret;
  49 }
  50
  51 void amdgpu_amdkfd_fini(void)
  52 {
  53         if (kgd2kfd)
  54                 kgd2kfd->exit();
  55 }
  56
  57 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
  58 {
  59         const struct kfd2kgd_calls *kfd2kgd;
  60
  61         if (!kgd2kfd)
  62                 return;
  63
  64         switch (adev->asic_type) {
  65 #ifdef CONFIG_DRM_AMDGPU_CIK
  66         case CHIP_KAVERI:
  67         case CHIP_HAWAII:
  68                 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
  69                 break;
  70 #endif
  71         case CHIP_CARRIZO:
  72         case CHIP_TONGA:
  73         case CHIP_FIJI:
  74         case CHIP_POLARIS10:
  75         case CHIP_POLARIS11:
  76                 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
  77                 break;
  78         case CHIP_VEGA10:
  79         case CHIP_VEGA20:
  80         case CHIP_RAVEN:
  81                 kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
  82                 break;
  83         default:
  84                 dev_info(adev->dev, "kfd not supported on this ASIC\n");
  85                 return;
  86         }
  87
  88         adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
  89                                    adev->pdev, kfd2kgd);
  90 }
  91
  92 /**
  93  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
  94  *                                setup amdkfd
  95  *
  96  * @adev: amdgpu_device pointer
  97  * @aperture_base: output returning doorbell aperture base physical address
  98  * @aperture_size: output returning doorbell aperture size in bytes
  99  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 100  *
 101  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 102  * takes doorbells required for its own rings and reports the setup to amdkfd.
 103  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 104  */
 105 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 106                                          phys_addr_t *aperture_base,
 107                                          size_t *aperture_size,
 108                                          size_t *start_offset)
 109 {
 110         /*
 111          * The first num_doorbells are used by amdgpu.
 112          * amdkfd takes whatever's left in the aperture.
 113          */
 114         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 115                 *aperture_base = adev->doorbell.base;
 116                 *aperture_size = adev->doorbell.size;
 117                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 118         } else {
 119                 *aperture_base = 0;
 120                 *aperture_size = 0;
 121                 *start_offset = 0;
 122         }
 123 }
 124
 125 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 126 {
 127         int i, n;
 128         int last_valid_bit;
 129         if (adev->kfd) {
 130                 struct kgd2kfd_shared_resources gpu_resources = {
 131                         .compute_vmid_bitmap = compute_vmid_bitmap,
 132                         .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
 133                         .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
 134                         .gpuvm_size = min(adev->vm_manager.max_pfn
 135                                           << AMDGPU_GPU_PAGE_SHIFT,
 136                                           AMDGPU_GMC_HOLE_START),
 137                         .drm_render_minor = adev->ddev->render->index
 138                 };
 139
 140                 /* this is going to have a few of the MSBs set that we need to
 141                  * clear */
 142                 bitmap_complement(gpu_resources.queue_bitmap,
 143                                   adev->gfx.mec.queue_bitmap,
 144                                   KGD_MAX_QUEUES);
 145
 146                 /* remove the KIQ bit as well */
 147                 if (adev->gfx.kiq.ring.ready)
 148                         clear_bit(amdgpu_gfx_queue_to_bit(adev,
 149                                                           adev->gfx.kiq.ring.me - 1,
 150                                                           adev->gfx.kiq.ring.pipe,
 151                                                           adev->gfx.kiq.ring.queue),
 152                                   gpu_resources.queue_bitmap);
 153
 154                 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
 155                  * nbits is not compile time constant */
 156                 last_valid_bit = 1 /* only first MEC can have compute queues */
 157                                 * adev->gfx.mec.num_pipe_per_mec
 158                                 * adev->gfx.mec.num_queue_per_pipe;
 159                 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
 160                         clear_bit(i, gpu_resources.queue_bitmap);
 161
 162                 amdgpu_doorbell_get_kfd_info(adev,
 163                                 &gpu_resources.doorbell_physical_address,
 164                                 &gpu_resources.doorbell_aperture_size,
 165                                 &gpu_resources.doorbell_start_offset);
 166
 167                 if (adev->asic_type < CHIP_VEGA10) {
 168                         kgd2kfd->device_init(adev->kfd, &gpu_resources);
 169                         return;
 170                 }
 171
 172                 n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
 173
 174                 for (i = 0; i < n; i += 2) {
 175                         /* On SOC15 the BIF is involved in routing
 176                          * doorbells using the low 12 bits of the
 177                          * address. Communicate the assignments to
 178                          * KFD. KFD uses two doorbell pages per
 179                          * process in case of 64-bit doorbells so we
 180                          * can use each doorbell assignment twice.
 181                          */
 182                         if (adev->asic_type == CHIP_VEGA10) {
 183                                 gpu_resources.sdma_doorbell[0][i] =
 184                                         AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
 185                                 gpu_resources.sdma_doorbell[0][i+1] =
 186                                         AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
 187                                 gpu_resources.sdma_doorbell[1][i] =
 188                                         AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
 189                                 gpu_resources.sdma_doorbell[1][i+1] =
 190                                         AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
 191                         } else {
 192                                 gpu_resources.sdma_doorbell[0][i] =
 193                                         AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
 194                                 gpu_resources.sdma_doorbell[0][i+1] =
 195                                         AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
 196                                 gpu_resources.sdma_doorbell[1][i] =
 197                                         AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
 198                                 gpu_resources.sdma_doorbell[1][i+1] =
 199                                         AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
 200                         }
 201                 }
 202                 /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
 203                  * SDMA, IH and VCN. So don't use them for the CP.
 204                  */
 205                 gpu_resources.reserved_doorbell_mask = 0x1e0;
 206                 gpu_resources.reserved_doorbell_val  = 0x0e0;
 207
 208                 kgd2kfd->device_init(adev->kfd, &gpu_resources);
 209         }
 210 }
 211
 212 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
 213 {
 214         if (adev->kfd) {
 215                 kgd2kfd->device_exit(adev->kfd);
 216                 adev->kfd = NULL;
 217         }
 218 }
 219
 220 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 221                 const void *ih_ring_entry)
 222 {
 223         if (adev->kfd)
 224                 kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
 225 }
 226
 227 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
 228 {
 229         if (adev->kfd)
 230                 kgd2kfd->suspend(adev->kfd);
 231 }
 232
 233 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
 234 {
 235         int r = 0;
 236
 237         if (adev->kfd)
 238                 r = kgd2kfd->resume(adev->kfd);
 239
 240         return r;
 241 }
 242
 243 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
 244 {
 245         int r = 0;
 246
 247         if (adev->kfd)
 248                 r = kgd2kfd->pre_reset(adev->kfd);
 249
 250         return r;
 251 }
 252
 253 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
 254 {
 255         int r = 0;
 256
 257         if (adev->kfd)
 258                 r = kgd2kfd->post_reset(adev->kfd);
 259
 260         return r;
 261 }
 262
 263 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
 264 {
 265         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 266
 267         if (amdgpu_device_should_recover_gpu(adev))
 268                 amdgpu_device_gpu_recover(adev, NULL);
 269 }
 270
 271 int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
 272                         void **mem_obj, uint64_t *gpu_addr,
 273                         void **cpu_ptr, bool mqd_gfx9)
 274 {
 275         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 276         struct amdgpu_bo *bo = NULL;
 277         struct amdgpu_bo_param bp;
 278         int r;
 279         void *cpu_ptr_tmp = NULL;
 280
 281         memset(&bp, 0, sizeof(bp));
 282         bp.size = size;
 283         bp.byte_align = PAGE_SIZE;
 284         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 285         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 286         bp.type = ttm_bo_type_kernel;
 287         bp.resv = NULL;
 288
 289         if (mqd_gfx9)
 290                 bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
 291
 292         r = amdgpu_bo_create(adev, &bp, &bo);
 293         if (r) {
 294                 dev_err(adev->dev,
 295                         "failed to allocate BO for amdkfd (%d)\n", r);
 296                 return r;
 297         }
 298
 299         /* map the buffer */
 300         r = amdgpu_bo_reserve(bo, true);
 301         if (r) {
 302                 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
 303                 goto allocate_mem_reserve_bo_failed;
 304         }
 305
 306         r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
 307         if (r) {
 308                 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
 309                 goto allocate_mem_pin_bo_failed;
 310         }
 311
 312         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 313         if (r) {
 314                 dev_err(adev->dev, "%p bind failed\n", bo);
 315                 goto allocate_mem_kmap_bo_failed;
 316         }
 317
 318         r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
 319         if (r) {
 320                 dev_err(adev->dev,
 321                         "(%d) failed to map bo to kernel for amdkfd\n", r);
 322                 goto allocate_mem_kmap_bo_failed;
 323         }
 324
 325         *mem_obj = bo;
 326         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 327         *cpu_ptr = cpu_ptr_tmp;
 328
 329         amdgpu_bo_unreserve(bo);
 330
 331         return 0;
 332
 333 allocate_mem_kmap_bo_failed:
 334         amdgpu_bo_unpin(bo);
 335 allocate_mem_pin_bo_failed:
 336         amdgpu_bo_unreserve(bo);
 337 allocate_mem_reserve_bo_failed:
 338         amdgpu_bo_unref(&bo);
 339
 340         return r;
 341 }
 342
 343 void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
 344 {
 345         struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
 346
 347         amdgpu_bo_reserve(bo, true);
 348         amdgpu_bo_kunmap(bo);
 349         amdgpu_bo_unpin(bo);
 350         amdgpu_bo_unreserve(bo);
 351         amdgpu_bo_unref(&(bo));
 352 }
 353
 354 void get_local_mem_info(struct kgd_dev *kgd,
 355                         struct kfd_local_mem_info *mem_info)
 356 {
 357         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 358         uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
 359                                              ~((1ULL << 32) - 1);
 360         resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
 361
 362         memset(mem_info, 0, sizeof(*mem_info));
 363         if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
 364                 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
 365                 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
 366                                 adev->gmc.visible_vram_size;
 367         } else {
 368                 mem_info->local_mem_size_public = 0;
 369                 mem_info->local_mem_size_private = adev->gmc.real_vram_size;
 370         }
 371         mem_info->vram_width = adev->gmc.vram_width;
 372
 373         pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
 374                         &adev->gmc.aper_base, &aper_limit,
 375                         mem_info->local_mem_size_public,
 376                         mem_info->local_mem_size_private);
 377
 378         if (amdgpu_sriov_vf(adev))
 379                 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
 380         else if (adev->powerplay.pp_funcs)
 381                 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
 382         else
 383                 mem_info->mem_clk_max = 100;
 384 }
 385
 386 uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
 387 {
 388         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 389
 390         if (adev->gfx.funcs->get_gpu_clock_counter)
 391                 return adev->gfx.funcs->get_gpu_clock_counter(adev);
 392         return 0;
 393 }
 394
 395 uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 396 {
 397         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 398
 399         /* the sclk is in quantas of 10kHz */
 400         if (amdgpu_sriov_vf(adev))
 401                 return adev->clock.default_sclk / 100;
 402         else if (adev->powerplay.pp_funcs)
 403                 return amdgpu_dpm_get_sclk(adev, false) / 100;
 404         else
 405                 return 100;
 406 }
 407
 408 void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
 409 {
 410         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 411         struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
 412
 413         memset(cu_info, 0, sizeof(*cu_info));
 414         if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
 415                 return;
 416
 417         cu_info->cu_active_number = acu_info.number;
 418         cu_info->cu_ao_mask = acu_info.ao_cu_mask;
 419         memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
 420                sizeof(acu_info.bitmap));
 421         cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 422         cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 423         cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 424         cu_info->simd_per_cu = acu_info.simd_per_cu;
 425         cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
 426         cu_info->wave_front_size = acu_info.wave_front_size;
 427         cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
 428         cu_info->lds_size = acu_info.lds_size;
 429 }
 430
 431 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
 432 {
 433         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 434
 435         return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 436 }
 437
 438 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
 439 {
 440         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 441
 442         return adev->gmc.xgmi.hive_id;
 443 }
 444
 445 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 446                                 uint32_t vmid, uint64_t gpu_addr,
 447                                 uint32_t *ib_cmd, uint32_t ib_len)
 448 {
 449         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 450         struct amdgpu_job *job;
 451         struct amdgpu_ib *ib;
 452         struct amdgpu_ring *ring;
 453         struct dma_fence *f = NULL;
 454         int ret;
 455
 456         switch (engine) {
 457         case KGD_ENGINE_MEC1:
 458                 ring = &adev->gfx.compute_ring[0];
 459                 break;
 460         case KGD_ENGINE_SDMA1:
 461                 ring = &adev->sdma.instance[0].ring;
 462                 break;
 463         case KGD_ENGINE_SDMA2:
 464                 ring = &adev->sdma.instance[1].ring;
 465                 break;
 466         default:
 467                 pr_err("Invalid engine in IB submission: %d\n", engine);
 468                 ret = -EINVAL;
 469                 goto err;
 470         }
 471
 472         ret = amdgpu_job_alloc(adev, 1, &job, NULL);
 473         if (ret)
 474                 goto err;
 475
 476         ib = &job->ibs[0];
 477         memset(ib, 0, sizeof(struct amdgpu_ib));
 478
 479         ib->gpu_addr = gpu_addr;
 480         ib->ptr = ib_cmd;
 481         ib->length_dw = ib_len;
 482         /* This works for NO_HWS. TODO: need to handle without knowing VMID */
 483         job->vmid = vmid;
 484
 485         ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
 486         if (ret) {
 487                 DRM_ERROR("amdgpu: failed to schedule IB.\n");
 488                 goto err_ib_sched;
 489         }
 490
 491         ret = dma_fence_wait(f, false);
 492
 493 err_ib_sched:
 494         dma_fence_put(f);
 495         amdgpu_job_free(job);
 496 err:
 497         return ret;
 498 }
 499
 500 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
 501 {
 502         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 503
 504         amdgpu_dpm_switch_power_profile(adev,
 505                                         PP_SMC_POWER_PROFILE_COMPUTE, !idle);
 506 }
 507
 508 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
 509 {
 510         if (adev->kfd) {
 511                 if ((1 << vmid) & compute_vmid_bitmap)
 512                         return true;
 513         }
 514
 515         return false;
 516 }
 517
 518 #ifndef CONFIG_HSA_AMD
 519 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
 520 {
 521         return false;
 522 }
 523
 524 void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
 525 {
 526 }
 527
 528 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
 529                                         struct amdgpu_vm *vm)
 530 {
 531 }
 532
 533 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
 534 {
 535         return NULL;
 536 }
 537
 538 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
 539 {
 540         return 0;
 541 }
 542
 543 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
 544 {
 545         return NULL;
 546 }
 547
 548 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 549 {
 550         return NULL;
 551 }
 552
 553 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
 554 {
 555         return NULL;
 556 }
 557 #endif