drivers/gpio/gpio-omap.c

   1 /*
   2  * Support functions for OMAP GPIO
   3  *
   4  * Copyright (C) 2003-2005 Nokia Corporation
   5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments
   8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/pm.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/gpio/driver.h>
  29 #include <linux/bitops.h>
  30 #include <linux/platform_data/gpio-omap.h>
  31
  32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
  33
  34 struct gpio_regs {
  35         u32 irqenable1;
  36         u32 irqenable2;
  37         u32 wake_en;
  38         u32 ctrl;
  39         u32 oe;
  40         u32 leveldetect0;
  41         u32 leveldetect1;
  42         u32 risingdetect;
  43         u32 fallingdetect;
  44         u32 dataout;
  45         u32 debounce;
  46         u32 debounce_en;
  47 };
  48
  49 struct gpio_bank {
  50         void __iomem *base;
  51         int irq;
  52         u32 non_wakeup_gpios;
  53         u32 enabled_non_wakeup_gpios;
  54         struct gpio_regs context;
  55         u32 saved_datain;
  56         u32 level_mask;
  57         u32 toggle_mask;
  58         raw_spinlock_t lock;
  59         raw_spinlock_t wa_lock;
  60         struct gpio_chip chip;
  61         struct clk *dbck;
  62         struct notifier_block nb;
  63         unsigned int is_suspended:1;
  64         u32 mod_usage;
  65         u32 irq_usage;
  66         u32 dbck_enable_mask;
  67         bool dbck_enabled;
  68         bool is_mpuio;
  69         bool dbck_flag;
  70         bool loses_context;
  71         bool context_valid;
  72         int stride;
  73         u32 width;
  74         int context_loss_count;
  75
  76         void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
  77         int (*get_context_loss_count)(struct device *dev);
  78
  79         struct omap_gpio_reg_offs *regs;
  80 };
  81
  82 #define GPIO_MOD_CTRL_BIT       BIT(0)
  83
  84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
  85 #define LINE_USED(line, offset) (line & (BIT(offset)))
  86
  87 static void omap_gpio_unmask_irq(struct irq_data *d);
  88
  89 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
  90 {
  91         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  92         return gpiochip_get_data(chip);
  93 }
  94
  95 static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
  96 {
  97         u32 val = readl_relaxed(reg);
  98
  99         if (set)
 100                 val |= mask;
 101         else
 102                 val &= ~mask;
 103
 104         writel_relaxed(val, reg);
 105
 106         return val;
 107 }
 108
 109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
 110                                     int is_input)
 111 {
 112         bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
 113                                          BIT(gpio), is_input);
 114 }
 115
 116
 117 /* set data out value using dedicate set/clear register */
 118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
 119                                       int enable)
 120 {
 121         void __iomem *reg = bank->base;
 122         u32 l = BIT(offset);
 123
 124         if (enable) {
 125                 reg += bank->regs->set_dataout;
 126                 bank->context.dataout |= l;
 127         } else {
 128                 reg += bank->regs->clr_dataout;
 129                 bank->context.dataout &= ~l;
 130         }
 131
 132         writel_relaxed(l, reg);
 133 }
 134
 135 /* set data out value using mask register */
 136 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
 137                                        int enable)
 138 {
 139         bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
 140                                               BIT(offset), enable);
 141 }
 142
 143 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
 144 {
 145         if (bank->dbck_enable_mask && !bank->dbck_enabled) {
 146                 clk_enable(bank->dbck);
 147                 bank->dbck_enabled = true;
 148
 149                 writel_relaxed(bank->dbck_enable_mask,
 150                              bank->base + bank->regs->debounce_en);
 151         }
 152 }
 153
 154 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
 155 {
 156         if (bank->dbck_enable_mask && bank->dbck_enabled) {
 157                 /*
 158                  * Disable debounce before cutting it's clock. If debounce is
 159                  * enabled but the clock is not, GPIO module seems to be unable
 160                  * to detect events and generate interrupts at least on OMAP3.
 161                  */
 162                 writel_relaxed(0, bank->base + bank->regs->debounce_en);
 163
 164                 clk_disable(bank->dbck);
 165                 bank->dbck_enabled = false;
 166         }
 167 }
 168
 169 /**
 170  * omap2_set_gpio_debounce - low level gpio debounce time
 171  * @bank: the gpio bank we're acting upon
 172  * @offset: the gpio number on this @bank
 173  * @debounce: debounce time to use
 174  *
 175  * OMAP's debounce time is in 31us steps
 176  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
 177  * so we need to convert and round up to the closest unit.
 178  *
 179  * Return: 0 on success, negative error otherwise.
 180  */
 181 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
 182                                    unsigned debounce)
 183 {
 184         void __iomem            *reg;
 185         u32                     val;
 186         u32                     l;
 187         bool                    enable = !!debounce;
 188
 189         if (!bank->dbck_flag)
 190                 return -ENOTSUPP;
 191
 192         if (enable) {
 193                 debounce = DIV_ROUND_UP(debounce, 31) - 1;
 194                 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
 195                         return -EINVAL;
 196         }
 197
 198         l = BIT(offset);
 199
 200         clk_enable(bank->dbck);
 201         reg = bank->base + bank->regs->debounce;
 202         writel_relaxed(debounce, reg);
 203
 204         val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
 205         bank->dbck_enable_mask = val;
 206
 207         clk_disable(bank->dbck);
 208         /*
 209          * Enable debounce clock per module.
 210          * This call is mandatory because in omap_gpio_request() when
 211          * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
 212          * runtime callbck fails to turn on dbck because dbck_enable_mask
 213          * used within _gpio_dbck_enable() is still not initialized at
 214          * that point. Therefore we have to enable dbck here.
 215          */
 216         omap_gpio_dbck_enable(bank);
 217         if (bank->dbck_enable_mask) {
 218                 bank->context.debounce = debounce;
 219                 bank->context.debounce_en = val;
 220         }
 221
 222         return 0;
 223 }
 224
 225 /**
 226  * omap_clear_gpio_debounce - clear debounce settings for a gpio
 227  * @bank: the gpio bank we're acting upon
 228  * @offset: the gpio number on this @bank
 229  *
 230  * If a gpio is using debounce, then clear the debounce enable bit and if
 231  * this is the only gpio in this bank using debounce, then clear the debounce
 232  * time too. The debounce clock will also be disabled when calling this function
 233  * if this is the only gpio in the bank using debounce.
 234  */
 235 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
 236 {
 237         u32 gpio_bit = BIT(offset);
 238
 239         if (!bank->dbck_flag)
 240                 return;
 241
 242         if (!(bank->dbck_enable_mask & gpio_bit))
 243                 return;
 244
 245         bank->dbck_enable_mask &= ~gpio_bit;
 246         bank->context.debounce_en &= ~gpio_bit;
 247         writel_relaxed(bank->context.debounce_en,
 248                      bank->base + bank->regs->debounce_en);
 249
 250         if (!bank->dbck_enable_mask) {
 251                 bank->context.debounce = 0;
 252                 writel_relaxed(bank->context.debounce, bank->base +
 253                              bank->regs->debounce);
 254                 clk_disable(bank->dbck);
 255                 bank->dbck_enabled = false;
 256         }
 257 }
 258
 259 /*
 260  * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
 261  * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
 262  * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
 263  * are capable waking up the system from off mode.
 264  */
 265 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
 266 {
 267         u32 no_wake = bank->non_wakeup_gpios;
 268
 269         if (no_wake)
 270                 return !!(~no_wake & gpio_mask);
 271
 272         return false;
 273 }
 274
 275 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
 276                                                 unsigned trigger)
 277 {
 278         void __iomem *base = bank->base;
 279         u32 gpio_bit = BIT(gpio);
 280
 281         omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
 282                       trigger & IRQ_TYPE_LEVEL_LOW);
 283         omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
 284                       trigger & IRQ_TYPE_LEVEL_HIGH);
 285
 286         /*
 287          * We need the edge detection enabled for to allow the GPIO block
 288          * to be woken from idle state.  Set the appropriate edge detection
 289          * in addition to the level detection.
 290          */
 291         omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
 292                       trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
 293         omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
 294                       trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
 295
 296         bank->context.leveldetect0 =
 297                         readl_relaxed(bank->base + bank->regs->leveldetect0);
 298         bank->context.leveldetect1 =
 299                         readl_relaxed(bank->base + bank->regs->leveldetect1);
 300         bank->context.risingdetect =
 301                         readl_relaxed(bank->base + bank->regs->risingdetect);
 302         bank->context.fallingdetect =
 303                         readl_relaxed(bank->base + bank->regs->fallingdetect);
 304
 305         bank->level_mask = bank->context.leveldetect0 |
 306                            bank->context.leveldetect1;
 307
 308         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 309                 omap_gpio_rmw(base + bank->regs->wkup_en, gpio_bit, trigger != 0);
 310                 bank->context.wake_en =
 311                         readl_relaxed(bank->base + bank->regs->wkup_en);
 312         }
 313
 314         /* This part needs to be executed always for OMAP{34xx, 44xx} */
 315         if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
 316                 /*
 317                  * Log the edge gpio and manually trigger the IRQ
 318                  * after resume if the input level changes
 319                  * to avoid irq lost during PER RET/OFF mode
 320                  * Applies for omap2 non-wakeup gpio and all omap3 gpios
 321                  */
 322                 if (trigger & IRQ_TYPE_EDGE_BOTH)
 323                         bank->enabled_non_wakeup_gpios |= gpio_bit;
 324                 else
 325                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 326         }
 327 }
 328
 329 /*
 330  * This only applies to chips that can't do both rising and falling edge
 331  * detection at once.  For all other chips, this function is a noop.
 332  */
 333 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 334 {
 335         if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
 336                 void __iomem *reg = bank->base + bank->regs->irqctrl;
 337
 338                 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
 339         }
 340 }
 341
 342 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
 343                                     unsigned trigger)
 344 {
 345         void __iomem *reg = bank->base;
 346         void __iomem *base = bank->base;
 347         u32 l = 0;
 348
 349         if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
 350                 omap_set_gpio_trigger(bank, gpio, trigger);
 351         } else if (bank->regs->irqctrl) {
 352                 reg += bank->regs->irqctrl;
 353
 354                 l = readl_relaxed(reg);
 355                 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 356                         bank->toggle_mask |= BIT(gpio);
 357                 if (trigger & IRQ_TYPE_EDGE_RISING)
 358                         l |= BIT(gpio);
 359                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 360                         l &= ~(BIT(gpio));
 361                 else
 362                         return -EINVAL;
 363
 364                 writel_relaxed(l, reg);
 365         } else if (bank->regs->edgectrl1) {
 366                 if (gpio & 0x08)
 367                         reg += bank->regs->edgectrl2;
 368                 else
 369                         reg += bank->regs->edgectrl1;
 370
 371                 gpio &= 0x07;
 372                 l = readl_relaxed(reg);
 373                 l &= ~(3 << (gpio << 1));
 374                 if (trigger & IRQ_TYPE_EDGE_RISING)
 375                         l |= 2 << (gpio << 1);
 376                 if (trigger & IRQ_TYPE_EDGE_FALLING)
 377                         l |= BIT(gpio << 1);
 378
 379                 /* Enable wake-up during idle for dynamic tick */
 380                 omap_gpio_rmw(base + bank->regs->wkup_en, BIT(gpio), trigger);
 381                 bank->context.wake_en =
 382                         readl_relaxed(bank->base + bank->regs->wkup_en);
 383                 writel_relaxed(l, reg);
 384         }
 385         return 0;
 386 }
 387
 388 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
 389 {
 390         if (bank->regs->pinctrl) {
 391                 void __iomem *reg = bank->base + bank->regs->pinctrl;
 392
 393                 /* Claim the pin for MPU */
 394                 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
 395         }
 396
 397         if (bank->regs->ctrl && !BANK_USED(bank)) {
 398                 void __iomem *reg = bank->base + bank->regs->ctrl;
 399                 u32 ctrl;
 400
 401                 ctrl = readl_relaxed(reg);
 402                 /* Module is enabled, clocks are not gated */
 403                 ctrl &= ~GPIO_MOD_CTRL_BIT;
 404                 writel_relaxed(ctrl, reg);
 405                 bank->context.ctrl = ctrl;
 406         }
 407 }
 408
 409 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
 410 {
 411         void __iomem *base = bank->base;
 412
 413         if (bank->regs->wkup_en &&
 414             !LINE_USED(bank->mod_usage, offset) &&
 415             !LINE_USED(bank->irq_usage, offset)) {
 416                 /* Disable wake-up during idle for dynamic tick */
 417                 omap_gpio_rmw(base + bank->regs->wkup_en, BIT(offset), 0);
 418                 bank->context.wake_en =
 419                         readl_relaxed(bank->base + bank->regs->wkup_en);
 420         }
 421
 422         if (bank->regs->ctrl && !BANK_USED(bank)) {
 423                 void __iomem *reg = bank->base + bank->regs->ctrl;
 424                 u32 ctrl;
 425
 426                 ctrl = readl_relaxed(reg);
 427                 /* Module is disabled, clocks are gated */
 428                 ctrl |= GPIO_MOD_CTRL_BIT;
 429                 writel_relaxed(ctrl, reg);
 430                 bank->context.ctrl = ctrl;
 431         }
 432 }
 433
 434 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
 435 {
 436         void __iomem *reg = bank->base + bank->regs->direction;
 437
 438         return readl_relaxed(reg) & BIT(offset);
 439 }
 440
 441 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
 442 {
 443         if (!LINE_USED(bank->mod_usage, offset)) {
 444                 omap_enable_gpio_module(bank, offset);
 445                 omap_set_gpio_direction(bank, offset, 1);
 446         }
 447         bank->irq_usage |= BIT(offset);
 448 }
 449
 450 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
 451 {
 452         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 453         int retval;
 454         unsigned long flags;
 455         unsigned offset = d->hwirq;
 456
 457         if (type & ~IRQ_TYPE_SENSE_MASK)
 458                 return -EINVAL;
 459
 460         if (!bank->regs->leveldetect0 &&
 461                 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 462                 return -EINVAL;
 463
 464         raw_spin_lock_irqsave(&bank->lock, flags);
 465         retval = omap_set_gpio_triggering(bank, offset, type);
 466         if (retval) {
 467                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 468                 goto error;
 469         }
 470         omap_gpio_init_irq(bank, offset);
 471         if (!omap_gpio_is_input(bank, offset)) {
 472                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 473                 retval = -EINVAL;
 474                 goto error;
 475         }
 476         raw_spin_unlock_irqrestore(&bank->lock, flags);
 477
 478         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 479                 irq_set_handler_locked(d, handle_level_irq);
 480         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 481                 /*
 482                  * Edge IRQs are already cleared/acked in irq_handler and
 483                  * not need to be masked, as result handle_edge_irq()
 484                  * logic is excessed here and may cause lose of interrupts.
 485                  * So just use handle_simple_irq.
 486                  */
 487                 irq_set_handler_locked(d, handle_simple_irq);
 488
 489         return 0;
 490
 491 error:
 492         return retval;
 493 }
 494
 495 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 496 {
 497         void __iomem *reg = bank->base;
 498
 499         reg += bank->regs->irqstatus;
 500         writel_relaxed(gpio_mask, reg);
 501
 502         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 503         if (bank->regs->irqstatus2) {
 504                 reg = bank->base + bank->regs->irqstatus2;
 505                 writel_relaxed(gpio_mask, reg);
 506         }
 507
 508         /* Flush posted write for the irq status to avoid spurious interrupts */
 509         readl_relaxed(reg);
 510 }
 511
 512 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
 513                                              unsigned offset)
 514 {
 515         omap_clear_gpio_irqbank(bank, BIT(offset));
 516 }
 517
 518 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
 519 {
 520         void __iomem *reg = bank->base;
 521         u32 l;
 522         u32 mask = (BIT(bank->width)) - 1;
 523
 524         reg += bank->regs->irqenable;
 525         l = readl_relaxed(reg);
 526         if (bank->regs->irqenable_inv)
 527                 l = ~l;
 528         l &= mask;
 529         return l;
 530 }
 531
 532 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 533 {
 534         void __iomem *reg = bank->base;
 535         u32 l;
 536
 537         if (bank->regs->set_irqenable) {
 538                 reg += bank->regs->set_irqenable;
 539                 l = gpio_mask;
 540                 bank->context.irqenable1 |= gpio_mask;
 541         } else {
 542                 reg += bank->regs->irqenable;
 543                 l = readl_relaxed(reg);
 544                 if (bank->regs->irqenable_inv)
 545                         l &= ~gpio_mask;
 546                 else
 547                         l |= gpio_mask;
 548                 bank->context.irqenable1 = l;
 549         }
 550
 551         writel_relaxed(l, reg);
 552 }
 553
 554 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 555 {
 556         void __iomem *reg = bank->base;
 557         u32 l;
 558
 559         if (bank->regs->clr_irqenable) {
 560                 reg += bank->regs->clr_irqenable;
 561                 l = gpio_mask;
 562                 bank->context.irqenable1 &= ~gpio_mask;
 563         } else {
 564                 reg += bank->regs->irqenable;
 565                 l = readl_relaxed(reg);
 566                 if (bank->regs->irqenable_inv)
 567                         l |= gpio_mask;
 568                 else
 569                         l &= ~gpio_mask;
 570                 bank->context.irqenable1 = l;
 571         }
 572
 573         writel_relaxed(l, reg);
 574 }
 575
 576 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
 577                                            unsigned offset, int enable)
 578 {
 579         if (enable)
 580                 omap_enable_gpio_irqbank(bank, BIT(offset));
 581         else
 582                 omap_disable_gpio_irqbank(bank, BIT(offset));
 583 }
 584
 585 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 586 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 587 {
 588         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 589
 590         return irq_set_irq_wake(bank->irq, enable);
 591 }
 592
 593 /*
 594  * We need to unmask the GPIO bank interrupt as soon as possible to
 595  * avoid missing GPIO interrupts for other lines in the bank.
 596  * Then we need to mask-read-clear-unmask the triggered GPIO lines
 597  * in the bank to avoid missing nested interrupts for a GPIO line.
 598  * If we wait to unmask individual GPIO lines in the bank after the
 599  * line's interrupt handler has been run, we may miss some nested
 600  * interrupts.
 601  */
 602 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
 603 {
 604         void __iomem *isr_reg = NULL;
 605         u32 enabled, isr, edge;
 606         unsigned int bit;
 607         struct gpio_bank *bank = gpiobank;
 608         unsigned long wa_lock_flags;
 609         unsigned long lock_flags;
 610
 611         isr_reg = bank->base + bank->regs->irqstatus;
 612         if (WARN_ON(!isr_reg))
 613                 goto exit;
 614
 615         if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
 616                       "gpio irq%i while runtime suspended?\n", irq))
 617                 return IRQ_NONE;
 618
 619         while (1) {
 620                 raw_spin_lock_irqsave(&bank->lock, lock_flags);
 621
 622                 enabled = omap_get_gpio_irqbank_mask(bank);
 623                 isr = readl_relaxed(isr_reg) & enabled;
 624
 625                 /*
 626                  * Clear edge sensitive interrupts before calling handler(s)
 627                  * so subsequent edge transitions are not missed while the
 628                  * handlers are running.
 629                  */
 630                 edge = isr & ~bank->level_mask;
 631                 if (edge)
 632                         omap_clear_gpio_irqbank(bank, edge);
 633
 634                 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 635
 636                 if (!isr)
 637                         break;
 638
 639                 while (isr) {
 640                         bit = __ffs(isr);
 641                         isr &= ~(BIT(bit));
 642
 643                         raw_spin_lock_irqsave(&bank->lock, lock_flags);
 644                         /*
 645                          * Some chips can't respond to both rising and falling
 646                          * at the same time.  If this irq was requested with
 647                          * both flags, we need to flip the ICR data for the IRQ
 648                          * to respond to the IRQ for the opposite direction.
 649                          * This will be indicated in the bank toggle_mask.
 650                          */
 651                         if (bank->toggle_mask & (BIT(bit)))
 652                                 omap_toggle_gpio_edge_triggering(bank, bit);
 653
 654                         raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 655
 656                         raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
 657
 658                         generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
 659                                                             bit));
 660
 661                         raw_spin_unlock_irqrestore(&bank->wa_lock,
 662                                                    wa_lock_flags);
 663                 }
 664         }
 665 exit:
 666         return IRQ_HANDLED;
 667 }
 668
 669 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
 670 {
 671         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 672         unsigned long flags;
 673         unsigned offset = d->hwirq;
 674
 675         raw_spin_lock_irqsave(&bank->lock, flags);
 676
 677         if (!LINE_USED(bank->mod_usage, offset))
 678                 omap_set_gpio_direction(bank, offset, 1);
 679         else if (!omap_gpio_is_input(bank, offset))
 680                 goto err;
 681         omap_enable_gpio_module(bank, offset);
 682         bank->irq_usage |= BIT(offset);
 683
 684         raw_spin_unlock_irqrestore(&bank->lock, flags);
 685         omap_gpio_unmask_irq(d);
 686
 687         return 0;
 688 err:
 689         raw_spin_unlock_irqrestore(&bank->lock, flags);
 690         return -EINVAL;
 691 }
 692
 693 static void omap_gpio_irq_shutdown(struct irq_data *d)
 694 {
 695         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 696         unsigned long flags;
 697         unsigned offset = d->hwirq;
 698
 699         raw_spin_lock_irqsave(&bank->lock, flags);
 700         bank->irq_usage &= ~(BIT(offset));
 701         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 702         omap_clear_gpio_irqstatus(bank, offset);
 703         omap_set_gpio_irqenable(bank, offset, 0);
 704         if (!LINE_USED(bank->mod_usage, offset))
 705                 omap_clear_gpio_debounce(bank, offset);
 706         omap_disable_gpio_module(bank, offset);
 707         raw_spin_unlock_irqrestore(&bank->lock, flags);
 708 }
 709
 710 static void omap_gpio_irq_bus_lock(struct irq_data *data)
 711 {
 712         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 713
 714         pm_runtime_get_sync(bank->chip.parent);
 715 }
 716
 717 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
 718 {
 719         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 720
 721         pm_runtime_put(bank->chip.parent);
 722 }
 723
 724 static void omap_gpio_mask_irq(struct irq_data *d)
 725 {
 726         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 727         unsigned offset = d->hwirq;
 728         unsigned long flags;
 729
 730         raw_spin_lock_irqsave(&bank->lock, flags);
 731         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 732         omap_set_gpio_irqenable(bank, offset, 0);
 733         raw_spin_unlock_irqrestore(&bank->lock, flags);
 734 }
 735
 736 static void omap_gpio_unmask_irq(struct irq_data *d)
 737 {
 738         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 739         unsigned offset = d->hwirq;
 740         u32 trigger = irqd_get_trigger_type(d);
 741         unsigned long flags;
 742
 743         raw_spin_lock_irqsave(&bank->lock, flags);
 744         omap_set_gpio_irqenable(bank, offset, 1);
 745
 746         /*
 747          * For level-triggered GPIOs, clearing must be done after the source
 748          * is cleared, thus after the handler has run. OMAP4 needs this done
 749          * after enabing the interrupt to clear the wakeup status.
 750          */
 751         if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
 752             trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 753                 omap_clear_gpio_irqstatus(bank, offset);
 754
 755         if (trigger)
 756                 omap_set_gpio_triggering(bank, offset, trigger);
 757
 758         raw_spin_unlock_irqrestore(&bank->lock, flags);
 759 }
 760
 761 /*---------------------------------------------------------------------*/
 762
 763 static int omap_mpuio_suspend_noirq(struct device *dev)
 764 {
 765         struct gpio_bank        *bank = dev_get_drvdata(dev);
 766         void __iomem            *mask_reg = bank->base +
 767                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 768         unsigned long           flags;
 769
 770         raw_spin_lock_irqsave(&bank->lock, flags);
 771         writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
 772         raw_spin_unlock_irqrestore(&bank->lock, flags);
 773
 774         return 0;
 775 }
 776
 777 static int omap_mpuio_resume_noirq(struct device *dev)
 778 {
 779         struct gpio_bank        *bank = dev_get_drvdata(dev);
 780         void __iomem            *mask_reg = bank->base +
 781                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 782         unsigned long           flags;
 783
 784         raw_spin_lock_irqsave(&bank->lock, flags);
 785         writel_relaxed(bank->context.wake_en, mask_reg);
 786         raw_spin_unlock_irqrestore(&bank->lock, flags);
 787
 788         return 0;
 789 }
 790
 791 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 792         .suspend_noirq = omap_mpuio_suspend_noirq,
 793         .resume_noirq = omap_mpuio_resume_noirq,
 794 };
 795
 796 /* use platform_driver for this. */
 797 static struct platform_driver omap_mpuio_driver = {
 798         .driver         = {
 799                 .name   = "mpuio",
 800                 .pm     = &omap_mpuio_dev_pm_ops,
 801         },
 802 };
 803
 804 static struct platform_device omap_mpuio_device = {
 805         .name           = "mpuio",
 806         .id             = -1,
 807         .dev = {
 808                 .driver = &omap_mpuio_driver.driver,
 809         }
 810         /* could list the /proc/iomem resources */
 811 };
 812
 813 static inline void omap_mpuio_init(struct gpio_bank *bank)
 814 {
 815         platform_set_drvdata(&omap_mpuio_device, bank);
 816
 817         if (platform_driver_register(&omap_mpuio_driver) == 0)
 818                 (void) platform_device_register(&omap_mpuio_device);
 819 }
 820
 821 /*---------------------------------------------------------------------*/
 822
 823 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 824 {
 825         struct gpio_bank *bank = gpiochip_get_data(chip);
 826         unsigned long flags;
 827
 828         pm_runtime_get_sync(chip->parent);
 829
 830         raw_spin_lock_irqsave(&bank->lock, flags);
 831         omap_enable_gpio_module(bank, offset);
 832         bank->mod_usage |= BIT(offset);
 833         raw_spin_unlock_irqrestore(&bank->lock, flags);
 834
 835         return 0;
 836 }
 837
 838 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 839 {
 840         struct gpio_bank *bank = gpiochip_get_data(chip);
 841         unsigned long flags;
 842
 843         raw_spin_lock_irqsave(&bank->lock, flags);
 844         bank->mod_usage &= ~(BIT(offset));
 845         if (!LINE_USED(bank->irq_usage, offset)) {
 846                 omap_set_gpio_direction(bank, offset, 1);
 847                 omap_clear_gpio_debounce(bank, offset);
 848         }
 849         omap_disable_gpio_module(bank, offset);
 850         raw_spin_unlock_irqrestore(&bank->lock, flags);
 851
 852         pm_runtime_put(chip->parent);
 853 }
 854
 855 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 856 {
 857         struct gpio_bank *bank = gpiochip_get_data(chip);
 858
 859         return !!(readl_relaxed(bank->base + bank->regs->direction) &
 860                   BIT(offset));
 861 }
 862
 863 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
 864 {
 865         struct gpio_bank *bank;
 866         unsigned long flags;
 867
 868         bank = gpiochip_get_data(chip);
 869         raw_spin_lock_irqsave(&bank->lock, flags);
 870         omap_set_gpio_direction(bank, offset, 1);
 871         raw_spin_unlock_irqrestore(&bank->lock, flags);
 872         return 0;
 873 }
 874
 875 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
 876 {
 877         struct gpio_bank *bank = gpiochip_get_data(chip);
 878         void __iomem *reg;
 879
 880         if (omap_gpio_is_input(bank, offset))
 881                 reg = bank->base + bank->regs->datain;
 882         else
 883                 reg = bank->base + bank->regs->dataout;
 884
 885         return (readl_relaxed(reg) & BIT(offset)) != 0;
 886 }
 887
 888 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
 889 {
 890         struct gpio_bank *bank;
 891         unsigned long flags;
 892
 893         bank = gpiochip_get_data(chip);
 894         raw_spin_lock_irqsave(&bank->lock, flags);
 895         bank->set_dataout(bank, offset, value);
 896         omap_set_gpio_direction(bank, offset, 0);
 897         raw_spin_unlock_irqrestore(&bank->lock, flags);
 898         return 0;
 899 }
 900
 901 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
 902                                   unsigned long *bits)
 903 {
 904         struct gpio_bank *bank = gpiochip_get_data(chip);
 905         void __iomem *base = bank->base;
 906         u32 direction, m, val = 0;
 907
 908         direction = readl_relaxed(base + bank->regs->direction);
 909
 910         m = direction & *mask;
 911         if (m)
 912                 val |= readl_relaxed(base + bank->regs->datain) & m;
 913
 914         m = ~direction & *mask;
 915         if (m)
 916                 val |= readl_relaxed(base + bank->regs->dataout) & m;
 917
 918         *bits = val;
 919
 920         return 0;
 921 }
 922
 923 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
 924                               unsigned debounce)
 925 {
 926         struct gpio_bank *bank;
 927         unsigned long flags;
 928         int ret;
 929
 930         bank = gpiochip_get_data(chip);
 931
 932         raw_spin_lock_irqsave(&bank->lock, flags);
 933         ret = omap2_set_gpio_debounce(bank, offset, debounce);
 934         raw_spin_unlock_irqrestore(&bank->lock, flags);
 935
 936         if (ret)
 937                 dev_info(chip->parent,
 938                          "Could not set line %u debounce to %u microseconds (%d)",
 939                          offset, debounce, ret);
 940
 941         return ret;
 942 }
 943
 944 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
 945                                 unsigned long config)
 946 {
 947         u32 debounce;
 948
 949         if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
 950                 return -ENOTSUPP;
 951
 952         debounce = pinconf_to_config_argument(config);
 953         return omap_gpio_debounce(chip, offset, debounce);
 954 }
 955
 956 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 957 {
 958         struct gpio_bank *bank;
 959         unsigned long flags;
 960
 961         bank = gpiochip_get_data(chip);
 962         raw_spin_lock_irqsave(&bank->lock, flags);
 963         bank->set_dataout(bank, offset, value);
 964         raw_spin_unlock_irqrestore(&bank->lock, flags);
 965 }
 966
 967 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
 968                                    unsigned long *bits)
 969 {
 970         struct gpio_bank *bank = gpiochip_get_data(chip);
 971         void __iomem *reg = bank->base + bank->regs->dataout;
 972         unsigned long flags;
 973         u32 l;
 974
 975         raw_spin_lock_irqsave(&bank->lock, flags);
 976         l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
 977         writel_relaxed(l, reg);
 978         bank->context.dataout = l;
 979         raw_spin_unlock_irqrestore(&bank->lock, flags);
 980 }
 981
 982 /*---------------------------------------------------------------------*/
 983
 984 static void omap_gpio_show_rev(struct gpio_bank *bank)
 985 {
 986         static bool called;
 987         u32 rev;
 988
 989         if (called || bank->regs->revision == USHRT_MAX)
 990                 return;
 991
 992         rev = readw_relaxed(bank->base + bank->regs->revision);
 993         pr_info("OMAP GPIO hardware version %d.%d\n",
 994                 (rev >> 4) & 0x0f, rev & 0x0f);
 995
 996         called = true;
 997 }
 998
 999 static void omap_gpio_mod_init(struct gpio_bank *bank)
1000 {
1001         void __iomem *base = bank->base;
1002         u32 l = 0xffffffff;
1003
1004         if (bank->width == 16)
1005                 l = 0xffff;
1006
1007         if (bank->is_mpuio) {
1008                 writel_relaxed(l, bank->base + bank->regs->irqenable);
1009                 return;
1010         }
1011
1012         omap_gpio_rmw(base + bank->regs->irqenable, l,
1013                       bank->regs->irqenable_inv);
1014         omap_gpio_rmw(base + bank->regs->irqstatus, l,
1015                       !bank->regs->irqenable_inv);
1016         if (bank->regs->debounce_en)
1017                 writel_relaxed(0, base + bank->regs->debounce_en);
1018
1019         /* Save OE default value (0xffffffff) in the context */
1020         bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1021          /* Initialize interface clk ungated, module enabled */
1022         if (bank->regs->ctrl)
1023                 writel_relaxed(0, base + bank->regs->ctrl);
1024 }
1025
1026 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1027 {
1028         struct gpio_irq_chip *irq;
1029         static int gpio;
1030         const char *label;
1031         int irq_base = 0;
1032         int ret;
1033
1034         /*
1035          * REVISIT eventually switch from OMAP-specific gpio structs
1036          * over to the generic ones
1037          */
1038         bank->chip.request = omap_gpio_request;
1039         bank->chip.free = omap_gpio_free;
1040         bank->chip.get_direction = omap_gpio_get_direction;
1041         bank->chip.direction_input = omap_gpio_input;
1042         bank->chip.get = omap_gpio_get;
1043         bank->chip.get_multiple = omap_gpio_get_multiple;
1044         bank->chip.direction_output = omap_gpio_output;
1045         bank->chip.set_config = omap_gpio_set_config;
1046         bank->chip.set = omap_gpio_set;
1047         bank->chip.set_multiple = omap_gpio_set_multiple;
1048         if (bank->is_mpuio) {
1049                 bank->chip.label = "mpuio";
1050                 if (bank->regs->wkup_en)
1051                         bank->chip.parent = &omap_mpuio_device.dev;
1052                 bank->chip.base = OMAP_MPUIO(0);
1053         } else {
1054                 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1055                                        gpio, gpio + bank->width - 1);
1056                 if (!label)
1057                         return -ENOMEM;
1058                 bank->chip.label = label;
1059                 bank->chip.base = gpio;
1060         }
1061         bank->chip.ngpio = bank->width;
1062
1063 #ifdef CONFIG_ARCH_OMAP1
1064         /*
1065          * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1066          * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1067          */
1068         irq_base = devm_irq_alloc_descs(bank->chip.parent,
1069                                         -1, 0, bank->width, 0);
1070         if (irq_base < 0) {
1071                 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1072                 return -ENODEV;
1073         }
1074 #endif
1075
1076         /* MPUIO is a bit different, reading IRQ status clears it */
1077         if (bank->is_mpuio && !bank->regs->wkup_en)
1078                 irqc->irq_set_wake = NULL;
1079
1080         irq = &bank->chip.irq;
1081         irq->chip = irqc;
1082         irq->handler = handle_bad_irq;
1083         irq->default_type = IRQ_TYPE_NONE;
1084         irq->num_parents = 1;
1085         irq->parents = &bank->irq;
1086         irq->first = irq_base;
1087
1088         ret = gpiochip_add_data(&bank->chip, bank);
1089         if (ret) {
1090                 dev_err(bank->chip.parent,
1091                         "Could not register gpio chip %d\n", ret);
1092                 return ret;
1093         }
1094
1095         ret = devm_request_irq(bank->chip.parent, bank->irq,
1096                                omap_gpio_irq_handler,
1097                                0, dev_name(bank->chip.parent), bank);
1098         if (ret)
1099                 gpiochip_remove(&bank->chip);
1100
1101         if (!bank->is_mpuio)
1102                 gpio += bank->width;
1103
1104         return ret;
1105 }
1106
1107 static void omap_gpio_init_context(struct gpio_bank *p)
1108 {
1109         struct omap_gpio_reg_offs *regs = p->regs;
1110         void __iomem *base = p->base;
1111
1112         p->context.ctrl         = readl_relaxed(base + regs->ctrl);
1113         p->context.oe           = readl_relaxed(base + regs->direction);
1114         p->context.wake_en      = readl_relaxed(base + regs->wkup_en);
1115         p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1116         p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1117         p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1118         p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1119         p->context.irqenable1   = readl_relaxed(base + regs->irqenable);
1120         p->context.irqenable2   = readl_relaxed(base + regs->irqenable2);
1121
1122         if (regs->set_dataout && p->regs->clr_dataout)
1123                 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1124         else
1125                 p->context.dataout = readl_relaxed(base + regs->dataout);
1126
1127         p->context_valid = true;
1128 }
1129
1130 static void omap_gpio_restore_context(struct gpio_bank *bank)
1131 {
1132         writel_relaxed(bank->context.wake_en,
1133                                 bank->base + bank->regs->wkup_en);
1134         writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1135         writel_relaxed(bank->context.leveldetect0,
1136                                 bank->base + bank->regs->leveldetect0);
1137         writel_relaxed(bank->context.leveldetect1,
1138                                 bank->base + bank->regs->leveldetect1);
1139         writel_relaxed(bank->context.risingdetect,
1140                                 bank->base + bank->regs->risingdetect);
1141         writel_relaxed(bank->context.fallingdetect,
1142                                 bank->base + bank->regs->fallingdetect);
1143         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1144                 writel_relaxed(bank->context.dataout,
1145                                 bank->base + bank->regs->set_dataout);
1146         else
1147                 writel_relaxed(bank->context.dataout,
1148                                 bank->base + bank->regs->dataout);
1149         writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1150
1151         if (bank->dbck_enable_mask) {
1152                 writel_relaxed(bank->context.debounce, bank->base +
1153                                         bank->regs->debounce);
1154                 writel_relaxed(bank->context.debounce_en,
1155                                         bank->base + bank->regs->debounce_en);
1156         }
1157
1158         writel_relaxed(bank->context.irqenable1,
1159                                 bank->base + bank->regs->irqenable);
1160         writel_relaxed(bank->context.irqenable2,
1161                                 bank->base + bank->regs->irqenable2);
1162 }
1163
1164 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1165 {
1166         struct device *dev = bank->chip.parent;
1167         void __iomem *base = bank->base;
1168         u32 nowake;
1169
1170         bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1171
1172         if (!bank->enabled_non_wakeup_gpios)
1173                 goto update_gpio_context_count;
1174
1175         if (!may_lose_context)
1176                 goto update_gpio_context_count;
1177
1178         /*
1179          * If going to OFF, remove triggering for all wkup domain
1180          * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1181          * generated.  See OMAP2420 Errata item 1.101.
1182          */
1183         if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1184                 nowake = bank->enabled_non_wakeup_gpios;
1185                 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1186                 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1187         }
1188
1189 update_gpio_context_count:
1190         if (bank->get_context_loss_count)
1191                 bank->context_loss_count =
1192                                 bank->get_context_loss_count(dev);
1193
1194         omap_gpio_dbck_disable(bank);
1195 }
1196
1197 static void omap_gpio_unidle(struct gpio_bank *bank)
1198 {
1199         struct device *dev = bank->chip.parent;
1200         u32 l = 0, gen, gen0, gen1;
1201         int c;
1202
1203         /*
1204          * On the first resume during the probe, the context has not
1205          * been initialised and so initialise it now. Also initialise
1206          * the context loss count.
1207          */
1208         if (bank->loses_context && !bank->context_valid) {
1209                 omap_gpio_init_context(bank);
1210
1211                 if (bank->get_context_loss_count)
1212                         bank->context_loss_count =
1213                                 bank->get_context_loss_count(dev);
1214         }
1215
1216         omap_gpio_dbck_enable(bank);
1217
1218         if (bank->loses_context) {
1219                 if (!bank->get_context_loss_count) {
1220                         omap_gpio_restore_context(bank);
1221                 } else {
1222                         c = bank->get_context_loss_count(dev);
1223                         if (c != bank->context_loss_count) {
1224                                 omap_gpio_restore_context(bank);
1225                         } else {
1226                                 return;
1227                         }
1228                 }
1229         } else {
1230                 /* Restore changes done for OMAP2420 errata 1.101 */
1231                 writel_relaxed(bank->context.fallingdetect,
1232                                bank->base + bank->regs->fallingdetect);
1233                 writel_relaxed(bank->context.risingdetect,
1234                                bank->base + bank->regs->risingdetect);
1235         }
1236
1237         l = readl_relaxed(bank->base + bank->regs->datain);
1238
1239         /*
1240          * Check if any of the non-wakeup interrupt GPIOs have changed
1241          * state.  If so, generate an IRQ by software.  This is
1242          * horribly racy, but it's the best we can do to work around
1243          * this silicon bug.
1244          */
1245         l ^= bank->saved_datain;
1246         l &= bank->enabled_non_wakeup_gpios;
1247
1248         /*
1249          * No need to generate IRQs for the rising edge for gpio IRQs
1250          * configured with falling edge only; and vice versa.
1251          */
1252         gen0 = l & bank->context.fallingdetect;
1253         gen0 &= bank->saved_datain;
1254
1255         gen1 = l & bank->context.risingdetect;
1256         gen1 &= ~(bank->saved_datain);
1257
1258         /* FIXME: Consider GPIO IRQs with level detections properly! */
1259         gen = l & (~(bank->context.fallingdetect) &
1260                                          ~(bank->context.risingdetect));
1261         /* Consider all GPIO IRQs needed to be updated */
1262         gen |= gen0 | gen1;
1263
1264         if (gen) {
1265                 u32 old0, old1;
1266
1267                 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1268                 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1269
1270                 if (!bank->regs->irqstatus_raw0) {
1271                         writel_relaxed(old0 | gen, bank->base +
1272                                                 bank->regs->leveldetect0);
1273                         writel_relaxed(old1 | gen, bank->base +
1274                                                 bank->regs->leveldetect1);
1275                 }
1276
1277                 if (bank->regs->irqstatus_raw0) {
1278                         writel_relaxed(old0 | l, bank->base +
1279                                                 bank->regs->leveldetect0);
1280                         writel_relaxed(old1 | l, bank->base +
1281                                                 bank->regs->leveldetect1);
1282                 }
1283                 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1284                 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1285         }
1286 }
1287
1288 static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1289                                   unsigned long cmd, void *v)
1290 {
1291         struct gpio_bank *bank;
1292         unsigned long flags;
1293
1294         bank = container_of(nb, struct gpio_bank, nb);
1295
1296         raw_spin_lock_irqsave(&bank->lock, flags);
1297         switch (cmd) {
1298         case CPU_CLUSTER_PM_ENTER:
1299                 if (bank->is_suspended)
1300                         break;
1301                 omap_gpio_idle(bank, true);
1302                 break;
1303         case CPU_CLUSTER_PM_ENTER_FAILED:
1304         case CPU_CLUSTER_PM_EXIT:
1305                 if (bank->is_suspended)
1306                         break;
1307                 omap_gpio_unidle(bank);
1308                 break;
1309         }
1310         raw_spin_unlock_irqrestore(&bank->lock, flags);
1311
1312         return NOTIFY_OK;
1313 }
1314
1315 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1316         .revision =             OMAP24XX_GPIO_REVISION,
1317         .direction =            OMAP24XX_GPIO_OE,
1318         .datain =               OMAP24XX_GPIO_DATAIN,
1319         .dataout =              OMAP24XX_GPIO_DATAOUT,
1320         .set_dataout =          OMAP24XX_GPIO_SETDATAOUT,
1321         .clr_dataout =          OMAP24XX_GPIO_CLEARDATAOUT,
1322         .irqstatus =            OMAP24XX_GPIO_IRQSTATUS1,
1323         .irqstatus2 =           OMAP24XX_GPIO_IRQSTATUS2,
1324         .irqenable =            OMAP24XX_GPIO_IRQENABLE1,
1325         .irqenable2 =           OMAP24XX_GPIO_IRQENABLE2,
1326         .set_irqenable =        OMAP24XX_GPIO_SETIRQENABLE1,
1327         .clr_irqenable =        OMAP24XX_GPIO_CLEARIRQENABLE1,
1328         .debounce =             OMAP24XX_GPIO_DEBOUNCE_VAL,
1329         .debounce_en =          OMAP24XX_GPIO_DEBOUNCE_EN,
1330         .ctrl =                 OMAP24XX_GPIO_CTRL,
1331         .wkup_en =              OMAP24XX_GPIO_WAKE_EN,
1332         .leveldetect0 =         OMAP24XX_GPIO_LEVELDETECT0,
1333         .leveldetect1 =         OMAP24XX_GPIO_LEVELDETECT1,
1334         .risingdetect =         OMAP24XX_GPIO_RISINGDETECT,
1335         .fallingdetect =        OMAP24XX_GPIO_FALLINGDETECT,
1336 };
1337
1338 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1339         .revision =             OMAP4_GPIO_REVISION,
1340         .direction =            OMAP4_GPIO_OE,
1341         .datain =               OMAP4_GPIO_DATAIN,
1342         .dataout =              OMAP4_GPIO_DATAOUT,
1343         .set_dataout =          OMAP4_GPIO_SETDATAOUT,
1344         .clr_dataout =          OMAP4_GPIO_CLEARDATAOUT,
1345         .irqstatus =            OMAP4_GPIO_IRQSTATUS0,
1346         .irqstatus2 =           OMAP4_GPIO_IRQSTATUS1,
1347         .irqstatus_raw0 =       OMAP4_GPIO_IRQSTATUSRAW0,
1348         .irqstatus_raw1 =       OMAP4_GPIO_IRQSTATUSRAW1,
1349         .irqenable =            OMAP4_GPIO_IRQSTATUSSET0,
1350         .irqenable2 =           OMAP4_GPIO_IRQSTATUSSET1,
1351         .set_irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
1352         .clr_irqenable =        OMAP4_GPIO_IRQSTATUSCLR0,
1353         .debounce =             OMAP4_GPIO_DEBOUNCINGTIME,
1354         .debounce_en =          OMAP4_GPIO_DEBOUNCENABLE,
1355         .ctrl =                 OMAP4_GPIO_CTRL,
1356         .wkup_en =              OMAP4_GPIO_IRQWAKEN0,
1357         .leveldetect0 =         OMAP4_GPIO_LEVELDETECT0,
1358         .leveldetect1 =         OMAP4_GPIO_LEVELDETECT1,
1359         .risingdetect =         OMAP4_GPIO_RISINGDETECT,
1360         .fallingdetect =        OMAP4_GPIO_FALLINGDETECT,
1361 };
1362
1363 static const struct omap_gpio_platform_data omap2_pdata = {
1364         .regs = &omap2_gpio_regs,
1365         .bank_width = 32,
1366         .dbck_flag = false,
1367 };
1368
1369 static const struct omap_gpio_platform_data omap3_pdata = {
1370         .regs = &omap2_gpio_regs,
1371         .bank_width = 32,
1372         .dbck_flag = true,
1373 };
1374
1375 static const struct omap_gpio_platform_data omap4_pdata = {
1376         .regs = &omap4_gpio_regs,
1377         .bank_width = 32,
1378         .dbck_flag = true,
1379 };
1380
1381 static const struct of_device_id omap_gpio_match[] = {
1382         {
1383                 .compatible = "ti,omap4-gpio",
1384                 .data = &omap4_pdata,
1385         },
1386         {
1387                 .compatible = "ti,omap3-gpio",
1388                 .data = &omap3_pdata,
1389         },
1390         {
1391                 .compatible = "ti,omap2-gpio",
1392                 .data = &omap2_pdata,
1393         },
1394         { },
1395 };
1396 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1397
1398 static int omap_gpio_probe(struct platform_device *pdev)
1399 {
1400         struct device *dev = &pdev->dev;
1401         struct device_node *node = dev->of_node;
1402         const struct of_device_id *match;
1403         const struct omap_gpio_platform_data *pdata;
1404         struct gpio_bank *bank;
1405         struct irq_chip *irqc;
1406         int ret;
1407
1408         match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1409
1410         pdata = match ? match->data : dev_get_platdata(dev);
1411         if (!pdata)
1412                 return -EINVAL;
1413
1414         bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1415         if (!bank)
1416                 return -ENOMEM;
1417
1418         irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1419         if (!irqc)
1420                 return -ENOMEM;
1421
1422         irqc->irq_startup = omap_gpio_irq_startup,
1423         irqc->irq_shutdown = omap_gpio_irq_shutdown,
1424         irqc->irq_ack = dummy_irq_chip.irq_ack,
1425         irqc->irq_mask = omap_gpio_mask_irq,
1426         irqc->irq_unmask = omap_gpio_unmask_irq,
1427         irqc->irq_set_type = omap_gpio_irq_type,
1428         irqc->irq_set_wake = omap_gpio_wake_enable,
1429         irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1430         irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1431         irqc->name = dev_name(&pdev->dev);
1432         irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1433         irqc->parent_device = dev;
1434
1435         bank->irq = platform_get_irq(pdev, 0);
1436         if (bank->irq <= 0) {
1437                 if (!bank->irq)
1438                         bank->irq = -ENXIO;
1439                 if (bank->irq != -EPROBE_DEFER)
1440                         dev_err(dev,
1441                                 "can't get irq resource ret=%d\n", bank->irq);
1442                 return bank->irq;
1443         }
1444
1445         bank->chip.parent = dev;
1446         bank->chip.owner = THIS_MODULE;
1447         bank->dbck_flag = pdata->dbck_flag;
1448         bank->stride = pdata->bank_stride;
1449         bank->width = pdata->bank_width;
1450         bank->is_mpuio = pdata->is_mpuio;
1451         bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1452         bank->regs = pdata->regs;
1453 #ifdef CONFIG_OF_GPIO
1454         bank->chip.of_node = of_node_get(node);
1455 #endif
1456
1457         if (node) {
1458                 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1459                         bank->loses_context = true;
1460         } else {
1461                 bank->loses_context = pdata->loses_context;
1462
1463                 if (bank->loses_context)
1464                         bank->get_context_loss_count =
1465                                 pdata->get_context_loss_count;
1466         }
1467
1468         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1469                 bank->set_dataout = omap_set_gpio_dataout_reg;
1470         else
1471                 bank->set_dataout = omap_set_gpio_dataout_mask;
1472
1473         raw_spin_lock_init(&bank->lock);
1474         raw_spin_lock_init(&bank->wa_lock);
1475
1476         /* Static mapping, never released */
1477         bank->base = devm_platform_ioremap_resource(pdev, 0);
1478         if (IS_ERR(bank->base)) {
1479                 return PTR_ERR(bank->base);
1480         }
1481
1482         if (bank->dbck_flag) {
1483                 bank->dbck = devm_clk_get(dev, "dbclk");
1484                 if (IS_ERR(bank->dbck)) {
1485                         dev_err(dev,
1486                                 "Could not get gpio dbck. Disable debounce\n");
1487                         bank->dbck_flag = false;
1488                 } else {
1489                         clk_prepare(bank->dbck);
1490                 }
1491         }
1492
1493         platform_set_drvdata(pdev, bank);
1494
1495         pm_runtime_enable(dev);
1496         pm_runtime_get_sync(dev);
1497
1498         if (bank->is_mpuio)
1499                 omap_mpuio_init(bank);
1500
1501         omap_gpio_mod_init(bank);
1502
1503         ret = omap_gpio_chip_init(bank, irqc);
1504         if (ret) {
1505                 pm_runtime_put_sync(dev);
1506                 pm_runtime_disable(dev);
1507                 if (bank->dbck_flag)
1508                         clk_unprepare(bank->dbck);
1509                 return ret;
1510         }
1511
1512         omap_gpio_show_rev(bank);
1513
1514         bank->nb.notifier_call = gpio_omap_cpu_notifier;
1515         cpu_pm_register_notifier(&bank->nb);
1516
1517         pm_runtime_put(dev);
1518
1519         return 0;
1520 }
1521
1522 static int omap_gpio_remove(struct platform_device *pdev)
1523 {
1524         struct gpio_bank *bank = platform_get_drvdata(pdev);
1525
1526         cpu_pm_unregister_notifier(&bank->nb);
1527         gpiochip_remove(&bank->chip);
1528         pm_runtime_disable(&pdev->dev);
1529         if (bank->dbck_flag)
1530                 clk_unprepare(bank->dbck);
1531
1532         return 0;
1533 }
1534
1535 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1536 {
1537         struct gpio_bank *bank = dev_get_drvdata(dev);
1538         unsigned long flags;
1539
1540         raw_spin_lock_irqsave(&bank->lock, flags);
1541         omap_gpio_idle(bank, true);
1542         bank->is_suspended = true;
1543         raw_spin_unlock_irqrestore(&bank->lock, flags);
1544
1545         return 0;
1546 }
1547
1548 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1549 {
1550         struct gpio_bank *bank = dev_get_drvdata(dev);
1551         unsigned long flags;
1552
1553         raw_spin_lock_irqsave(&bank->lock, flags);
1554         omap_gpio_unidle(bank);
1555         bank->is_suspended = false;
1556         raw_spin_unlock_irqrestore(&bank->lock, flags);
1557
1558         return 0;
1559 }
1560
1561 static const struct dev_pm_ops gpio_pm_ops = {
1562         SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1563                                                                         NULL)
1564 };
1565
1566 static struct platform_driver omap_gpio_driver = {
1567         .probe          = omap_gpio_probe,
1568         .remove         = omap_gpio_remove,
1569         .driver         = {
1570                 .name   = "omap_gpio",
1571                 .pm     = &gpio_pm_ops,
1572                 .of_match_table = omap_gpio_match,
1573         },
1574 };
1575
1576 /*
1577  * gpio driver register needs to be done before
1578  * machine_init functions access gpio APIs.
1579  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1580  */
1581 static int __init omap_gpio_drv_reg(void)
1582 {
1583         return platform_driver_register(&omap_gpio_driver);
1584 }
1585 postcore_initcall(omap_gpio_drv_reg);
1586
1587 static void __exit omap_gpio_exit(void)
1588 {
1589         platform_driver_unregister(&omap_gpio_driver);
1590 }
1591 module_exit(omap_gpio_exit);
1592
1593 MODULE_DESCRIPTION("omap gpio driver");
1594 MODULE_ALIAS("platform:gpio-omap");
1595 MODULE_LICENSE("GPL v2");