drivers/edac/altera_edac.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
   4  *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
   5  *  Copyright 2011-2012 Calxeda, Inc.
   6  */
   7
   8 #include <asm/cacheflush.h>
   9 #include <linux/ctype.h>
  10 #include <linux/delay.h>
  11 #include <linux/edac.h>
  12 #include <linux/firmware/intel/stratix10-smc.h>
  13 #include <linux/genalloc.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irqchip/chained_irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/notifier.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <linux/types.h>
  25 #include <linux/uaccess.h>
  26
  27 #include "altera_edac.h"
  28 #include "edac_module.h"
  29
  30 #define EDAC_MOD_STR            "altera_edac"
  31 #define EDAC_DEVICE             "Altera"
  32
  33 #ifdef CONFIG_EDAC_ALTERA_SDRAM
  34 static const struct altr_sdram_prv_data c5_data = {
  35         .ecc_ctrl_offset    = CV_CTLCFG_OFST,
  36         .ecc_ctl_en_mask    = CV_CTLCFG_ECC_AUTO_EN,
  37         .ecc_stat_offset    = CV_DRAMSTS_OFST,
  38         .ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
  39         .ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
  40         .ecc_saddr_offset   = CV_ERRADDR_OFST,
  41         .ecc_daddr_offset   = CV_ERRADDR_OFST,
  42         .ecc_cecnt_offset   = CV_SBECOUNT_OFST,
  43         .ecc_uecnt_offset   = CV_DBECOUNT_OFST,
  44         .ecc_irq_en_offset  = CV_DRAMINTR_OFST,
  45         .ecc_irq_en_mask    = CV_DRAMINTR_INTREN,
  46         .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
  47         .ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
  48         .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
  49         .ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
  50         .ce_ue_trgr_offset  = CV_CTLCFG_OFST,
  51         .ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,
  52         .ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,
  53 };
  54
  55 static const struct altr_sdram_prv_data a10_data = {
  56         .ecc_ctrl_offset    = A10_ECCCTRL1_OFST,
  57         .ecc_ctl_en_mask    = A10_ECCCTRL1_ECC_EN,
  58         .ecc_stat_offset    = A10_INTSTAT_OFST,
  59         .ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
  60         .ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
  61         .ecc_saddr_offset   = A10_SERRADDR_OFST,
  62         .ecc_daddr_offset   = A10_DERRADDR_OFST,
  63         .ecc_irq_en_offset  = A10_ERRINTEN_OFST,
  64         .ecc_irq_en_mask    = A10_ECC_IRQ_EN_MASK,
  65         .ecc_irq_clr_offset = A10_INTSTAT_OFST,
  66         .ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
  67         .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
  68         .ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
  69         .ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,
  70         .ce_set_mask        = A10_DIAGINT_TSERRA_MASK,
  71         .ue_set_mask        = A10_DIAGINT_TDERRA_MASK,
  72 };
  73
  74 /*********************** EDAC Memory Controller Functions ****************/
  75
  76 /* The SDRAM controller uses the EDAC Memory Controller framework.       */
  77
  78 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
  79 {
  80         struct mem_ctl_info *mci = dev_id;
  81         struct altr_sdram_mc_data *drvdata = mci->pvt_info;
  82         const struct altr_sdram_prv_data *priv = drvdata->data;
  83         u32 status, err_count = 1, err_addr;
  84
  85         regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
  86
  87         if (status & priv->ecc_stat_ue_mask) {
  88                 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
  89                             &err_addr);
  90                 if (priv->ecc_uecnt_offset)
  91                         regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
  92                                     &err_count);
  93                 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
  94                       err_count, err_addr);
  95         }
  96         if (status & priv->ecc_stat_ce_mask) {
  97                 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
  98                             &err_addr);
  99                 if (priv->ecc_uecnt_offset)
 100                         regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
 101                                     &err_count);
 102                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
 103                                      err_addr >> PAGE_SHIFT,
 104                                      err_addr & ~PAGE_MASK, 0,
 105                                      0, 0, -1, mci->ctl_name, "");
 106                 /* Clear IRQ to resume */
 107                 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
 108                              priv->ecc_irq_clr_mask);
 109
 110                 return IRQ_HANDLED;
 111         }
 112         return IRQ_NONE;
 113 }
 114
 115 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
 116                                             const char __user *data,
 117                                             size_t count, loff_t *ppos)
 118 {
 119         struct mem_ctl_info *mci = file->private_data;
 120         struct altr_sdram_mc_data *drvdata = mci->pvt_info;
 121         const struct altr_sdram_prv_data *priv = drvdata->data;
 122         u32 *ptemp;
 123         dma_addr_t dma_handle;
 124         u32 reg, read_reg;
 125
 126         ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
 127         if (!ptemp) {
 128                 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 129                 edac_printk(KERN_ERR, EDAC_MC,
 130                             "Inject: Buffer Allocation error\n");
 131                 return -ENOMEM;
 132         }
 133
 134         regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 135                     &read_reg);
 136         read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
 137
 138         /* Error are injected by writing a word while the SBE or DBE
 139          * bit in the CTLCFG register is set. Reading the word will
 140          * trigger the SBE or DBE error and the corresponding IRQ.
 141          */
 142         if (count == 3) {
 143                 edac_printk(KERN_ALERT, EDAC_MC,
 144                             "Inject Double bit error\n");
 145                 local_irq_disable();
 146                 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 147                              (read_reg | priv->ue_set_mask));
 148                 local_irq_enable();
 149         } else {
 150                 edac_printk(KERN_ALERT, EDAC_MC,
 151                             "Inject Single bit error\n");
 152                 local_irq_disable();
 153                 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 154                              (read_reg | priv->ce_set_mask));
 155                 local_irq_enable();
 156         }
 157
 158         ptemp[0] = 0x5A5A5A5A;
 159         ptemp[1] = 0xA5A5A5A5;
 160
 161         /* Clear the error injection bits */
 162         regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
 163         /* Ensure it has been written out */
 164         wmb();
 165
 166         /*
 167          * To trigger the error, we need to read the data back
 168          * (the data was written with errors above).
 169          * The READ_ONCE macros and printk are used to prevent the
 170          * the compiler optimizing these reads out.
 171          */
 172         reg = READ_ONCE(ptemp[0]);
 173         read_reg = READ_ONCE(ptemp[1]);
 174         /* Force Read */
 175         rmb();
 176
 177         edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
 178                     reg, read_reg);
 179
 180         dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 181
 182         return count;
 183 }
 184
 185 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
 186         .open = simple_open,
 187         .write = altr_sdr_mc_err_inject_write,
 188         .llseek = generic_file_llseek,
 189 };
 190
 191 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
 192 {
 193         if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 194                 return;
 195
 196         if (!mci->debugfs)
 197                 return;
 198
 199         edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
 200                                  &altr_sdr_mc_debug_inject_fops);
 201 }
 202
 203 /* Get total memory size from Open Firmware DTB */
 204 static unsigned long get_total_mem(void)
 205 {
 206         struct device_node *np = NULL;
 207         struct resource res;
 208         int ret;
 209         unsigned long total_mem = 0;
 210
 211         for_each_node_by_type(np, "memory") {
 212                 ret = of_address_to_resource(np, 0, &res);
 213                 if (ret)
 214                         continue;
 215
 216                 total_mem += resource_size(&res);
 217         }
 218         edac_dbg(0, "total_mem 0x%lx\n", total_mem);
 219         return total_mem;
 220 }
 221
 222 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
 223         { .compatible = "altr,sdram-edac", .data = &c5_data},
 224         { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
 225         {},
 226 };
 227 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
 228
 229 static int a10_init(struct regmap *mc_vbase)
 230 {
 231         if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
 232                                A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
 233                 edac_printk(KERN_ERR, EDAC_MC,
 234                             "Error setting SB IRQ mode\n");
 235                 return -ENODEV;
 236         }
 237
 238         if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
 239                 edac_printk(KERN_ERR, EDAC_MC,
 240                             "Error setting trigger count\n");
 241                 return -ENODEV;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
 248 {
 249         void __iomem  *sm_base;
 250         int  ret = 0;
 251
 252         if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
 253                                 dev_name(&pdev->dev))) {
 254                 edac_printk(KERN_ERR, EDAC_MC,
 255                             "Unable to request mem region\n");
 256                 return -EBUSY;
 257         }
 258
 259         sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 260         if (!sm_base) {
 261                 edac_printk(KERN_ERR, EDAC_MC,
 262                             "Unable to ioremap device\n");
 263
 264                 ret = -ENOMEM;
 265                 goto release;
 266         }
 267
 268         iowrite32(mask, sm_base);
 269
 270         iounmap(sm_base);
 271
 272 release:
 273         release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 274
 275         return ret;
 276 }
 277
 278 static int socfpga_is_a10(void);
 279 static int altr_sdram_probe(struct platform_device *pdev)
 280 {
 281         const struct of_device_id *id;
 282         struct edac_mc_layer layers[2];
 283         struct mem_ctl_info *mci;
 284         struct altr_sdram_mc_data *drvdata;
 285         const struct altr_sdram_prv_data *priv;
 286         struct regmap *mc_vbase;
 287         struct dimm_info *dimm;
 288         u32 read_reg;
 289         int irq, irq2, res = 0;
 290         unsigned long mem_size, irqflags = 0;
 291
 292         id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
 293         if (!id)
 294                 return -ENODEV;
 295
 296         /* Grab the register range from the sdr controller in device tree */
 297         mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 298                                                    "altr,sdr-syscon");
 299         if (IS_ERR(mc_vbase)) {
 300                 edac_printk(KERN_ERR, EDAC_MC,
 301                             "regmap for altr,sdr-syscon lookup failed.\n");
 302                 return -ENODEV;
 303         }
 304
 305         /* Check specific dependencies for the module */
 306         priv = of_match_node(altr_sdram_ctrl_of_match,
 307                              pdev->dev.of_node)->data;
 308
 309         /* Validate the SDRAM controller has ECC enabled */
 310         if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
 311             ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
 312                 edac_printk(KERN_ERR, EDAC_MC,
 313                             "No ECC/ECC disabled [0x%08X]\n", read_reg);
 314                 return -ENODEV;
 315         }
 316
 317         /* Grab memory size from device tree. */
 318         mem_size = get_total_mem();
 319         if (!mem_size) {
 320                 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
 321                 return -ENODEV;
 322         }
 323
 324         /* Ensure the SDRAM Interrupt is disabled */
 325         if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
 326                                priv->ecc_irq_en_mask, 0)) {
 327                 edac_printk(KERN_ERR, EDAC_MC,
 328                             "Error disabling SDRAM ECC IRQ\n");
 329                 return -ENODEV;
 330         }
 331
 332         /* Toggle to clear the SDRAM Error count */
 333         if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 334                                priv->ecc_cnt_rst_mask,
 335                                priv->ecc_cnt_rst_mask)) {
 336                 edac_printk(KERN_ERR, EDAC_MC,
 337                             "Error clearing SDRAM ECC count\n");
 338                 return -ENODEV;
 339         }
 340
 341         if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 342                                priv->ecc_cnt_rst_mask, 0)) {
 343                 edac_printk(KERN_ERR, EDAC_MC,
 344                             "Error clearing SDRAM ECC count\n");
 345                 return -ENODEV;
 346         }
 347
 348         irq = platform_get_irq(pdev, 0);
 349         if (irq < 0) {
 350                 edac_printk(KERN_ERR, EDAC_MC,
 351                             "No irq %d in DT\n", irq);
 352                 return -ENODEV;
 353         }
 354
 355         /* Arria10 has a 2nd IRQ */
 356         irq2 = platform_get_irq(pdev, 1);
 357
 358         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 359         layers[0].size = 1;
 360         layers[0].is_virt_csrow = true;
 361         layers[1].type = EDAC_MC_LAYER_CHANNEL;
 362         layers[1].size = 1;
 363         layers[1].is_virt_csrow = false;
 364         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 365                             sizeof(struct altr_sdram_mc_data));
 366         if (!mci)
 367                 return -ENOMEM;
 368
 369         mci->pdev = &pdev->dev;
 370         drvdata = mci->pvt_info;
 371         drvdata->mc_vbase = mc_vbase;
 372         drvdata->data = priv;
 373         platform_set_drvdata(pdev, mci);
 374
 375         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 376                 edac_printk(KERN_ERR, EDAC_MC,
 377                             "Unable to get managed device resource\n");
 378                 res = -ENOMEM;
 379                 goto free;
 380         }
 381
 382         mci->mtype_cap = MEM_FLAG_DDR3;
 383         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 384         mci->edac_cap = EDAC_FLAG_SECDED;
 385         mci->mod_name = EDAC_MOD_STR;
 386         mci->ctl_name = dev_name(&pdev->dev);
 387         mci->scrub_mode = SCRUB_SW_SRC;
 388         mci->dev_name = dev_name(&pdev->dev);
 389
 390         dimm = *mci->dimms;
 391         dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
 392         dimm->grain = 8;
 393         dimm->dtype = DEV_X8;
 394         dimm->mtype = MEM_DDR3;
 395         dimm->edac_mode = EDAC_SECDED;
 396
 397         res = edac_mc_add_mc(mci);
 398         if (res < 0)
 399                 goto err;
 400
 401         /* Only the Arria10 has separate IRQs */
 402         if (socfpga_is_a10()) {
 403                 /* Arria10 specific initialization */
 404                 res = a10_init(mc_vbase);
 405                 if (res < 0)
 406                         goto err2;
 407
 408                 res = devm_request_irq(&pdev->dev, irq2,
 409                                        altr_sdram_mc_err_handler,
 410                                        IRQF_SHARED, dev_name(&pdev->dev), mci);
 411                 if (res < 0) {
 412                         edac_mc_printk(mci, KERN_ERR,
 413                                        "Unable to request irq %d\n", irq2);
 414                         res = -ENODEV;
 415                         goto err2;
 416                 }
 417
 418                 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
 419                 if (res < 0)
 420                         goto err2;
 421
 422                 irqflags = IRQF_SHARED;
 423         }
 424
 425         res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
 426                                irqflags, dev_name(&pdev->dev), mci);
 427         if (res < 0) {
 428                 edac_mc_printk(mci, KERN_ERR,
 429                                "Unable to request irq %d\n", irq);
 430                 res = -ENODEV;
 431                 goto err2;
 432         }
 433
 434         /* Infrastructure ready - enable the IRQ */
 435         if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
 436                                priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
 437                 edac_mc_printk(mci, KERN_ERR,
 438                                "Error enabling SDRAM ECC IRQ\n");
 439                 res = -ENODEV;
 440                 goto err2;
 441         }
 442
 443         altr_sdr_mc_create_debugfs_nodes(mci);
 444
 445         devres_close_group(&pdev->dev, NULL);
 446
 447         return 0;
 448
 449 err2:
 450         edac_mc_del_mc(&pdev->dev);
 451 err:
 452         devres_release_group(&pdev->dev, NULL);
 453 free:
 454         edac_mc_free(mci);
 455         edac_printk(KERN_ERR, EDAC_MC,
 456                     "EDAC Probe Failed; Error %d\n", res);
 457
 458         return res;
 459 }
 460
 461 static int altr_sdram_remove(struct platform_device *pdev)
 462 {
 463         struct mem_ctl_info *mci = platform_get_drvdata(pdev);
 464
 465         edac_mc_del_mc(&pdev->dev);
 466         edac_mc_free(mci);
 467         platform_set_drvdata(pdev, NULL);
 468
 469         return 0;
 470 }
 471
 472 /*
 473  * If you want to suspend, need to disable EDAC by removing it
 474  * from the device tree or defconfig.
 475  */
 476 #ifdef CONFIG_PM
 477 static int altr_sdram_prepare(struct device *dev)
 478 {
 479         pr_err("Suspend not allowed when EDAC is enabled.\n");
 480
 481         return -EPERM;
 482 }
 483
 484 static const struct dev_pm_ops altr_sdram_pm_ops = {
 485         .prepare = altr_sdram_prepare,
 486 };
 487 #endif
 488
 489 static struct platform_driver altr_sdram_edac_driver = {
 490         .probe = altr_sdram_probe,
 491         .remove = altr_sdram_remove,
 492         .driver = {
 493                 .name = "altr_sdram_edac",
 494 #ifdef CONFIG_PM
 495                 .pm = &altr_sdram_pm_ops,
 496 #endif
 497                 .of_match_table = altr_sdram_ctrl_of_match,
 498         },
 499 };
 500
 501 module_platform_driver(altr_sdram_edac_driver);
 502
 503 #endif  /* CONFIG_EDAC_ALTERA_SDRAM */
 504
 505 /**************** Stratix 10 EDAC Memory Controller Functions ************/
 506
 507 /**
 508  * s10_protected_reg_write
 509  * Write to a protected SMC register.
 510  * @context: Not used.
 511  * @reg: Address of register
 512  * @value: Value to write
 513  * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
 514  *         INTEL_SIP_SMC_REG_ERROR on error
 515  *         INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
 516  */
 517 static int s10_protected_reg_write(void *context, unsigned int reg,
 518                                    unsigned int val)
 519 {
 520         struct arm_smccc_res result;
 521         unsigned long offset = (unsigned long)context;
 522
 523         arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0,
 524                       0, 0, 0, &result);
 525
 526         return (int)result.a0;
 527 }
 528
 529 /**
 530  * s10_protected_reg_read
 531  * Read the status of a protected SMC register
 532  * @context: Not used.
 533  * @reg: Address of register
 534  * @value: Value read.
 535  * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
 536  *         INTEL_SIP_SMC_REG_ERROR on error
 537  *         INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
 538  */
 539 static int s10_protected_reg_read(void *context, unsigned int reg,
 540                                   unsigned int *val)
 541 {
 542         struct arm_smccc_res result;
 543         unsigned long offset = (unsigned long)context;
 544
 545         arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0,
 546                       0, 0, 0, &result);
 547
 548         *val = (unsigned int)result.a1;
 549
 550         return (int)result.a0;
 551 }
 552
 553 static const struct regmap_config s10_sdram_regmap_cfg = {
 554         .name = "s10_ddr",
 555         .reg_bits = 32,
 556         .reg_stride = 4,
 557         .val_bits = 32,
 558         .max_register = 0xffd12228,
 559         .reg_read = s10_protected_reg_read,
 560         .reg_write = s10_protected_reg_write,
 561         .use_single_read = true,
 562         .use_single_write = true,
 563 };
 564
 565 /************** </Stratix10 EDAC Memory Controller Functions> ***********/
 566
 567 /************************* EDAC Parent Probe *************************/
 568
 569 static const struct of_device_id altr_edac_device_of_match[];
 570
 571 static const struct of_device_id altr_edac_of_match[] = {
 572         { .compatible = "altr,socfpga-ecc-manager" },
 573         {},
 574 };
 575 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
 576
 577 static int altr_edac_probe(struct platform_device *pdev)
 578 {
 579         of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
 580                              NULL, &pdev->dev);
 581         return 0;
 582 }
 583
 584 static struct platform_driver altr_edac_driver = {
 585         .probe =  altr_edac_probe,
 586         .driver = {
 587                 .name = "socfpga_ecc_manager",
 588                 .of_match_table = altr_edac_of_match,
 589         },
 590 };
 591 module_platform_driver(altr_edac_driver);
 592
 593 /************************* EDAC Device Functions *************************/
 594
 595 /*
 596  * EDAC Device Functions (shared between various IPs).
 597  * The discrete memories use the EDAC Device framework. The probe
 598  * and error handling functions are very similar between memories
 599  * so they are shared. The memory allocation and freeing for EDAC
 600  * trigger testing are different for each memory.
 601  */
 602
 603 static const struct edac_device_prv_data ocramecc_data;
 604 static const struct edac_device_prv_data l2ecc_data;
 605 static const struct edac_device_prv_data a10_ocramecc_data;
 606 static const struct edac_device_prv_data a10_l2ecc_data;
 607
 608 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
 609 {
 610         irqreturn_t ret_value = IRQ_NONE;
 611         struct edac_device_ctl_info *dci = dev_id;
 612         struct altr_edac_device_dev *drvdata = dci->pvt_info;
 613         const struct edac_device_prv_data *priv = drvdata->data;
 614
 615         if (irq == drvdata->sb_irq) {
 616                 if (priv->ce_clear_mask)
 617                         writel(priv->ce_clear_mask, drvdata->base);
 618                 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
 619                 ret_value = IRQ_HANDLED;
 620         } else if (irq == drvdata->db_irq) {
 621                 if (priv->ue_clear_mask)
 622                         writel(priv->ue_clear_mask, drvdata->base);
 623                 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
 624                 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 625                 ret_value = IRQ_HANDLED;
 626         } else {
 627                 WARN_ON(1);
 628         }
 629
 630         return ret_value;
 631 }
 632
 633 static ssize_t altr_edac_device_trig(struct file *file,
 634                                      const char __user *user_buf,
 635                                      size_t count, loff_t *ppos)
 636
 637 {
 638         u32 *ptemp, i, error_mask;
 639         int result = 0;
 640         u8 trig_type;
 641         unsigned long flags;
 642         struct edac_device_ctl_info *edac_dci = file->private_data;
 643         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 644         const struct edac_device_prv_data *priv = drvdata->data;
 645         void *generic_ptr = edac_dci->dev;
 646
 647         if (!user_buf || get_user(trig_type, user_buf))
 648                 return -EFAULT;
 649
 650         if (!priv->alloc_mem)
 651                 return -ENOMEM;
 652
 653         /*
 654          * Note that generic_ptr is initialized to the device * but in
 655          * some alloc_functions, this is overridden and returns data.
 656          */
 657         ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
 658         if (!ptemp) {
 659                 edac_printk(KERN_ERR, EDAC_DEVICE,
 660                             "Inject: Buffer Allocation error\n");
 661                 return -ENOMEM;
 662         }
 663
 664         if (trig_type == ALTR_UE_TRIGGER_CHAR)
 665                 error_mask = priv->ue_set_mask;
 666         else
 667                 error_mask = priv->ce_set_mask;
 668
 669         edac_printk(KERN_ALERT, EDAC_DEVICE,
 670                     "Trigger Error Mask (0x%X)\n", error_mask);
 671
 672         local_irq_save(flags);
 673         /* write ECC corrupted data out. */
 674         for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
 675                 /* Read data so we're in the correct state */
 676                 rmb();
 677                 if (READ_ONCE(ptemp[i]))
 678                         result = -1;
 679                 /* Toggle Error bit (it is latched), leave ECC enabled */
 680                 writel(error_mask, (drvdata->base + priv->set_err_ofst));
 681                 writel(priv->ecc_enable_mask, (drvdata->base +
 682                                                priv->set_err_ofst));
 683                 ptemp[i] = i;
 684         }
 685         /* Ensure it has been written out */
 686         wmb();
 687         local_irq_restore(flags);
 688
 689         if (result)
 690                 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
 691
 692         /* Read out written data. ECC error caused here */
 693         for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
 694                 if (READ_ONCE(ptemp[i]) != i)
 695                         edac_printk(KERN_ERR, EDAC_DEVICE,
 696                                     "Read doesn't match written data\n");
 697
 698         if (priv->free_mem)
 699                 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
 700
 701         return count;
 702 }
 703
 704 static const struct file_operations altr_edac_device_inject_fops = {
 705         .open = simple_open,
 706         .write = altr_edac_device_trig,
 707         .llseek = generic_file_llseek,
 708 };
 709
 710 static ssize_t altr_edac_a10_device_trig(struct file *file,
 711                                          const char __user *user_buf,
 712                                          size_t count, loff_t *ppos);
 713
 714 static const struct file_operations altr_edac_a10_device_inject_fops = {
 715         .open = simple_open,
 716         .write = altr_edac_a10_device_trig,
 717         .llseek = generic_file_llseek,
 718 };
 719
 720 static ssize_t altr_edac_a10_device_trig2(struct file *file,
 721                                           const char __user *user_buf,
 722                                           size_t count, loff_t *ppos);
 723
 724 static const struct file_operations altr_edac_a10_device_inject2_fops = {
 725         .open = simple_open,
 726         .write = altr_edac_a10_device_trig2,
 727         .llseek = generic_file_llseek,
 728 };
 729
 730 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
 731                                       const struct edac_device_prv_data *priv)
 732 {
 733         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 734
 735         if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 736                 return;
 737
 738         drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
 739         if (!drvdata->debugfs_dir)
 740                 return;
 741
 742         if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
 743                                       drvdata->debugfs_dir, edac_dci,
 744                                       priv->inject_fops))
 745                 debugfs_remove_recursive(drvdata->debugfs_dir);
 746 }
 747
 748 static const struct of_device_id altr_edac_device_of_match[] = {
 749 #ifdef CONFIG_EDAC_ALTERA_L2C
 750         { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
 751 #endif
 752 #ifdef CONFIG_EDAC_ALTERA_OCRAM
 753         { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
 754 #endif
 755         {},
 756 };
 757 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
 758
 759 /*
 760  * altr_edac_device_probe()
 761  *      This is a generic EDAC device driver that will support
 762  *      various Altera memory devices such as the L2 cache ECC and
 763  *      OCRAM ECC as well as the memories for other peripherals.
 764  *      Module specific initialization is done by passing the
 765  *      function index in the device tree.
 766  */
 767 static int altr_edac_device_probe(struct platform_device *pdev)
 768 {
 769         struct edac_device_ctl_info *dci;
 770         struct altr_edac_device_dev *drvdata;
 771         struct resource *r;
 772         int res = 0;
 773         struct device_node *np = pdev->dev.of_node;
 774         char *ecc_name = (char *)np->name;
 775         static int dev_instance;
 776
 777         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 778                 edac_printk(KERN_ERR, EDAC_DEVICE,
 779                             "Unable to open devm\n");
 780                 return -ENOMEM;
 781         }
 782
 783         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 784         if (!r) {
 785                 edac_printk(KERN_ERR, EDAC_DEVICE,
 786                             "Unable to get mem resource\n");
 787                 res = -ENODEV;
 788                 goto fail;
 789         }
 790
 791         if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 792                                      dev_name(&pdev->dev))) {
 793                 edac_printk(KERN_ERR, EDAC_DEVICE,
 794                             "%s:Error requesting mem region\n", ecc_name);
 795                 res = -EBUSY;
 796                 goto fail;
 797         }
 798
 799         dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
 800                                          1, ecc_name, 1, 0, NULL, 0,
 801                                          dev_instance++);
 802
 803         if (!dci) {
 804                 edac_printk(KERN_ERR, EDAC_DEVICE,
 805                             "%s: Unable to allocate EDAC device\n", ecc_name);
 806                 res = -ENOMEM;
 807                 goto fail;
 808         }
 809
 810         drvdata = dci->pvt_info;
 811         dci->dev = &pdev->dev;
 812         platform_set_drvdata(pdev, dci);
 813         drvdata->edac_dev_name = ecc_name;
 814
 815         drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 816         if (!drvdata->base) {
 817                 res = -ENOMEM;
 818                 goto fail1;
 819         }
 820
 821         /* Get driver specific data for this EDAC device */
 822         drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
 823
 824         /* Check specific dependencies for the module */
 825         if (drvdata->data->setup) {
 826                 res = drvdata->data->setup(drvdata);
 827                 if (res)
 828                         goto fail1;
 829         }
 830
 831         drvdata->sb_irq = platform_get_irq(pdev, 0);
 832         res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
 833                                altr_edac_device_handler,
 834                                0, dev_name(&pdev->dev), dci);
 835         if (res)
 836                 goto fail1;
 837
 838         drvdata->db_irq = platform_get_irq(pdev, 1);
 839         res = devm_request_irq(&pdev->dev, drvdata->db_irq,
 840                                altr_edac_device_handler,
 841                                0, dev_name(&pdev->dev), dci);
 842         if (res)
 843                 goto fail1;
 844
 845         dci->mod_name = "Altera ECC Manager";
 846         dci->dev_name = drvdata->edac_dev_name;
 847
 848         res = edac_device_add_device(dci);
 849         if (res)
 850                 goto fail1;
 851
 852         altr_create_edacdev_dbgfs(dci, drvdata->data);
 853
 854         devres_close_group(&pdev->dev, NULL);
 855
 856         return 0;
 857
 858 fail1:
 859         edac_device_free_ctl_info(dci);
 860 fail:
 861         devres_release_group(&pdev->dev, NULL);
 862         edac_printk(KERN_ERR, EDAC_DEVICE,
 863                     "%s:Error setting up EDAC device: %d\n", ecc_name, res);
 864
 865         return res;
 866 }
 867
 868 static int altr_edac_device_remove(struct platform_device *pdev)
 869 {
 870         struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
 871         struct altr_edac_device_dev *drvdata = dci->pvt_info;
 872
 873         debugfs_remove_recursive(drvdata->debugfs_dir);
 874         edac_device_del_device(&pdev->dev);
 875         edac_device_free_ctl_info(dci);
 876
 877         return 0;
 878 }
 879
 880 static struct platform_driver altr_edac_device_driver = {
 881         .probe =  altr_edac_device_probe,
 882         .remove = altr_edac_device_remove,
 883         .driver = {
 884                 .name = "altr_edac_device",
 885                 .of_match_table = altr_edac_device_of_match,
 886         },
 887 };
 888 module_platform_driver(altr_edac_device_driver);
 889
 890 /******************* Arria10 Device ECC Shared Functions *****************/
 891
 892 /*
 893  *  Test for memory's ECC dependencies upon entry because platform specific
 894  *  startup should have initialized the memory and enabled the ECC.
 895  *  Can't turn on ECC here because accessing un-initialized memory will
 896  *  cause CE/UE errors possibly causing an ABORT.
 897  */
 898 static int __maybe_unused
 899 altr_check_ecc_deps(struct altr_edac_device_dev *device)
 900 {
 901         void __iomem  *base = device->base;
 902         const struct edac_device_prv_data *prv = device->data;
 903
 904         if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
 905                 return 0;
 906
 907         edac_printk(KERN_ERR, EDAC_DEVICE,
 908                     "%s: No ECC present or ECC disabled.\n",
 909                     device->edac_dev_name);
 910         return -ENODEV;
 911 }
 912
 913 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
 914 {
 915         struct altr_edac_device_dev *dci = dev_id;
 916         void __iomem  *base = dci->base;
 917
 918         if (irq == dci->sb_irq) {
 919                 writel(ALTR_A10_ECC_SERRPENA,
 920                        base + ALTR_A10_ECC_INTSTAT_OFST);
 921                 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
 922
 923                 return IRQ_HANDLED;
 924         } else if (irq == dci->db_irq) {
 925                 writel(ALTR_A10_ECC_DERRPENA,
 926                        base + ALTR_A10_ECC_INTSTAT_OFST);
 927                 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
 928                 if (dci->data->panic)
 929                         panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 930
 931                 return IRQ_HANDLED;
 932         }
 933
 934         WARN_ON(1);
 935
 936         return IRQ_NONE;
 937 }
 938
 939 /******************* Arria10 Memory Buffer Functions *********************/
 940
 941 static inline int a10_get_irq_mask(struct device_node *np)
 942 {
 943         int irq;
 944         const u32 *handle = of_get_property(np, "interrupts", NULL);
 945
 946         if (!handle)
 947                 return -ENODEV;
 948         irq = be32_to_cpup(handle);
 949         return irq;
 950 }
 951
 952 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
 953 {
 954         u32 value = readl(ioaddr);
 955
 956         value |= bit_mask;
 957         writel(value, ioaddr);
 958 }
 959
 960 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
 961 {
 962         u32 value = readl(ioaddr);
 963
 964         value &= ~bit_mask;
 965         writel(value, ioaddr);
 966 }
 967
 968 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
 969 {
 970         u32 value = readl(ioaddr);
 971
 972         return (value & bit_mask) ? 1 : 0;
 973 }
 974
 975 /*
 976  * This function uses the memory initialization block in the Arria10 ECC
 977  * controller to initialize/clear the entire memory data and ECC data.
 978  */
 979 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
 980 {
 981         int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
 982         u32 init_mask, stat_mask, clear_mask;
 983         int ret = 0;
 984
 985         if (port) {
 986                 init_mask = ALTR_A10_ECC_INITB;
 987                 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
 988                 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
 989         } else {
 990                 init_mask = ALTR_A10_ECC_INITA;
 991                 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
 992                 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
 993         }
 994
 995         ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
 996         while (limit--) {
 997                 if (ecc_test_bits(stat_mask,
 998                                   (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
 999                         break;
1000                 udelay(1);
1001         }
1002         if (limit < 0)
1003                 ret = -EBUSY;
1004
1005         /* Clear any pending ECC interrupts */
1006         writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
1007
1008         return ret;
1009 }
1010
1011 static int socfpga_is_a10(void)
1012 {
1013         return of_machine_is_compatible("altr,socfpga-arria10");
1014 }
1015
1016 static int socfpga_is_s10(void)
1017 {
1018         return of_machine_is_compatible("altr,socfpga-stratix10");
1019 }
1020
1021 static __init int __maybe_unused
1022 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
1023                         u32 ecc_ctrl_en_mask, bool dual_port)
1024 {
1025         int ret = 0;
1026         void __iomem *ecc_block_base;
1027         struct regmap *ecc_mgr_map;
1028         char *ecc_name;
1029         struct device_node *np_eccmgr;
1030
1031         ecc_name = (char *)np->name;
1032
1033         /* Get the ECC Manager - parent of the device EDACs */
1034         np_eccmgr = of_get_parent(np);
1035
1036         if (socfpga_is_a10()) {
1037                 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1038                                                               "altr,sysmgr-syscon");
1039         } else {
1040                 struct device_node *sysmgr_np;
1041                 struct resource res;
1042                 uintptr_t base;
1043
1044                 sysmgr_np = of_parse_phandle(np_eccmgr,
1045                                              "altr,sysmgr-syscon", 0);
1046                 if (!sysmgr_np) {
1047                         edac_printk(KERN_ERR, EDAC_DEVICE,
1048                                     "Unable to find altr,sysmgr-syscon\n");
1049                         return -ENODEV;
1050                 }
1051
1052                 if (of_address_to_resource(sysmgr_np, 0, &res)) {
1053                         of_node_put(sysmgr_np);
1054                         return -ENOMEM;
1055                 }
1056
1057                 /* Need physical address for SMCC call */
1058                 base = res.start;
1059
1060                 ecc_mgr_map = regmap_init(NULL, NULL, (void *)base,
1061                                           &s10_sdram_regmap_cfg);
1062                 of_node_put(sysmgr_np);
1063         }
1064         of_node_put(np_eccmgr);
1065         if (IS_ERR(ecc_mgr_map)) {
1066                 edac_printk(KERN_ERR, EDAC_DEVICE,
1067                             "Unable to get syscon altr,sysmgr-syscon\n");
1068                 return -ENODEV;
1069         }
1070
1071         /* Map the ECC Block */
1072         ecc_block_base = of_iomap(np, 0);
1073         if (!ecc_block_base) {
1074                 edac_printk(KERN_ERR, EDAC_DEVICE,
1075                             "Unable to map %s ECC block\n", ecc_name);
1076                 return -ENODEV;
1077         }
1078
1079         /* Disable ECC */
1080         regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
1081         writel(ALTR_A10_ECC_SERRINTEN,
1082                (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
1083         ecc_clear_bits(ecc_ctrl_en_mask,
1084                        (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
1085         /* Ensure all writes complete */
1086         wmb();
1087         /* Use HW initialization block to initialize memory for ECC */
1088         ret = altr_init_memory_port(ecc_block_base, 0);
1089         if (ret) {
1090                 edac_printk(KERN_ERR, EDAC_DEVICE,
1091                             "ECC: cannot init %s PORTA memory\n", ecc_name);
1092                 goto out;
1093         }
1094
1095         if (dual_port) {
1096                 ret = altr_init_memory_port(ecc_block_base, 1);
1097                 if (ret) {
1098                         edac_printk(KERN_ERR, EDAC_DEVICE,
1099                                     "ECC: cannot init %s PORTB memory\n",
1100                                     ecc_name);
1101                         goto out;
1102                 }
1103         }
1104
1105         /* Interrupt mode set to every SBERR */
1106         regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1107                      ALTR_A10_ECC_INTMODE);
1108         /* Enable ECC */
1109         ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1110                                         ALTR_A10_ECC_CTRL_OFST));
1111         writel(ALTR_A10_ECC_SERRINTEN,
1112                (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1113         regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1114         /* Ensure all writes complete */
1115         wmb();
1116 out:
1117         iounmap(ecc_block_base);
1118         return ret;
1119 }
1120
1121 static int validate_parent_available(struct device_node *np);
1122 static const struct of_device_id altr_edac_a10_device_of_match[];
1123 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1124 {
1125         int irq;
1126         struct device_node *child, *np;
1127
1128         if (!socfpga_is_a10() && !socfpga_is_s10())
1129                 return -ENODEV;
1130
1131         np = of_find_compatible_node(NULL, NULL,
1132                                      "altr,socfpga-a10-ecc-manager");
1133         if (!np) {
1134                 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1135                 return -ENODEV;
1136         }
1137
1138         for_each_child_of_node(np, child) {
1139                 const struct of_device_id *pdev_id;
1140                 const struct edac_device_prv_data *prv;
1141
1142                 if (!of_device_is_available(child))
1143                         continue;
1144                 if (!of_device_is_compatible(child, compat))
1145                         continue;
1146
1147                 if (validate_parent_available(child))
1148                         continue;
1149
1150                 irq = a10_get_irq_mask(child);
1151                 if (irq < 0)
1152                         continue;
1153
1154                 /* Get matching node and check for valid result */
1155                 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1156                 if (IS_ERR_OR_NULL(pdev_id))
1157                         continue;
1158
1159                 /* Validate private data pointer before dereferencing */
1160                 prv = pdev_id->data;
1161                 if (!prv)
1162                         continue;
1163
1164                 altr_init_a10_ecc_block(child, BIT(irq),
1165                                         prv->ecc_enable_mask, 0);
1166         }
1167
1168         of_node_put(np);
1169         return 0;
1170 }
1171
1172 /*********************** SDRAM EDAC Device Functions *********************/
1173
1174 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1175
1176 static const struct edac_device_prv_data s10_sdramecc_data = {
1177         .setup = altr_check_ecc_deps,
1178         .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1179         .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1180         .ecc_enable_mask = ALTR_S10_ECC_EN,
1181         .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1182         .ce_set_mask = ALTR_S10_ECC_TSERRA,
1183         .ue_set_mask = ALTR_S10_ECC_TDERRA,
1184         .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1185         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1186         .inject_fops = &altr_edac_a10_device_inject_fops,
1187 };
1188 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
1189
1190 /*********************** OCRAM EDAC Device Functions *********************/
1191
1192 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1193
1194 static void *ocram_alloc_mem(size_t size, void **other)
1195 {
1196         struct device_node *np;
1197         struct gen_pool *gp;
1198         void *sram_addr;
1199
1200         np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1201         if (!np)
1202                 return NULL;
1203
1204         gp = of_gen_pool_get(np, "iram", 0);
1205         of_node_put(np);
1206         if (!gp)
1207                 return NULL;
1208
1209         sram_addr = (void *)gen_pool_alloc(gp, size);
1210         if (!sram_addr)
1211                 return NULL;
1212
1213         memset(sram_addr, 0, size);
1214         /* Ensure data is written out */
1215         wmb();
1216
1217         /* Remember this handle for freeing  later */
1218         *other = gp;
1219
1220         return sram_addr;
1221 }
1222
1223 static void ocram_free_mem(void *p, size_t size, void *other)
1224 {
1225         gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1226 }
1227
1228 static const struct edac_device_prv_data ocramecc_data = {
1229         .setup = altr_check_ecc_deps,
1230         .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1231         .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1232         .alloc_mem = ocram_alloc_mem,
1233         .free_mem = ocram_free_mem,
1234         .ecc_enable_mask = ALTR_OCR_ECC_EN,
1235         .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1236         .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1237         .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1238         .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1239         .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1240         .inject_fops = &altr_edac_device_inject_fops,
1241 };
1242
1243 static int __maybe_unused
1244 altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1245 {
1246         void __iomem  *base = device->base;
1247         int ret;
1248
1249         ret = altr_check_ecc_deps(device);
1250         if (ret)
1251                 return ret;
1252
1253         /* Verify OCRAM has been initialized */
1254         if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1255                            (base + ALTR_A10_ECC_INITSTAT_OFST)))
1256                 return -ENODEV;
1257
1258         /* Enable IRQ on Single Bit Error */
1259         writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1260         /* Ensure all writes complete */
1261         wmb();
1262
1263         return 0;
1264 }
1265
1266 static const struct edac_device_prv_data a10_ocramecc_data = {
1267         .setup = altr_check_ocram_deps_init,
1268         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1269         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1270         .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1271         .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1272         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1273         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1274         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1275         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1276         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1277         .inject_fops = &altr_edac_a10_device_inject2_fops,
1278         /*
1279          * OCRAM panic on uncorrectable error because sleep/resume
1280          * functions and FPGA contents are stored in OCRAM. Prefer
1281          * a kernel panic over executing/loading corrupted data.
1282          */
1283         .panic = true,
1284 };
1285
1286 #endif  /* CONFIG_EDAC_ALTERA_OCRAM */
1287
1288 /********************* L2 Cache EDAC Device Functions ********************/
1289
1290 #ifdef CONFIG_EDAC_ALTERA_L2C
1291
1292 static void *l2_alloc_mem(size_t size, void **other)
1293 {
1294         struct device *dev = *other;
1295         void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1296
1297         if (!ptemp)
1298                 return NULL;
1299
1300         /* Make sure everything is written out */
1301         wmb();
1302
1303         /*
1304          * Clean all cache levels up to LoC (includes L2)
1305          * This ensures the corrupted data is written into
1306          * L2 cache for readback test (which causes ECC error).
1307          */
1308         flush_cache_all();
1309
1310         return ptemp;
1311 }
1312
1313 static void l2_free_mem(void *p, size_t size, void *other)
1314 {
1315         struct device *dev = other;
1316
1317         if (dev && p)
1318                 devm_kfree(dev, p);
1319 }
1320
1321 /*
1322  * altr_l2_check_deps()
1323  *      Test for L2 cache ECC dependencies upon entry because
1324  *      platform specific startup should have initialized the L2
1325  *      memory and enabled the ECC.
1326  *      Bail if ECC is not enabled.
1327  *      Note that L2 Cache Enable is forced at build time.
1328  */
1329 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1330 {
1331         void __iomem *base = device->base;
1332         const struct edac_device_prv_data *prv = device->data;
1333
1334         if ((readl(base) & prv->ecc_enable_mask) ==
1335              prv->ecc_enable_mask)
1336                 return 0;
1337
1338         edac_printk(KERN_ERR, EDAC_DEVICE,
1339                     "L2: No ECC present, or ECC disabled\n");
1340         return -ENODEV;
1341 }
1342
1343 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1344 {
1345         struct altr_edac_device_dev *dci = dev_id;
1346
1347         if (irq == dci->sb_irq) {
1348                 regmap_write(dci->edac->ecc_mgr_map,
1349                              A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1350                              A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1351                 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1352
1353                 return IRQ_HANDLED;
1354         } else if (irq == dci->db_irq) {
1355                 regmap_write(dci->edac->ecc_mgr_map,
1356                              A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1357                              A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1358                 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1359                 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1360
1361                 return IRQ_HANDLED;
1362         }
1363
1364         WARN_ON(1);
1365
1366         return IRQ_NONE;
1367 }
1368
1369 static const struct edac_device_prv_data l2ecc_data = {
1370         .setup = altr_l2_check_deps,
1371         .ce_clear_mask = 0,
1372         .ue_clear_mask = 0,
1373         .alloc_mem = l2_alloc_mem,
1374         .free_mem = l2_free_mem,
1375         .ecc_enable_mask = ALTR_L2_ECC_EN,
1376         .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1377         .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1378         .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1379         .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1380         .inject_fops = &altr_edac_device_inject_fops,
1381 };
1382
1383 static const struct edac_device_prv_data a10_l2ecc_data = {
1384         .setup = altr_l2_check_deps,
1385         .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1386         .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1387         .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1388         .alloc_mem = l2_alloc_mem,
1389         .free_mem = l2_free_mem,
1390         .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1391         .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1392         .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1393         .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1394         .ecc_irq_handler = altr_edac_a10_l2_irq,
1395         .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1396         .inject_fops = &altr_edac_device_inject_fops,
1397 };
1398
1399 #endif  /* CONFIG_EDAC_ALTERA_L2C */
1400
1401 /********************* Ethernet Device Functions ********************/
1402
1403 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1404
1405 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1406 {
1407         int ret;
1408
1409         ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1410         if (ret)
1411                 return ret;
1412
1413         return altr_check_ecc_deps(dev);
1414 }
1415
1416 static const struct edac_device_prv_data a10_enetecc_data = {
1417         .setup = socfpga_init_ethernet_ecc,
1418         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1419         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1420         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1421         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1422         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1423         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1424         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1425         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1426         .inject_fops = &altr_edac_a10_device_inject2_fops,
1427 };
1428
1429 #endif  /* CONFIG_EDAC_ALTERA_ETHERNET */
1430
1431 /********************** NAND Device Functions **********************/
1432
1433 #ifdef CONFIG_EDAC_ALTERA_NAND
1434
1435 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1436 {
1437         int ret;
1438
1439         ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1440         if (ret)
1441                 return ret;
1442
1443         return altr_check_ecc_deps(device);
1444 }
1445
1446 static const struct edac_device_prv_data a10_nandecc_data = {
1447         .setup = socfpga_init_nand_ecc,
1448         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1449         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1450         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1451         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1452         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1453         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1454         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1455         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1456         .inject_fops = &altr_edac_a10_device_inject_fops,
1457 };
1458
1459 #endif  /* CONFIG_EDAC_ALTERA_NAND */
1460
1461 /********************** DMA Device Functions **********************/
1462
1463 #ifdef CONFIG_EDAC_ALTERA_DMA
1464
1465 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1466 {
1467         int ret;
1468
1469         ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1470         if (ret)
1471                 return ret;
1472
1473         return altr_check_ecc_deps(device);
1474 }
1475
1476 static const struct edac_device_prv_data a10_dmaecc_data = {
1477         .setup = socfpga_init_dma_ecc,
1478         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1479         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1480         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1481         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1482         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1483         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1484         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1485         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1486         .inject_fops = &altr_edac_a10_device_inject_fops,
1487 };
1488
1489 #endif  /* CONFIG_EDAC_ALTERA_DMA */
1490
1491 /********************** USB Device Functions **********************/
1492
1493 #ifdef CONFIG_EDAC_ALTERA_USB
1494
1495 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1496 {
1497         int ret;
1498
1499         ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1500         if (ret)
1501                 return ret;
1502
1503         return altr_check_ecc_deps(device);
1504 }
1505
1506 static const struct edac_device_prv_data a10_usbecc_data = {
1507         .setup = socfpga_init_usb_ecc,
1508         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1509         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1510         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1511         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1512         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1513         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1514         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1515         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1516         .inject_fops = &altr_edac_a10_device_inject2_fops,
1517 };
1518
1519 #endif  /* CONFIG_EDAC_ALTERA_USB */
1520
1521 /********************** QSPI Device Functions **********************/
1522
1523 #ifdef CONFIG_EDAC_ALTERA_QSPI
1524
1525 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1526 {
1527         int ret;
1528
1529         ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1530         if (ret)
1531                 return ret;
1532
1533         return altr_check_ecc_deps(device);
1534 }
1535
1536 static const struct edac_device_prv_data a10_qspiecc_data = {
1537         .setup = socfpga_init_qspi_ecc,
1538         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1539         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1540         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1541         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1542         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1543         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1544         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1545         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1546         .inject_fops = &altr_edac_a10_device_inject_fops,
1547 };
1548
1549 #endif  /* CONFIG_EDAC_ALTERA_QSPI */
1550
1551 /********************* SDMMC Device Functions **********************/
1552
1553 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1554
1555 static const struct edac_device_prv_data a10_sdmmceccb_data;
1556 static int altr_portb_setup(struct altr_edac_device_dev *device)
1557 {
1558         struct edac_device_ctl_info *dci;
1559         struct altr_edac_device_dev *altdev;
1560         char *ecc_name = "sdmmcb-ecc";
1561         int edac_idx, rc;
1562         struct device_node *np;
1563         const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1564
1565         rc = altr_check_ecc_deps(device);
1566         if (rc)
1567                 return rc;
1568
1569         np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1570         if (!np) {
1571                 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1572                 return -ENODEV;
1573         }
1574
1575         /* Create the PortB EDAC device */
1576         edac_idx = edac_device_alloc_index();
1577         dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1578                                          ecc_name, 1, 0, NULL, 0, edac_idx);
1579         if (!dci) {
1580                 edac_printk(KERN_ERR, EDAC_DEVICE,
1581                             "%s: Unable to allocate PortB EDAC device\n",
1582                             ecc_name);
1583                 return -ENOMEM;
1584         }
1585
1586         /* Initialize the PortB EDAC device structure from PortA structure */
1587         altdev = dci->pvt_info;
1588         *altdev = *device;
1589
1590         if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1591                 return -ENOMEM;
1592
1593         /* Update PortB specific values */
1594         altdev->edac_dev_name = ecc_name;
1595         altdev->edac_idx = edac_idx;
1596         altdev->edac_dev = dci;
1597         altdev->data = prv;
1598         dci->dev = &altdev->ddev;
1599         dci->ctl_name = "Altera ECC Manager";
1600         dci->mod_name = ecc_name;
1601         dci->dev_name = ecc_name;
1602
1603         /* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */
1604 #ifdef CONFIG_ARCH_STRATIX10
1605         altdev->sb_irq = irq_of_parse_and_map(np, 1);
1606 #else
1607         altdev->sb_irq = irq_of_parse_and_map(np, 2);
1608 #endif
1609         if (!altdev->sb_irq) {
1610                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1611                 rc = -ENODEV;
1612                 goto err_release_group_1;
1613         }
1614         rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1615                               prv->ecc_irq_handler,
1616                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1617                               ecc_name, altdev);
1618         if (rc) {
1619                 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1620                 goto err_release_group_1;
1621         }
1622
1623 #ifdef CONFIG_ARCH_STRATIX10
1624         /* Use IRQ to determine SError origin instead of assigning IRQ */
1625         rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1626         if (rc) {
1627                 edac_printk(KERN_ERR, EDAC_DEVICE,
1628                             "Error PortB DBIRQ alloc\n");
1629                 goto err_release_group_1;
1630         }
1631 #else
1632         altdev->db_irq = irq_of_parse_and_map(np, 3);
1633         if (!altdev->db_irq) {
1634                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1635                 rc = -ENODEV;
1636                 goto err_release_group_1;
1637         }
1638         rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1639                               prv->ecc_irq_handler,
1640                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1641                               ecc_name, altdev);
1642         if (rc) {
1643                 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1644                 goto err_release_group_1;
1645         }
1646 #endif
1647
1648         rc = edac_device_add_device(dci);
1649         if (rc) {
1650                 edac_printk(KERN_ERR, EDAC_DEVICE,
1651                             "edac_device_add_device portB failed\n");
1652                 rc = -ENOMEM;
1653                 goto err_release_group_1;
1654         }
1655         altr_create_edacdev_dbgfs(dci, prv);
1656
1657         list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1658
1659         devres_remove_group(&altdev->ddev, altr_portb_setup);
1660
1661         return 0;
1662
1663 err_release_group_1:
1664         edac_device_free_ctl_info(dci);
1665         devres_release_group(&altdev->ddev, altr_portb_setup);
1666         edac_printk(KERN_ERR, EDAC_DEVICE,
1667                     "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1668         return rc;
1669 }
1670
1671 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1672 {
1673         int rc = -ENODEV;
1674         struct device_node *child;
1675
1676         child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1677         if (!child)
1678                 return -ENODEV;
1679
1680         if (!of_device_is_available(child))
1681                 goto exit;
1682
1683         if (validate_parent_available(child))
1684                 goto exit;
1685
1686         /* Init portB */
1687         rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1688                                      a10_sdmmceccb_data.ecc_enable_mask, 1);
1689         if (rc)
1690                 goto exit;
1691
1692         /* Setup portB */
1693         return altr_portb_setup(device);
1694
1695 exit:
1696         of_node_put(child);
1697         return rc;
1698 }
1699
1700 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1701 {
1702         struct altr_edac_device_dev *ad = dev_id;
1703         void __iomem  *base = ad->base;
1704         const struct edac_device_prv_data *priv = ad->data;
1705
1706         if (irq == ad->sb_irq) {
1707                 writel(priv->ce_clear_mask,
1708                        base + ALTR_A10_ECC_INTSTAT_OFST);
1709                 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1710                 return IRQ_HANDLED;
1711         } else if (irq == ad->db_irq) {
1712                 writel(priv->ue_clear_mask,
1713                        base + ALTR_A10_ECC_INTSTAT_OFST);
1714                 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1715                 return IRQ_HANDLED;
1716         }
1717
1718         WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1719
1720         return IRQ_NONE;
1721 }
1722
1723 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1724         .setup = socfpga_init_sdmmc_ecc,
1725         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1726         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1727         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1728         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1729         .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1730         .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1731         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1732         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1733         .inject_fops = &altr_edac_a10_device_inject_fops,
1734 };
1735
1736 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1737         .setup = socfpga_init_sdmmc_ecc,
1738         .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1739         .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1740         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1741         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1742         .ce_set_mask = ALTR_A10_ECC_TSERRB,
1743         .ue_set_mask = ALTR_A10_ECC_TDERRB,
1744         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1745         .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1746         .inject_fops = &altr_edac_a10_device_inject_fops,
1747 };
1748
1749 #endif  /* CONFIG_EDAC_ALTERA_SDMMC */
1750
1751 /********************* Arria10 EDAC Device Functions *************************/
1752 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1753 #ifdef CONFIG_EDAC_ALTERA_L2C
1754         { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1755 #endif
1756 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1757         { .compatible = "altr,socfpga-a10-ocram-ecc",
1758           .data = &a10_ocramecc_data },
1759 #endif
1760 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1761         { .compatible = "altr,socfpga-eth-mac-ecc",
1762           .data = &a10_enetecc_data },
1763 #endif
1764 #ifdef CONFIG_EDAC_ALTERA_NAND
1765         { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1766 #endif
1767 #ifdef CONFIG_EDAC_ALTERA_DMA
1768         { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1769 #endif
1770 #ifdef CONFIG_EDAC_ALTERA_USB
1771         { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1772 #endif
1773 #ifdef CONFIG_EDAC_ALTERA_QSPI
1774         { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1775 #endif
1776 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1777         { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1778 #endif
1779 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1780         { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1781 #endif
1782         {},
1783 };
1784 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1785
1786 /*
1787  * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1788  * because 2 IRQs are shared among the all ECC peripherals. The ECC
1789  * manager manages the IRQs and the children.
1790  * Based on xgene_edac.c peripheral code.
1791  */
1792
1793 static ssize_t altr_edac_a10_device_trig(struct file *file,
1794                                          const char __user *user_buf,
1795                                          size_t count, loff_t *ppos)
1796 {
1797         struct edac_device_ctl_info *edac_dci = file->private_data;
1798         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1799         const struct edac_device_prv_data *priv = drvdata->data;
1800         void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1801         unsigned long flags;
1802         u8 trig_type;
1803
1804         if (!user_buf || get_user(trig_type, user_buf))
1805                 return -EFAULT;
1806
1807         local_irq_save(flags);
1808         if (trig_type == ALTR_UE_TRIGGER_CHAR)
1809                 writel(priv->ue_set_mask, set_addr);
1810         else
1811                 writel(priv->ce_set_mask, set_addr);
1812
1813         /* Ensure the interrupt test bits are set */
1814         wmb();
1815         local_irq_restore(flags);
1816
1817         return count;
1818 }
1819
1820 /*
1821  * The Stratix10 EDAC Error Injection Functions differ from Arria10
1822  * slightly. A few Arria10 peripherals can use this injection function.
1823  * Inject the error into the memory and then readback to trigger the IRQ.
1824  */
1825 static ssize_t altr_edac_a10_device_trig2(struct file *file,
1826                                           const char __user *user_buf,
1827                                           size_t count, loff_t *ppos)
1828 {
1829         struct edac_device_ctl_info *edac_dci = file->private_data;
1830         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1831         const struct edac_device_prv_data *priv = drvdata->data;
1832         void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1833         unsigned long flags;
1834         u8 trig_type;
1835
1836         if (!user_buf || get_user(trig_type, user_buf))
1837                 return -EFAULT;
1838
1839         local_irq_save(flags);
1840         if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1841                 writel(priv->ue_set_mask, set_addr);
1842         } else {
1843                 /* Setup read/write of 4 bytes */
1844                 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1845                 /* Setup Address to 0 */
1846                 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1847                 /* Setup accctrl to read & ecc & data override */
1848                 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1849                 /* Kick it. */
1850                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1851                 /* Setup write for single bit change */
1852                 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1853                        drvdata->base + ECC_BLK_WDATA0_OFST);
1854                 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1855                        drvdata->base + ECC_BLK_WDATA1_OFST);
1856                 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1857                        drvdata->base + ECC_BLK_WDATA2_OFST);
1858                 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1859                        drvdata->base + ECC_BLK_WDATA3_OFST);
1860
1861                 /* Copy Read ECC to Write ECC */
1862                 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1863                        drvdata->base + ECC_BLK_WECC0_OFST);
1864                 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1865                        drvdata->base + ECC_BLK_WECC1_OFST);
1866                 /* Setup accctrl to write & ecc override & data override */
1867                 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1868                 /* Kick it. */
1869                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1870                 /* Setup accctrl to read & ecc overwrite & data overwrite */
1871                 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1872                 /* Kick it. */
1873                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1874         }
1875
1876         /* Ensure the interrupt test bits are set */
1877         wmb();
1878         local_irq_restore(flags);
1879
1880         return count;
1881 }
1882
1883 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1884 {
1885         int dberr, bit, sm_offset, irq_status;
1886         struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1887         struct irq_chip *chip = irq_desc_get_chip(desc);
1888         int irq = irq_desc_get_irq(desc);
1889         unsigned long bits;
1890
1891         dberr = (irq == edac->db_irq) ? 1 : 0;
1892         sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1893                             A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1894
1895         chained_irq_enter(chip, desc);
1896
1897         regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1898
1899         bits = irq_status;
1900         for_each_set_bit(bit, &bits, 32) {
1901                 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1902                 if (irq)
1903                         generic_handle_irq(irq);
1904         }
1905
1906         chained_irq_exit(chip, desc);
1907 }
1908
1909 static int validate_parent_available(struct device_node *np)
1910 {
1911         struct device_node *parent;
1912         int ret = 0;
1913
1914         /* SDRAM must be present for Linux (implied parent) */
1915         if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1916                 return 0;
1917
1918         /* Ensure parent device is enabled if parent node exists */
1919         parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1920         if (parent && !of_device_is_available(parent))
1921                 ret = -ENODEV;
1922
1923         of_node_put(parent);
1924         return ret;
1925 }
1926
1927 static int get_s10_sdram_edac_resource(struct device_node *np,
1928                                        struct resource *res)
1929 {
1930         struct device_node *parent;
1931         int ret;
1932
1933         parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1934         if (!parent)
1935                 return -ENODEV;
1936
1937         ret = of_address_to_resource(parent, 0, res);
1938         of_node_put(parent);
1939
1940         return ret;
1941 }
1942
1943 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1944                                     struct device_node *np)
1945 {
1946         struct edac_device_ctl_info *dci;
1947         struct altr_edac_device_dev *altdev;
1948         char *ecc_name = (char *)np->name;
1949         struct resource res;
1950         int edac_idx;
1951         int rc = 0;
1952         const struct edac_device_prv_data *prv;
1953         /* Get matching node and check for valid result */
1954         const struct of_device_id *pdev_id =
1955                 of_match_node(altr_edac_a10_device_of_match, np);
1956         if (IS_ERR_OR_NULL(pdev_id))
1957                 return -ENODEV;
1958
1959         /* Get driver specific data for this EDAC device */
1960         prv = pdev_id->data;
1961         if (IS_ERR_OR_NULL(prv))
1962                 return -ENODEV;
1963
1964         if (validate_parent_available(np))
1965                 return -ENODEV;
1966
1967         if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1968                 return -ENOMEM;
1969
1970         if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1971                 rc = get_s10_sdram_edac_resource(np, &res);
1972         else
1973                 rc = of_address_to_resource(np, 0, &res);
1974
1975         if (rc < 0) {
1976                 edac_printk(KERN_ERR, EDAC_DEVICE,
1977                             "%s: no resource address\n", ecc_name);
1978                 goto err_release_group;
1979         }
1980
1981         edac_idx = edac_device_alloc_index();
1982         dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1983                                          1, ecc_name, 1, 0, NULL, 0,
1984                                          edac_idx);
1985
1986         if (!dci) {
1987                 edac_printk(KERN_ERR, EDAC_DEVICE,
1988                             "%s: Unable to allocate EDAC device\n", ecc_name);
1989                 rc = -ENOMEM;
1990                 goto err_release_group;
1991         }
1992
1993         altdev = dci->pvt_info;
1994         dci->dev = edac->dev;
1995         altdev->edac_dev_name = ecc_name;
1996         altdev->edac_idx = edac_idx;
1997         altdev->edac = edac;
1998         altdev->edac_dev = dci;
1999         altdev->data = prv;
2000         altdev->ddev = *edac->dev;
2001         dci->dev = &altdev->ddev;
2002         dci->ctl_name = "Altera ECC Manager";
2003         dci->mod_name = ecc_name;
2004         dci->dev_name = ecc_name;
2005
2006         altdev->base = devm_ioremap_resource(edac->dev, &res);
2007         if (IS_ERR(altdev->base)) {
2008                 rc = PTR_ERR(altdev->base);
2009                 goto err_release_group1;
2010         }
2011
2012         /* Check specific dependencies for the module */
2013         if (altdev->data->setup) {
2014                 rc = altdev->data->setup(altdev);
2015                 if (rc)
2016                         goto err_release_group1;
2017         }
2018
2019         altdev->sb_irq = irq_of_parse_and_map(np, 0);
2020         if (!altdev->sb_irq) {
2021                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
2022                 rc = -ENODEV;
2023                 goto err_release_group1;
2024         }
2025         rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
2026                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
2027                               ecc_name, altdev);
2028         if (rc) {
2029                 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
2030                 goto err_release_group1;
2031         }
2032
2033 #ifdef CONFIG_ARCH_STRATIX10
2034         /* Use IRQ to determine SError origin instead of assigning IRQ */
2035         rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
2036         if (rc) {
2037                 edac_printk(KERN_ERR, EDAC_DEVICE,
2038                             "Unable to parse DB IRQ index\n");
2039                 goto err_release_group1;
2040         }
2041 #else
2042         altdev->db_irq = irq_of_parse_and_map(np, 1);
2043         if (!altdev->db_irq) {
2044                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
2045                 rc = -ENODEV;
2046                 goto err_release_group1;
2047         }
2048         rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
2049                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
2050                               ecc_name, altdev);
2051         if (rc) {
2052                 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
2053                 goto err_release_group1;
2054         }
2055 #endif
2056
2057         rc = edac_device_add_device(dci);
2058         if (rc) {
2059                 dev_err(edac->dev, "edac_device_add_device failed\n");
2060                 rc = -ENOMEM;
2061                 goto err_release_group1;
2062         }
2063
2064         altr_create_edacdev_dbgfs(dci, prv);
2065
2066         list_add(&altdev->next, &edac->a10_ecc_devices);
2067
2068         devres_remove_group(edac->dev, altr_edac_a10_device_add);
2069
2070         return 0;
2071
2072 err_release_group1:
2073         edac_device_free_ctl_info(dci);
2074 err_release_group:
2075         devres_release_group(edac->dev, NULL);
2076         edac_printk(KERN_ERR, EDAC_DEVICE,
2077                     "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
2078
2079         return rc;
2080 }
2081
2082 static void a10_eccmgr_irq_mask(struct irq_data *d)
2083 {
2084         struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2085
2086         regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2087                      BIT(d->hwirq));
2088 }
2089
2090 static void a10_eccmgr_irq_unmask(struct irq_data *d)
2091 {
2092         struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2093
2094         regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2095                      BIT(d->hwirq));
2096 }
2097
2098 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2099                                     irq_hw_number_t hwirq)
2100 {
2101         struct altr_arria10_edac *edac = d->host_data;
2102
2103         irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2104         irq_set_chip_data(irq, edac);
2105         irq_set_noprobe(irq);
2106
2107         return 0;
2108 }
2109
2110 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2111         .map = a10_eccmgr_irqdomain_map,
2112         .xlate = irq_domain_xlate_twocell,
2113 };
2114
2115 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2116 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2117
2118 #ifdef CONFIG_ARCH_STRATIX10
2119 /* panic routine issues reboot on non-zero panic_timeout */
2120 extern int panic_timeout;
2121
2122 /*
2123  * The double bit error is handled through SError which is fatal. This is
2124  * called as a panic notifier to printout ECC error info as part of the panic.
2125  */
2126 static int s10_edac_dberr_handler(struct notifier_block *this,
2127                                   unsigned long event, void *ptr)
2128 {
2129         struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2130         int err_addr, dberror;
2131
2132         regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2133                     &dberror);
2134         regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2135         if (dberror & S10_DBE_IRQ_MASK) {
2136                 struct list_head *position;
2137                 struct altr_edac_device_dev *ed;
2138                 struct arm_smccc_res result;
2139
2140                 /* Find the matching DBE in the list of devices */
2141                 list_for_each(position, &edac->a10_ecc_devices) {
2142                         ed = list_entry(position, struct altr_edac_device_dev,
2143                                         next);
2144                         if (!(BIT(ed->db_irq) & dberror))
2145                                 continue;
2146
2147                         writel(ALTR_A10_ECC_DERRPENA,
2148                                ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2149                         err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2150                         regmap_write(edac->ecc_mgr_map,
2151                                      S10_SYSMGR_UE_ADDR_OFST, err_addr);
2152                         edac_printk(KERN_ERR, EDAC_DEVICE,
2153                                     "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2154                                     ed->edac_dev_name, err_addr);
2155                         break;
2156                 }
2157                 /* Notify the System through SMC. Reboot delay = 1 second */
2158                 panic_timeout = 1;
2159                 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2160                               0, 0, &result);
2161         }
2162
2163         return NOTIFY_DONE;
2164 }
2165 #endif
2166
2167 /****************** Arria 10 EDAC Probe Function *********************/
2168 static int altr_edac_a10_probe(struct platform_device *pdev)
2169 {
2170         struct altr_arria10_edac *edac;
2171         struct device_node *child;
2172
2173         edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2174         if (!edac)
2175                 return -ENOMEM;
2176
2177         edac->dev = &pdev->dev;
2178         platform_set_drvdata(pdev, edac);
2179         INIT_LIST_HEAD(&edac->a10_ecc_devices);
2180
2181         if (socfpga_is_a10()) {
2182                 edac->ecc_mgr_map =
2183                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2184                                                         "altr,sysmgr-syscon");
2185         } else {
2186                 struct device_node *sysmgr_np;
2187                 struct resource res;
2188                 uintptr_t base;
2189
2190                 sysmgr_np = of_parse_phandle(pdev->dev.of_node,
2191                                              "altr,sysmgr-syscon", 0);
2192                 if (!sysmgr_np) {
2193                         edac_printk(KERN_ERR, EDAC_DEVICE,
2194                                     "Unable to find altr,sysmgr-syscon\n");
2195                         return -ENODEV;
2196                 }
2197
2198                 if (of_address_to_resource(sysmgr_np, 0, &res))
2199                         return -ENOMEM;
2200
2201                 /* Need physical address for SMCC call */
2202                 base = res.start;
2203
2204                 edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL,
2205                                                      (void *)base,
2206                                                      &s10_sdram_regmap_cfg);
2207         }
2208
2209         if (IS_ERR(edac->ecc_mgr_map)) {
2210                 edac_printk(KERN_ERR, EDAC_DEVICE,
2211                             "Unable to get syscon altr,sysmgr-syscon\n");
2212                 return PTR_ERR(edac->ecc_mgr_map);
2213         }
2214
2215         edac->irq_chip.name = pdev->dev.of_node->name;
2216         edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2217         edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2218         edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2219                                              &a10_eccmgr_ic_ops, edac);
2220         if (!edac->domain) {
2221                 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2222                 return -ENOMEM;
2223         }
2224
2225         edac->sb_irq = platform_get_irq(pdev, 0);
2226         if (edac->sb_irq < 0) {
2227                 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2228                 return edac->sb_irq;
2229         }
2230
2231         irq_set_chained_handler_and_data(edac->sb_irq,
2232                                          altr_edac_a10_irq_handler,
2233                                          edac);
2234
2235 #ifdef CONFIG_ARCH_STRATIX10
2236         {
2237                 int dberror, err_addr;
2238
2239                 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2240                 atomic_notifier_chain_register(&panic_notifier_list,
2241                                                &edac->panic_notifier);
2242
2243                 /* Printout a message if uncorrectable error previously. */
2244                 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2245                             &dberror);
2246                 if (dberror) {
2247                         regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2248                                     &err_addr);
2249                         edac_printk(KERN_ERR, EDAC_DEVICE,
2250                                     "Previous Boot UE detected[0x%X] @ 0x%X\n",
2251                                     dberror, err_addr);
2252                         /* Reset the sticky registers */
2253                         regmap_write(edac->ecc_mgr_map,
2254                                      S10_SYSMGR_UE_VAL_OFST, 0);
2255                         regmap_write(edac->ecc_mgr_map,
2256                                      S10_SYSMGR_UE_ADDR_OFST, 0);
2257                 }
2258         }
2259 #else
2260         edac->db_irq = platform_get_irq(pdev, 1);
2261         if (edac->db_irq < 0) {
2262                 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2263                 return edac->db_irq;
2264         }
2265         irq_set_chained_handler_and_data(edac->db_irq,
2266                                          altr_edac_a10_irq_handler, edac);
2267 #endif
2268
2269         for_each_child_of_node(pdev->dev.of_node, child) {
2270                 if (!of_device_is_available(child))
2271                         continue;
2272
2273                 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
2274                     of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
2275                     of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
2276                     of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
2277                     of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
2278                     of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
2279                     of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
2280 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2281                     of_device_is_compatible(child, "altr,sdram-edac-s10") ||
2282 #endif
2283                     of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
2284
2285                         altr_edac_a10_device_add(edac, child);
2286
2287 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2288                 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2289                         of_platform_populate(pdev->dev.of_node,
2290                                              altr_sdram_ctrl_of_match,
2291                                              NULL, &pdev->dev);
2292 #endif
2293         }
2294
2295         return 0;
2296 }
2297
2298 static const struct of_device_id altr_edac_a10_of_match[] = {
2299         { .compatible = "altr,socfpga-a10-ecc-manager" },
2300         { .compatible = "altr,socfpga-s10-ecc-manager" },
2301         {},
2302 };
2303 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2304
2305 static struct platform_driver altr_edac_a10_driver = {
2306         .probe =  altr_edac_a10_probe,
2307         .driver = {
2308                 .name = "socfpga_a10_ecc_manager",
2309                 .of_match_table = altr_edac_a10_of_match,
2310         },
2311 };
2312 module_platform_driver(altr_edac_a10_driver);
2313
2314 MODULE_LICENSE("GPL v2");
2315 MODULE_AUTHOR("Thor Thayer");
2316 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");