drivers/dma/qcom/bam_dma.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14 /*
  15  * QCOM BAM DMA engine driver
  16  *
  17  * QCOM BAM DMA blocks are distributed amongst a number of the on-chip
  18  * peripherals on the MSM 8x74.  The configuration of the channels are dependent
  19  * on the way they are hard wired to that specific peripheral.  The peripheral
  20  * device tree entries specify the configuration of each channel.
  21  *
  22  * The DMA controller requires the use of external memory for storage of the
  23  * hardware descriptors for each channel.  The descriptor FIFO is accessed as a
  24  * circular buffer and operations are managed according to the offset within the
  25  * FIFO.  After pipe/channel reset, all of the pipe registers and internal state
  26  * are back to defaults.
  27  *
  28  * During DMA operations, we write descriptors to the FIFO, being careful to
  29  * handle wrapping and then write the last FIFO offset to that channel's
  30  * P_EVNT_REG register to kick off the transaction.  The P_SW_OFSTS register
  31  * indicates the current FIFO offset that is being processed, so there is some
  32  * indication of where the hardware is currently working.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/io.h>
  37 #include <linux/init.h>
  38 #include <linux/slab.h>
  39 #include <linux/module.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/scatterlist.h>
  43 #include <linux/device.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/of.h>
  46 #include <linux/of_address.h>
  47 #include <linux/of_irq.h>
  48 #include <linux/of_dma.h>
  49 #include <linux/circ_buf.h>
  50 #include <linux/clk.h>
  51 #include <linux/dmaengine.h>
  52 #include <linux/pm_runtime.h>
  53
  54 #include "../dmaengine.h"
  55 #include "../virt-dma.h"
  56
  57 struct bam_desc_hw {
  58         __le32 addr;            /* Buffer physical address */
  59         __le16 size;            /* Buffer size in bytes */
  60         __le16 flags;
  61 };
  62
  63 #define BAM_DMA_AUTOSUSPEND_DELAY 100
  64
  65 #define DESC_FLAG_INT BIT(15)
  66 #define DESC_FLAG_EOT BIT(14)
  67 #define DESC_FLAG_EOB BIT(13)
  68 #define DESC_FLAG_NWD BIT(12)
  69 #define DESC_FLAG_CMD BIT(11)
  70
  71 struct bam_async_desc {
  72         struct virt_dma_desc vd;
  73
  74         u32 num_desc;
  75         u32 xfer_len;
  76
  77         /* transaction flags, EOT|EOB|NWD */
  78         u16 flags;
  79
  80         struct bam_desc_hw *curr_desc;
  81
  82         /* list node for the desc in the bam_chan list of descriptors */
  83         struct list_head desc_node;
  84         enum dma_transfer_direction dir;
  85         size_t length;
  86         struct bam_desc_hw desc[0];
  87 };
  88
  89 enum bam_reg {
  90         BAM_CTRL,
  91         BAM_REVISION,
  92         BAM_NUM_PIPES,
  93         BAM_DESC_CNT_TRSHLD,
  94         BAM_IRQ_SRCS,
  95         BAM_IRQ_SRCS_MSK,
  96         BAM_IRQ_SRCS_UNMASKED,
  97         BAM_IRQ_STTS,
  98         BAM_IRQ_CLR,
  99         BAM_IRQ_EN,
 100         BAM_CNFG_BITS,
 101         BAM_IRQ_SRCS_EE,
 102         BAM_IRQ_SRCS_MSK_EE,
 103         BAM_P_CTRL,
 104         BAM_P_RST,
 105         BAM_P_HALT,
 106         BAM_P_IRQ_STTS,
 107         BAM_P_IRQ_CLR,
 108         BAM_P_IRQ_EN,
 109         BAM_P_EVNT_DEST_ADDR,
 110         BAM_P_EVNT_REG,
 111         BAM_P_SW_OFSTS,
 112         BAM_P_DATA_FIFO_ADDR,
 113         BAM_P_DESC_FIFO_ADDR,
 114         BAM_P_EVNT_GEN_TRSHLD,
 115         BAM_P_FIFO_SIZES,
 116 };
 117
 118 struct reg_offset_data {
 119         u32 base_offset;
 120         unsigned int pipe_mult, evnt_mult, ee_mult;
 121 };
 122
 123 static const struct reg_offset_data bam_v1_3_reg_info[] = {
 124         [BAM_CTRL]              = { 0x0F80, 0x00, 0x00, 0x00 },
 125         [BAM_REVISION]          = { 0x0F84, 0x00, 0x00, 0x00 },
 126         [BAM_NUM_PIPES]         = { 0x0FBC, 0x00, 0x00, 0x00 },
 127         [BAM_DESC_CNT_TRSHLD]   = { 0x0F88, 0x00, 0x00, 0x00 },
 128         [BAM_IRQ_SRCS]          = { 0x0F8C, 0x00, 0x00, 0x00 },
 129         [BAM_IRQ_SRCS_MSK]      = { 0x0F90, 0x00, 0x00, 0x00 },
 130         [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 },
 131         [BAM_IRQ_STTS]          = { 0x0F94, 0x00, 0x00, 0x00 },
 132         [BAM_IRQ_CLR]           = { 0x0F98, 0x00, 0x00, 0x00 },
 133         [BAM_IRQ_EN]            = { 0x0F9C, 0x00, 0x00, 0x00 },
 134         [BAM_CNFG_BITS]         = { 0x0FFC, 0x00, 0x00, 0x00 },
 135         [BAM_IRQ_SRCS_EE]       = { 0x1800, 0x00, 0x00, 0x80 },
 136         [BAM_IRQ_SRCS_MSK_EE]   = { 0x1804, 0x00, 0x00, 0x80 },
 137         [BAM_P_CTRL]            = { 0x0000, 0x80, 0x00, 0x00 },
 138         [BAM_P_RST]             = { 0x0004, 0x80, 0x00, 0x00 },
 139         [BAM_P_HALT]            = { 0x0008, 0x80, 0x00, 0x00 },
 140         [BAM_P_IRQ_STTS]        = { 0x0010, 0x80, 0x00, 0x00 },
 141         [BAM_P_IRQ_CLR]         = { 0x0014, 0x80, 0x00, 0x00 },
 142         [BAM_P_IRQ_EN]          = { 0x0018, 0x80, 0x00, 0x00 },
 143         [BAM_P_EVNT_DEST_ADDR]  = { 0x102C, 0x00, 0x40, 0x00 },
 144         [BAM_P_EVNT_REG]        = { 0x1018, 0x00, 0x40, 0x00 },
 145         [BAM_P_SW_OFSTS]        = { 0x1000, 0x00, 0x40, 0x00 },
 146         [BAM_P_DATA_FIFO_ADDR]  = { 0x1024, 0x00, 0x40, 0x00 },
 147         [BAM_P_DESC_FIFO_ADDR]  = { 0x101C, 0x00, 0x40, 0x00 },
 148         [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 },
 149         [BAM_P_FIFO_SIZES]      = { 0x1020, 0x00, 0x40, 0x00 },
 150 };
 151
 152 static const struct reg_offset_data bam_v1_4_reg_info[] = {
 153         [BAM_CTRL]              = { 0x0000, 0x00, 0x00, 0x00 },
 154         [BAM_REVISION]          = { 0x0004, 0x00, 0x00, 0x00 },
 155         [BAM_NUM_PIPES]         = { 0x003C, 0x00, 0x00, 0x00 },
 156         [BAM_DESC_CNT_TRSHLD]   = { 0x0008, 0x00, 0x00, 0x00 },
 157         [BAM_IRQ_SRCS]          = { 0x000C, 0x00, 0x00, 0x00 },
 158         [BAM_IRQ_SRCS_MSK]      = { 0x0010, 0x00, 0x00, 0x00 },
 159         [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 },
 160         [BAM_IRQ_STTS]          = { 0x0014, 0x00, 0x00, 0x00 },
 161         [BAM_IRQ_CLR]           = { 0x0018, 0x00, 0x00, 0x00 },
 162         [BAM_IRQ_EN]            = { 0x001C, 0x00, 0x00, 0x00 },
 163         [BAM_CNFG_BITS]         = { 0x007C, 0x00, 0x00, 0x00 },
 164         [BAM_IRQ_SRCS_EE]       = { 0x0800, 0x00, 0x00, 0x80 },
 165         [BAM_IRQ_SRCS_MSK_EE]   = { 0x0804, 0x00, 0x00, 0x80 },
 166         [BAM_P_CTRL]            = { 0x1000, 0x1000, 0x00, 0x00 },
 167         [BAM_P_RST]             = { 0x1004, 0x1000, 0x00, 0x00 },
 168         [BAM_P_HALT]            = { 0x1008, 0x1000, 0x00, 0x00 },
 169         [BAM_P_IRQ_STTS]        = { 0x1010, 0x1000, 0x00, 0x00 },
 170         [BAM_P_IRQ_CLR]         = { 0x1014, 0x1000, 0x00, 0x00 },
 171         [BAM_P_IRQ_EN]          = { 0x1018, 0x1000, 0x00, 0x00 },
 172         [BAM_P_EVNT_DEST_ADDR]  = { 0x182C, 0x00, 0x1000, 0x00 },
 173         [BAM_P_EVNT_REG]        = { 0x1818, 0x00, 0x1000, 0x00 },
 174         [BAM_P_SW_OFSTS]        = { 0x1800, 0x00, 0x1000, 0x00 },
 175         [BAM_P_DATA_FIFO_ADDR]  = { 0x1824, 0x00, 0x1000, 0x00 },
 176         [BAM_P_DESC_FIFO_ADDR]  = { 0x181C, 0x00, 0x1000, 0x00 },
 177         [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 },
 178         [BAM_P_FIFO_SIZES]      = { 0x1820, 0x00, 0x1000, 0x00 },
 179 };
 180
 181 static const struct reg_offset_data bam_v1_7_reg_info[] = {
 182         [BAM_CTRL]              = { 0x00000, 0x00, 0x00, 0x00 },
 183         [BAM_REVISION]          = { 0x01000, 0x00, 0x00, 0x00 },
 184         [BAM_NUM_PIPES]         = { 0x01008, 0x00, 0x00, 0x00 },
 185         [BAM_DESC_CNT_TRSHLD]   = { 0x00008, 0x00, 0x00, 0x00 },
 186         [BAM_IRQ_SRCS]          = { 0x03010, 0x00, 0x00, 0x00 },
 187         [BAM_IRQ_SRCS_MSK]      = { 0x03014, 0x00, 0x00, 0x00 },
 188         [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 },
 189         [BAM_IRQ_STTS]          = { 0x00014, 0x00, 0x00, 0x00 },
 190         [BAM_IRQ_CLR]           = { 0x00018, 0x00, 0x00, 0x00 },
 191         [BAM_IRQ_EN]            = { 0x0001C, 0x00, 0x00, 0x00 },
 192         [BAM_CNFG_BITS]         = { 0x0007C, 0x00, 0x00, 0x00 },
 193         [BAM_IRQ_SRCS_EE]       = { 0x03000, 0x00, 0x00, 0x1000 },
 194         [BAM_IRQ_SRCS_MSK_EE]   = { 0x03004, 0x00, 0x00, 0x1000 },
 195         [BAM_P_CTRL]            = { 0x13000, 0x1000, 0x00, 0x00 },
 196         [BAM_P_RST]             = { 0x13004, 0x1000, 0x00, 0x00 },
 197         [BAM_P_HALT]            = { 0x13008, 0x1000, 0x00, 0x00 },
 198         [BAM_P_IRQ_STTS]        = { 0x13010, 0x1000, 0x00, 0x00 },
 199         [BAM_P_IRQ_CLR]         = { 0x13014, 0x1000, 0x00, 0x00 },
 200         [BAM_P_IRQ_EN]          = { 0x13018, 0x1000, 0x00, 0x00 },
 201         [BAM_P_EVNT_DEST_ADDR]  = { 0x1382C, 0x00, 0x1000, 0x00 },
 202         [BAM_P_EVNT_REG]        = { 0x13818, 0x00, 0x1000, 0x00 },
 203         [BAM_P_SW_OFSTS]        = { 0x13800, 0x00, 0x1000, 0x00 },
 204         [BAM_P_DATA_FIFO_ADDR]  = { 0x13824, 0x00, 0x1000, 0x00 },
 205         [BAM_P_DESC_FIFO_ADDR]  = { 0x1381C, 0x00, 0x1000, 0x00 },
 206         [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 },
 207         [BAM_P_FIFO_SIZES]      = { 0x13820, 0x00, 0x1000, 0x00 },
 208 };
 209
 210 /* BAM CTRL */
 211 #define BAM_SW_RST                      BIT(0)
 212 #define BAM_EN                          BIT(1)
 213 #define BAM_EN_ACCUM                    BIT(4)
 214 #define BAM_TESTBUS_SEL_SHIFT           5
 215 #define BAM_TESTBUS_SEL_MASK            0x3F
 216 #define BAM_DESC_CACHE_SEL_SHIFT        13
 217 #define BAM_DESC_CACHE_SEL_MASK         0x3
 218 #define BAM_CACHED_DESC_STORE           BIT(15)
 219 #define IBC_DISABLE                     BIT(16)
 220
 221 /* BAM REVISION */
 222 #define REVISION_SHIFT          0
 223 #define REVISION_MASK           0xFF
 224 #define NUM_EES_SHIFT           8
 225 #define NUM_EES_MASK            0xF
 226 #define CE_BUFFER_SIZE          BIT(13)
 227 #define AXI_ACTIVE              BIT(14)
 228 #define USE_VMIDMT              BIT(15)
 229 #define SECURED                 BIT(16)
 230 #define BAM_HAS_NO_BYPASS       BIT(17)
 231 #define HIGH_FREQUENCY_BAM      BIT(18)
 232 #define INACTIV_TMRS_EXST       BIT(19)
 233 #define NUM_INACTIV_TMRS        BIT(20)
 234 #define DESC_CACHE_DEPTH_SHIFT  21
 235 #define DESC_CACHE_DEPTH_1      (0 << DESC_CACHE_DEPTH_SHIFT)
 236 #define DESC_CACHE_DEPTH_2      (1 << DESC_CACHE_DEPTH_SHIFT)
 237 #define DESC_CACHE_DEPTH_3      (2 << DESC_CACHE_DEPTH_SHIFT)
 238 #define DESC_CACHE_DEPTH_4      (3 << DESC_CACHE_DEPTH_SHIFT)
 239 #define CMD_DESC_EN             BIT(23)
 240 #define INACTIV_TMR_BASE_SHIFT  24
 241 #define INACTIV_TMR_BASE_MASK   0xFF
 242
 243 /* BAM NUM PIPES */
 244 #define BAM_NUM_PIPES_SHIFT             0
 245 #define BAM_NUM_PIPES_MASK              0xFF
 246 #define PERIPH_NON_PIPE_GRP_SHIFT       16
 247 #define PERIPH_NON_PIP_GRP_MASK         0xFF
 248 #define BAM_NON_PIPE_GRP_SHIFT          24
 249 #define BAM_NON_PIPE_GRP_MASK           0xFF
 250
 251 /* BAM CNFG BITS */
 252 #define BAM_PIPE_CNFG           BIT(2)
 253 #define BAM_FULL_PIPE           BIT(11)
 254 #define BAM_NO_EXT_P_RST        BIT(12)
 255 #define BAM_IBC_DISABLE         BIT(13)
 256 #define BAM_SB_CLK_REQ          BIT(14)
 257 #define BAM_PSM_CSW_REQ         BIT(15)
 258 #define BAM_PSM_P_RES           BIT(16)
 259 #define BAM_AU_P_RES            BIT(17)
 260 #define BAM_SI_P_RES            BIT(18)
 261 #define BAM_WB_P_RES            BIT(19)
 262 #define BAM_WB_BLK_CSW          BIT(20)
 263 #define BAM_WB_CSW_ACK_IDL      BIT(21)
 264 #define BAM_WB_RETR_SVPNT       BIT(22)
 265 #define BAM_WB_DSC_AVL_P_RST    BIT(23)
 266 #define BAM_REG_P_EN            BIT(24)
 267 #define BAM_PSM_P_HD_DATA       BIT(25)
 268 #define BAM_AU_ACCUMED          BIT(26)
 269 #define BAM_CMD_ENABLE          BIT(27)
 270
 271 #define BAM_CNFG_BITS_DEFAULT   (BAM_PIPE_CNFG |        \
 272                                  BAM_NO_EXT_P_RST |     \
 273                                  BAM_IBC_DISABLE |      \
 274                                  BAM_SB_CLK_REQ |       \
 275                                  BAM_PSM_CSW_REQ |      \
 276                                  BAM_PSM_P_RES |        \
 277                                  BAM_AU_P_RES |         \
 278                                  BAM_SI_P_RES |         \
 279                                  BAM_WB_P_RES |         \
 280                                  BAM_WB_BLK_CSW |       \
 281                                  BAM_WB_CSW_ACK_IDL |   \
 282                                  BAM_WB_RETR_SVPNT |    \
 283                                  BAM_WB_DSC_AVL_P_RST | \
 284                                  BAM_REG_P_EN |         \
 285                                  BAM_PSM_P_HD_DATA |    \
 286                                  BAM_AU_ACCUMED |       \
 287                                  BAM_CMD_ENABLE)
 288
 289 /* PIPE CTRL */
 290 #define P_EN                    BIT(1)
 291 #define P_DIRECTION             BIT(3)
 292 #define P_SYS_STRM              BIT(4)
 293 #define P_SYS_MODE              BIT(5)
 294 #define P_AUTO_EOB              BIT(6)
 295 #define P_AUTO_EOB_SEL_SHIFT    7
 296 #define P_AUTO_EOB_SEL_512      (0 << P_AUTO_EOB_SEL_SHIFT)
 297 #define P_AUTO_EOB_SEL_256      (1 << P_AUTO_EOB_SEL_SHIFT)
 298 #define P_AUTO_EOB_SEL_128      (2 << P_AUTO_EOB_SEL_SHIFT)
 299 #define P_AUTO_EOB_SEL_64       (3 << P_AUTO_EOB_SEL_SHIFT)
 300 #define P_PREFETCH_LIMIT_SHIFT  9
 301 #define P_PREFETCH_LIMIT_32     (0 << P_PREFETCH_LIMIT_SHIFT)
 302 #define P_PREFETCH_LIMIT_16     (1 << P_PREFETCH_LIMIT_SHIFT)
 303 #define P_PREFETCH_LIMIT_4      (2 << P_PREFETCH_LIMIT_SHIFT)
 304 #define P_WRITE_NWD             BIT(11)
 305 #define P_LOCK_GROUP_SHIFT      16
 306 #define P_LOCK_GROUP_MASK       0x1F
 307
 308 /* BAM_DESC_CNT_TRSHLD */
 309 #define CNT_TRSHLD              0xffff
 310 #define DEFAULT_CNT_THRSHLD     0x4
 311
 312 /* BAM_IRQ_SRCS */
 313 #define BAM_IRQ                 BIT(31)
 314 #define P_IRQ                   0x7fffffff
 315
 316 /* BAM_IRQ_SRCS_MSK */
 317 #define BAM_IRQ_MSK             BAM_IRQ
 318 #define P_IRQ_MSK               P_IRQ
 319
 320 /* BAM_IRQ_STTS */
 321 #define BAM_TIMER_IRQ           BIT(4)
 322 #define BAM_EMPTY_IRQ           BIT(3)
 323 #define BAM_ERROR_IRQ           BIT(2)
 324 #define BAM_HRESP_ERR_IRQ       BIT(1)
 325
 326 /* BAM_IRQ_CLR */
 327 #define BAM_TIMER_CLR           BIT(4)
 328 #define BAM_EMPTY_CLR           BIT(3)
 329 #define BAM_ERROR_CLR           BIT(2)
 330 #define BAM_HRESP_ERR_CLR       BIT(1)
 331
 332 /* BAM_IRQ_EN */
 333 #define BAM_TIMER_EN            BIT(4)
 334 #define BAM_EMPTY_EN            BIT(3)
 335 #define BAM_ERROR_EN            BIT(2)
 336 #define BAM_HRESP_ERR_EN        BIT(1)
 337
 338 /* BAM_P_IRQ_EN */
 339 #define P_PRCSD_DESC_EN         BIT(0)
 340 #define P_TIMER_EN              BIT(1)
 341 #define P_WAKE_EN               BIT(2)
 342 #define P_OUT_OF_DESC_EN        BIT(3)
 343 #define P_ERR_EN                BIT(4)
 344 #define P_TRNSFR_END_EN         BIT(5)
 345 #define P_DEFAULT_IRQS_EN       (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN)
 346
 347 /* BAM_P_SW_OFSTS */
 348 #define P_SW_OFSTS_MASK         0xffff
 349
 350 #define BAM_DESC_FIFO_SIZE      SZ_32K
 351 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
 352 #define BAM_FIFO_SIZE   (SZ_32K - 8)
 353 #define IS_BUSY(chan)   (CIRC_SPACE(bchan->tail, bchan->head,\
 354                          MAX_DESCRIPTORS + 1) == 0)
 355
 356 struct bam_chan {
 357         struct virt_dma_chan vc;
 358
 359         struct bam_device *bdev;
 360
 361         /* configuration from device tree */
 362         u32 id;
 363
 364         /* runtime configuration */
 365         struct dma_slave_config slave;
 366
 367         /* fifo storage */
 368         struct bam_desc_hw *fifo_virt;
 369         dma_addr_t fifo_phys;
 370
 371         /* fifo markers */
 372         unsigned short head;            /* start of active descriptor entries */
 373         unsigned short tail;            /* end of active descriptor entries */
 374
 375         unsigned int initialized;       /* is the channel hw initialized? */
 376         unsigned int paused;            /* is the channel paused? */
 377         unsigned int reconfigure;       /* new slave config? */
 378         /* list of descriptors currently processed */
 379         struct list_head desc_list;
 380
 381         struct list_head node;
 382 };
 383
 384 static inline struct bam_chan *to_bam_chan(struct dma_chan *common)
 385 {
 386         return container_of(common, struct bam_chan, vc.chan);
 387 }
 388
 389 struct bam_device {
 390         void __iomem *regs;
 391         struct device *dev;
 392         struct dma_device common;
 393         struct device_dma_parameters dma_parms;
 394         struct bam_chan *channels;
 395         u32 num_channels;
 396
 397         /* execution environment ID, from DT */
 398         u32 ee;
 399         bool controlled_remotely;
 400
 401         const struct reg_offset_data *layout;
 402
 403         struct clk *bamclk;
 404         int irq;
 405
 406         /* dma start transaction tasklet */
 407         struct tasklet_struct task;
 408 };
 409
 410 /**
 411  * bam_addr - returns BAM register address
 412  * @bdev: bam device
 413  * @pipe: pipe instance (ignored when register doesn't have multiple instances)
 414  * @reg:  register enum
 415  */
 416 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe,
 417                 enum bam_reg reg)
 418 {
 419         const struct reg_offset_data r = bdev->layout[reg];
 420
 421         return bdev->regs + r.base_offset +
 422                 r.pipe_mult * pipe +
 423                 r.evnt_mult * pipe +
 424                 r.ee_mult * bdev->ee;
 425 }
 426
 427 /**
 428  * bam_reset_channel - Reset individual BAM DMA channel
 429  * @bchan: bam channel
 430  *
 431  * This function resets a specific BAM channel
 432  */
 433 static void bam_reset_channel(struct bam_chan *bchan)
 434 {
 435         struct bam_device *bdev = bchan->bdev;
 436
 437         lockdep_assert_held(&bchan->vc.lock);
 438
 439         /* reset channel */
 440         writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST));
 441         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST));
 442
 443         /* don't allow cpu to reorder BAM register accesses done after this */
 444         wmb();
 445
 446         /* make sure hw is initialized when channel is used the first time  */
 447         bchan->initialized = 0;
 448 }
 449
 450 /**
 451  * bam_chan_init_hw - Initialize channel hardware
 452  * @bchan: bam channel
 453  *
 454  * This function resets and initializes the BAM channel
 455  */
 456 static void bam_chan_init_hw(struct bam_chan *bchan,
 457         enum dma_transfer_direction dir)
 458 {
 459         struct bam_device *bdev = bchan->bdev;
 460         u32 val;
 461
 462         /* Reset the channel to clear internal state of the FIFO */
 463         bam_reset_channel(bchan);
 464
 465         /*
 466          * write out 8 byte aligned address.  We have enough space for this
 467          * because we allocated 1 more descriptor (8 bytes) than we can use
 468          */
 469         writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
 470                         bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
 471         writel_relaxed(BAM_FIFO_SIZE,
 472                         bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
 473
 474         /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */
 475         writel_relaxed(P_DEFAULT_IRQS_EN,
 476                         bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
 477
 478         /* unmask the specific pipe and EE combo */
 479         val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 480         val |= BIT(bchan->id);
 481         writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 482
 483         /* don't allow cpu to reorder the channel enable done below */
 484         wmb();
 485
 486         /* set fixed direction and mode, then enable channel */
 487         val = P_EN | P_SYS_MODE;
 488         if (dir == DMA_DEV_TO_MEM)
 489                 val |= P_DIRECTION;
 490
 491         writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL));
 492
 493         bchan->initialized = 1;
 494
 495         /* init FIFO pointers */
 496         bchan->head = 0;
 497         bchan->tail = 0;
 498 }
 499
 500 /**
 501  * bam_alloc_chan - Allocate channel resources for DMA channel.
 502  * @chan: specified channel
 503  *
 504  * This function allocates the FIFO descriptor memory
 505  */
 506 static int bam_alloc_chan(struct dma_chan *chan)
 507 {
 508         struct bam_chan *bchan = to_bam_chan(chan);
 509         struct bam_device *bdev = bchan->bdev;
 510
 511         if (bchan->fifo_virt)
 512                 return 0;
 513
 514         /* allocate FIFO descriptor space, but only if necessary */
 515         bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE,
 516                                         &bchan->fifo_phys, GFP_KERNEL);
 517
 518         if (!bchan->fifo_virt) {
 519                 dev_err(bdev->dev, "Failed to allocate desc fifo\n");
 520                 return -ENOMEM;
 521         }
 522
 523         return 0;
 524 }
 525
 526 /**
 527  * bam_free_chan - Frees dma resources associated with specific channel
 528  * @chan: specified channel
 529  *
 530  * Free the allocated fifo descriptor memory and channel resources
 531  *
 532  */
 533 static void bam_free_chan(struct dma_chan *chan)
 534 {
 535         struct bam_chan *bchan = to_bam_chan(chan);
 536         struct bam_device *bdev = bchan->bdev;
 537         u32 val;
 538         unsigned long flags;
 539         int ret;
 540
 541         ret = pm_runtime_get_sync(bdev->dev);
 542         if (ret < 0)
 543                 return;
 544
 545         vchan_free_chan_resources(to_virt_chan(chan));
 546
 547         if (!list_empty(&bchan->desc_list)) {
 548                 dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
 549                 goto err;
 550         }
 551
 552         spin_lock_irqsave(&bchan->vc.lock, flags);
 553         bam_reset_channel(bchan);
 554         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 555
 556         dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt,
 557                     bchan->fifo_phys);
 558         bchan->fifo_virt = NULL;
 559
 560         /* mask irq for pipe/channel */
 561         val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 562         val &= ~BIT(bchan->id);
 563         writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 564
 565         /* disable irq */
 566         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
 567
 568 err:
 569         pm_runtime_mark_last_busy(bdev->dev);
 570         pm_runtime_put_autosuspend(bdev->dev);
 571 }
 572
 573 /**
 574  * bam_slave_config - set slave configuration for channel
 575  * @chan: dma channel
 576  * @cfg: slave configuration
 577  *
 578  * Sets slave configuration for channel
 579  *
 580  */
 581 static int bam_slave_config(struct dma_chan *chan,
 582                             struct dma_slave_config *cfg)
 583 {
 584         struct bam_chan *bchan = to_bam_chan(chan);
 585         unsigned long flag;
 586
 587         spin_lock_irqsave(&bchan->vc.lock, flag);
 588         memcpy(&bchan->slave, cfg, sizeof(*cfg));
 589         bchan->reconfigure = 1;
 590         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 591
 592         return 0;
 593 }
 594
 595 /**
 596  * bam_prep_slave_sg - Prep slave sg transaction
 597  *
 598  * @chan: dma channel
 599  * @sgl: scatter gather list
 600  * @sg_len: length of sg
 601  * @direction: DMA transfer direction
 602  * @flags: DMA flags
 603  * @context: transfer context (unused)
 604  */
 605 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan,
 606         struct scatterlist *sgl, unsigned int sg_len,
 607         enum dma_transfer_direction direction, unsigned long flags,
 608         void *context)
 609 {
 610         struct bam_chan *bchan = to_bam_chan(chan);
 611         struct bam_device *bdev = bchan->bdev;
 612         struct bam_async_desc *async_desc;
 613         struct scatterlist *sg;
 614         u32 i;
 615         struct bam_desc_hw *desc;
 616         unsigned int num_alloc = 0;
 617
 618
 619         if (!is_slave_direction(direction)) {
 620                 dev_err(bdev->dev, "invalid dma direction\n");
 621                 return NULL;
 622         }
 623
 624         /* calculate number of required entries */
 625         for_each_sg(sgl, sg, sg_len, i)
 626                 num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_FIFO_SIZE);
 627
 628         /* allocate enough room to accomodate the number of entries */
 629         async_desc = kzalloc(sizeof(*async_desc) +
 630                         (num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT);
 631
 632         if (!async_desc)
 633                 goto err_out;
 634
 635         if (flags & DMA_PREP_FENCE)
 636                 async_desc->flags |= DESC_FLAG_NWD;
 637
 638         if (flags & DMA_PREP_INTERRUPT)
 639                 async_desc->flags |= DESC_FLAG_EOT;
 640
 641         async_desc->num_desc = num_alloc;
 642         async_desc->curr_desc = async_desc->desc;
 643         async_desc->dir = direction;
 644
 645         /* fill in temporary descriptors */
 646         desc = async_desc->desc;
 647         for_each_sg(sgl, sg, sg_len, i) {
 648                 unsigned int remainder = sg_dma_len(sg);
 649                 unsigned int curr_offset = 0;
 650
 651                 do {
 652                         if (flags & DMA_PREP_CMD)
 653                                 desc->flags |= cpu_to_le16(DESC_FLAG_CMD);
 654
 655                         desc->addr = cpu_to_le32(sg_dma_address(sg) +
 656                                                  curr_offset);
 657
 658                         if (remainder > BAM_FIFO_SIZE) {
 659                                 desc->size = cpu_to_le16(BAM_FIFO_SIZE);
 660                                 remainder -= BAM_FIFO_SIZE;
 661                                 curr_offset += BAM_FIFO_SIZE;
 662                         } else {
 663                                 desc->size = cpu_to_le16(remainder);
 664                                 remainder = 0;
 665                         }
 666
 667                         async_desc->length += desc->size;
 668                         desc++;
 669                 } while (remainder > 0);
 670         }
 671
 672         return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
 673
 674 err_out:
 675         kfree(async_desc);
 676         return NULL;
 677 }
 678
 679 /**
 680  * bam_dma_terminate_all - terminate all transactions on a channel
 681  * @bchan: bam dma channel
 682  *
 683  * Dequeues and frees all transactions
 684  * No callbacks are done
 685  *
 686  */
 687 static int bam_dma_terminate_all(struct dma_chan *chan)
 688 {
 689         struct bam_chan *bchan = to_bam_chan(chan);
 690         struct bam_async_desc *async_desc, *tmp;
 691         unsigned long flag;
 692         LIST_HEAD(head);
 693
 694         /* remove all transactions, including active transaction */
 695         spin_lock_irqsave(&bchan->vc.lock, flag);
 696         list_for_each_entry_safe(async_desc, tmp,
 697                                  &bchan->desc_list, desc_node) {
 698                 list_add(&async_desc->vd.node, &bchan->vc.desc_issued);
 699                 list_del(&async_desc->desc_node);
 700         }
 701
 702         vchan_get_all_descriptors(&bchan->vc, &head);
 703         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 704
 705         vchan_dma_desc_free_list(&bchan->vc, &head);
 706
 707         return 0;
 708 }
 709
 710 /**
 711  * bam_pause - Pause DMA channel
 712  * @chan: dma channel
 713  *
 714  */
 715 static int bam_pause(struct dma_chan *chan)
 716 {
 717         struct bam_chan *bchan = to_bam_chan(chan);
 718         struct bam_device *bdev = bchan->bdev;
 719         unsigned long flag;
 720         int ret;
 721
 722         ret = pm_runtime_get_sync(bdev->dev);
 723         if (ret < 0)
 724                 return ret;
 725
 726         spin_lock_irqsave(&bchan->vc.lock, flag);
 727         writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT));
 728         bchan->paused = 1;
 729         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 730         pm_runtime_mark_last_busy(bdev->dev);
 731         pm_runtime_put_autosuspend(bdev->dev);
 732
 733         return 0;
 734 }
 735
 736 /**
 737  * bam_resume - Resume DMA channel operations
 738  * @chan: dma channel
 739  *
 740  */
 741 static int bam_resume(struct dma_chan *chan)
 742 {
 743         struct bam_chan *bchan = to_bam_chan(chan);
 744         struct bam_device *bdev = bchan->bdev;
 745         unsigned long flag;
 746         int ret;
 747
 748         ret = pm_runtime_get_sync(bdev->dev);
 749         if (ret < 0)
 750                 return ret;
 751
 752         spin_lock_irqsave(&bchan->vc.lock, flag);
 753         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT));
 754         bchan->paused = 0;
 755         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 756         pm_runtime_mark_last_busy(bdev->dev);
 757         pm_runtime_put_autosuspend(bdev->dev);
 758
 759         return 0;
 760 }
 761
 762 /**
 763  * process_channel_irqs - processes the channel interrupts
 764  * @bdev: bam controller
 765  *
 766  * This function processes the channel interrupts
 767  *
 768  */
 769 static u32 process_channel_irqs(struct bam_device *bdev)
 770 {
 771         u32 i, srcs, pipe_stts, offset, avail;
 772         unsigned long flags;
 773         struct bam_async_desc *async_desc, *tmp;
 774
 775         srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE));
 776
 777         /* return early if no pipe/channel interrupts are present */
 778         if (!(srcs & P_IRQ))
 779                 return srcs;
 780
 781         for (i = 0; i < bdev->num_channels; i++) {
 782                 struct bam_chan *bchan = &bdev->channels[i];
 783
 784                 if (!(srcs & BIT(i)))
 785                         continue;
 786
 787                 /* clear pipe irq */
 788                 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS));
 789
 790                 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
 791
 792                 spin_lock_irqsave(&bchan->vc.lock, flags);
 793
 794                 offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) &
 795                                        P_SW_OFSTS_MASK;
 796                 offset /= sizeof(struct bam_desc_hw);
 797
 798                 /* Number of bytes available to read */
 799                 avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
 800
 801                 list_for_each_entry_safe(async_desc, tmp,
 802                                          &bchan->desc_list, desc_node) {
 803                         /* Not enough data to read */
 804                         if (avail < async_desc->xfer_len)
 805                                 break;
 806
 807                         /* manage FIFO */
 808                         bchan->head += async_desc->xfer_len;
 809                         bchan->head %= MAX_DESCRIPTORS;
 810
 811                         async_desc->num_desc -= async_desc->xfer_len;
 812                         async_desc->curr_desc += async_desc->xfer_len;
 813                         avail -= async_desc->xfer_len;
 814
 815                         /*
 816                          * if complete, process cookie. Otherwise
 817                          * push back to front of desc_issued so that
 818                          * it gets restarted by the tasklet
 819                          */
 820                         if (!async_desc->num_desc) {
 821                                 vchan_cookie_complete(&async_desc->vd);
 822                         } else {
 823                                 list_add(&async_desc->vd.node,
 824                                          &bchan->vc.desc_issued);
 825                         }
 826                         list_del(&async_desc->desc_node);
 827                 }
 828
 829                 spin_unlock_irqrestore(&bchan->vc.lock, flags);
 830         }
 831
 832         return srcs;
 833 }
 834
 835 /**
 836  * bam_dma_irq - irq handler for bam controller
 837  * @irq: IRQ of interrupt
 838  * @data: callback data
 839  *
 840  * IRQ handler for the bam controller
 841  */
 842 static irqreturn_t bam_dma_irq(int irq, void *data)
 843 {
 844         struct bam_device *bdev = data;
 845         u32 clr_mask = 0, srcs = 0;
 846         int ret;
 847
 848         srcs |= process_channel_irqs(bdev);
 849
 850         /* kick off tasklet to start next dma transfer */
 851         if (srcs & P_IRQ)
 852                 tasklet_schedule(&bdev->task);
 853
 854         ret = pm_runtime_get_sync(bdev->dev);
 855         if (ret < 0)
 856                 return ret;
 857
 858         if (srcs & BAM_IRQ) {
 859                 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS));
 860
 861                 /*
 862                  * don't allow reorder of the various accesses to the BAM
 863                  * registers
 864                  */
 865                 mb();
 866
 867                 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
 868         }
 869
 870         pm_runtime_mark_last_busy(bdev->dev);
 871         pm_runtime_put_autosuspend(bdev->dev);
 872
 873         return IRQ_HANDLED;
 874 }
 875
 876 /**
 877  * bam_tx_status - returns status of transaction
 878  * @chan: dma channel
 879  * @cookie: transaction cookie
 880  * @txstate: DMA transaction state
 881  *
 882  * Return status of dma transaction
 883  */
 884 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 885                 struct dma_tx_state *txstate)
 886 {
 887         struct bam_chan *bchan = to_bam_chan(chan);
 888         struct bam_async_desc *async_desc;
 889         struct virt_dma_desc *vd;
 890         int ret;
 891         size_t residue = 0;
 892         unsigned int i;
 893         unsigned long flags;
 894
 895         ret = dma_cookie_status(chan, cookie, txstate);
 896         if (ret == DMA_COMPLETE)
 897                 return ret;
 898
 899         if (!txstate)
 900                 return bchan->paused ? DMA_PAUSED : ret;
 901
 902         spin_lock_irqsave(&bchan->vc.lock, flags);
 903         vd = vchan_find_desc(&bchan->vc, cookie);
 904         if (vd) {
 905                 residue = container_of(vd, struct bam_async_desc, vd)->length;
 906         } else {
 907                 list_for_each_entry(async_desc, &bchan->desc_list, desc_node) {
 908                         if (async_desc->vd.tx.cookie != cookie)
 909                                 continue;
 910
 911                         for (i = 0; i < async_desc->num_desc; i++)
 912                                 residue += async_desc->curr_desc[i].size;
 913                 }
 914         }
 915
 916         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 917
 918         dma_set_residue(txstate, residue);
 919
 920         if (ret == DMA_IN_PROGRESS && bchan->paused)
 921                 ret = DMA_PAUSED;
 922
 923         return ret;
 924 }
 925
 926 /**
 927  * bam_apply_new_config
 928  * @bchan: bam dma channel
 929  * @dir: DMA direction
 930  */
 931 static void bam_apply_new_config(struct bam_chan *bchan,
 932         enum dma_transfer_direction dir)
 933 {
 934         struct bam_device *bdev = bchan->bdev;
 935         u32 maxburst;
 936
 937         if (dir == DMA_DEV_TO_MEM)
 938                 maxburst = bchan->slave.src_maxburst;
 939         else
 940                 maxburst = bchan->slave.dst_maxburst;
 941
 942         writel_relaxed(maxburst, bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
 943
 944         bchan->reconfigure = 0;
 945 }
 946
 947 /**
 948  * bam_start_dma - start next transaction
 949  * @bchan - bam dma channel
 950  */
 951 static void bam_start_dma(struct bam_chan *bchan)
 952 {
 953         struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
 954         struct bam_device *bdev = bchan->bdev;
 955         struct bam_async_desc *async_desc = NULL;
 956         struct bam_desc_hw *desc;
 957         struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
 958                                         sizeof(struct bam_desc_hw));
 959         int ret;
 960         unsigned int avail;
 961         struct dmaengine_desc_callback cb;
 962
 963         lockdep_assert_held(&bchan->vc.lock);
 964
 965         if (!vd)
 966                 return;
 967
 968         ret = pm_runtime_get_sync(bdev->dev);
 969         if (ret < 0)
 970                 return;
 971
 972         while (vd && !IS_BUSY(bchan)) {
 973                 list_del(&vd->node);
 974
 975                 async_desc = container_of(vd, struct bam_async_desc, vd);
 976
 977                 /* on first use, initialize the channel hardware */
 978                 if (!bchan->initialized)
 979                         bam_chan_init_hw(bchan, async_desc->dir);
 980
 981                 /* apply new slave config changes, if necessary */
 982                 if (bchan->reconfigure)
 983                         bam_apply_new_config(bchan, async_desc->dir);
 984
 985                 desc = async_desc->curr_desc;
 986                 avail = CIRC_SPACE(bchan->tail, bchan->head,
 987                                    MAX_DESCRIPTORS + 1);
 988
 989                 if (async_desc->num_desc > avail)
 990                         async_desc->xfer_len = avail;
 991                 else
 992                         async_desc->xfer_len = async_desc->num_desc;
 993
 994                 /* set any special flags on the last descriptor */
 995                 if (async_desc->num_desc == async_desc->xfer_len)
 996                         desc[async_desc->xfer_len - 1].flags |=
 997                                                 cpu_to_le16(async_desc->flags);
 998
 999                 vd = vchan_next_desc(&bchan->vc);
1000
1001                 dmaengine_desc_get_callback(&async_desc->vd.tx, &cb);
1002
1003                 /*
1004                  * An interrupt is generated at this desc, if
1005                  *  - FIFO is FULL.
1006                  *  - No more descriptors to add.
1007                  *  - If a callback completion was requested for this DESC,
1008                  *     In this case, BAM will deliver the completion callback
1009                  *     for this desc and continue processing the next desc.
1010                  */
1011                 if (((avail <= async_desc->xfer_len) || !vd ||
1012                      dmaengine_desc_callback_valid(&cb)) &&
1013                     !(async_desc->flags & DESC_FLAG_EOT))
1014                         desc[async_desc->xfer_len - 1].flags |=
1015                                 cpu_to_le16(DESC_FLAG_INT);
1016
1017                 if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
1018                         u32 partial = MAX_DESCRIPTORS - bchan->tail;
1019
1020                         memcpy(&fifo[bchan->tail], desc,
1021                                partial * sizeof(struct bam_desc_hw));
1022                         memcpy(fifo, &desc[partial],
1023                                (async_desc->xfer_len - partial) *
1024                                 sizeof(struct bam_desc_hw));
1025                 } else {
1026                         memcpy(&fifo[bchan->tail], desc,
1027                                async_desc->xfer_len *
1028                                sizeof(struct bam_desc_hw));
1029                 }
1030
1031                 bchan->tail += async_desc->xfer_len;
1032                 bchan->tail %= MAX_DESCRIPTORS;
1033                 list_add_tail(&async_desc->desc_node, &bchan->desc_list);
1034         }
1035
1036         /* ensure descriptor writes and dma start not reordered */
1037         wmb();
1038         writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw),
1039                         bam_addr(bdev, bchan->id, BAM_P_EVNT_REG));
1040
1041         pm_runtime_mark_last_busy(bdev->dev);
1042         pm_runtime_put_autosuspend(bdev->dev);
1043 }
1044
1045 /**
1046  * dma_tasklet - DMA IRQ tasklet
1047  * @data: tasklet argument (bam controller structure)
1048  *
1049  * Sets up next DMA operation and then processes all completed transactions
1050  */
1051 static void dma_tasklet(unsigned long data)
1052 {
1053         struct bam_device *bdev = (struct bam_device *)data;
1054         struct bam_chan *bchan;
1055         unsigned long flags;
1056         unsigned int i;
1057
1058         /* go through the channels and kick off transactions */
1059         for (i = 0; i < bdev->num_channels; i++) {
1060                 bchan = &bdev->channels[i];
1061                 spin_lock_irqsave(&bchan->vc.lock, flags);
1062
1063                 if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan))
1064                         bam_start_dma(bchan);
1065                 spin_unlock_irqrestore(&bchan->vc.lock, flags);
1066         }
1067
1068 }
1069
1070 /**
1071  * bam_issue_pending - starts pending transactions
1072  * @chan: dma channel
1073  *
1074  * Calls tasklet directly which in turn starts any pending transactions
1075  */
1076 static void bam_issue_pending(struct dma_chan *chan)
1077 {
1078         struct bam_chan *bchan = to_bam_chan(chan);
1079         unsigned long flags;
1080
1081         spin_lock_irqsave(&bchan->vc.lock, flags);
1082
1083         /* if work pending and idle, start a transaction */
1084         if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan))
1085                 bam_start_dma(bchan);
1086
1087         spin_unlock_irqrestore(&bchan->vc.lock, flags);
1088 }
1089
1090 /**
1091  * bam_dma_free_desc - free descriptor memory
1092  * @vd: virtual descriptor
1093  *
1094  */
1095 static void bam_dma_free_desc(struct virt_dma_desc *vd)
1096 {
1097         struct bam_async_desc *async_desc = container_of(vd,
1098                         struct bam_async_desc, vd);
1099
1100         kfree(async_desc);
1101 }
1102
1103 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec,
1104                 struct of_dma *of)
1105 {
1106         struct bam_device *bdev = container_of(of->of_dma_data,
1107                                         struct bam_device, common);
1108         unsigned int request;
1109
1110         if (dma_spec->args_count != 1)
1111                 return NULL;
1112
1113         request = dma_spec->args[0];
1114         if (request >= bdev->num_channels)
1115                 return NULL;
1116
1117         return dma_get_slave_channel(&(bdev->channels[request].vc.chan));
1118 }
1119
1120 /**
1121  * bam_init
1122  * @bdev: bam device
1123  *
1124  * Initialization helper for global bam registers
1125  */
1126 static int bam_init(struct bam_device *bdev)
1127 {
1128         u32 val;
1129
1130         /* read revision and configuration information */
1131         val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION)) >> NUM_EES_SHIFT;
1132         val &= NUM_EES_MASK;
1133
1134         /* check that configured EE is within range */
1135         if (bdev->ee >= val)
1136                 return -EINVAL;
1137
1138         val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES));
1139         bdev->num_channels = val & BAM_NUM_PIPES_MASK;
1140
1141         if (bdev->controlled_remotely)
1142                 return 0;
1143
1144         /* s/w reset bam */
1145         /* after reset all pipes are disabled and idle */
1146         val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL));
1147         val |= BAM_SW_RST;
1148         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1149         val &= ~BAM_SW_RST;
1150         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1151
1152         /* make sure previous stores are visible before enabling BAM */
1153         wmb();
1154
1155         /* enable bam */
1156         val |= BAM_EN;
1157         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1158
1159         /* set descriptor threshhold, start with 4 bytes */
1160         writel_relaxed(DEFAULT_CNT_THRSHLD,
1161                         bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
1162
1163         /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
1164         writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
1165
1166         /* enable irqs for errors */
1167         writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
1168                         bam_addr(bdev, 0, BAM_IRQ_EN));
1169
1170         /* unmask global bam interrupt */
1171         writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
1172
1173         return 0;
1174 }
1175
1176 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
1177         u32 index)
1178 {
1179         bchan->id = index;
1180         bchan->bdev = bdev;
1181
1182         vchan_init(&bchan->vc, &bdev->common);
1183         bchan->vc.desc_free = bam_dma_free_desc;
1184         INIT_LIST_HEAD(&bchan->desc_list);
1185 }
1186
1187 static const struct of_device_id bam_of_match[] = {
1188         { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
1189         { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
1190         { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info },
1191         {}
1192 };
1193
1194 MODULE_DEVICE_TABLE(of, bam_of_match);
1195
1196 static int bam_dma_probe(struct platform_device *pdev)
1197 {
1198         struct bam_device *bdev;
1199         const struct of_device_id *match;
1200         struct resource *iores;
1201         int ret, i;
1202
1203         bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL);
1204         if (!bdev)
1205                 return -ENOMEM;
1206
1207         bdev->dev = &pdev->dev;
1208
1209         match = of_match_node(bam_of_match, pdev->dev.of_node);
1210         if (!match) {
1211                 dev_err(&pdev->dev, "Unsupported BAM module\n");
1212                 return -ENODEV;
1213         }
1214
1215         bdev->layout = match->data;
1216
1217         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1218         bdev->regs = devm_ioremap_resource(&pdev->dev, iores);
1219         if (IS_ERR(bdev->regs))
1220                 return PTR_ERR(bdev->regs);
1221
1222         bdev->irq = platform_get_irq(pdev, 0);
1223         if (bdev->irq < 0)
1224                 return bdev->irq;
1225
1226         ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee);
1227         if (ret) {
1228                 dev_err(bdev->dev, "Execution environment unspecified\n");
1229                 return ret;
1230         }
1231
1232         bdev->controlled_remotely = of_property_read_bool(pdev->dev.of_node,
1233                                                 "qcom,controlled-remotely");
1234
1235         bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
1236         if (IS_ERR(bdev->bamclk))
1237                 return PTR_ERR(bdev->bamclk);
1238
1239         ret = clk_prepare_enable(bdev->bamclk);
1240         if (ret) {
1241                 dev_err(bdev->dev, "failed to prepare/enable clock\n");
1242                 return ret;
1243         }
1244
1245         ret = bam_init(bdev);
1246         if (ret)
1247                 goto err_disable_clk;
1248
1249         tasklet_init(&bdev->task, dma_tasklet, (unsigned long)bdev);
1250
1251         bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels,
1252                                 sizeof(*bdev->channels), GFP_KERNEL);
1253
1254         if (!bdev->channels) {
1255                 ret = -ENOMEM;
1256                 goto err_tasklet_kill;
1257         }
1258
1259         /* allocate and initialize channels */
1260         INIT_LIST_HEAD(&bdev->common.channels);
1261
1262         for (i = 0; i < bdev->num_channels; i++)
1263                 bam_channel_init(bdev, &bdev->channels[i], i);
1264
1265         ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq,
1266                         IRQF_TRIGGER_HIGH, "bam_dma", bdev);
1267         if (ret)
1268                 goto err_bam_channel_exit;
1269
1270         /* set max dma segment size */
1271         bdev->common.dev = bdev->dev;
1272         bdev->common.dev->dma_parms = &bdev->dma_parms;
1273         ret = dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE);
1274         if (ret) {
1275                 dev_err(bdev->dev, "cannot set maximum segment size\n");
1276                 goto err_bam_channel_exit;
1277         }
1278
1279         platform_set_drvdata(pdev, bdev);
1280
1281         /* set capabilities */
1282         dma_cap_zero(bdev->common.cap_mask);
1283         dma_cap_set(DMA_SLAVE, bdev->common.cap_mask);
1284
1285         /* initialize dmaengine apis */
1286         bdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1287         bdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1288         bdev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
1289         bdev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
1290         bdev->common.device_alloc_chan_resources = bam_alloc_chan;
1291         bdev->common.device_free_chan_resources = bam_free_chan;
1292         bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
1293         bdev->common.device_config = bam_slave_config;
1294         bdev->common.device_pause = bam_pause;
1295         bdev->common.device_resume = bam_resume;
1296         bdev->common.device_terminate_all = bam_dma_terminate_all;
1297         bdev->common.device_issue_pending = bam_issue_pending;
1298         bdev->common.device_tx_status = bam_tx_status;
1299         bdev->common.dev = bdev->dev;
1300
1301         ret = dma_async_device_register(&bdev->common);
1302         if (ret) {
1303                 dev_err(bdev->dev, "failed to register dma async device\n");
1304                 goto err_bam_channel_exit;
1305         }
1306
1307         ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate,
1308                                         &bdev->common);
1309         if (ret)
1310                 goto err_unregister_dma;
1311
1312         pm_runtime_irq_safe(&pdev->dev);
1313         pm_runtime_set_autosuspend_delay(&pdev->dev, BAM_DMA_AUTOSUSPEND_DELAY);
1314         pm_runtime_use_autosuspend(&pdev->dev);
1315         pm_runtime_mark_last_busy(&pdev->dev);
1316         pm_runtime_set_active(&pdev->dev);
1317         pm_runtime_enable(&pdev->dev);
1318
1319         return 0;
1320
1321 err_unregister_dma:
1322         dma_async_device_unregister(&bdev->common);
1323 err_bam_channel_exit:
1324         for (i = 0; i < bdev->num_channels; i++)
1325                 tasklet_kill(&bdev->channels[i].vc.task);
1326 err_tasklet_kill:
1327         tasklet_kill(&bdev->task);
1328 err_disable_clk:
1329         clk_disable_unprepare(bdev->bamclk);
1330
1331         return ret;
1332 }
1333
1334 static int bam_dma_remove(struct platform_device *pdev)
1335 {
1336         struct bam_device *bdev = platform_get_drvdata(pdev);
1337         u32 i;
1338
1339         pm_runtime_force_suspend(&pdev->dev);
1340
1341         of_dma_controller_free(pdev->dev.of_node);
1342         dma_async_device_unregister(&bdev->common);
1343
1344         /* mask all interrupts for this execution environment */
1345         writel_relaxed(0, bam_addr(bdev, 0,  BAM_IRQ_SRCS_MSK_EE));
1346
1347         devm_free_irq(bdev->dev, bdev->irq, bdev);
1348
1349         for (i = 0; i < bdev->num_channels; i++) {
1350                 bam_dma_terminate_all(&bdev->channels[i].vc.chan);
1351                 tasklet_kill(&bdev->channels[i].vc.task);
1352
1353                 if (!bdev->channels[i].fifo_virt)
1354                         continue;
1355
1356                 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE,
1357                             bdev->channels[i].fifo_virt,
1358                             bdev->channels[i].fifo_phys);
1359         }
1360
1361         tasklet_kill(&bdev->task);
1362
1363         clk_disable_unprepare(bdev->bamclk);
1364
1365         return 0;
1366 }
1367
1368 static int __maybe_unused bam_dma_runtime_suspend(struct device *dev)
1369 {
1370         struct bam_device *bdev = dev_get_drvdata(dev);
1371
1372         clk_disable(bdev->bamclk);
1373
1374         return 0;
1375 }
1376
1377 static int __maybe_unused bam_dma_runtime_resume(struct device *dev)
1378 {
1379         struct bam_device *bdev = dev_get_drvdata(dev);
1380         int ret;
1381
1382         ret = clk_enable(bdev->bamclk);
1383         if (ret < 0) {
1384                 dev_err(dev, "clk_enable failed: %d\n", ret);
1385                 return ret;
1386         }
1387
1388         return 0;
1389 }
1390
1391 static int __maybe_unused bam_dma_suspend(struct device *dev)
1392 {
1393         struct bam_device *bdev = dev_get_drvdata(dev);
1394
1395         pm_runtime_force_suspend(dev);
1396
1397         clk_unprepare(bdev->bamclk);
1398
1399         return 0;
1400 }
1401
1402 static int __maybe_unused bam_dma_resume(struct device *dev)
1403 {
1404         struct bam_device *bdev = dev_get_drvdata(dev);
1405         int ret;
1406
1407         ret = clk_prepare(bdev->bamclk);
1408         if (ret)
1409                 return ret;
1410
1411         pm_runtime_force_resume(dev);
1412
1413         return 0;
1414 }
1415
1416 static const struct dev_pm_ops bam_dma_pm_ops = {
1417         SET_LATE_SYSTEM_SLEEP_PM_OPS(bam_dma_suspend, bam_dma_resume)
1418         SET_RUNTIME_PM_OPS(bam_dma_runtime_suspend, bam_dma_runtime_resume,
1419                                 NULL)
1420 };
1421
1422 static struct platform_driver bam_dma_driver = {
1423         .probe = bam_dma_probe,
1424         .remove = bam_dma_remove,
1425         .driver = {
1426                 .name = "bam-dma-engine",
1427                 .pm = &bam_dma_pm_ops,
1428                 .of_match_table = bam_of_match,
1429         },
1430 };
1431
1432 module_platform_driver(bam_dma_driver);
1433
1434 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
1435 MODULE_DESCRIPTION("QCOM BAM DMA engine driver");
1436 MODULE_LICENSE("GPL v2");