drivers/dma/ioat/dma.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2009 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
  25  * copy operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/dmaengine.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/i7300_idle.h>
  37 #include "dma.h"
  38 #include "registers.h"
  39 #include "hw.h"
  40
  41 int ioat_pending_level = 4;
  42 module_param(ioat_pending_level, int, 0644);
  43 MODULE_PARM_DESC(ioat_pending_level,
  44                  "high-water mark for pushing ioat descriptors (default: 4)");
  45
  46 /* internal functions */
  47 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
  48 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
  49
  50 /**
  51  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
  52  * @irq: interrupt id
  53  * @data: interrupt data
  54  */
  55 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
  56 {
  57         struct ioatdma_device *instance = data;
  58         struct ioat_chan_common *chan;
  59         unsigned long attnstatus;
  60         int bit;
  61         u8 intrctrl;
  62
  63         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
  64
  65         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
  66                 return IRQ_NONE;
  67
  68         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
  69                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  70                 return IRQ_NONE;
  71         }
  72
  73         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
  74         for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
  75                 chan = ioat_chan_by_index(instance, bit);
  76                 tasklet_schedule(&chan->cleanup_task);
  77         }
  78
  79         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  80         return IRQ_HANDLED;
  81 }
  82
  83 /**
  84  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
  85  * @irq: interrupt id
  86  * @data: interrupt data
  87  */
  88 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
  89 {
  90         struct ioat_chan_common *chan = data;
  91
  92         tasklet_schedule(&chan->cleanup_task);
  93
  94         return IRQ_HANDLED;
  95 }
  96
  97 /* common channel initialization */
  98 void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx)
  99 {
 100         struct dma_device *dma = &device->common;
 101         struct dma_chan *c = &chan->common;
 102         unsigned long data = (unsigned long) c;
 103
 104         chan->device = device;
 105         chan->reg_base = device->reg_base + (0x80 * (idx + 1));
 106         spin_lock_init(&chan->cleanup_lock);
 107         chan->common.device = dma;
 108         list_add_tail(&chan->common.device_node, &dma->channels);
 109         device->idx[idx] = chan;
 110         init_timer(&chan->timer);
 111         chan->timer.function = device->timer_fn;
 112         chan->timer.data = data;
 113         tasklet_init(&chan->cleanup_task, device->cleanup_fn, data);
 114         tasklet_disable(&chan->cleanup_task);
 115 }
 116
 117 /**
 118  * ioat1_dma_enumerate_channels - find and initialize the device's channels
 119  * @device: the device to be enumerated
 120  */
 121 static int ioat1_enumerate_channels(struct ioatdma_device *device)
 122 {
 123         u8 xfercap_scale;
 124         u32 xfercap;
 125         int i;
 126         struct ioat_dma_chan *ioat;
 127         struct device *dev = &device->pdev->dev;
 128         struct dma_device *dma = &device->common;
 129
 130         INIT_LIST_HEAD(&dma->channels);
 131         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 132         dma->chancnt &= 0x1f; /* bits [4:0] valid */
 133         if (dma->chancnt > ARRAY_SIZE(device->idx)) {
 134                 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
 135                          dma->chancnt, ARRAY_SIZE(device->idx));
 136                 dma->chancnt = ARRAY_SIZE(device->idx);
 137         }
 138         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 139         xfercap_scale &= 0x1f; /* bits [4:0] valid */
 140         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
 141         dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
 142
 143 #ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
 144         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
 145                 dma->chancnt--;
 146 #endif
 147         for (i = 0; i < dma->chancnt; i++) {
 148                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
 149                 if (!ioat)
 150                         break;
 151
 152                 ioat_init_channel(device, &ioat->base, i);
 153                 ioat->xfercap = xfercap;
 154                 spin_lock_init(&ioat->desc_lock);
 155                 INIT_LIST_HEAD(&ioat->free_desc);
 156                 INIT_LIST_HEAD(&ioat->used_desc);
 157         }
 158         dma->chancnt = i;
 159         return i;
 160 }
 161
 162 /**
 163  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 164  *                                 descriptors to hw
 165  * @chan: DMA channel handle
 166  */
 167 static inline void
 168 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
 169 {
 170         void __iomem *reg_base = ioat->base.reg_base;
 171
 172         dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
 173                 __func__, ioat->pending);
 174         ioat->pending = 0;
 175         writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
 176 }
 177
 178 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 179 {
 180         struct ioat_dma_chan *ioat = to_ioat_chan(chan);
 181
 182         if (ioat->pending > 0) {
 183                 spin_lock_bh(&ioat->desc_lock);
 184                 __ioat1_dma_memcpy_issue_pending(ioat);
 185                 spin_unlock_bh(&ioat->desc_lock);
 186         }
 187 }
 188
 189 /**
 190  * ioat1_reset_channel - restart a channel
 191  * @ioat: IOAT DMA channel handle
 192  */
 193 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
 194 {
 195         struct ioat_chan_common *chan = &ioat->base;
 196         void __iomem *reg_base = chan->reg_base;
 197         u32 chansts, chanerr;
 198
 199         dev_warn(to_dev(chan), "reset\n");
 200         chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
 201         chansts = *chan->completion & IOAT_CHANSTS_STATUS;
 202         if (chanerr) {
 203                 dev_err(to_dev(chan),
 204                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
 205                         chan_num(chan), chansts, chanerr);
 206                 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
 207         }
 208
 209         /*
 210          * whack it upside the head with a reset
 211          * and wait for things to settle out.
 212          * force the pending count to a really big negative
 213          * to make sure no one forces an issue_pending
 214          * while we're waiting.
 215          */
 216
 217         ioat->pending = INT_MIN;
 218         writeb(IOAT_CHANCMD_RESET,
 219                reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 220         set_bit(IOAT_RESET_PENDING, &chan->state);
 221         mod_timer(&chan->timer, jiffies + RESET_DELAY);
 222 }
 223
 224 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 225 {
 226         struct dma_chan *c = tx->chan;
 227         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 228         struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
 229         struct ioat_chan_common *chan = &ioat->base;
 230         struct ioat_desc_sw *first;
 231         struct ioat_desc_sw *chain_tail;
 232         dma_cookie_t cookie;
 233
 234         spin_lock_bh(&ioat->desc_lock);
 235         /* cookie incr and addition to used_list must be atomic */
 236         cookie = c->cookie;
 237         cookie++;
 238         if (cookie < 0)
 239                 cookie = 1;
 240         c->cookie = cookie;
 241         tx->cookie = cookie;
 242         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 243
 244         /* write address into NextDescriptor field of last desc in chain */
 245         first = to_ioat_desc(desc->tx_list.next);
 246         chain_tail = to_ioat_desc(ioat->used_desc.prev);
 247         /* make descriptor updates globally visible before chaining */
 248         wmb();
 249         chain_tail->hw->next = first->txd.phys;
 250         list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
 251         dump_desc_dbg(ioat, chain_tail);
 252         dump_desc_dbg(ioat, first);
 253
 254         if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
 255                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 256
 257         ioat->active += desc->hw->tx_cnt;
 258         ioat->pending += desc->hw->tx_cnt;
 259         if (ioat->pending >= ioat_pending_level)
 260                 __ioat1_dma_memcpy_issue_pending(ioat);
 261         spin_unlock_bh(&ioat->desc_lock);
 262
 263         return cookie;
 264 }
 265
 266 /**
 267  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 268  * @ioat: the channel supplying the memory pool for the descriptors
 269  * @flags: allocation flags
 270  */
 271 static struct ioat_desc_sw *
 272 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
 273 {
 274         struct ioat_dma_descriptor *desc;
 275         struct ioat_desc_sw *desc_sw;
 276         struct ioatdma_device *ioatdma_device;
 277         dma_addr_t phys;
 278
 279         ioatdma_device = ioat->base.device;
 280         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
 281         if (unlikely(!desc))
 282                 return NULL;
 283
 284         desc_sw = kzalloc(sizeof(*desc_sw), flags);
 285         if (unlikely(!desc_sw)) {
 286                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
 287                 return NULL;
 288         }
 289
 290         memset(desc, 0, sizeof(*desc));
 291
 292         INIT_LIST_HEAD(&desc_sw->tx_list);
 293         dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
 294         desc_sw->txd.tx_submit = ioat1_tx_submit;
 295         desc_sw->hw = desc;
 296         desc_sw->txd.phys = phys;
 297         set_desc_id(desc_sw, -1);
 298
 299         return desc_sw;
 300 }
 301
 302 static int ioat_initial_desc_count = 256;
 303 module_param(ioat_initial_desc_count, int, 0644);
 304 MODULE_PARM_DESC(ioat_initial_desc_count,
 305                  "ioat1: initial descriptors per channel (default: 256)");
 306 /**
 307  * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
 308  * @chan: the channel to be filled out
 309  */
 310 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
 311 {
 312         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 313         struct ioat_chan_common *chan = &ioat->base;
 314         struct ioat_desc_sw *desc;
 315         u32 chanerr;
 316         int i;
 317         LIST_HEAD(tmp_list);
 318
 319         /* have we already been set up? */
 320         if (!list_empty(&ioat->free_desc))
 321                 return ioat->desccount;
 322
 323         /* Setup register to interrupt and write completion status on error */
 324         writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
 325
 326         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 327         if (chanerr) {
 328                 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
 329                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 330         }
 331
 332         /* Allocate descriptors */
 333         for (i = 0; i < ioat_initial_desc_count; i++) {
 334                 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
 335                 if (!desc) {
 336                         dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
 337                         break;
 338                 }
 339                 set_desc_id(desc, i);
 340                 list_add_tail(&desc->node, &tmp_list);
 341         }
 342         spin_lock_bh(&ioat->desc_lock);
 343         ioat->desccount = i;
 344         list_splice(&tmp_list, &ioat->free_desc);
 345         spin_unlock_bh(&ioat->desc_lock);
 346
 347         /* allocate a completion writeback area */
 348         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 349         chan->completion = pci_pool_alloc(chan->device->completion_pool,
 350                                           GFP_KERNEL, &chan->completion_dma);
 351         memset(chan->completion, 0, sizeof(*chan->completion));
 352         writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
 353                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 354         writel(((u64) chan->completion_dma) >> 32,
 355                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 356
 357         tasklet_enable(&chan->cleanup_task);
 358         ioat1_dma_start_null_desc(ioat);  /* give chain to dma device */
 359         dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
 360                 __func__, ioat->desccount);
 361         return ioat->desccount;
 362 }
 363
 364 /**
 365  * ioat1_dma_free_chan_resources - release all the descriptors
 366  * @chan: the channel to be cleaned
 367  */
 368 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
 369 {
 370         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 371         struct ioat_chan_common *chan = &ioat->base;
 372         struct ioatdma_device *ioatdma_device = chan->device;
 373         struct ioat_desc_sw *desc, *_desc;
 374         int in_use_descs = 0;
 375
 376         /* Before freeing channel resources first check
 377          * if they have been previously allocated for this channel.
 378          */
 379         if (ioat->desccount == 0)
 380                 return;
 381
 382         tasklet_disable(&chan->cleanup_task);
 383         del_timer_sync(&chan->timer);
 384         ioat1_cleanup(ioat);
 385
 386         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 387          * before removing DMA descriptor resources.
 388          */
 389         writeb(IOAT_CHANCMD_RESET,
 390                chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 391         mdelay(100);
 392
 393         spin_lock_bh(&ioat->desc_lock);
 394         list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
 395                 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
 396                         __func__, desc_id(desc));
 397                 dump_desc_dbg(ioat, desc);
 398                 in_use_descs++;
 399                 list_del(&desc->node);
 400                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 401                               desc->txd.phys);
 402                 kfree(desc);
 403         }
 404         list_for_each_entry_safe(desc, _desc,
 405                                  &ioat->free_desc, node) {
 406                 list_del(&desc->node);
 407                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 408                               desc->txd.phys);
 409                 kfree(desc);
 410         }
 411         spin_unlock_bh(&ioat->desc_lock);
 412
 413         pci_pool_free(ioatdma_device->completion_pool,
 414                       chan->completion,
 415                       chan->completion_dma);
 416
 417         /* one is ok since we left it on there on purpose */
 418         if (in_use_descs > 1)
 419                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
 420                         in_use_descs - 1);
 421
 422         chan->last_completion = 0;
 423         chan->completion_dma = 0;
 424         ioat->pending = 0;
 425         ioat->desccount = 0;
 426 }
 427
 428 /**
 429  * ioat1_dma_get_next_descriptor - return the next available descriptor
 430  * @ioat: IOAT DMA channel handle
 431  *
 432  * Gets the next descriptor from the chain, and must be called with the
 433  * channel's desc_lock held.  Allocates more descriptors if the channel
 434  * has run out.
 435  */
 436 static struct ioat_desc_sw *
 437 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
 438 {
 439         struct ioat_desc_sw *new;
 440
 441         if (!list_empty(&ioat->free_desc)) {
 442                 new = to_ioat_desc(ioat->free_desc.next);
 443                 list_del(&new->node);
 444         } else {
 445                 /* try to get another desc */
 446                 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
 447                 if (!new) {
 448                         dev_err(to_dev(&ioat->base), "alloc failed\n");
 449                         return NULL;
 450                 }
 451         }
 452         dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
 453                 __func__, desc_id(new));
 454         prefetch(new->hw);
 455         return new;
 456 }
 457
 458 static struct dma_async_tx_descriptor *
 459 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
 460                       dma_addr_t dma_src, size_t len, unsigned long flags)
 461 {
 462         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 463         struct ioat_desc_sw *desc;
 464         size_t copy;
 465         LIST_HEAD(chain);
 466         dma_addr_t src = dma_src;
 467         dma_addr_t dest = dma_dest;
 468         size_t total_len = len;
 469         struct ioat_dma_descriptor *hw = NULL;
 470         int tx_cnt = 0;
 471
 472         spin_lock_bh(&ioat->desc_lock);
 473         desc = ioat1_dma_get_next_descriptor(ioat);
 474         do {
 475                 if (!desc)
 476                         break;
 477
 478                 tx_cnt++;
 479                 copy = min_t(size_t, len, ioat->xfercap);
 480
 481                 hw = desc->hw;
 482                 hw->size = copy;
 483                 hw->ctl = 0;
 484                 hw->src_addr = src;
 485                 hw->dst_addr = dest;
 486
 487                 list_add_tail(&desc->node, &chain);
 488
 489                 len -= copy;
 490                 dest += copy;
 491                 src += copy;
 492                 if (len) {
 493                         struct ioat_desc_sw *next;
 494
 495                         async_tx_ack(&desc->txd);
 496                         next = ioat1_dma_get_next_descriptor(ioat);
 497                         hw->next = next ? next->txd.phys : 0;
 498                         dump_desc_dbg(ioat, desc);
 499                         desc = next;
 500                 } else
 501                         hw->next = 0;
 502         } while (len);
 503
 504         if (!desc) {
 505                 struct ioat_chan_common *chan = &ioat->base;
 506
 507                 dev_err(to_dev(chan),
 508                         "chan%d - get_next_desc failed\n", chan_num(chan));
 509                 list_splice(&chain, &ioat->free_desc);
 510                 spin_unlock_bh(&ioat->desc_lock);
 511                 return NULL;
 512         }
 513         spin_unlock_bh(&ioat->desc_lock);
 514
 515         desc->txd.flags = flags;
 516         desc->len = total_len;
 517         list_splice(&chain, &desc->tx_list);
 518         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 519         hw->ctl_f.compl_write = 1;
 520         hw->tx_cnt = tx_cnt;
 521         dump_desc_dbg(ioat, desc);
 522
 523         return &desc->txd;
 524 }
 525
 526 static void ioat1_cleanup_event(unsigned long data)
 527 {
 528         struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
 529
 530         ioat1_cleanup(ioat);
 531         writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
 532 }
 533
 534 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
 535                     size_t len, struct ioat_dma_descriptor *hw)
 536 {
 537         struct pci_dev *pdev = chan->device->pdev;
 538         size_t offset = len - hw->size;
 539
 540         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
 541                 ioat_unmap(pdev, hw->dst_addr - offset, len,
 542                            PCI_DMA_FROMDEVICE, flags, 1);
 543
 544         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
 545                 ioat_unmap(pdev, hw->src_addr - offset, len,
 546                            PCI_DMA_TODEVICE, flags, 0);
 547 }
 548
 549 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
 550 {
 551         unsigned long phys_complete;
 552         u64 completion;
 553
 554         completion = *chan->completion;
 555         phys_complete = ioat_chansts_to_addr(completion);
 556
 557         dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
 558                 (unsigned long long) phys_complete);
 559
 560         if (is_ioat_halted(completion)) {
 561                 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 562                 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
 563                         chanerr);
 564
 565                 /* TODO do something to salvage the situation */
 566         }
 567
 568         return phys_complete;
 569 }
 570
 571 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
 572                            unsigned long *phys_complete)
 573 {
 574         *phys_complete = ioat_get_current_completion(chan);
 575         if (*phys_complete == chan->last_completion)
 576                 return false;
 577         clear_bit(IOAT_COMPLETION_ACK, &chan->state);
 578         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 579
 580         return true;
 581 }
 582
 583 static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
 584 {
 585         struct ioat_chan_common *chan = &ioat->base;
 586         struct list_head *_desc, *n;
 587         struct dma_async_tx_descriptor *tx;
 588
 589         dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n",
 590                  __func__, phys_complete);
 591         list_for_each_safe(_desc, n, &ioat->used_desc) {
 592                 struct ioat_desc_sw *desc;
 593
 594                 prefetch(n);
 595                 desc = list_entry(_desc, typeof(*desc), node);
 596                 tx = &desc->txd;
 597                 /*
 598                  * Incoming DMA requests may use multiple descriptors,
 599                  * due to exceeding xfercap, perhaps. If so, only the
 600                  * last one will have a cookie, and require unmapping.
 601                  */
 602                 dump_desc_dbg(ioat, desc);
 603                 if (tx->cookie) {
 604                         chan->completed_cookie = tx->cookie;
 605                         tx->cookie = 0;
 606                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 607                         ioat->active -= desc->hw->tx_cnt;
 608                         if (tx->callback) {
 609                                 tx->callback(tx->callback_param);
 610                                 tx->callback = NULL;
 611                         }
 612                 }
 613
 614                 if (tx->phys != phys_complete) {
 615                         /*
 616                          * a completed entry, but not the last, so clean
 617                          * up if the client is done with the descriptor
 618                          */
 619                         if (async_tx_test_ack(tx))
 620                                 list_move_tail(&desc->node, &ioat->free_desc);
 621                 } else {
 622                         /*
 623                          * last used desc. Do not remove, so we can
 624                          * append from it.
 625                          */
 626
 627                         /* if nothing else is pending, cancel the
 628                          * completion timeout
 629                          */
 630                         if (n == &ioat->used_desc) {
 631                                 dev_dbg(to_dev(chan),
 632                                         "%s cancel completion timeout\n",
 633                                         __func__);
 634                                 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
 635                         }
 636
 637                         /* TODO check status bits? */
 638                         break;
 639                 }
 640         }
 641
 642         chan->last_completion = phys_complete;
 643 }
 644
 645 /**
 646  * ioat1_cleanup - cleanup up finished descriptors
 647  * @chan: ioat channel to be cleaned up
 648  *
 649  * To prevent lock contention we defer cleanup when the locks are
 650  * contended with a terminal timeout that forces cleanup and catches
 651  * completion notification errors.
 652  */
 653 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
 654 {
 655         struct ioat_chan_common *chan = &ioat->base;
 656         unsigned long phys_complete;
 657
 658         prefetch(chan->completion);
 659
 660         if (!spin_trylock_bh(&chan->cleanup_lock))
 661                 return;
 662
 663         if (!ioat_cleanup_preamble(chan, &phys_complete)) {
 664                 spin_unlock_bh(&chan->cleanup_lock);
 665                 return;
 666         }
 667
 668         if (!spin_trylock_bh(&ioat->desc_lock)) {
 669                 spin_unlock_bh(&chan->cleanup_lock);
 670                 return;
 671         }
 672
 673         __cleanup(ioat, phys_complete);
 674
 675         spin_unlock_bh(&ioat->desc_lock);
 676         spin_unlock_bh(&chan->cleanup_lock);
 677 }
 678
 679 static void ioat1_timer_event(unsigned long data)
 680 {
 681         struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
 682         struct ioat_chan_common *chan = &ioat->base;
 683
 684         dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
 685
 686         spin_lock_bh(&chan->cleanup_lock);
 687         if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
 688                 struct ioat_desc_sw *desc;
 689
 690                 spin_lock_bh(&ioat->desc_lock);
 691
 692                 /* restart active descriptors */
 693                 desc = to_ioat_desc(ioat->used_desc.prev);
 694                 ioat_set_chainaddr(ioat, desc->txd.phys);
 695                 ioat_start(chan);
 696
 697                 ioat->pending = 0;
 698                 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
 699                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 700                 spin_unlock_bh(&ioat->desc_lock);
 701         } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
 702                 unsigned long phys_complete;
 703
 704                 spin_lock_bh(&ioat->desc_lock);
 705                 /* if we haven't made progress and we have already
 706                  * acknowledged a pending completion once, then be more
 707                  * forceful with a restart
 708                  */
 709                 if (ioat_cleanup_preamble(chan, &phys_complete))
 710                         __cleanup(ioat, phys_complete);
 711                 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
 712                         ioat1_reset_channel(ioat);
 713                 else {
 714                         u64 status = ioat_chansts(chan);
 715
 716                         /* manually update the last completion address */
 717                         if (ioat_chansts_to_addr(status) != 0)
 718                                 *chan->completion = status;
 719
 720                         set_bit(IOAT_COMPLETION_ACK, &chan->state);
 721                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 722                 }
 723                 spin_unlock_bh(&ioat->desc_lock);
 724         }
 725         spin_unlock_bh(&chan->cleanup_lock);
 726 }
 727
 728 enum dma_status
 729 ioat_is_dma_complete(struct dma_chan *c, dma_cookie_t cookie,
 730                       dma_cookie_t *done, dma_cookie_t *used)
 731 {
 732         struct ioat_chan_common *chan = to_chan_common(c);
 733         struct ioatdma_device *device = chan->device;
 734
 735         if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
 736                 return DMA_SUCCESS;
 737
 738         device->cleanup_fn((unsigned long) c);
 739
 740         return ioat_is_complete(c, cookie, done, used);
 741 }
 742
 743 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
 744 {
 745         struct ioat_chan_common *chan = &ioat->base;
 746         struct ioat_desc_sw *desc;
 747         struct ioat_dma_descriptor *hw;
 748
 749         spin_lock_bh(&ioat->desc_lock);
 750
 751         desc = ioat1_dma_get_next_descriptor(ioat);
 752
 753         if (!desc) {
 754                 dev_err(to_dev(chan),
 755                         "Unable to start null desc - get next desc failed\n");
 756                 spin_unlock_bh(&ioat->desc_lock);
 757                 return;
 758         }
 759
 760         hw = desc->hw;
 761         hw->ctl = 0;
 762         hw->ctl_f.null = 1;
 763         hw->ctl_f.int_en = 1;
 764         hw->ctl_f.compl_write = 1;
 765         /* set size to non-zero value (channel returns error when size is 0) */
 766         hw->size = NULL_DESC_BUFFER_SIZE;
 767         hw->src_addr = 0;
 768         hw->dst_addr = 0;
 769         async_tx_ack(&desc->txd);
 770         hw->next = 0;
 771         list_add_tail(&desc->node, &ioat->used_desc);
 772         dump_desc_dbg(ioat, desc);
 773
 774         ioat_set_chainaddr(ioat, desc->txd.phys);
 775         ioat_start(chan);
 776         spin_unlock_bh(&ioat->desc_lock);
 777 }
 778
 779 /*
 780  * Perform a IOAT transaction to verify the HW works.
 781  */
 782 #define IOAT_TEST_SIZE 2000
 783
 784 static void __devinit ioat_dma_test_callback(void *dma_async_param)
 785 {
 786         struct completion *cmp = dma_async_param;
 787
 788         complete(cmp);
 789 }
 790
 791 /**
 792  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
 793  * @device: device to be tested
 794  */
 795 int __devinit ioat_dma_self_test(struct ioatdma_device *device)
 796 {
 797         int i;
 798         u8 *src;
 799         u8 *dest;
 800         struct dma_device *dma = &device->common;
 801         struct device *dev = &device->pdev->dev;
 802         struct dma_chan *dma_chan;
 803         struct dma_async_tx_descriptor *tx;
 804         dma_addr_t dma_dest, dma_src;
 805         dma_cookie_t cookie;
 806         int err = 0;
 807         struct completion cmp;
 808         unsigned long tmo;
 809         unsigned long flags;
 810
 811         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 812         if (!src)
 813                 return -ENOMEM;
 814         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 815         if (!dest) {
 816                 kfree(src);
 817                 return -ENOMEM;
 818         }
 819
 820         /* Fill in src buffer */
 821         for (i = 0; i < IOAT_TEST_SIZE; i++)
 822                 src[i] = (u8)i;
 823
 824         /* Start copy, using first DMA channel */
 825         dma_chan = container_of(dma->channels.next, struct dma_chan,
 826                                 device_node);
 827         if (dma->device_alloc_chan_resources(dma_chan) < 1) {
 828                 dev_err(dev, "selftest cannot allocate chan resource\n");
 829                 err = -ENODEV;
 830                 goto out;
 831         }
 832
 833         dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
 834         dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
 835         flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
 836                 DMA_PREP_INTERRUPT;
 837         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
 838                                                    IOAT_TEST_SIZE, flags);
 839         if (!tx) {
 840                 dev_err(dev, "Self-test prep failed, disabling\n");
 841                 err = -ENODEV;
 842                 goto free_resources;
 843         }
 844
 845         async_tx_ack(tx);
 846         init_completion(&cmp);
 847         tx->callback = ioat_dma_test_callback;
 848         tx->callback_param = &cmp;
 849         cookie = tx->tx_submit(tx);
 850         if (cookie < 0) {
 851                 dev_err(dev, "Self-test setup failed, disabling\n");
 852                 err = -ENODEV;
 853                 goto free_resources;
 854         }
 855         dma->device_issue_pending(dma_chan);
 856
 857         tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
 858
 859         if (tmo == 0 ||
 860             dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL)
 861                                         != DMA_SUCCESS) {
 862                 dev_err(dev, "Self-test copy timed out, disabling\n");
 863                 err = -ENODEV;
 864                 goto free_resources;
 865         }
 866         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
 867                 dev_err(dev, "Self-test copy failed compare, disabling\n");
 868                 err = -ENODEV;
 869                 goto free_resources;
 870         }
 871
 872 free_resources:
 873         dma->device_free_chan_resources(dma_chan);
 874 out:
 875         kfree(src);
 876         kfree(dest);
 877         return err;
 878 }
 879
 880 static char ioat_interrupt_style[32] = "msix";
 881 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
 882                     sizeof(ioat_interrupt_style), 0644);
 883 MODULE_PARM_DESC(ioat_interrupt_style,
 884                  "set ioat interrupt style: msix (default), "
 885                  "msix-single-vector, msi, intx)");
 886
 887 /**
 888  * ioat_dma_setup_interrupts - setup interrupt handler
 889  * @device: ioat device
 890  */
 891 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
 892 {
 893         struct ioat_chan_common *chan;
 894         struct pci_dev *pdev = device->pdev;
 895         struct device *dev = &pdev->dev;
 896         struct msix_entry *msix;
 897         int i, j, msixcnt;
 898         int err = -EINVAL;
 899         u8 intrctrl = 0;
 900
 901         if (!strcmp(ioat_interrupt_style, "msix"))
 902                 goto msix;
 903         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
 904                 goto msix_single_vector;
 905         if (!strcmp(ioat_interrupt_style, "msi"))
 906                 goto msi;
 907         if (!strcmp(ioat_interrupt_style, "intx"))
 908                 goto intx;
 909         dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
 910         goto err_no_irq;
 911
 912 msix:
 913         /* The number of MSI-X vectors should equal the number of channels */
 914         msixcnt = device->common.chancnt;
 915         for (i = 0; i < msixcnt; i++)
 916                 device->msix_entries[i].entry = i;
 917
 918         err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
 919         if (err < 0)
 920                 goto msi;
 921         if (err > 0)
 922                 goto msix_single_vector;
 923
 924         for (i = 0; i < msixcnt; i++) {
 925                 msix = &device->msix_entries[i];
 926                 chan = ioat_chan_by_index(device, i);
 927                 err = devm_request_irq(dev, msix->vector,
 928                                        ioat_dma_do_interrupt_msix, 0,
 929                                        "ioat-msix", chan);
 930                 if (err) {
 931                         for (j = 0; j < i; j++) {
 932                                 msix = &device->msix_entries[j];
 933                                 chan = ioat_chan_by_index(device, j);
 934                                 devm_free_irq(dev, msix->vector, chan);
 935                         }
 936                         goto msix_single_vector;
 937                 }
 938         }
 939         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
 940         goto done;
 941
 942 msix_single_vector:
 943         msix = &device->msix_entries[0];
 944         msix->entry = 0;
 945         err = pci_enable_msix(pdev, device->msix_entries, 1);
 946         if (err)
 947                 goto msi;
 948
 949         err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
 950                                "ioat-msix", device);
 951         if (err) {
 952                 pci_disable_msix(pdev);
 953                 goto msi;
 954         }
 955         goto done;
 956
 957 msi:
 958         err = pci_enable_msi(pdev);
 959         if (err)
 960                 goto intx;
 961
 962         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
 963                                "ioat-msi", device);
 964         if (err) {
 965                 pci_disable_msi(pdev);
 966                 goto intx;
 967         }
 968         goto done;
 969
 970 intx:
 971         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
 972                                IRQF_SHARED, "ioat-intx", device);
 973         if (err)
 974                 goto err_no_irq;
 975
 976 done:
 977         if (device->intr_quirk)
 978                 device->intr_quirk(device);
 979         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
 980         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
 981         return 0;
 982
 983 err_no_irq:
 984         /* Disable all interrupt generation */
 985         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
 986         dev_err(dev, "no usable interrupts\n");
 987         return err;
 988 }
 989
 990 static void ioat_disable_interrupts(struct ioatdma_device *device)
 991 {
 992         /* Disable all interrupt generation */
 993         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
 994 }
 995
 996 int __devinit ioat_probe(struct ioatdma_device *device)
 997 {
 998         int err = -ENODEV;
 999         struct dma_device *dma = &device->common;
1000         struct pci_dev *pdev = device->pdev;
1001         struct device *dev = &pdev->dev;
1002
1003         /* DMA coherent memory pool for DMA descriptor allocations */
1004         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1005                                            sizeof(struct ioat_dma_descriptor),
1006                                            64, 0);
1007         if (!device->dma_pool) {
1008                 err = -ENOMEM;
1009                 goto err_dma_pool;
1010         }
1011
1012         device->completion_pool = pci_pool_create("completion_pool", pdev,
1013                                                   sizeof(u64), SMP_CACHE_BYTES,
1014                                                   SMP_CACHE_BYTES);
1015
1016         if (!device->completion_pool) {
1017                 err = -ENOMEM;
1018                 goto err_completion_pool;
1019         }
1020
1021         device->enumerate_channels(device);
1022
1023         dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1024         dma->dev = &pdev->dev;
1025
1026         if (!dma->chancnt) {
1027                 dev_err(dev, "channel enumeration error\n");
1028                 goto err_setup_interrupts;
1029         }
1030
1031         err = ioat_dma_setup_interrupts(device);
1032         if (err)
1033                 goto err_setup_interrupts;
1034
1035         err = device->self_test(device);
1036         if (err)
1037                 goto err_self_test;
1038
1039         return 0;
1040
1041 err_self_test:
1042         ioat_disable_interrupts(device);
1043 err_setup_interrupts:
1044         pci_pool_destroy(device->completion_pool);
1045 err_completion_pool:
1046         pci_pool_destroy(device->dma_pool);
1047 err_dma_pool:
1048         return err;
1049 }
1050
1051 int __devinit ioat_register(struct ioatdma_device *device)
1052 {
1053         int err = dma_async_device_register(&device->common);
1054
1055         if (err) {
1056                 ioat_disable_interrupts(device);
1057                 pci_pool_destroy(device->completion_pool);
1058                 pci_pool_destroy(device->dma_pool);
1059         }
1060
1061         return err;
1062 }
1063
1064 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1065 static void ioat1_intr_quirk(struct ioatdma_device *device)
1066 {
1067         struct pci_dev *pdev = device->pdev;
1068         u32 dmactrl;
1069
1070         pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1071         if (pdev->msi_enabled)
1072                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1073         else
1074                 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1075         pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1076 }
1077
1078 static ssize_t ring_size_show(struct dma_chan *c, char *page)
1079 {
1080         struct ioat_dma_chan *ioat = to_ioat_chan(c);
1081
1082         return sprintf(page, "%d\n", ioat->desccount);
1083 }
1084 static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
1085
1086 static ssize_t ring_active_show(struct dma_chan *c, char *page)
1087 {
1088         struct ioat_dma_chan *ioat = to_ioat_chan(c);
1089
1090         return sprintf(page, "%d\n", ioat->active);
1091 }
1092 static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
1093
1094 static ssize_t cap_show(struct dma_chan *c, char *page)
1095 {
1096         struct dma_device *dma = c->device;
1097
1098         return sprintf(page, "copy%s%s%s%s%s%s\n",
1099                        dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "",
1100                        dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "",
1101                        dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "",
1102                        dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "",
1103                        dma_has_cap(DMA_MEMSET, dma->cap_mask)  ? " fill" : "",
1104                        dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : "");
1105
1106 }
1107 struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap);
1108
1109 static ssize_t version_show(struct dma_chan *c, char *page)
1110 {
1111         struct dma_device *dma = c->device;
1112         struct ioatdma_device *device = to_ioatdma_device(dma);
1113
1114         return sprintf(page, "%d.%d\n",
1115                        device->version >> 4, device->version & 0xf);
1116 }
1117 struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version);
1118
1119 static struct attribute *ioat1_attrs[] = {
1120         &ring_size_attr.attr,
1121         &ring_active_attr.attr,
1122         &ioat_cap_attr.attr,
1123         &ioat_version_attr.attr,
1124         NULL,
1125 };
1126
1127 static ssize_t
1128 ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page)
1129 {
1130         struct ioat_sysfs_entry *entry;
1131         struct ioat_chan_common *chan;
1132
1133         entry = container_of(attr, struct ioat_sysfs_entry, attr);
1134         chan = container_of(kobj, struct ioat_chan_common, kobj);
1135
1136         if (!entry->show)
1137                 return -EIO;
1138         return entry->show(&chan->common, page);
1139 }
1140
1141 const struct sysfs_ops ioat_sysfs_ops = {
1142         .show   = ioat_attr_show,
1143 };
1144
1145 static struct kobj_type ioat1_ktype = {
1146         .sysfs_ops = &ioat_sysfs_ops,
1147         .default_attrs = ioat1_attrs,
1148 };
1149
1150 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type)
1151 {
1152         struct dma_device *dma = &device->common;
1153         struct dma_chan *c;
1154
1155         list_for_each_entry(c, &dma->channels, device_node) {
1156                 struct ioat_chan_common *chan = to_chan_common(c);
1157                 struct kobject *parent = &c->dev->device.kobj;
1158                 int err;
1159
1160                 err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata");
1161                 if (err) {
1162                         dev_warn(to_dev(chan),
1163                                  "sysfs init error (%d), continuing...\n", err);
1164                         kobject_put(&chan->kobj);
1165                         set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state);
1166                 }
1167         }
1168 }
1169
1170 void ioat_kobject_del(struct ioatdma_device *device)
1171 {
1172         struct dma_device *dma = &device->common;
1173         struct dma_chan *c;
1174
1175         list_for_each_entry(c, &dma->channels, device_node) {
1176                 struct ioat_chan_common *chan = to_chan_common(c);
1177
1178                 if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) {
1179                         kobject_del(&chan->kobj);
1180                         kobject_put(&chan->kobj);
1181                 }
1182         }
1183 }
1184
1185 int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
1186 {
1187         struct pci_dev *pdev = device->pdev;
1188         struct dma_device *dma;
1189         int err;
1190
1191         device->intr_quirk = ioat1_intr_quirk;
1192         device->enumerate_channels = ioat1_enumerate_channels;
1193         device->self_test = ioat_dma_self_test;
1194         device->timer_fn = ioat1_timer_event;
1195         device->cleanup_fn = ioat1_cleanup_event;
1196         dma = &device->common;
1197         dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1198         dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1199         dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1200         dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1201         dma->device_is_tx_complete = ioat_is_dma_complete;
1202
1203         err = ioat_probe(device);
1204         if (err)
1205                 return err;
1206         ioat_set_tcp_copy_break(4096);
1207         err = ioat_register(device);
1208         if (err)
1209                 return err;
1210         ioat_kobject_add(device, &ioat1_ktype);
1211
1212         if (dca)
1213                 device->dca = ioat_dca_init(pdev, device->reg_base);
1214
1215         return err;
1216 }
1217
1218 void __devexit ioat_dma_remove(struct ioatdma_device *device)
1219 {
1220         struct dma_device *dma = &device->common;
1221
1222         ioat_disable_interrupts(device);
1223
1224         ioat_kobject_del(device);
1225
1226         dma_async_device_unregister(dma);
1227
1228         pci_pool_destroy(device->dma_pool);
1229         pci_pool_destroy(device->completion_pool);
1230
1231         INIT_LIST_HEAD(&dma->channels);
1232 }