drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/module.h>
  23 #include <linux/types.h>
  24 #include <linux/bitops.h>
  25 #include <linux/mm.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/clk.h>
  28 #include <linux/delay.h>
  29 #include <linux/sched.h>
  30 #include <linux/semaphore.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/device.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/firmware.h>
  35 #include <linux/slab.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/dmaengine.h>
  38 #include <linux/of.h>
  39 #include <linux/of_address.h>
  40 #include <linux/of_device.h>
  41 #include <linux/of_dma.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/dma-imx-sdma.h>
  45 #include <linux/platform_data/dma-imx.h>
  46 #include <linux/regmap.h>
  47 #include <linux/mfd/syscon.h>
  48 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  49
  50 #include "dmaengine.h"
  51
  52 /* SDMA registers */
  53 #define SDMA_H_C0PTR            0x000
  54 #define SDMA_H_INTR             0x004
  55 #define SDMA_H_STATSTOP         0x008
  56 #define SDMA_H_START            0x00c
  57 #define SDMA_H_EVTOVR           0x010
  58 #define SDMA_H_DSPOVR           0x014
  59 #define SDMA_H_HOSTOVR          0x018
  60 #define SDMA_H_EVTPEND          0x01c
  61 #define SDMA_H_DSPENBL          0x020
  62 #define SDMA_H_RESET            0x024
  63 #define SDMA_H_EVTERR           0x028
  64 #define SDMA_H_INTRMSK          0x02c
  65 #define SDMA_H_PSW              0x030
  66 #define SDMA_H_EVTERRDBG        0x034
  67 #define SDMA_H_CONFIG           0x038
  68 #define SDMA_ONCE_ENB           0x040
  69 #define SDMA_ONCE_DATA          0x044
  70 #define SDMA_ONCE_INSTR         0x048
  71 #define SDMA_ONCE_STAT          0x04c
  72 #define SDMA_ONCE_CMD           0x050
  73 #define SDMA_EVT_MIRROR         0x054
  74 #define SDMA_ILLINSTADDR        0x058
  75 #define SDMA_CHN0ADDR           0x05c
  76 #define SDMA_ONCE_RTB           0x060
  77 #define SDMA_XTRIG_CONF1        0x070
  78 #define SDMA_XTRIG_CONF2        0x074
  79 #define SDMA_CHNENBL0_IMX35     0x200
  80 #define SDMA_CHNENBL0_IMX31     0x080
  81 #define SDMA_CHNPRI_0           0x100
  82
  83 /*
  84  * Buffer descriptor status values.
  85  */
  86 #define BD_DONE  0x01
  87 #define BD_WRAP  0x02
  88 #define BD_CONT  0x04
  89 #define BD_INTR  0x08
  90 #define BD_RROR  0x10
  91 #define BD_LAST  0x20
  92 #define BD_EXTD  0x80
  93
  94 /*
  95  * Data Node descriptor status values.
  96  */
  97 #define DND_END_OF_FRAME  0x80
  98 #define DND_END_OF_XFER   0x40
  99 #define DND_DONE          0x20
 100 #define DND_UNUSED        0x01
 101
 102 /*
 103  * IPCV2 descriptor status values.
 104  */
 105 #define BD_IPCV2_END_OF_FRAME  0x40
 106
 107 #define IPCV2_MAX_NODES        50
 108 /*
 109  * Error bit set in the CCB status field by the SDMA,
 110  * in setbd routine, in case of a transfer error
 111  */
 112 #define DATA_ERROR  0x10000000
 113
 114 /*
 115  * Buffer descriptor commands.
 116  */
 117 #define C0_ADDR             0x01
 118 #define C0_LOAD             0x02
 119 #define C0_DUMP             0x03
 120 #define C0_SETCTX           0x07
 121 #define C0_GETCTX           0x03
 122 #define C0_SETDM            0x01
 123 #define C0_SETPM            0x04
 124 #define C0_GETDM            0x02
 125 #define C0_GETPM            0x08
 126 /*
 127  * Change endianness indicator in the BD command field
 128  */
 129 #define CHANGE_ENDIANNESS   0x80
 130
 131 /*
 132  *  p_2_p watermark_level description
 133  *      Bits            Name                    Description
 134  *      0-7             Lower WML               Lower watermark level
 135  *      8               PS                      1: Pad Swallowing
 136  *                                              0: No Pad Swallowing
 137  *      9               PA                      1: Pad Adding
 138  *                                              0: No Pad Adding
 139  *      10              SPDIF                   If this bit is set both source
 140  *                                              and destination are on SPBA
 141  *      11              Source Bit(SP)          1: Source on SPBA
 142  *                                              0: Source on AIPS
 143  *      12              Destination Bit(DP)     1: Destination on SPBA
 144  *                                              0: Destination on AIPS
 145  *      13-15           ---------               MUST BE 0
 146  *      16-23           Higher WML              HWML
 147  *      24-27           N                       Total number of samples after
 148  *                                              which Pad adding/Swallowing
 149  *                                              must be done. It must be odd.
 150  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 151  *                                              LWML event mask
 152  *                                              0: LWE in EVENTS register
 153  *                                              1: LWE in EVENTS2 register
 154  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 155  *                                              HWML event mask
 156  *                                              0: HWE in EVENTS register
 157  *                                              1: HWE in EVENTS2 register
 158  *      30              ---------               MUST BE 0
 159  *      31              CONT                    1: Amount of samples to be
 160  *                                              transferred is unknown and
 161  *                                              script will keep on
 162  *                                              transferring samples as long as
 163  *                                              both events are detected and
 164  *                                              script must be manually stopped
 165  *                                              by the application
 166  *                                              0: The amount of samples to be
 167  *                                              transferred is equal to the
 168  *                                              count field of mode word
 169  */
 170 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 171 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 172 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 173 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 174 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 175 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 176 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 177 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 178 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 179 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 180
 181 #define SDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 182                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 183                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 184
 185 #define SDMA_DMA_DIRECTIONS     (BIT(DMA_DEV_TO_MEM) | \
 186                                  BIT(DMA_MEM_TO_DEV) | \
 187                                  BIT(DMA_DEV_TO_DEV))
 188
 189 /*
 190  * Mode/Count of data node descriptors - IPCv2
 191  */
 192 struct sdma_mode_count {
 193         u32 count   : 16; /* size of the buffer pointed by this BD */
 194         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 195         u32 command :  8; /* command mostly used for channel 0 */
 196 };
 197
 198 /*
 199  * Buffer descriptor
 200  */
 201 struct sdma_buffer_descriptor {
 202         struct sdma_mode_count  mode;
 203         u32 buffer_addr;        /* address of the buffer described */
 204         u32 ext_buffer_addr;    /* extended buffer address */
 205 } __attribute__ ((packed));
 206
 207 /**
 208  * struct sdma_channel_control - Channel control Block
 209  *
 210  * @current_bd_ptr      current buffer descriptor processed
 211  * @base_bd_ptr         first element of buffer descriptor array
 212  * @unused              padding. The SDMA engine expects an array of 128 byte
 213  *                      control blocks
 214  */
 215 struct sdma_channel_control {
 216         u32 current_bd_ptr;
 217         u32 base_bd_ptr;
 218         u32 unused[2];
 219 } __attribute__ ((packed));
 220
 221 /**
 222  * struct sdma_state_registers - SDMA context for a channel
 223  *
 224  * @pc:         program counter
 225  * @t:          test bit: status of arithmetic & test instruction
 226  * @rpc:        return program counter
 227  * @sf:         source fault while loading data
 228  * @spc:        loop start program counter
 229  * @df:         destination fault while storing data
 230  * @epc:        loop end program counter
 231  * @lm:         loop mode
 232  */
 233 struct sdma_state_registers {
 234         u32 pc     :14;
 235         u32 unused1: 1;
 236         u32 t      : 1;
 237         u32 rpc    :14;
 238         u32 unused0: 1;
 239         u32 sf     : 1;
 240         u32 spc    :14;
 241         u32 unused2: 1;
 242         u32 df     : 1;
 243         u32 epc    :14;
 244         u32 lm     : 2;
 245 } __attribute__ ((packed));
 246
 247 /**
 248  * struct sdma_context_data - sdma context specific to a channel
 249  *
 250  * @channel_state:      channel state bits
 251  * @gReg:               general registers
 252  * @mda:                burst dma destination address register
 253  * @msa:                burst dma source address register
 254  * @ms:                 burst dma status register
 255  * @md:                 burst dma data register
 256  * @pda:                peripheral dma destination address register
 257  * @psa:                peripheral dma source address register
 258  * @ps:                 peripheral dma status register
 259  * @pd:                 peripheral dma data register
 260  * @ca:                 CRC polynomial register
 261  * @cs:                 CRC accumulator register
 262  * @dda:                dedicated core destination address register
 263  * @dsa:                dedicated core source address register
 264  * @ds:                 dedicated core status register
 265  * @dd:                 dedicated core data register
 266  */
 267 struct sdma_context_data {
 268         struct sdma_state_registers  channel_state;
 269         u32  gReg[8];
 270         u32  mda;
 271         u32  msa;
 272         u32  ms;
 273         u32  md;
 274         u32  pda;
 275         u32  psa;
 276         u32  ps;
 277         u32  pd;
 278         u32  ca;
 279         u32  cs;
 280         u32  dda;
 281         u32  dsa;
 282         u32  ds;
 283         u32  dd;
 284         u32  scratch0;
 285         u32  scratch1;
 286         u32  scratch2;
 287         u32  scratch3;
 288         u32  scratch4;
 289         u32  scratch5;
 290         u32  scratch6;
 291         u32  scratch7;
 292 } __attribute__ ((packed));
 293
 294 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 295
 296 struct sdma_engine;
 297
 298 /**
 299  * struct sdma_channel - housekeeping for a SDMA channel
 300  *
 301  * @sdma                pointer to the SDMA engine for this channel
 302  * @channel             the channel number, matches dmaengine chan_id + 1
 303  * @direction           transfer type. Needed for setting SDMA script
 304  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 305  * @event_id0           aka dma request line
 306  * @event_id1           for channels that use 2 events
 307  * @word_size           peripheral access size
 308  * @buf_tail            ID of the buffer that was processed
 309  * @buf_ptail           ID of the previous buffer that was processed
 310  * @num_bd              max NUM_BD. number of descriptors currently handling
 311  */
 312 struct sdma_channel {
 313         struct sdma_engine              *sdma;
 314         unsigned int                    channel;
 315         enum dma_transfer_direction             direction;
 316         enum sdma_peripheral_type       peripheral_type;
 317         unsigned int                    event_id0;
 318         unsigned int                    event_id1;
 319         enum dma_slave_buswidth         word_size;
 320         unsigned int                    buf_tail;
 321         unsigned int                    buf_ptail;
 322         unsigned int                    num_bd;
 323         unsigned int                    period_len;
 324         struct sdma_buffer_descriptor   *bd;
 325         dma_addr_t                      bd_phys;
 326         unsigned int                    pc_from_device, pc_to_device;
 327         unsigned int                    device_to_device;
 328         unsigned long                   flags;
 329         dma_addr_t                      per_address, per_address2;
 330         unsigned long                   event_mask[2];
 331         unsigned long                   watermark_level;
 332         u32                             shp_addr, per_addr;
 333         struct dma_chan                 chan;
 334         spinlock_t                      lock;
 335         struct dma_async_tx_descriptor  desc;
 336         enum dma_status                 status;
 337         unsigned int                    chn_count;
 338         unsigned int                    chn_real_count;
 339         struct tasklet_struct           tasklet;
 340         struct imx_dma_data             data;
 341 };
 342
 343 #define IMX_DMA_SG_LOOP         BIT(0)
 344
 345 #define MAX_DMA_CHANNELS 32
 346 #define MXC_SDMA_DEFAULT_PRIORITY 1
 347 #define MXC_SDMA_MIN_PRIORITY 1
 348 #define MXC_SDMA_MAX_PRIORITY 7
 349
 350 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 351
 352 /**
 353  * struct sdma_firmware_header - Layout of the firmware image
 354  *
 355  * @magic               "SDMA"
 356  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 357  *                      changes.
 358  * @version_minor       firmware minor version (for binary compatible changes)
 359  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 360  * @num_script_addrs    Number of script addresses in this image
 361  * @ram_code_start      offset of SDMA ram image in this firmware image
 362  * @ram_code_size       size of SDMA ram image
 363  * @script_addrs        Stores the start address of the SDMA scripts
 364  *                      (in SDMA memory space)
 365  */
 366 struct sdma_firmware_header {
 367         u32     magic;
 368         u32     version_major;
 369         u32     version_minor;
 370         u32     script_addrs_start;
 371         u32     num_script_addrs;
 372         u32     ram_code_start;
 373         u32     ram_code_size;
 374 };
 375
 376 struct sdma_driver_data {
 377         int chnenbl0;
 378         int num_events;
 379         struct sdma_script_start_addrs  *script_addrs;
 380 };
 381
 382 struct sdma_engine {
 383         struct device                   *dev;
 384         struct device_dma_parameters    dma_parms;
 385         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 386         struct sdma_channel_control     *channel_control;
 387         void __iomem                    *regs;
 388         struct sdma_context_data        *context;
 389         dma_addr_t                      context_phys;
 390         struct dma_device               dma_device;
 391         struct clk                      *clk_ipg;
 392         struct clk                      *clk_ahb;
 393         spinlock_t                      channel_0_lock;
 394         u32                             script_number;
 395         struct sdma_script_start_addrs  *script_addrs;
 396         const struct sdma_driver_data   *drvdata;
 397         u32                             spba_start_addr;
 398         u32                             spba_end_addr;
 399         unsigned int                    irq;
 400 };
 401
 402 static struct sdma_driver_data sdma_imx31 = {
 403         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 404         .num_events = 32,
 405 };
 406
 407 static struct sdma_script_start_addrs sdma_script_imx25 = {
 408         .ap_2_ap_addr = 729,
 409         .uart_2_mcu_addr = 904,
 410         .per_2_app_addr = 1255,
 411         .mcu_2_app_addr = 834,
 412         .uartsh_2_mcu_addr = 1120,
 413         .per_2_shp_addr = 1329,
 414         .mcu_2_shp_addr = 1048,
 415         .ata_2_mcu_addr = 1560,
 416         .mcu_2_ata_addr = 1479,
 417         .app_2_per_addr = 1189,
 418         .app_2_mcu_addr = 770,
 419         .shp_2_per_addr = 1407,
 420         .shp_2_mcu_addr = 979,
 421 };
 422
 423 static struct sdma_driver_data sdma_imx25 = {
 424         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 425         .num_events = 48,
 426         .script_addrs = &sdma_script_imx25,
 427 };
 428
 429 static struct sdma_driver_data sdma_imx35 = {
 430         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 431         .num_events = 48,
 432 };
 433
 434 static struct sdma_script_start_addrs sdma_script_imx51 = {
 435         .ap_2_ap_addr = 642,
 436         .uart_2_mcu_addr = 817,
 437         .mcu_2_app_addr = 747,
 438         .mcu_2_shp_addr = 961,
 439         .ata_2_mcu_addr = 1473,
 440         .mcu_2_ata_addr = 1392,
 441         .app_2_per_addr = 1033,
 442         .app_2_mcu_addr = 683,
 443         .shp_2_per_addr = 1251,
 444         .shp_2_mcu_addr = 892,
 445 };
 446
 447 static struct sdma_driver_data sdma_imx51 = {
 448         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 449         .num_events = 48,
 450         .script_addrs = &sdma_script_imx51,
 451 };
 452
 453 static struct sdma_script_start_addrs sdma_script_imx53 = {
 454         .ap_2_ap_addr = 642,
 455         .app_2_mcu_addr = 683,
 456         .mcu_2_app_addr = 747,
 457         .uart_2_mcu_addr = 817,
 458         .shp_2_mcu_addr = 891,
 459         .mcu_2_shp_addr = 960,
 460         .uartsh_2_mcu_addr = 1032,
 461         .spdif_2_mcu_addr = 1100,
 462         .mcu_2_spdif_addr = 1134,
 463         .firi_2_mcu_addr = 1193,
 464         .mcu_2_firi_addr = 1290,
 465 };
 466
 467 static struct sdma_driver_data sdma_imx53 = {
 468         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 469         .num_events = 48,
 470         .script_addrs = &sdma_script_imx53,
 471 };
 472
 473 static struct sdma_script_start_addrs sdma_script_imx6q = {
 474         .ap_2_ap_addr = 642,
 475         .uart_2_mcu_addr = 817,
 476         .mcu_2_app_addr = 747,
 477         .per_2_per_addr = 6331,
 478         .uartsh_2_mcu_addr = 1032,
 479         .mcu_2_shp_addr = 960,
 480         .app_2_mcu_addr = 683,
 481         .shp_2_mcu_addr = 891,
 482         .spdif_2_mcu_addr = 1100,
 483         .mcu_2_spdif_addr = 1134,
 484 };
 485
 486 static struct sdma_driver_data sdma_imx6q = {
 487         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 488         .num_events = 48,
 489         .script_addrs = &sdma_script_imx6q,
 490 };
 491
 492 static struct sdma_script_start_addrs sdma_script_imx7d = {
 493         .ap_2_ap_addr = 644,
 494         .uart_2_mcu_addr = 819,
 495         .mcu_2_app_addr = 749,
 496         .uartsh_2_mcu_addr = 1034,
 497         .mcu_2_shp_addr = 962,
 498         .app_2_mcu_addr = 685,
 499         .shp_2_mcu_addr = 893,
 500         .spdif_2_mcu_addr = 1102,
 501         .mcu_2_spdif_addr = 1136,
 502 };
 503
 504 static struct sdma_driver_data sdma_imx7d = {
 505         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 506         .num_events = 48,
 507         .script_addrs = &sdma_script_imx7d,
 508 };
 509
 510 static const struct platform_device_id sdma_devtypes[] = {
 511         {
 512                 .name = "imx25-sdma",
 513                 .driver_data = (unsigned long)&sdma_imx25,
 514         }, {
 515                 .name = "imx31-sdma",
 516                 .driver_data = (unsigned long)&sdma_imx31,
 517         }, {
 518                 .name = "imx35-sdma",
 519                 .driver_data = (unsigned long)&sdma_imx35,
 520         }, {
 521                 .name = "imx51-sdma",
 522                 .driver_data = (unsigned long)&sdma_imx51,
 523         }, {
 524                 .name = "imx53-sdma",
 525                 .driver_data = (unsigned long)&sdma_imx53,
 526         }, {
 527                 .name = "imx6q-sdma",
 528                 .driver_data = (unsigned long)&sdma_imx6q,
 529         }, {
 530                 .name = "imx7d-sdma",
 531                 .driver_data = (unsigned long)&sdma_imx7d,
 532         }, {
 533                 /* sentinel */
 534         }
 535 };
 536 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 537
 538 static const struct of_device_id sdma_dt_ids[] = {
 539         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 540         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 541         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 542         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 543         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 544         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 545         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
 546         { /* sentinel */ }
 547 };
 548 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 549
 550 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 551 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 552 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 553 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 554
 555 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 556 {
 557         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 558         return chnenbl0 + event * 4;
 559 }
 560
 561 static int sdma_config_ownership(struct sdma_channel *sdmac,
 562                 bool event_override, bool mcu_override, bool dsp_override)
 563 {
 564         struct sdma_engine *sdma = sdmac->sdma;
 565         int channel = sdmac->channel;
 566         unsigned long evt, mcu, dsp;
 567
 568         if (event_override && mcu_override && dsp_override)
 569                 return -EINVAL;
 570
 571         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 572         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 573         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 574
 575         if (dsp_override)
 576                 __clear_bit(channel, &dsp);
 577         else
 578                 __set_bit(channel, &dsp);
 579
 580         if (event_override)
 581                 __clear_bit(channel, &evt);
 582         else
 583                 __set_bit(channel, &evt);
 584
 585         if (mcu_override)
 586                 __clear_bit(channel, &mcu);
 587         else
 588                 __set_bit(channel, &mcu);
 589
 590         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 591         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 592         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 593
 594         return 0;
 595 }
 596
 597 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 598 {
 599         writel(BIT(channel), sdma->regs + SDMA_H_START);
 600 }
 601
 602 /*
 603  * sdma_run_channel0 - run a channel and wait till it's done
 604  */
 605 static int sdma_run_channel0(struct sdma_engine *sdma)
 606 {
 607         int ret;
 608         u32 reg;
 609
 610         sdma_enable_channel(sdma, 0);
 611
 612         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 613                                                 reg, !(reg & 1), 1, 500);
 614         if (ret)
 615                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 616
 617         /* Set bits of CONFIG register with dynamic context switching */
 618         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
 619                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 620
 621         return ret;
 622 }
 623
 624 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 625                 u32 address)
 626 {
 627         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 628         void *buf_virt;
 629         dma_addr_t buf_phys;
 630         int ret;
 631         unsigned long flags;
 632
 633         buf_virt = dma_alloc_coherent(NULL,
 634                         size,
 635                         &buf_phys, GFP_KERNEL);
 636         if (!buf_virt) {
 637                 return -ENOMEM;
 638         }
 639
 640         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 641
 642         bd0->mode.command = C0_SETPM;
 643         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 644         bd0->mode.count = size / 2;
 645         bd0->buffer_addr = buf_phys;
 646         bd0->ext_buffer_addr = address;
 647
 648         memcpy(buf_virt, buf, size);
 649
 650         ret = sdma_run_channel0(sdma);
 651
 652         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 653
 654         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 655
 656         return ret;
 657 }
 658
 659 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 660 {
 661         struct sdma_engine *sdma = sdmac->sdma;
 662         int channel = sdmac->channel;
 663         unsigned long val;
 664         u32 chnenbl = chnenbl_ofs(sdma, event);
 665
 666         val = readl_relaxed(sdma->regs + chnenbl);
 667         __set_bit(channel, &val);
 668         writel_relaxed(val, sdma->regs + chnenbl);
 669 }
 670
 671 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 672 {
 673         struct sdma_engine *sdma = sdmac->sdma;
 674         int channel = sdmac->channel;
 675         u32 chnenbl = chnenbl_ofs(sdma, event);
 676         unsigned long val;
 677
 678         val = readl_relaxed(sdma->regs + chnenbl);
 679         __clear_bit(channel, &val);
 680         writel_relaxed(val, sdma->regs + chnenbl);
 681 }
 682
 683 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 684 {
 685         struct sdma_buffer_descriptor *bd;
 686         int error = 0;
 687         enum dma_status old_status = sdmac->status;
 688
 689         /*
 690          * loop mode. Iterate over descriptors, re-setup them and
 691          * call callback function.
 692          */
 693         while (1) {
 694                 bd = &sdmac->bd[sdmac->buf_tail];
 695
 696                 if (bd->mode.status & BD_DONE)
 697                         break;
 698
 699                 if (bd->mode.status & BD_RROR) {
 700                         bd->mode.status &= ~BD_RROR;
 701                         sdmac->status = DMA_ERROR;
 702                         error = -EIO;
 703                 }
 704
 705                /*
 706                 * We use bd->mode.count to calculate the residue, since contains
 707                 * the number of bytes present in the current buffer descriptor.
 708                 */
 709
 710                 sdmac->chn_real_count = bd->mode.count;
 711                 bd->mode.status |= BD_DONE;
 712                 bd->mode.count = sdmac->period_len;
 713                 sdmac->buf_ptail = sdmac->buf_tail;
 714                 sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd;
 715
 716                 /*
 717                  * The callback is called from the interrupt context in order
 718                  * to reduce latency and to avoid the risk of altering the
 719                  * SDMA transaction status by the time the client tasklet is
 720                  * executed.
 721                  */
 722
 723                 dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
 724
 725                 if (error)
 726                         sdmac->status = old_status;
 727         }
 728 }
 729
 730 static void mxc_sdma_handle_channel_normal(unsigned long data)
 731 {
 732         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 733         struct sdma_buffer_descriptor *bd;
 734         int i, error = 0;
 735
 736         sdmac->chn_real_count = 0;
 737         /*
 738          * non loop mode. Iterate over all descriptors, collect
 739          * errors and call callback function
 740          */
 741         for (i = 0; i < sdmac->num_bd; i++) {
 742                 bd = &sdmac->bd[i];
 743
 744                  if (bd->mode.status & (BD_DONE | BD_RROR))
 745                         error = -EIO;
 746                  sdmac->chn_real_count += bd->mode.count;
 747         }
 748
 749         if (error)
 750                 sdmac->status = DMA_ERROR;
 751         else
 752                 sdmac->status = DMA_COMPLETE;
 753
 754         dma_cookie_complete(&sdmac->desc);
 755
 756         dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
 757 }
 758
 759 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 760 {
 761         struct sdma_engine *sdma = dev_id;
 762         unsigned long stat;
 763
 764         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 765         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 766         /* channel 0 is special and not handled here, see run_channel0() */
 767         stat &= ~1;
 768
 769         while (stat) {
 770                 int channel = fls(stat) - 1;
 771                 struct sdma_channel *sdmac = &sdma->channel[channel];
 772
 773                 if (sdmac->flags & IMX_DMA_SG_LOOP)
 774                         sdma_update_channel_loop(sdmac);
 775                 else
 776                         tasklet_schedule(&sdmac->tasklet);
 777
 778                 __clear_bit(channel, &stat);
 779         }
 780
 781         return IRQ_HANDLED;
 782 }
 783
 784 /*
 785  * sets the pc of SDMA script according to the peripheral type
 786  */
 787 static void sdma_get_pc(struct sdma_channel *sdmac,
 788                 enum sdma_peripheral_type peripheral_type)
 789 {
 790         struct sdma_engine *sdma = sdmac->sdma;
 791         int per_2_emi = 0, emi_2_per = 0;
 792         /*
 793          * These are needed once we start to support transfers between
 794          * two peripherals or memory-to-memory transfers
 795          */
 796         int per_2_per = 0;
 797
 798         sdmac->pc_from_device = 0;
 799         sdmac->pc_to_device = 0;
 800         sdmac->device_to_device = 0;
 801
 802         switch (peripheral_type) {
 803         case IMX_DMATYPE_MEMORY:
 804                 break;
 805         case IMX_DMATYPE_DSP:
 806                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 807                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 808                 break;
 809         case IMX_DMATYPE_FIRI:
 810                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 811                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 812                 break;
 813         case IMX_DMATYPE_UART:
 814                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 815                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 816                 break;
 817         case IMX_DMATYPE_UART_SP:
 818                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 819                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 820                 break;
 821         case IMX_DMATYPE_ATA:
 822                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 823                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 824                 break;
 825         case IMX_DMATYPE_CSPI:
 826         case IMX_DMATYPE_EXT:
 827         case IMX_DMATYPE_SSI:
 828         case IMX_DMATYPE_SAI:
 829                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 830                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 831                 break;
 832         case IMX_DMATYPE_SSI_DUAL:
 833                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 834                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 835                 break;
 836         case IMX_DMATYPE_SSI_SP:
 837         case IMX_DMATYPE_MMC:
 838         case IMX_DMATYPE_SDHC:
 839         case IMX_DMATYPE_CSPI_SP:
 840         case IMX_DMATYPE_ESAI:
 841         case IMX_DMATYPE_MSHC_SP:
 842                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 843                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 844                 break;
 845         case IMX_DMATYPE_ASRC:
 846                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 847                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 848                 per_2_per = sdma->script_addrs->per_2_per_addr;
 849                 break;
 850         case IMX_DMATYPE_ASRC_SP:
 851                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 852                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 853                 per_2_per = sdma->script_addrs->per_2_per_addr;
 854                 break;
 855         case IMX_DMATYPE_MSHC:
 856                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 857                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 858                 break;
 859         case IMX_DMATYPE_CCM:
 860                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 861                 break;
 862         case IMX_DMATYPE_SPDIF:
 863                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 864                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 865                 break;
 866         case IMX_DMATYPE_IPU_MEMORY:
 867                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 868                 break;
 869         default:
 870                 break;
 871         }
 872
 873         sdmac->pc_from_device = per_2_emi;
 874         sdmac->pc_to_device = emi_2_per;
 875         sdmac->device_to_device = per_2_per;
 876 }
 877
 878 static int sdma_load_context(struct sdma_channel *sdmac)
 879 {
 880         struct sdma_engine *sdma = sdmac->sdma;
 881         int channel = sdmac->channel;
 882         int load_address;
 883         struct sdma_context_data *context = sdma->context;
 884         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 885         int ret;
 886         unsigned long flags;
 887
 888         if (sdmac->direction == DMA_DEV_TO_MEM)
 889                 load_address = sdmac->pc_from_device;
 890         else if (sdmac->direction == DMA_DEV_TO_DEV)
 891                 load_address = sdmac->device_to_device;
 892         else
 893                 load_address = sdmac->pc_to_device;
 894
 895         if (load_address < 0)
 896                 return load_address;
 897
 898         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 899         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 900         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 901         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 902         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 903         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 904
 905         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 906
 907         memset(context, 0, sizeof(*context));
 908         context->channel_state.pc = load_address;
 909
 910         /* Send by context the event mask,base address for peripheral
 911          * and watermark level
 912          */
 913         context->gReg[0] = sdmac->event_mask[1];
 914         context->gReg[1] = sdmac->event_mask[0];
 915         context->gReg[2] = sdmac->per_addr;
 916         context->gReg[6] = sdmac->shp_addr;
 917         context->gReg[7] = sdmac->watermark_level;
 918
 919         bd0->mode.command = C0_SETDM;
 920         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 921         bd0->mode.count = sizeof(*context) / 4;
 922         bd0->buffer_addr = sdma->context_phys;
 923         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 924         ret = sdma_run_channel0(sdma);
 925
 926         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 927
 928         return ret;
 929 }
 930
 931 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 932 {
 933         return container_of(chan, struct sdma_channel, chan);
 934 }
 935
 936 static int sdma_disable_channel(struct dma_chan *chan)
 937 {
 938         struct sdma_channel *sdmac = to_sdma_chan(chan);
 939         struct sdma_engine *sdma = sdmac->sdma;
 940         int channel = sdmac->channel;
 941
 942         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 943         sdmac->status = DMA_ERROR;
 944
 945         return 0;
 946 }
 947
 948 static int sdma_disable_channel_with_delay(struct dma_chan *chan)
 949 {
 950         sdma_disable_channel(chan);
 951
 952         /*
 953          * According to NXP R&D team a delay of one BD SDMA cost time
 954          * (maximum is 1ms) should be added after disable of the channel
 955          * bit, to ensure SDMA core has really been stopped after SDMA
 956          * clients call .device_terminate_all.
 957          */
 958         mdelay(1);
 959
 960         return 0;
 961 }
 962
 963 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
 964 {
 965         struct sdma_engine *sdma = sdmac->sdma;
 966
 967         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
 968         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
 969
 970         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
 971         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
 972
 973         if (sdmac->event_id0 > 31)
 974                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
 975
 976         if (sdmac->event_id1 > 31)
 977                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
 978
 979         /*
 980          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
 981          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
 982          * r0(event_mask[1]) and r1(event_mask[0]).
 983          */
 984         if (lwml > hwml) {
 985                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
 986                                                 SDMA_WATERMARK_LEVEL_HWML);
 987                 sdmac->watermark_level |= hwml;
 988                 sdmac->watermark_level |= lwml << 16;
 989                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
 990         }
 991
 992         if (sdmac->per_address2 >= sdma->spba_start_addr &&
 993                         sdmac->per_address2 <= sdma->spba_end_addr)
 994                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
 995
 996         if (sdmac->per_address >= sdma->spba_start_addr &&
 997                         sdmac->per_address <= sdma->spba_end_addr)
 998                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
 999
1000         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1001 }
1002
1003 static int sdma_config_channel(struct dma_chan *chan)
1004 {
1005         struct sdma_channel *sdmac = to_sdma_chan(chan);
1006         int ret;
1007
1008         sdma_disable_channel(chan);
1009
1010         sdmac->event_mask[0] = 0;
1011         sdmac->event_mask[1] = 0;
1012         sdmac->shp_addr = 0;
1013         sdmac->per_addr = 0;
1014
1015         if (sdmac->event_id0) {
1016                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1017                         return -EINVAL;
1018                 sdma_event_enable(sdmac, sdmac->event_id0);
1019         }
1020
1021         if (sdmac->event_id1) {
1022                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1023                         return -EINVAL;
1024                 sdma_event_enable(sdmac, sdmac->event_id1);
1025         }
1026
1027         switch (sdmac->peripheral_type) {
1028         case IMX_DMATYPE_DSP:
1029                 sdma_config_ownership(sdmac, false, true, true);
1030                 break;
1031         case IMX_DMATYPE_MEMORY:
1032                 sdma_config_ownership(sdmac, false, true, false);
1033                 break;
1034         default:
1035                 sdma_config_ownership(sdmac, true, true, false);
1036                 break;
1037         }
1038
1039         sdma_get_pc(sdmac, sdmac->peripheral_type);
1040
1041         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1042                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1043                 /* Handle multiple event channels differently */
1044                 if (sdmac->event_id1) {
1045                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1046                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1047                                 sdma_set_watermarklevel_for_p2p(sdmac);
1048                 } else
1049                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1050
1051                 /* Address */
1052                 sdmac->shp_addr = sdmac->per_address;
1053                 sdmac->per_addr = sdmac->per_address2;
1054         } else {
1055                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1056         }
1057
1058         ret = sdma_load_context(sdmac);
1059
1060         return ret;
1061 }
1062
1063 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1064                 unsigned int priority)
1065 {
1066         struct sdma_engine *sdma = sdmac->sdma;
1067         int channel = sdmac->channel;
1068
1069         if (priority < MXC_SDMA_MIN_PRIORITY
1070             || priority > MXC_SDMA_MAX_PRIORITY) {
1071                 return -EINVAL;
1072         }
1073
1074         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1075
1076         return 0;
1077 }
1078
1079 static int sdma_request_channel(struct sdma_channel *sdmac)
1080 {
1081         struct sdma_engine *sdma = sdmac->sdma;
1082         int channel = sdmac->channel;
1083         int ret = -EBUSY;
1084
1085         sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
1086                                         GFP_KERNEL);
1087         if (!sdmac->bd) {
1088                 ret = -ENOMEM;
1089                 goto out;
1090         }
1091
1092         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
1093         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1094
1095         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1096         return 0;
1097 out:
1098
1099         return ret;
1100 }
1101
1102 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
1103 {
1104         unsigned long flags;
1105         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1106         dma_cookie_t cookie;
1107
1108         spin_lock_irqsave(&sdmac->lock, flags);
1109
1110         cookie = dma_cookie_assign(tx);
1111
1112         spin_unlock_irqrestore(&sdmac->lock, flags);
1113
1114         return cookie;
1115 }
1116
1117 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1118 {
1119         struct sdma_channel *sdmac = to_sdma_chan(chan);
1120         struct imx_dma_data *data = chan->private;
1121         int prio, ret;
1122
1123         if (!data)
1124                 return -EINVAL;
1125
1126         switch (data->priority) {
1127         case DMA_PRIO_HIGH:
1128                 prio = 3;
1129                 break;
1130         case DMA_PRIO_MEDIUM:
1131                 prio = 2;
1132                 break;
1133         case DMA_PRIO_LOW:
1134         default:
1135                 prio = 1;
1136                 break;
1137         }
1138
1139         sdmac->peripheral_type = data->peripheral_type;
1140         sdmac->event_id0 = data->dma_request;
1141         sdmac->event_id1 = data->dma_request2;
1142
1143         ret = clk_enable(sdmac->sdma->clk_ipg);
1144         if (ret)
1145                 return ret;
1146         ret = clk_enable(sdmac->sdma->clk_ahb);
1147         if (ret)
1148                 goto disable_clk_ipg;
1149
1150         ret = sdma_request_channel(sdmac);
1151         if (ret)
1152                 goto disable_clk_ahb;
1153
1154         ret = sdma_set_channel_priority(sdmac, prio);
1155         if (ret)
1156                 goto disable_clk_ahb;
1157
1158         dma_async_tx_descriptor_init(&sdmac->desc, chan);
1159         sdmac->desc.tx_submit = sdma_tx_submit;
1160         /* txd.flags will be overwritten in prep funcs */
1161         sdmac->desc.flags = DMA_CTRL_ACK;
1162
1163         return 0;
1164
1165 disable_clk_ahb:
1166         clk_disable(sdmac->sdma->clk_ahb);
1167 disable_clk_ipg:
1168         clk_disable(sdmac->sdma->clk_ipg);
1169         return ret;
1170 }
1171
1172 static void sdma_free_chan_resources(struct dma_chan *chan)
1173 {
1174         struct sdma_channel *sdmac = to_sdma_chan(chan);
1175         struct sdma_engine *sdma = sdmac->sdma;
1176
1177         sdma_disable_channel(chan);
1178
1179         if (sdmac->event_id0)
1180                 sdma_event_disable(sdmac, sdmac->event_id0);
1181         if (sdmac->event_id1)
1182                 sdma_event_disable(sdmac, sdmac->event_id1);
1183
1184         sdmac->event_id0 = 0;
1185         sdmac->event_id1 = 0;
1186
1187         sdma_set_channel_priority(sdmac, 0);
1188
1189         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1190
1191         clk_disable(sdma->clk_ipg);
1192         clk_disable(sdma->clk_ahb);
1193 }
1194
1195 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1196                 struct dma_chan *chan, struct scatterlist *sgl,
1197                 unsigned int sg_len, enum dma_transfer_direction direction,
1198                 unsigned long flags, void *context)
1199 {
1200         struct sdma_channel *sdmac = to_sdma_chan(chan);
1201         struct sdma_engine *sdma = sdmac->sdma;
1202         int ret, i, count;
1203         int channel = sdmac->channel;
1204         struct scatterlist *sg;
1205
1206         if (sdmac->status == DMA_IN_PROGRESS)
1207                 return NULL;
1208         sdmac->status = DMA_IN_PROGRESS;
1209
1210         sdmac->flags = 0;
1211
1212         sdmac->buf_tail = 0;
1213         sdmac->buf_ptail = 0;
1214         sdmac->chn_real_count = 0;
1215
1216         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1217                         sg_len, channel);
1218
1219         sdmac->direction = direction;
1220         ret = sdma_load_context(sdmac);
1221         if (ret)
1222                 goto err_out;
1223
1224         if (sg_len > NUM_BD) {
1225                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1226                                 channel, sg_len, NUM_BD);
1227                 ret = -EINVAL;
1228                 goto err_out;
1229         }
1230
1231         sdmac->chn_count = 0;
1232         for_each_sg(sgl, sg, sg_len, i) {
1233                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1234                 int param;
1235
1236                 bd->buffer_addr = sg->dma_address;
1237
1238                 count = sg_dma_len(sg);
1239
1240                 if (count > 0xffff) {
1241                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1242                                         channel, count, 0xffff);
1243                         ret = -EINVAL;
1244                         goto err_out;
1245                 }
1246
1247                 bd->mode.count = count;
1248                 sdmac->chn_count += count;
1249
1250                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1251                         ret =  -EINVAL;
1252                         goto err_out;
1253                 }
1254
1255                 switch (sdmac->word_size) {
1256                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1257                         bd->mode.command = 0;
1258                         if (count & 3 || sg->dma_address & 3)
1259                                 return NULL;
1260                         break;
1261                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1262                         bd->mode.command = 2;
1263                         if (count & 1 || sg->dma_address & 1)
1264                                 return NULL;
1265                         break;
1266                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1267                         bd->mode.command = 1;
1268                         break;
1269                 default:
1270                         return NULL;
1271                 }
1272
1273                 param = BD_DONE | BD_EXTD | BD_CONT;
1274
1275                 if (i + 1 == sg_len) {
1276                         param |= BD_INTR;
1277                         param |= BD_LAST;
1278                         param &= ~BD_CONT;
1279                 }
1280
1281                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1282                                 i, count, (u64)sg->dma_address,
1283                                 param & BD_WRAP ? "wrap" : "",
1284                                 param & BD_INTR ? " intr" : "");
1285
1286                 bd->mode.status = param;
1287         }
1288
1289         sdmac->num_bd = sg_len;
1290         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1291
1292         return &sdmac->desc;
1293 err_out:
1294         sdmac->status = DMA_ERROR;
1295         return NULL;
1296 }
1297
1298 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1299                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1300                 size_t period_len, enum dma_transfer_direction direction,
1301                 unsigned long flags)
1302 {
1303         struct sdma_channel *sdmac = to_sdma_chan(chan);
1304         struct sdma_engine *sdma = sdmac->sdma;
1305         int num_periods = buf_len / period_len;
1306         int channel = sdmac->channel;
1307         int ret, i = 0, buf = 0;
1308
1309         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1310
1311         if (sdmac->status == DMA_IN_PROGRESS)
1312                 return NULL;
1313
1314         sdmac->status = DMA_IN_PROGRESS;
1315
1316         sdmac->buf_tail = 0;
1317         sdmac->buf_ptail = 0;
1318         sdmac->chn_real_count = 0;
1319         sdmac->period_len = period_len;
1320
1321         sdmac->flags |= IMX_DMA_SG_LOOP;
1322         sdmac->direction = direction;
1323         ret = sdma_load_context(sdmac);
1324         if (ret)
1325                 goto err_out;
1326
1327         if (num_periods > NUM_BD) {
1328                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1329                                 channel, num_periods, NUM_BD);
1330                 goto err_out;
1331         }
1332
1333         if (period_len > 0xffff) {
1334                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1335                                 channel, period_len, 0xffff);
1336                 goto err_out;
1337         }
1338
1339         while (buf < buf_len) {
1340                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1341                 int param;
1342
1343                 bd->buffer_addr = dma_addr;
1344
1345                 bd->mode.count = period_len;
1346
1347                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1348                         goto err_out;
1349                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1350                         bd->mode.command = 0;
1351                 else
1352                         bd->mode.command = sdmac->word_size;
1353
1354                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1355                 if (i + 1 == num_periods)
1356                         param |= BD_WRAP;
1357
1358                 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1359                                 i, period_len, (u64)dma_addr,
1360                                 param & BD_WRAP ? "wrap" : "",
1361                                 param & BD_INTR ? " intr" : "");
1362
1363                 bd->mode.status = param;
1364
1365                 dma_addr += period_len;
1366                 buf += period_len;
1367
1368                 i++;
1369         }
1370
1371         sdmac->num_bd = num_periods;
1372         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1373
1374         return &sdmac->desc;
1375 err_out:
1376         sdmac->status = DMA_ERROR;
1377         return NULL;
1378 }
1379
1380 static int sdma_config(struct dma_chan *chan,
1381                        struct dma_slave_config *dmaengine_cfg)
1382 {
1383         struct sdma_channel *sdmac = to_sdma_chan(chan);
1384
1385         if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1386                 sdmac->per_address = dmaengine_cfg->src_addr;
1387                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1388                         dmaengine_cfg->src_addr_width;
1389                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1390         } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1391                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1392                 sdmac->per_address = dmaengine_cfg->dst_addr;
1393                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1394                         SDMA_WATERMARK_LEVEL_LWML;
1395                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1396                         SDMA_WATERMARK_LEVEL_HWML;
1397                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1398         } else {
1399                 sdmac->per_address = dmaengine_cfg->dst_addr;
1400                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1401                         dmaengine_cfg->dst_addr_width;
1402                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1403         }
1404         sdmac->direction = dmaengine_cfg->direction;
1405         return sdma_config_channel(chan);
1406 }
1407
1408 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1409                                       dma_cookie_t cookie,
1410                                       struct dma_tx_state *txstate)
1411 {
1412         struct sdma_channel *sdmac = to_sdma_chan(chan);
1413         u32 residue;
1414
1415         if (sdmac->flags & IMX_DMA_SG_LOOP)
1416                 residue = (sdmac->num_bd - sdmac->buf_ptail) *
1417                            sdmac->period_len - sdmac->chn_real_count;
1418         else
1419                 residue = sdmac->chn_count - sdmac->chn_real_count;
1420
1421         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1422                          residue);
1423
1424         return sdmac->status;
1425 }
1426
1427 static void sdma_issue_pending(struct dma_chan *chan)
1428 {
1429         struct sdma_channel *sdmac = to_sdma_chan(chan);
1430         struct sdma_engine *sdma = sdmac->sdma;
1431
1432         if (sdmac->status == DMA_IN_PROGRESS)
1433                 sdma_enable_channel(sdma, sdmac->channel);
1434 }
1435
1436 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1437 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1438 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1439 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1440
1441 static void sdma_add_scripts(struct sdma_engine *sdma,
1442                 const struct sdma_script_start_addrs *addr)
1443 {
1444         s32 *addr_arr = (u32 *)addr;
1445         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1446         int i;
1447
1448         /* use the default firmware in ROM if missing external firmware */
1449         if (!sdma->script_number)
1450                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1451
1452         for (i = 0; i < sdma->script_number; i++)
1453                 if (addr_arr[i] > 0)
1454                         saddr_arr[i] = addr_arr[i];
1455 }
1456
1457 static void sdma_load_firmware(const struct firmware *fw, void *context)
1458 {
1459         struct sdma_engine *sdma = context;
1460         const struct sdma_firmware_header *header;
1461         const struct sdma_script_start_addrs *addr;
1462         unsigned short *ram_code;
1463
1464         if (!fw) {
1465                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1466                 /* In this case we just use the ROM firmware. */
1467                 return;
1468         }
1469
1470         if (fw->size < sizeof(*header))
1471                 goto err_firmware;
1472
1473         header = (struct sdma_firmware_header *)fw->data;
1474
1475         if (header->magic != SDMA_FIRMWARE_MAGIC)
1476                 goto err_firmware;
1477         if (header->ram_code_start + header->ram_code_size > fw->size)
1478                 goto err_firmware;
1479         switch (header->version_major) {
1480         case 1:
1481                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1482                 break;
1483         case 2:
1484                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1485                 break;
1486         case 3:
1487                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1488                 break;
1489         case 4:
1490                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1491                 break;
1492         default:
1493                 dev_err(sdma->dev, "unknown firmware version\n");
1494                 goto err_firmware;
1495         }
1496
1497         addr = (void *)header + header->script_addrs_start;
1498         ram_code = (void *)header + header->ram_code_start;
1499
1500         clk_enable(sdma->clk_ipg);
1501         clk_enable(sdma->clk_ahb);
1502         /* download the RAM image for SDMA */
1503         sdma_load_script(sdma, ram_code,
1504                         header->ram_code_size,
1505                         addr->ram_code_start_addr);
1506         clk_disable(sdma->clk_ipg);
1507         clk_disable(sdma->clk_ahb);
1508
1509         sdma_add_scripts(sdma, addr);
1510
1511         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1512                         header->version_major,
1513                         header->version_minor);
1514
1515 err_firmware:
1516         release_firmware(fw);
1517 }
1518
1519 #define EVENT_REMAP_CELLS 3
1520
1521 static int sdma_event_remap(struct sdma_engine *sdma)
1522 {
1523         struct device_node *np = sdma->dev->of_node;
1524         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1525         struct property *event_remap;
1526         struct regmap *gpr;
1527         char propname[] = "fsl,sdma-event-remap";
1528         u32 reg, val, shift, num_map, i;
1529         int ret = 0;
1530
1531         if (IS_ERR(np) || IS_ERR(gpr_np))
1532                 goto out;
1533
1534         event_remap = of_find_property(np, propname, NULL);
1535         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1536         if (!num_map) {
1537                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1538                 goto out;
1539         } else if (num_map % EVENT_REMAP_CELLS) {
1540                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1541                                 propname, EVENT_REMAP_CELLS);
1542                 ret = -EINVAL;
1543                 goto out;
1544         }
1545
1546         gpr = syscon_node_to_regmap(gpr_np);
1547         if (IS_ERR(gpr)) {
1548                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1549                 ret = PTR_ERR(gpr);
1550                 goto out;
1551         }
1552
1553         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1554                 ret = of_property_read_u32_index(np, propname, i, &reg);
1555                 if (ret) {
1556                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1557                                         propname, i);
1558                         goto out;
1559                 }
1560
1561                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1562                 if (ret) {
1563                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1564                                         propname, i + 1);
1565                         goto out;
1566                 }
1567
1568                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1569                 if (ret) {
1570                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1571                                         propname, i + 2);
1572                         goto out;
1573                 }
1574
1575                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1576         }
1577
1578 out:
1579         if (!IS_ERR(gpr_np))
1580                 of_node_put(gpr_np);
1581
1582         return ret;
1583 }
1584
1585 static int sdma_get_firmware(struct sdma_engine *sdma,
1586                 const char *fw_name)
1587 {
1588         int ret;
1589
1590         ret = request_firmware_nowait(THIS_MODULE,
1591                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1592                         GFP_KERNEL, sdma, sdma_load_firmware);
1593
1594         return ret;
1595 }
1596
1597 static int sdma_init(struct sdma_engine *sdma)
1598 {
1599         int i, ret;
1600         dma_addr_t ccb_phys;
1601
1602         ret = clk_enable(sdma->clk_ipg);
1603         if (ret)
1604                 return ret;
1605         ret = clk_enable(sdma->clk_ahb);
1606         if (ret)
1607                 goto disable_clk_ipg;
1608
1609         /* Be sure SDMA has not started yet */
1610         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1611
1612         sdma->channel_control = dma_alloc_coherent(NULL,
1613                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1614                         sizeof(struct sdma_context_data),
1615                         &ccb_phys, GFP_KERNEL);
1616
1617         if (!sdma->channel_control) {
1618                 ret = -ENOMEM;
1619                 goto err_dma_alloc;
1620         }
1621
1622         sdma->context = (void *)sdma->channel_control +
1623                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1624         sdma->context_phys = ccb_phys +
1625                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1626
1627         /* Zero-out the CCB structures array just allocated */
1628         memset(sdma->channel_control, 0,
1629                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1630
1631         /* disable all channels */
1632         for (i = 0; i < sdma->drvdata->num_events; i++)
1633                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1634
1635         /* All channels have priority 0 */
1636         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1637                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1638
1639         ret = sdma_request_channel(&sdma->channel[0]);
1640         if (ret)
1641                 goto err_dma_alloc;
1642
1643         sdma_config_ownership(&sdma->channel[0], false, true, false);
1644
1645         /* Set Command Channel (Channel Zero) */
1646         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1647
1648         /* Set bits of CONFIG register but with static context switching */
1649         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1650         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1651
1652         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1653
1654         /* Initializes channel's priorities */
1655         sdma_set_channel_priority(&sdma->channel[0], 7);
1656
1657         clk_disable(sdma->clk_ipg);
1658         clk_disable(sdma->clk_ahb);
1659
1660         return 0;
1661
1662 err_dma_alloc:
1663         clk_disable(sdma->clk_ahb);
1664 disable_clk_ipg:
1665         clk_disable(sdma->clk_ipg);
1666         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1667         return ret;
1668 }
1669
1670 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1671 {
1672         struct sdma_channel *sdmac = to_sdma_chan(chan);
1673         struct imx_dma_data *data = fn_param;
1674
1675         if (!imx_dma_is_general_purpose(chan))
1676                 return false;
1677
1678         sdmac->data = *data;
1679         chan->private = &sdmac->data;
1680
1681         return true;
1682 }
1683
1684 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1685                                    struct of_dma *ofdma)
1686 {
1687         struct sdma_engine *sdma = ofdma->of_dma_data;
1688         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1689         struct imx_dma_data data;
1690
1691         if (dma_spec->args_count != 3)
1692                 return NULL;
1693
1694         data.dma_request = dma_spec->args[0];
1695         data.peripheral_type = dma_spec->args[1];
1696         data.priority = dma_spec->args[2];
1697         /*
1698          * init dma_request2 to zero, which is not used by the dts.
1699          * For P2P, dma_request2 is init from dma_request_channel(),
1700          * chan->private will point to the imx_dma_data, and in
1701          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1702          * be set to sdmac->event_id1.
1703          */
1704         data.dma_request2 = 0;
1705
1706         return dma_request_channel(mask, sdma_filter_fn, &data);
1707 }
1708
1709 static int sdma_probe(struct platform_device *pdev)
1710 {
1711         const struct of_device_id *of_id =
1712                         of_match_device(sdma_dt_ids, &pdev->dev);
1713         struct device_node *np = pdev->dev.of_node;
1714         struct device_node *spba_bus;
1715         const char *fw_name;
1716         int ret;
1717         int irq;
1718         struct resource *iores;
1719         struct resource spba_res;
1720         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1721         int i;
1722         struct sdma_engine *sdma;
1723         s32 *saddr_arr;
1724         const struct sdma_driver_data *drvdata = NULL;
1725
1726         if (of_id)
1727                 drvdata = of_id->data;
1728         else if (pdev->id_entry)
1729                 drvdata = (void *)pdev->id_entry->driver_data;
1730
1731         if (!drvdata) {
1732                 dev_err(&pdev->dev, "unable to find driver data\n");
1733                 return -EINVAL;
1734         }
1735
1736         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1737         if (ret)
1738                 return ret;
1739
1740         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1741         if (!sdma)
1742                 return -ENOMEM;
1743
1744         spin_lock_init(&sdma->channel_0_lock);
1745
1746         sdma->dev = &pdev->dev;
1747         sdma->drvdata = drvdata;
1748
1749         irq = platform_get_irq(pdev, 0);
1750         if (irq < 0)
1751                 return irq;
1752
1753         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1754         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1755         if (IS_ERR(sdma->regs))
1756                 return PTR_ERR(sdma->regs);
1757
1758         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1759         if (IS_ERR(sdma->clk_ipg))
1760                 return PTR_ERR(sdma->clk_ipg);
1761
1762         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1763         if (IS_ERR(sdma->clk_ahb))
1764                 return PTR_ERR(sdma->clk_ahb);
1765
1766         ret = clk_prepare(sdma->clk_ipg);
1767         if (ret)
1768                 return ret;
1769
1770         ret = clk_prepare(sdma->clk_ahb);
1771         if (ret)
1772                 goto err_clk;
1773
1774         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1775                                sdma);
1776         if (ret)
1777                 goto err_irq;
1778
1779         sdma->irq = irq;
1780
1781         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1782         if (!sdma->script_addrs) {
1783                 ret = -ENOMEM;
1784                 goto err_irq;
1785         }
1786
1787         /* initially no scripts available */
1788         saddr_arr = (s32 *)sdma->script_addrs;
1789         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1790                 saddr_arr[i] = -EINVAL;
1791
1792         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1793         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1794
1795         INIT_LIST_HEAD(&sdma->dma_device.channels);
1796         /* Initialize channel parameters */
1797         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1798                 struct sdma_channel *sdmac = &sdma->channel[i];
1799
1800                 sdmac->sdma = sdma;
1801                 spin_lock_init(&sdmac->lock);
1802
1803                 sdmac->chan.device = &sdma->dma_device;
1804                 dma_cookie_init(&sdmac->chan);
1805                 sdmac->channel = i;
1806
1807                 tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal,
1808                              (unsigned long) sdmac);
1809                 /*
1810                  * Add the channel to the DMAC list. Do not add channel 0 though
1811                  * because we need it internally in the SDMA driver. This also means
1812                  * that channel 0 in dmaengine counting matches sdma channel 1.
1813                  */
1814                 if (i)
1815                         list_add_tail(&sdmac->chan.device_node,
1816                                         &sdma->dma_device.channels);
1817         }
1818
1819         ret = sdma_init(sdma);
1820         if (ret)
1821                 goto err_init;
1822
1823         ret = sdma_event_remap(sdma);
1824         if (ret)
1825                 goto err_init;
1826
1827         if (sdma->drvdata->script_addrs)
1828                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1829         if (pdata && pdata->script_addrs)
1830                 sdma_add_scripts(sdma, pdata->script_addrs);
1831
1832         if (pdata) {
1833                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1834                 if (ret)
1835                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1836         } else {
1837                 /*
1838                  * Because that device tree does not encode ROM script address,
1839                  * the RAM script in firmware is mandatory for device tree
1840                  * probe, otherwise it fails.
1841                  */
1842                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1843                                               &fw_name);
1844                 if (ret)
1845                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1846                 else {
1847                         ret = sdma_get_firmware(sdma, fw_name);
1848                         if (ret)
1849                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1850                 }
1851         }
1852
1853         sdma->dma_device.dev = &pdev->dev;
1854
1855         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1856         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1857         sdma->dma_device.device_tx_status = sdma_tx_status;
1858         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1859         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1860         sdma->dma_device.device_config = sdma_config;
1861         sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay;
1862         sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
1863         sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
1864         sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
1865         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1866         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1867         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1868         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1869
1870         platform_set_drvdata(pdev, sdma);
1871
1872         ret = dma_async_device_register(&sdma->dma_device);
1873         if (ret) {
1874                 dev_err(&pdev->dev, "unable to register\n");
1875                 goto err_init;
1876         }
1877
1878         if (np) {
1879                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1880                 if (ret) {
1881                         dev_err(&pdev->dev, "failed to register controller\n");
1882                         goto err_register;
1883                 }
1884
1885                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1886                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1887                 if (!ret) {
1888                         sdma->spba_start_addr = spba_res.start;
1889                         sdma->spba_end_addr = spba_res.end;
1890                 }
1891                 of_node_put(spba_bus);
1892         }
1893
1894         return 0;
1895
1896 err_register:
1897         dma_async_device_unregister(&sdma->dma_device);
1898 err_init:
1899         kfree(sdma->script_addrs);
1900 err_irq:
1901         clk_unprepare(sdma->clk_ahb);
1902 err_clk:
1903         clk_unprepare(sdma->clk_ipg);
1904         return ret;
1905 }
1906
1907 static int sdma_remove(struct platform_device *pdev)
1908 {
1909         struct sdma_engine *sdma = platform_get_drvdata(pdev);
1910         int i;
1911
1912         devm_free_irq(&pdev->dev, sdma->irq, sdma);
1913         dma_async_device_unregister(&sdma->dma_device);
1914         kfree(sdma->script_addrs);
1915         clk_unprepare(sdma->clk_ahb);
1916         clk_unprepare(sdma->clk_ipg);
1917         /* Kill the tasklet */
1918         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1919                 struct sdma_channel *sdmac = &sdma->channel[i];
1920
1921                 tasklet_kill(&sdmac->tasklet);
1922         }
1923
1924         platform_set_drvdata(pdev, NULL);
1925         return 0;
1926 }
1927
1928 static struct platform_driver sdma_driver = {
1929         .driver         = {
1930                 .name   = "imx-sdma",
1931                 .of_match_table = sdma_dt_ids,
1932         },
1933         .id_table       = sdma_devtypes,
1934         .remove         = sdma_remove,
1935         .probe          = sdma_probe,
1936 };
1937
1938 module_platform_driver(sdma_driver);
1939
1940 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1941 MODULE_DESCRIPTION("i.MX SDMA driver");
1942 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
1943 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
1944 #endif
1945 #if IS_ENABLED(CONFIG_SOC_IMX7D)
1946 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
1947 #endif
1948 MODULE_LICENSE("GPL");