drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mm.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has been tested with the Atmel AT32AP7000, which does not
  37  * support descriptor writeback.
  38  */
  39
  40 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  41                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  42                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  43                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  44                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  45                         DW_DMA_MSIZE_16;                        \
  46                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  47                         DW_DMA_MSIZE_16;                        \
  48                 u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ?         \
  49                         _dwc->dws.p_master : _dwc->dws.m_master;        \
  50                 u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ?         \
  51                         _dwc->dws.p_master : _dwc->dws.m_master;        \
  52                                                                 \
  53                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  54                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  55                  | DWC_CTLL_LLP_D_EN                            \
  56                  | DWC_CTLL_LLP_S_EN                            \
  57                  | DWC_CTLL_DMS(_dms)                           \
  58                  | DWC_CTLL_SMS(_sms));                         \
  59         })
  60
  61 /* The set of bus widths supported by the DMA controller */
  62 #define DW_DMA_BUSWIDTHS                          \
  63         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)       | \
  64         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)          | \
  65         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)         | \
  66         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  67
  68 /*----------------------------------------------------------------------*/
  69
  70 static struct device *chan2dev(struct dma_chan *chan)
  71 {
  72         return &chan->dev->device;
  73 }
  74
  75 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  76 {
  77         return to_dw_desc(dwc->active_list.next);
  78 }
  79
  80 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
  81 {
  82         struct dw_desc          *desc = txd_to_dw_desc(tx);
  83         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
  84         dma_cookie_t            cookie;
  85         unsigned long           flags;
  86
  87         spin_lock_irqsave(&dwc->lock, flags);
  88         cookie = dma_cookie_assign(tx);
  89
  90         /*
  91          * REVISIT: We should attempt to chain as many descriptors as
  92          * possible, perhaps even appending to those already submitted
  93          * for DMA. But this is hard to do in a race-free manner.
  94          */
  95
  96         list_add_tail(&desc->desc_node, &dwc->queue);
  97         spin_unlock_irqrestore(&dwc->lock, flags);
  98         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n",
  99                  __func__, desc->txd.cookie);
 100
 101         return cookie;
 102 }
 103
 104 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
 105 {
 106         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 107         struct dw_desc *desc;
 108         dma_addr_t phys;
 109
 110         desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys);
 111         if (!desc)
 112                 return NULL;
 113
 114         dwc->descs_allocated++;
 115         INIT_LIST_HEAD(&desc->tx_list);
 116         dma_async_tx_descriptor_init(&desc->txd, &dwc->chan);
 117         desc->txd.tx_submit = dwc_tx_submit;
 118         desc->txd.flags = DMA_CTRL_ACK;
 119         desc->txd.phys = phys;
 120         return desc;
 121 }
 122
 123 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 124 {
 125         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 126         struct dw_desc *child, *_next;
 127
 128         if (unlikely(!desc))
 129                 return;
 130
 131         list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) {
 132                 list_del(&child->desc_node);
 133                 dma_pool_free(dw->desc_pool, child, child->txd.phys);
 134                 dwc->descs_allocated--;
 135         }
 136
 137         dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
 138         dwc->descs_allocated--;
 139 }
 140
 141 static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc)
 142 {
 143         u32 cfghi = 0;
 144         u32 cfglo = 0;
 145
 146         /* Set default burst alignment */
 147         cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
 148
 149         /* Low 4 bits of the request lines */
 150         cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
 151         cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
 152
 153         /* Request line extension (2 bits) */
 154         cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
 155         cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
 156
 157         channel_writel(dwc, CFG_LO, cfglo);
 158         channel_writel(dwc, CFG_HI, cfghi);
 159 }
 160
 161 static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
 162 {
 163         u32 cfghi = DWC_CFGH_FIFO_MODE;
 164         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 165         bool hs_polarity = dwc->dws.hs_polarity;
 166
 167         cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
 168         cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
 169
 170         /* Set polarity of handshake interface */
 171         cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
 172
 173         channel_writel(dwc, CFG_LO, cfglo);
 174         channel_writel(dwc, CFG_HI, cfghi);
 175 }
 176
 177 static void dwc_initialize(struct dw_dma_chan *dwc)
 178 {
 179         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 180
 181         if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
 182                 return;
 183
 184         if (dw->pdata->is_idma32)
 185                 dwc_initialize_chan_idma32(dwc);
 186         else
 187                 dwc_initialize_chan_dw(dwc);
 188
 189         /* Enable interrupts */
 190         channel_set_bit(dw, MASK.XFER, dwc->mask);
 191         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 192
 193         set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
 194 }
 195
 196 /*----------------------------------------------------------------------*/
 197
 198 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 199 {
 200         dev_err(chan2dev(&dwc->chan),
 201                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 202                 channel_readl(dwc, SAR),
 203                 channel_readl(dwc, DAR),
 204                 channel_readl(dwc, LLP),
 205                 channel_readl(dwc, CTL_HI),
 206                 channel_readl(dwc, CTL_LO));
 207 }
 208
 209 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 210 {
 211         channel_clear_bit(dw, CH_EN, dwc->mask);
 212         while (dma_readl(dw, CH_EN) & dwc->mask)
 213                 cpu_relax();
 214 }
 215
 216 static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes,
 217                           unsigned int width, size_t *len)
 218 {
 219         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 220         u32 block;
 221
 222         /* Always in bytes for iDMA 32-bit */
 223         if (dw->pdata->is_idma32)
 224                 width = 0;
 225
 226         if ((bytes >> width) > dwc->block_size) {
 227                 block = dwc->block_size;
 228                 *len = block << width;
 229         } else {
 230                 block = bytes >> width;
 231                 *len = bytes;
 232         }
 233
 234         return block;
 235 }
 236
 237 static size_t block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
 238 {
 239         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 240
 241         if (dw->pdata->is_idma32)
 242                 return IDMA32C_CTLH_BLOCK_TS(block);
 243
 244         return DWC_CTLH_BLOCK_TS(block) << width;
 245 }
 246
 247 /*----------------------------------------------------------------------*/
 248
 249 /* Perform single block transfer */
 250 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 251                                        struct dw_desc *desc)
 252 {
 253         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 254         u32             ctllo;
 255
 256         /*
 257          * Software emulation of LLP mode relies on interrupts to continue
 258          * multi block transfer.
 259          */
 260         ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN;
 261
 262         channel_writel(dwc, SAR, lli_read(desc, sar));
 263         channel_writel(dwc, DAR, lli_read(desc, dar));
 264         channel_writel(dwc, CTL_LO, ctllo);
 265         channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi));
 266         channel_set_bit(dw, CH_EN, dwc->mask);
 267
 268         /* Move pointer to next descriptor */
 269         dwc->tx_node_active = dwc->tx_node_active->next;
 270 }
 271
 272 /* Called with dwc->lock held and bh disabled */
 273 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 274 {
 275         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 276         u8              lms = DWC_LLP_LMS(dwc->dws.m_master);
 277         unsigned long   was_soft_llp;
 278
 279         /* ASSERT:  channel is idle */
 280         if (dma_readl(dw, CH_EN) & dwc->mask) {
 281                 dev_err(chan2dev(&dwc->chan),
 282                         "%s: BUG: Attempted to start non-idle channel\n",
 283                         __func__);
 284                 dwc_dump_chan_regs(dwc);
 285
 286                 /* The tasklet will hopefully advance the queue... */
 287                 return;
 288         }
 289
 290         if (dwc->nollp) {
 291                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 292                                                 &dwc->flags);
 293                 if (was_soft_llp) {
 294                         dev_err(chan2dev(&dwc->chan),
 295                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 296                         return;
 297                 }
 298
 299                 dwc_initialize(dwc);
 300
 301                 first->residue = first->total_len;
 302                 dwc->tx_node_active = &first->tx_list;
 303
 304                 /* Submit first block */
 305                 dwc_do_single_block(dwc, first);
 306
 307                 return;
 308         }
 309
 310         dwc_initialize(dwc);
 311
 312         channel_writel(dwc, LLP, first->txd.phys | lms);
 313         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 314         channel_writel(dwc, CTL_HI, 0);
 315         channel_set_bit(dw, CH_EN, dwc->mask);
 316 }
 317
 318 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 319 {
 320         struct dw_desc *desc;
 321
 322         if (list_empty(&dwc->queue))
 323                 return;
 324
 325         list_move(dwc->queue.next, &dwc->active_list);
 326         desc = dwc_first_active(dwc);
 327         dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
 328         dwc_dostart(dwc, desc);
 329 }
 330
 331 /*----------------------------------------------------------------------*/
 332
 333 static void
 334 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 335                 bool callback_required)
 336 {
 337         struct dma_async_tx_descriptor  *txd = &desc->txd;
 338         struct dw_desc                  *child;
 339         unsigned long                   flags;
 340         struct dmaengine_desc_callback  cb;
 341
 342         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 343
 344         spin_lock_irqsave(&dwc->lock, flags);
 345         dma_cookie_complete(txd);
 346         if (callback_required)
 347                 dmaengine_desc_get_callback(txd, &cb);
 348         else
 349                 memset(&cb, 0, sizeof(cb));
 350
 351         /* async_tx_ack */
 352         list_for_each_entry(child, &desc->tx_list, desc_node)
 353                 async_tx_ack(&child->txd);
 354         async_tx_ack(&desc->txd);
 355         dwc_desc_put(dwc, desc);
 356         spin_unlock_irqrestore(&dwc->lock, flags);
 357
 358         dmaengine_desc_callback_invoke(&cb, NULL);
 359 }
 360
 361 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 362 {
 363         struct dw_desc *desc, *_desc;
 364         LIST_HEAD(list);
 365         unsigned long flags;
 366
 367         spin_lock_irqsave(&dwc->lock, flags);
 368         if (dma_readl(dw, CH_EN) & dwc->mask) {
 369                 dev_err(chan2dev(&dwc->chan),
 370                         "BUG: XFER bit set, but channel not idle!\n");
 371
 372                 /* Try to continue after resetting the channel... */
 373                 dwc_chan_disable(dw, dwc);
 374         }
 375
 376         /*
 377          * Submit queued descriptors ASAP, i.e. before we go through
 378          * the completed ones.
 379          */
 380         list_splice_init(&dwc->active_list, &list);
 381         dwc_dostart_first_queued(dwc);
 382
 383         spin_unlock_irqrestore(&dwc->lock, flags);
 384
 385         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 386                 dwc_descriptor_complete(dwc, desc, true);
 387 }
 388
 389 /* Returns how many bytes were already received from source */
 390 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 391 {
 392         u32 ctlhi = channel_readl(dwc, CTL_HI);
 393         u32 ctllo = channel_readl(dwc, CTL_LO);
 394
 395         return block2bytes(dwc, ctlhi, ctllo >> 4 & 7);
 396 }
 397
 398 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 399 {
 400         dma_addr_t llp;
 401         struct dw_desc *desc, *_desc;
 402         struct dw_desc *child;
 403         u32 status_xfer;
 404         unsigned long flags;
 405
 406         spin_lock_irqsave(&dwc->lock, flags);
 407         llp = channel_readl(dwc, LLP);
 408         status_xfer = dma_readl(dw, RAW.XFER);
 409
 410         if (status_xfer & dwc->mask) {
 411                 /* Everything we've submitted is done */
 412                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 413
 414                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 415                         struct list_head *head, *active = dwc->tx_node_active;
 416
 417                         /*
 418                          * We are inside first active descriptor.
 419                          * Otherwise something is really wrong.
 420                          */
 421                         desc = dwc_first_active(dwc);
 422
 423                         head = &desc->tx_list;
 424                         if (active != head) {
 425                                 /* Update residue to reflect last sent descriptor */
 426                                 if (active == head->next)
 427                                         desc->residue -= desc->len;
 428                                 else
 429                                         desc->residue -= to_dw_desc(active->prev)->len;
 430
 431                                 child = to_dw_desc(active);
 432
 433                                 /* Submit next block */
 434                                 dwc_do_single_block(dwc, child);
 435
 436                                 spin_unlock_irqrestore(&dwc->lock, flags);
 437                                 return;
 438                         }
 439
 440                         /* We are done here */
 441                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 442                 }
 443
 444                 spin_unlock_irqrestore(&dwc->lock, flags);
 445
 446                 dwc_complete_all(dw, dwc);
 447                 return;
 448         }
 449
 450         if (list_empty(&dwc->active_list)) {
 451                 spin_unlock_irqrestore(&dwc->lock, flags);
 452                 return;
 453         }
 454
 455         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 456                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 457                 spin_unlock_irqrestore(&dwc->lock, flags);
 458                 return;
 459         }
 460
 461         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 462
 463         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 464                 /* Initial residue value */
 465                 desc->residue = desc->total_len;
 466
 467                 /* Check first descriptors addr */
 468                 if (desc->txd.phys == DWC_LLP_LOC(llp)) {
 469                         spin_unlock_irqrestore(&dwc->lock, flags);
 470                         return;
 471                 }
 472
 473                 /* Check first descriptors llp */
 474                 if (lli_read(desc, llp) == llp) {
 475                         /* This one is currently in progress */
 476                         desc->residue -= dwc_get_sent(dwc);
 477                         spin_unlock_irqrestore(&dwc->lock, flags);
 478                         return;
 479                 }
 480
 481                 desc->residue -= desc->len;
 482                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 483                         if (lli_read(child, llp) == llp) {
 484                                 /* Currently in progress */
 485                                 desc->residue -= dwc_get_sent(dwc);
 486                                 spin_unlock_irqrestore(&dwc->lock, flags);
 487                                 return;
 488                         }
 489                         desc->residue -= child->len;
 490                 }
 491
 492                 /*
 493                  * No descriptors so far seem to be in progress, i.e.
 494                  * this one must be done.
 495                  */
 496                 spin_unlock_irqrestore(&dwc->lock, flags);
 497                 dwc_descriptor_complete(dwc, desc, true);
 498                 spin_lock_irqsave(&dwc->lock, flags);
 499         }
 500
 501         dev_err(chan2dev(&dwc->chan),
 502                 "BUG: All descriptors done, but channel not idle!\n");
 503
 504         /* Try to continue after resetting the channel... */
 505         dwc_chan_disable(dw, dwc);
 506
 507         dwc_dostart_first_queued(dwc);
 508         spin_unlock_irqrestore(&dwc->lock, flags);
 509 }
 510
 511 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc)
 512 {
 513         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 514                  lli_read(desc, sar),
 515                  lli_read(desc, dar),
 516                  lli_read(desc, llp),
 517                  lli_read(desc, ctlhi),
 518                  lli_read(desc, ctllo));
 519 }
 520
 521 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 522 {
 523         struct dw_desc *bad_desc;
 524         struct dw_desc *child;
 525         unsigned long flags;
 526
 527         dwc_scan_descriptors(dw, dwc);
 528
 529         spin_lock_irqsave(&dwc->lock, flags);
 530
 531         /*
 532          * The descriptor currently at the head of the active list is
 533          * borked. Since we don't have any way to report errors, we'll
 534          * just have to scream loudly and try to carry on.
 535          */
 536         bad_desc = dwc_first_active(dwc);
 537         list_del_init(&bad_desc->desc_node);
 538         list_move(dwc->queue.next, dwc->active_list.prev);
 539
 540         /* Clear the error flag and try to restart the controller */
 541         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 542         if (!list_empty(&dwc->active_list))
 543                 dwc_dostart(dwc, dwc_first_active(dwc));
 544
 545         /*
 546          * WARN may seem harsh, but since this only happens
 547          * when someone submits a bad physical address in a
 548          * descriptor, we should consider ourselves lucky that the
 549          * controller flagged an error instead of scribbling over
 550          * random memory locations.
 551          */
 552         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 553                                        "  cookie: %d\n", bad_desc->txd.cookie);
 554         dwc_dump_lli(dwc, bad_desc);
 555         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 556                 dwc_dump_lli(dwc, child);
 557
 558         spin_unlock_irqrestore(&dwc->lock, flags);
 559
 560         /* Pretend the descriptor completed successfully */
 561         dwc_descriptor_complete(dwc, bad_desc, true);
 562 }
 563
 564 static void dw_dma_tasklet(unsigned long data)
 565 {
 566         struct dw_dma *dw = (struct dw_dma *)data;
 567         struct dw_dma_chan *dwc;
 568         u32 status_xfer;
 569         u32 status_err;
 570         unsigned int i;
 571
 572         status_xfer = dma_readl(dw, RAW.XFER);
 573         status_err = dma_readl(dw, RAW.ERROR);
 574
 575         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 576
 577         for (i = 0; i < dw->dma.chancnt; i++) {
 578                 dwc = &dw->chan[i];
 579                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 580                         dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n");
 581                 else if (status_err & (1 << i))
 582                         dwc_handle_error(dw, dwc);
 583                 else if (status_xfer & (1 << i))
 584                         dwc_scan_descriptors(dw, dwc);
 585         }
 586
 587         /* Re-enable interrupts */
 588         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 589         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 590 }
 591
 592 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 593 {
 594         struct dw_dma *dw = dev_id;
 595         u32 status;
 596
 597         /* Check if we have any interrupt from the DMAC which is not in use */
 598         if (!dw->in_use)
 599                 return IRQ_NONE;
 600
 601         status = dma_readl(dw, STATUS_INT);
 602         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 603
 604         /* Check if we have any interrupt from the DMAC */
 605         if (!status)
 606                 return IRQ_NONE;
 607
 608         /*
 609          * Just disable the interrupts. We'll turn them back on in the
 610          * softirq handler.
 611          */
 612         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 613         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 614         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 615
 616         status = dma_readl(dw, STATUS_INT);
 617         if (status) {
 618                 dev_err(dw->dma.dev,
 619                         "BUG: Unexpected interrupts pending: 0x%x\n",
 620                         status);
 621
 622                 /* Try to recover */
 623                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 624                 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
 625                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 626                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 627                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 628         }
 629
 630         tasklet_schedule(&dw->tasklet);
 631
 632         return IRQ_HANDLED;
 633 }
 634
 635 /*----------------------------------------------------------------------*/
 636
 637 static struct dma_async_tx_descriptor *
 638 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 639                 size_t len, unsigned long flags)
 640 {
 641         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 642         struct dw_dma           *dw = to_dw_dma(chan->device);
 643         struct dw_desc          *desc;
 644         struct dw_desc          *first;
 645         struct dw_desc          *prev;
 646         size_t                  xfer_count;
 647         size_t                  offset;
 648         u8                      m_master = dwc->dws.m_master;
 649         unsigned int            src_width;
 650         unsigned int            dst_width;
 651         unsigned int            data_width = dw->pdata->data_width[m_master];
 652         u32                     ctllo;
 653         u8                      lms = DWC_LLP_LMS(m_master);
 654
 655         dev_vdbg(chan2dev(chan),
 656                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 657                         &dest, &src, len, flags);
 658
 659         if (unlikely(!len)) {
 660                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 661                 return NULL;
 662         }
 663
 664         dwc->direction = DMA_MEM_TO_MEM;
 665
 666         src_width = dst_width = __ffs(data_width | src | dest | len);
 667
 668         ctllo = DWC_DEFAULT_CTLLO(chan)
 669                         | DWC_CTLL_DST_WIDTH(dst_width)
 670                         | DWC_CTLL_SRC_WIDTH(src_width)
 671                         | DWC_CTLL_DST_INC
 672                         | DWC_CTLL_SRC_INC
 673                         | DWC_CTLL_FC_M2M;
 674         prev = first = NULL;
 675
 676         for (offset = 0; offset < len; offset += xfer_count) {
 677                 desc = dwc_desc_get(dwc);
 678                 if (!desc)
 679                         goto err_desc_get;
 680
 681                 lli_write(desc, sar, src + offset);
 682                 lli_write(desc, dar, dest + offset);
 683                 lli_write(desc, ctllo, ctllo);
 684                 lli_write(desc, ctlhi, bytes2block(dwc, len - offset, src_width, &xfer_count));
 685                 desc->len = xfer_count;
 686
 687                 if (!first) {
 688                         first = desc;
 689                 } else {
 690                         lli_write(prev, llp, desc->txd.phys | lms);
 691                         list_add_tail(&desc->desc_node, &first->tx_list);
 692                 }
 693                 prev = desc;
 694         }
 695
 696         if (flags & DMA_PREP_INTERRUPT)
 697                 /* Trigger interrupt after last block */
 698                 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
 699
 700         prev->lli.llp = 0;
 701         lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 702         first->txd.flags = flags;
 703         first->total_len = len;
 704
 705         return &first->txd;
 706
 707 err_desc_get:
 708         dwc_desc_put(dwc, first);
 709         return NULL;
 710 }
 711
 712 static struct dma_async_tx_descriptor *
 713 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 714                 unsigned int sg_len, enum dma_transfer_direction direction,
 715                 unsigned long flags, void *context)
 716 {
 717         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 718         struct dw_dma           *dw = to_dw_dma(chan->device);
 719         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 720         struct dw_desc          *prev;
 721         struct dw_desc          *first;
 722         u32                     ctllo;
 723         u8                      m_master = dwc->dws.m_master;
 724         u8                      lms = DWC_LLP_LMS(m_master);
 725         dma_addr_t              reg;
 726         unsigned int            reg_width;
 727         unsigned int            mem_width;
 728         unsigned int            data_width = dw->pdata->data_width[m_master];
 729         unsigned int            i;
 730         struct scatterlist      *sg;
 731         size_t                  total_len = 0;
 732
 733         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 734
 735         if (unlikely(!is_slave_direction(direction) || !sg_len))
 736                 return NULL;
 737
 738         dwc->direction = direction;
 739
 740         prev = first = NULL;
 741
 742         switch (direction) {
 743         case DMA_MEM_TO_DEV:
 744                 reg_width = __ffs(sconfig->dst_addr_width);
 745                 reg = sconfig->dst_addr;
 746                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 747                                 | DWC_CTLL_DST_WIDTH(reg_width)
 748                                 | DWC_CTLL_DST_FIX
 749                                 | DWC_CTLL_SRC_INC);
 750
 751                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 752                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 753
 754                 for_each_sg(sgl, sg, sg_len, i) {
 755                         struct dw_desc  *desc;
 756                         u32             len, mem;
 757                         size_t          dlen;
 758
 759                         mem = sg_dma_address(sg);
 760                         len = sg_dma_len(sg);
 761
 762                         mem_width = __ffs(data_width | mem | len);
 763
 764 slave_sg_todev_fill_desc:
 765                         desc = dwc_desc_get(dwc);
 766                         if (!desc)
 767                                 goto err_desc_get;
 768
 769                         lli_write(desc, sar, mem);
 770                         lli_write(desc, dar, reg);
 771                         lli_write(desc, ctlhi, bytes2block(dwc, len, mem_width, &dlen));
 772                         lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width));
 773                         desc->len = dlen;
 774
 775                         if (!first) {
 776                                 first = desc;
 777                         } else {
 778                                 lli_write(prev, llp, desc->txd.phys | lms);
 779                                 list_add_tail(&desc->desc_node, &first->tx_list);
 780                         }
 781                         prev = desc;
 782
 783                         mem += dlen;
 784                         len -= dlen;
 785                         total_len += dlen;
 786
 787                         if (len)
 788                                 goto slave_sg_todev_fill_desc;
 789                 }
 790                 break;
 791         case DMA_DEV_TO_MEM:
 792                 reg_width = __ffs(sconfig->src_addr_width);
 793                 reg = sconfig->src_addr;
 794                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 795                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 796                                 | DWC_CTLL_DST_INC
 797                                 | DWC_CTLL_SRC_FIX);
 798
 799                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 800                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 801
 802                 for_each_sg(sgl, sg, sg_len, i) {
 803                         struct dw_desc  *desc;
 804                         u32             len, mem;
 805                         size_t          dlen;
 806
 807                         mem = sg_dma_address(sg);
 808                         len = sg_dma_len(sg);
 809
 810 slave_sg_fromdev_fill_desc:
 811                         desc = dwc_desc_get(dwc);
 812                         if (!desc)
 813                                 goto err_desc_get;
 814
 815                         lli_write(desc, sar, reg);
 816                         lli_write(desc, dar, mem);
 817                         lli_write(desc, ctlhi, bytes2block(dwc, len, reg_width, &dlen));
 818                         mem_width = __ffs(data_width | mem | dlen);
 819                         lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
 820                         desc->len = dlen;
 821
 822                         if (!first) {
 823                                 first = desc;
 824                         } else {
 825                                 lli_write(prev, llp, desc->txd.phys | lms);
 826                                 list_add_tail(&desc->desc_node, &first->tx_list);
 827                         }
 828                         prev = desc;
 829
 830                         mem += dlen;
 831                         len -= dlen;
 832                         total_len += dlen;
 833
 834                         if (len)
 835                                 goto slave_sg_fromdev_fill_desc;
 836                 }
 837                 break;
 838         default:
 839                 return NULL;
 840         }
 841
 842         if (flags & DMA_PREP_INTERRUPT)
 843                 /* Trigger interrupt after last block */
 844                 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
 845
 846         prev->lli.llp = 0;
 847         lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 848         first->total_len = total_len;
 849
 850         return &first->txd;
 851
 852 err_desc_get:
 853         dev_err(chan2dev(chan),
 854                 "not enough descriptors available. Direction %d\n", direction);
 855         dwc_desc_put(dwc, first);
 856         return NULL;
 857 }
 858
 859 bool dw_dma_filter(struct dma_chan *chan, void *param)
 860 {
 861         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 862         struct dw_dma_slave *dws = param;
 863
 864         if (dws->dma_dev != chan->device->dev)
 865                 return false;
 866
 867         /* We have to copy data since dws can be temporary storage */
 868         memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave));
 869
 870         return true;
 871 }
 872 EXPORT_SYMBOL_GPL(dw_dma_filter);
 873
 874 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 875 {
 876         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 877         struct dma_slave_config *sc = &dwc->dma_sconfig;
 878         struct dw_dma *dw = to_dw_dma(chan->device);
 879         /*
 880          * Fix sconfig's burst size according to dw_dmac. We need to convert
 881          * them as:
 882          * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 883          *
 884          * NOTE: burst size 2 is not supported by DesignWare controller.
 885          *       iDMA 32-bit supports it.
 886          */
 887         u32 s = dw->pdata->is_idma32 ? 1 : 2;
 888
 889         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 890
 891         sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0;
 892         sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0;
 893
 894         return 0;
 895 }
 896
 897 static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain)
 898 {
 899         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 900         unsigned int            count = 20;     /* timeout iterations */
 901         u32                     cfglo;
 902
 903         cfglo = channel_readl(dwc, CFG_LO);
 904         if (dw->pdata->is_idma32) {
 905                 if (drain)
 906                         cfglo |= IDMA32C_CFGL_CH_DRAIN;
 907                 else
 908                         cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
 909         }
 910         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 911         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 912                 udelay(2);
 913
 914         set_bit(DW_DMA_IS_PAUSED, &dwc->flags);
 915 }
 916
 917 static int dwc_pause(struct dma_chan *chan)
 918 {
 919         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 920         unsigned long           flags;
 921
 922         spin_lock_irqsave(&dwc->lock, flags);
 923         dwc_chan_pause(dwc, false);
 924         spin_unlock_irqrestore(&dwc->lock, flags);
 925
 926         return 0;
 927 }
 928
 929 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
 930 {
 931         u32 cfglo = channel_readl(dwc, CFG_LO);
 932
 933         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 934
 935         clear_bit(DW_DMA_IS_PAUSED, &dwc->flags);
 936 }
 937
 938 static int dwc_resume(struct dma_chan *chan)
 939 {
 940         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 941         unsigned long           flags;
 942
 943         spin_lock_irqsave(&dwc->lock, flags);
 944
 945         if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
 946                 dwc_chan_resume(dwc);
 947
 948         spin_unlock_irqrestore(&dwc->lock, flags);
 949
 950         return 0;
 951 }
 952
 953 static int dwc_terminate_all(struct dma_chan *chan)
 954 {
 955         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 956         struct dw_dma           *dw = to_dw_dma(chan->device);
 957         struct dw_desc          *desc, *_desc;
 958         unsigned long           flags;
 959         LIST_HEAD(list);
 960
 961         spin_lock_irqsave(&dwc->lock, flags);
 962
 963         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 964
 965         dwc_chan_pause(dwc, true);
 966
 967         dwc_chan_disable(dw, dwc);
 968
 969         dwc_chan_resume(dwc);
 970
 971         /* active_list entries will end up before queued entries */
 972         list_splice_init(&dwc->queue, &list);
 973         list_splice_init(&dwc->active_list, &list);
 974
 975         spin_unlock_irqrestore(&dwc->lock, flags);
 976
 977         /* Flush all pending and queued descriptors */
 978         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 979                 dwc_descriptor_complete(dwc, desc, false);
 980
 981         return 0;
 982 }
 983
 984 static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c)
 985 {
 986         struct dw_desc *desc;
 987
 988         list_for_each_entry(desc, &dwc->active_list, desc_node)
 989                 if (desc->txd.cookie == c)
 990                         return desc;
 991
 992         return NULL;
 993 }
 994
 995 static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie)
 996 {
 997         struct dw_desc *desc;
 998         unsigned long flags;
 999         u32 residue;
1000
1001         spin_lock_irqsave(&dwc->lock, flags);
1002
1003         desc = dwc_find_desc(dwc, cookie);
1004         if (desc) {
1005                 if (desc == dwc_first_active(dwc)) {
1006                         residue = desc->residue;
1007                         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1008                                 residue -= dwc_get_sent(dwc);
1009                 } else {
1010                         residue = desc->total_len;
1011                 }
1012         } else {
1013                 residue = 0;
1014         }
1015
1016         spin_unlock_irqrestore(&dwc->lock, flags);
1017         return residue;
1018 }
1019
1020 static enum dma_status
1021 dwc_tx_status(struct dma_chan *chan,
1022               dma_cookie_t cookie,
1023               struct dma_tx_state *txstate)
1024 {
1025         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1026         enum dma_status         ret;
1027
1028         ret = dma_cookie_status(chan, cookie, txstate);
1029         if (ret == DMA_COMPLETE)
1030                 return ret;
1031
1032         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1033
1034         ret = dma_cookie_status(chan, cookie, txstate);
1035         if (ret == DMA_COMPLETE)
1036                 return ret;
1037
1038         dma_set_residue(txstate, dwc_get_residue(dwc, cookie));
1039
1040         if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS)
1041                 return DMA_PAUSED;
1042
1043         return ret;
1044 }
1045
1046 static void dwc_issue_pending(struct dma_chan *chan)
1047 {
1048         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1049         unsigned long           flags;
1050
1051         spin_lock_irqsave(&dwc->lock, flags);
1052         if (list_empty(&dwc->active_list))
1053                 dwc_dostart_first_queued(dwc);
1054         spin_unlock_irqrestore(&dwc->lock, flags);
1055 }
1056
1057 /*----------------------------------------------------------------------*/
1058
1059 /*
1060  * Program FIFO size of channels.
1061  *
1062  * By default full FIFO (1024 bytes) is assigned to channel 0. Here we
1063  * slice FIFO on equal parts between channels.
1064  */
1065 static void idma32_fifo_partition(struct dw_dma *dw)
1066 {
1067         u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) |
1068                     IDMA32C_FP_UPDATE;
1069         u64 fifo_partition = 0;
1070
1071         if (!dw->pdata->is_idma32)
1072                 return;
1073
1074         /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
1075         fifo_partition |= value << 0;
1076
1077         /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
1078         fifo_partition |= value << 32;
1079
1080         /* Program FIFO Partition registers - 128 bytes for each channel */
1081         idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
1082         idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
1083 }
1084
1085 static void dw_dma_off(struct dw_dma *dw)
1086 {
1087         unsigned int i;
1088
1089         dma_writel(dw, CFG, 0);
1090
1091         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1092         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1093         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1094         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1095         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1096
1097         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1098                 cpu_relax();
1099
1100         for (i = 0; i < dw->dma.chancnt; i++)
1101                 clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags);
1102 }
1103
1104 static void dw_dma_on(struct dw_dma *dw)
1105 {
1106         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1107 }
1108
1109 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1110 {
1111         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1112         struct dw_dma           *dw = to_dw_dma(chan->device);
1113
1114         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1115
1116         /* ASSERT:  channel is idle */
1117         if (dma_readl(dw, CH_EN) & dwc->mask) {
1118                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1119                 return -EIO;
1120         }
1121
1122         dma_cookie_init(chan);
1123
1124         /*
1125          * NOTE: some controllers may have additional features that we
1126          * need to initialize here, like "scatter-gather" (which
1127          * doesn't mean what you think it means), and status writeback.
1128          */
1129
1130         /*
1131          * We need controller-specific data to set up slave transfers.
1132          */
1133         if (chan->private && !dw_dma_filter(chan, chan->private)) {
1134                 dev_warn(chan2dev(chan), "Wrong controller-specific data\n");
1135                 return -EINVAL;
1136         }
1137
1138         /* Enable controller here if needed */
1139         if (!dw->in_use)
1140                 dw_dma_on(dw);
1141         dw->in_use |= dwc->mask;
1142
1143         return 0;
1144 }
1145
1146 static void dwc_free_chan_resources(struct dma_chan *chan)
1147 {
1148         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1149         struct dw_dma           *dw = to_dw_dma(chan->device);
1150         unsigned long           flags;
1151         LIST_HEAD(list);
1152
1153         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1154                         dwc->descs_allocated);
1155
1156         /* ASSERT:  channel is idle */
1157         BUG_ON(!list_empty(&dwc->active_list));
1158         BUG_ON(!list_empty(&dwc->queue));
1159         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1160
1161         spin_lock_irqsave(&dwc->lock, flags);
1162
1163         /* Clear custom channel configuration */
1164         memset(&dwc->dws, 0, sizeof(struct dw_dma_slave));
1165
1166         clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
1167
1168         /* Disable interrupts */
1169         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1170         channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1171         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1172
1173         spin_unlock_irqrestore(&dwc->lock, flags);
1174
1175         /* Disable controller in case it was a last user */
1176         dw->in_use &= ~dwc->mask;
1177         if (!dw->in_use)
1178                 dw_dma_off(dw);
1179
1180         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1181 }
1182
1183 int dw_dma_probe(struct dw_dma_chip *chip)
1184 {
1185         struct dw_dma_platform_data *pdata;
1186         struct dw_dma           *dw;
1187         bool                    autocfg = false;
1188         unsigned int            dw_params;
1189         unsigned int            i;
1190         int                     err;
1191
1192         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1193         if (!dw)
1194                 return -ENOMEM;
1195
1196         dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
1197         if (!dw->pdata)
1198                 return -ENOMEM;
1199
1200         dw->regs = chip->regs;
1201         chip->dw = dw;
1202
1203         pm_runtime_get_sync(chip->dev);
1204
1205         if (!chip->pdata) {
1206                 dw_params = dma_readl(dw, DW_PARAMS);
1207                 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1208
1209                 autocfg = dw_params >> DW_PARAMS_EN & 1;
1210                 if (!autocfg) {
1211                         err = -EINVAL;
1212                         goto err_pdata;
1213                 }
1214
1215                 /* Reassign the platform data pointer */
1216                 pdata = dw->pdata;
1217
1218                 /* Get hardware configuration parameters */
1219                 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1220                 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1221                 for (i = 0; i < pdata->nr_masters; i++) {
1222                         pdata->data_width[i] =
1223                                 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3);
1224                 }
1225                 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
1226
1227                 /* Fill platform data with the default values */
1228                 pdata->is_private = true;
1229                 pdata->is_memcpy = true;
1230                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1231                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1232         } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1233                 err = -EINVAL;
1234                 goto err_pdata;
1235         } else {
1236                 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata));
1237
1238                 /* Reassign the platform data pointer */
1239                 pdata = dw->pdata;
1240         }
1241
1242         dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1243                                 GFP_KERNEL);
1244         if (!dw->chan) {
1245                 err = -ENOMEM;
1246                 goto err_pdata;
1247         }
1248
1249         /* Calculate all channel mask before DMA setup */
1250         dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1251
1252         /* Force dma off, just in case */
1253         dw_dma_off(dw);
1254
1255         idma32_fifo_partition(dw);
1256
1257         /* Device and instance ID for IRQ and DMA pool */
1258         if (pdata->is_idma32)
1259                 snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", chip->id);
1260         else
1261                 snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", chip->id);
1262
1263         /* Create a pool of consistent memory blocks for hardware descriptors */
1264         dw->desc_pool = dmam_pool_create(dw->name, chip->dev,
1265                                          sizeof(struct dw_desc), 4, 0);
1266         if (!dw->desc_pool) {
1267                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1268                 err = -ENOMEM;
1269                 goto err_pdata;
1270         }
1271
1272         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1273
1274         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1275                           dw->name, dw);
1276         if (err)
1277                 goto err_pdata;
1278
1279         INIT_LIST_HEAD(&dw->dma.channels);
1280         for (i = 0; i < pdata->nr_channels; i++) {
1281                 struct dw_dma_chan      *dwc = &dw->chan[i];
1282
1283                 dwc->chan.device = &dw->dma;
1284                 dma_cookie_init(&dwc->chan);
1285                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1286                         list_add_tail(&dwc->chan.device_node,
1287                                         &dw->dma.channels);
1288                 else
1289                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1290
1291                 /* 7 is highest priority & 0 is lowest. */
1292                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1293                         dwc->priority = pdata->nr_channels - i - 1;
1294                 else
1295                         dwc->priority = i;
1296
1297                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1298                 spin_lock_init(&dwc->lock);
1299                 dwc->mask = 1 << i;
1300
1301                 INIT_LIST_HEAD(&dwc->active_list);
1302                 INIT_LIST_HEAD(&dwc->queue);
1303
1304                 channel_clear_bit(dw, CH_EN, dwc->mask);
1305
1306                 dwc->direction = DMA_TRANS_NONE;
1307
1308                 /* Hardware configuration */
1309                 if (autocfg) {
1310                         unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1311                         void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
1312                         unsigned int dwc_params = readl(addr);
1313
1314                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1315                                            dwc_params);
1316
1317                         /*
1318                          * Decode maximum block size for given channel. The
1319                          * stored 4 bit value represents blocks from 0x00 for 3
1320                          * up to 0x0a for 4095.
1321                          */
1322                         dwc->block_size =
1323                                 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;
1324                         dwc->nollp =
1325                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1326                 } else {
1327                         dwc->block_size = pdata->block_size;
1328                         dwc->nollp = !pdata->multi_block[i];
1329                 }
1330         }
1331
1332         /* Clear all interrupts on all channels. */
1333         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1334         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1335         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1336         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1337         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1338
1339         /* Set capabilities */
1340         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1341         if (pdata->is_private)
1342                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1343         if (pdata->is_memcpy)
1344                 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1345
1346         dw->dma.dev = chip->dev;
1347         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1348         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1349
1350         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1351         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1352
1353         dw->dma.device_config = dwc_config;
1354         dw->dma.device_pause = dwc_pause;
1355         dw->dma.device_resume = dwc_resume;
1356         dw->dma.device_terminate_all = dwc_terminate_all;
1357
1358         dw->dma.device_tx_status = dwc_tx_status;
1359         dw->dma.device_issue_pending = dwc_issue_pending;
1360
1361         /* DMA capabilities */
1362         dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1363         dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1364         dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1365                              BIT(DMA_MEM_TO_MEM);
1366         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1367
1368         err = dma_async_device_register(&dw->dma);
1369         if (err)
1370                 goto err_dma_register;
1371
1372         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1373                  pdata->nr_channels);
1374
1375         pm_runtime_put_sync_suspend(chip->dev);
1376
1377         return 0;
1378
1379 err_dma_register:
1380         free_irq(chip->irq, dw);
1381 err_pdata:
1382         pm_runtime_put_sync_suspend(chip->dev);
1383         return err;
1384 }
1385 EXPORT_SYMBOL_GPL(dw_dma_probe);
1386
1387 int dw_dma_remove(struct dw_dma_chip *chip)
1388 {
1389         struct dw_dma           *dw = chip->dw;
1390         struct dw_dma_chan      *dwc, *_dwc;
1391
1392         pm_runtime_get_sync(chip->dev);
1393
1394         dw_dma_off(dw);
1395         dma_async_device_unregister(&dw->dma);
1396
1397         free_irq(chip->irq, dw);
1398         tasklet_kill(&dw->tasklet);
1399
1400         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1401                         chan.device_node) {
1402                 list_del(&dwc->chan.device_node);
1403                 channel_clear_bit(dw, CH_EN, dwc->mask);
1404         }
1405
1406         pm_runtime_put_sync_suspend(chip->dev);
1407         return 0;
1408 }
1409 EXPORT_SYMBOL_GPL(dw_dma_remove);
1410
1411 int dw_dma_disable(struct dw_dma_chip *chip)
1412 {
1413         struct dw_dma *dw = chip->dw;
1414
1415         dw_dma_off(dw);
1416         return 0;
1417 }
1418 EXPORT_SYMBOL_GPL(dw_dma_disable);
1419
1420 int dw_dma_enable(struct dw_dma_chip *chip)
1421 {
1422         struct dw_dma *dw = chip->dw;
1423
1424         idma32_fifo_partition(dw);
1425
1426         dw_dma_on(dw);
1427         return 0;
1428 }
1429 EXPORT_SYMBOL_GPL(dw_dma_enable);
1430
1431 MODULE_LICENSE("GPL v2");
1432 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1433 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1434 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");