drivers/crypto/sunxi-ss/sun4i-ss-core.c

   1 /*
   2  * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
   3  *
   4  * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
   5  *
   6  * Core file which registers crypto algorithms supported by the SS.
   7  *
   8  * You could find a link for the datasheet in Documentation/arm/sunxi/README
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/crypto.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <crypto/scatterwalk.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/reset.h>
  26
  27 #include "sun4i-ss.h"
  28
  29 static struct sun4i_ss_alg_template ss_algs[] = {
  30 {       .type = CRYPTO_ALG_TYPE_AHASH,
  31         .mode = SS_OP_MD5,
  32         .alg.hash = {
  33                 .init = sun4i_hash_init,
  34                 .update = sun4i_hash_update,
  35                 .final = sun4i_hash_final,
  36                 .finup = sun4i_hash_finup,
  37                 .digest = sun4i_hash_digest,
  38                 .export = sun4i_hash_export_md5,
  39                 .import = sun4i_hash_import_md5,
  40                 .halg = {
  41                         .digestsize = MD5_DIGEST_SIZE,
  42                         .statesize = sizeof(struct md5_state),
  43                         .base = {
  44                                 .cra_name = "md5",
  45                                 .cra_driver_name = "md5-sun4i-ss",
  46                                 .cra_priority = 300,
  47                                 .cra_alignmask = 3,
  48                                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
  49                                 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
  50                                 .cra_module = THIS_MODULE,
  51                                 .cra_init = sun4i_hash_crainit
  52                         }
  53                 }
  54         }
  55 },
  56 {       .type = CRYPTO_ALG_TYPE_AHASH,
  57         .mode = SS_OP_SHA1,
  58         .alg.hash = {
  59                 .init = sun4i_hash_init,
  60                 .update = sun4i_hash_update,
  61                 .final = sun4i_hash_final,
  62                 .finup = sun4i_hash_finup,
  63                 .digest = sun4i_hash_digest,
  64                 .export = sun4i_hash_export_sha1,
  65                 .import = sun4i_hash_import_sha1,
  66                 .halg = {
  67                         .digestsize = SHA1_DIGEST_SIZE,
  68                         .statesize = sizeof(struct sha1_state),
  69                         .base = {
  70                                 .cra_name = "sha1",
  71                                 .cra_driver_name = "sha1-sun4i-ss",
  72                                 .cra_priority = 300,
  73                                 .cra_alignmask = 3,
  74                                 .cra_blocksize = SHA1_BLOCK_SIZE,
  75                                 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
  76                                 .cra_module = THIS_MODULE,
  77                                 .cra_init = sun4i_hash_crainit
  78                         }
  79                 }
  80         }
  81 },
  82 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
  83         .alg.crypto = {
  84                 .setkey         = sun4i_ss_aes_setkey,
  85                 .encrypt        = sun4i_ss_cbc_aes_encrypt,
  86                 .decrypt        = sun4i_ss_cbc_aes_decrypt,
  87                 .min_keysize    = AES_MIN_KEY_SIZE,
  88                 .max_keysize    = AES_MAX_KEY_SIZE,
  89                 .ivsize         = AES_BLOCK_SIZE,
  90                 .base = {
  91                         .cra_name = "cbc(aes)",
  92                         .cra_driver_name = "cbc-aes-sun4i-ss",
  93                         .cra_priority = 300,
  94                         .cra_blocksize = AES_BLOCK_SIZE,
  95                         .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
  96                         .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
  97                         .cra_module = THIS_MODULE,
  98                         .cra_alignmask = 3,
  99                         .cra_init = sun4i_ss_cipher_init,
 100                         .cra_exit = sun4i_ss_cipher_exit,
 101                 }
 102         }
 103 },
 104 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 105         .alg.crypto = {
 106                 .setkey         = sun4i_ss_aes_setkey,
 107                 .encrypt        = sun4i_ss_ecb_aes_encrypt,
 108                 .decrypt        = sun4i_ss_ecb_aes_decrypt,
 109                 .min_keysize    = AES_MIN_KEY_SIZE,
 110                 .max_keysize    = AES_MAX_KEY_SIZE,
 111                 .base = {
 112                         .cra_name = "ecb(aes)",
 113                         .cra_driver_name = "ecb-aes-sun4i-ss",
 114                         .cra_priority = 300,
 115                         .cra_blocksize = AES_BLOCK_SIZE,
 116                         .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
 117                         .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
 118                         .cra_module = THIS_MODULE,
 119                         .cra_alignmask = 3,
 120                         .cra_init = sun4i_ss_cipher_init,
 121                         .cra_exit = sun4i_ss_cipher_exit,
 122                 }
 123         }
 124 },
 125 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 126         .alg.crypto = {
 127                 .setkey         = sun4i_ss_des_setkey,
 128                 .encrypt        = sun4i_ss_cbc_des_encrypt,
 129                 .decrypt        = sun4i_ss_cbc_des_decrypt,
 130                 .min_keysize    = DES_KEY_SIZE,
 131                 .max_keysize    = DES_KEY_SIZE,
 132                 .ivsize         = DES_BLOCK_SIZE,
 133                 .base = {
 134                         .cra_name = "cbc(des)",
 135                         .cra_driver_name = "cbc-des-sun4i-ss",
 136                         .cra_priority = 300,
 137                         .cra_blocksize = DES_BLOCK_SIZE,
 138                         .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
 139                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 140                         .cra_module = THIS_MODULE,
 141                         .cra_alignmask = 3,
 142                         .cra_init = sun4i_ss_cipher_init,
 143                         .cra_exit = sun4i_ss_cipher_exit,
 144                 }
 145         }
 146 },
 147 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 148         .alg.crypto = {
 149                 .setkey         = sun4i_ss_des_setkey,
 150                 .encrypt        = sun4i_ss_ecb_des_encrypt,
 151                 .decrypt        = sun4i_ss_ecb_des_decrypt,
 152                 .min_keysize    = DES_KEY_SIZE,
 153                 .max_keysize    = DES_KEY_SIZE,
 154                 .base = {
 155                         .cra_name = "ecb(des)",
 156                         .cra_driver_name = "ecb-des-sun4i-ss",
 157                         .cra_priority = 300,
 158                         .cra_blocksize = DES_BLOCK_SIZE,
 159                         .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
 160                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 161                         .cra_module = THIS_MODULE,
 162                         .cra_alignmask = 3,
 163                         .cra_init = sun4i_ss_cipher_init,
 164                         .cra_exit = sun4i_ss_cipher_exit,
 165                 }
 166         }
 167 },
 168 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 169         .alg.crypto = {
 170                 .setkey         = sun4i_ss_des3_setkey,
 171                 .encrypt        = sun4i_ss_cbc_des3_encrypt,
 172                 .decrypt        = sun4i_ss_cbc_des3_decrypt,
 173                 .min_keysize    = DES3_EDE_KEY_SIZE,
 174                 .max_keysize    = DES3_EDE_KEY_SIZE,
 175                 .ivsize         = DES3_EDE_BLOCK_SIZE,
 176                 .base = {
 177                         .cra_name = "cbc(des3_ede)",
 178                         .cra_driver_name = "cbc-des3-sun4i-ss",
 179                         .cra_priority = 300,
 180                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
 181                         .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
 182                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 183                         .cra_module = THIS_MODULE,
 184                         .cra_alignmask = 3,
 185                         .cra_init = sun4i_ss_cipher_init,
 186                         .cra_exit = sun4i_ss_cipher_exit,
 187                 }
 188         }
 189 },
 190 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 191         .alg.crypto = {
 192                 .setkey         = sun4i_ss_des3_setkey,
 193                 .encrypt        = sun4i_ss_ecb_des3_encrypt,
 194                 .decrypt        = sun4i_ss_ecb_des3_decrypt,
 195                 .min_keysize    = DES3_EDE_KEY_SIZE,
 196                 .max_keysize    = DES3_EDE_KEY_SIZE,
 197                 .base = {
 198                         .cra_name = "ecb(des3_ede)",
 199                         .cra_driver_name = "ecb-des3-sun4i-ss",
 200                         .cra_priority = 300,
 201                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
 202                         .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK,
 203                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 204                         .cra_module = THIS_MODULE,
 205                         .cra_alignmask = 3,
 206                         .cra_init = sun4i_ss_cipher_init,
 207                         .cra_exit = sun4i_ss_cipher_exit,
 208                 }
 209         }
 210 },
 211 #ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG
 212 {
 213         .type = CRYPTO_ALG_TYPE_RNG,
 214         .alg.rng = {
 215                 .base = {
 216                         .cra_name               = "stdrng",
 217                         .cra_driver_name        = "sun4i_ss_rng",
 218                         .cra_priority           = 300,
 219                         .cra_ctxsize            = 0,
 220                         .cra_module             = THIS_MODULE,
 221                 },
 222                 .generate               = sun4i_ss_prng_generate,
 223                 .seed                   = sun4i_ss_prng_seed,
 224                 .seedsize               = SS_SEED_LEN / BITS_PER_BYTE,
 225         }
 226 },
 227 #endif
 228 };
 229
 230 static int sun4i_ss_probe(struct platform_device *pdev)
 231 {
 232         struct resource *res;
 233         u32 v;
 234         int err, i;
 235         unsigned long cr;
 236         const unsigned long cr_ahb = 24 * 1000 * 1000;
 237         const unsigned long cr_mod = 150 * 1000 * 1000;
 238         struct sun4i_ss_ctx *ss;
 239
 240         if (!pdev->dev.of_node)
 241                 return -ENODEV;
 242
 243         ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
 244         if (!ss)
 245                 return -ENOMEM;
 246
 247         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 248         ss->base = devm_ioremap_resource(&pdev->dev, res);
 249         if (IS_ERR(ss->base)) {
 250                 dev_err(&pdev->dev, "Cannot request MMIO\n");
 251                 return PTR_ERR(ss->base);
 252         }
 253
 254         ss->ssclk = devm_clk_get(&pdev->dev, "mod");
 255         if (IS_ERR(ss->ssclk)) {
 256                 err = PTR_ERR(ss->ssclk);
 257                 dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
 258                 return err;
 259         }
 260         dev_dbg(&pdev->dev, "clock ss acquired\n");
 261
 262         ss->busclk = devm_clk_get(&pdev->dev, "ahb");
 263         if (IS_ERR(ss->busclk)) {
 264                 err = PTR_ERR(ss->busclk);
 265                 dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
 266                 return err;
 267         }
 268         dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
 269
 270         ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
 271         if (IS_ERR(ss->reset)) {
 272                 if (PTR_ERR(ss->reset) == -EPROBE_DEFER)
 273                         return PTR_ERR(ss->reset);
 274                 dev_info(&pdev->dev, "no reset control found\n");
 275                 ss->reset = NULL;
 276         }
 277
 278         /* Enable both clocks */
 279         err = clk_prepare_enable(ss->busclk);
 280         if (err) {
 281                 dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
 282                 return err;
 283         }
 284         err = clk_prepare_enable(ss->ssclk);
 285         if (err) {
 286                 dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
 287                 goto error_ssclk;
 288         }
 289
 290         /*
 291          * Check that clock have the correct rates given in the datasheet
 292          * Try to set the clock to the maximum allowed
 293          */
 294         err = clk_set_rate(ss->ssclk, cr_mod);
 295         if (err) {
 296                 dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
 297                 goto error_clk;
 298         }
 299
 300         /* Deassert reset if we have a reset control */
 301         if (ss->reset) {
 302                 err = reset_control_deassert(ss->reset);
 303                 if (err) {
 304                         dev_err(&pdev->dev, "Cannot deassert reset control\n");
 305                         goto error_clk;
 306                 }
 307         }
 308
 309         /*
 310          * The only impact on clocks below requirement are bad performance,
 311          * so do not print "errors"
 312          * warn on Overclocked clocks
 313          */
 314         cr = clk_get_rate(ss->busclk);
 315         if (cr >= cr_ahb)
 316                 dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
 317                         cr, cr / 1000000, cr_ahb);
 318         else
 319                 dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
 320                          cr, cr / 1000000, cr_ahb);
 321
 322         cr = clk_get_rate(ss->ssclk);
 323         if (cr <= cr_mod)
 324                 if (cr < cr_mod)
 325                         dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
 326                                  cr, cr / 1000000, cr_mod);
 327                 else
 328                         dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
 329                                 cr, cr / 1000000, cr_mod);
 330         else
 331                 dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
 332                          cr, cr / 1000000, cr_mod);
 333
 334         /*
 335          * Datasheet named it "Die Bonding ID"
 336          * I expect to be a sort of Security System Revision number.
 337          * Since the A80 seems to have an other version of SS
 338          * this info could be useful
 339          */
 340         writel(SS_ENABLED, ss->base + SS_CTL);
 341         v = readl(ss->base + SS_CTL);
 342         v >>= 16;
 343         v &= 0x07;
 344         dev_info(&pdev->dev, "Die ID %d\n", v);
 345         writel(0, ss->base + SS_CTL);
 346
 347         ss->dev = &pdev->dev;
 348
 349         spin_lock_init(&ss->slock);
 350
 351         for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
 352                 ss_algs[i].ss = ss;
 353                 switch (ss_algs[i].type) {
 354                 case CRYPTO_ALG_TYPE_SKCIPHER:
 355                         err = crypto_register_skcipher(&ss_algs[i].alg.crypto);
 356                         if (err) {
 357                                 dev_err(ss->dev, "Fail to register %s\n",
 358                                         ss_algs[i].alg.crypto.base.cra_name);
 359                                 goto error_alg;
 360                         }
 361                         break;
 362                 case CRYPTO_ALG_TYPE_AHASH:
 363                         err = crypto_register_ahash(&ss_algs[i].alg.hash);
 364                         if (err) {
 365                                 dev_err(ss->dev, "Fail to register %s\n",
 366                                         ss_algs[i].alg.hash.halg.base.cra_name);
 367                                 goto error_alg;
 368                         }
 369                         break;
 370                 case CRYPTO_ALG_TYPE_RNG:
 371                         err = crypto_register_rng(&ss_algs[i].alg.rng);
 372                         if (err) {
 373                                 dev_err(ss->dev, "Fail to register %s\n",
 374                                         ss_algs[i].alg.rng.base.cra_name);
 375                         }
 376                         break;
 377                 }
 378         }
 379         platform_set_drvdata(pdev, ss);
 380         return 0;
 381 error_alg:
 382         i--;
 383         for (; i >= 0; i--) {
 384                 switch (ss_algs[i].type) {
 385                 case CRYPTO_ALG_TYPE_SKCIPHER:
 386                         crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
 387                         break;
 388                 case CRYPTO_ALG_TYPE_AHASH:
 389                         crypto_unregister_ahash(&ss_algs[i].alg.hash);
 390                         break;
 391                 case CRYPTO_ALG_TYPE_RNG:
 392                         crypto_unregister_rng(&ss_algs[i].alg.rng);
 393                         break;
 394                 }
 395         }
 396         if (ss->reset)
 397                 reset_control_assert(ss->reset);
 398 error_clk:
 399         clk_disable_unprepare(ss->ssclk);
 400 error_ssclk:
 401         clk_disable_unprepare(ss->busclk);
 402         return err;
 403 }
 404
 405 static int sun4i_ss_remove(struct platform_device *pdev)
 406 {
 407         int i;
 408         struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
 409
 410         for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
 411                 switch (ss_algs[i].type) {
 412                 case CRYPTO_ALG_TYPE_SKCIPHER:
 413                         crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
 414                         break;
 415                 case CRYPTO_ALG_TYPE_AHASH:
 416                         crypto_unregister_ahash(&ss_algs[i].alg.hash);
 417                         break;
 418                 case CRYPTO_ALG_TYPE_RNG:
 419                         crypto_unregister_rng(&ss_algs[i].alg.rng);
 420                         break;
 421                 }
 422         }
 423
 424         writel(0, ss->base + SS_CTL);
 425         if (ss->reset)
 426                 reset_control_assert(ss->reset);
 427         clk_disable_unprepare(ss->busclk);
 428         clk_disable_unprepare(ss->ssclk);
 429         return 0;
 430 }
 431
 432 static const struct of_device_id a20ss_crypto_of_match_table[] = {
 433         { .compatible = "allwinner,sun4i-a10-crypto" },
 434         {}
 435 };
 436 MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
 437
 438 static struct platform_driver sun4i_ss_driver = {
 439         .probe          = sun4i_ss_probe,
 440         .remove         = sun4i_ss_remove,
 441         .driver         = {
 442                 .name           = "sun4i-ss",
 443                 .of_match_table = a20ss_crypto_of_match_table,
 444         },
 445 };
 446
 447 module_platform_driver(sun4i_ss_driver);
 448
 449 MODULE_ALIAS("platform:sun4i-ss");
 450 MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
 451 MODULE_LICENSE("GPL");
 452 MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");