drivers/clocksource/tcb_clksrc.c

   1 #include <linux/init.h>
   2 #include <linux/clocksource.h>
   3 #include <linux/clockchips.h>
   4 #include <linux/interrupt.h>
   5 #include <linux/irq.h>
   6
   7 #include <linux/clk.h>
   8 #include <linux/err.h>
   9 #include <linux/ioport.h>
  10 #include <linux/io.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/syscore_ops.h>
  13 #include <linux/atmel_tc.h>
  14
  15
  16 /*
  17  * We're configured to use a specific TC block, one that's not hooked
  18  * up to external hardware, to provide a time solution:
  19  *
  20  *   - Two channels combine to create a free-running 32 bit counter
  21  *     with a base rate of 5+ MHz, packaged as a clocksource (with
  22  *     resolution better than 200 nsec).
  23  *   - Some chips support 32 bit counter. A single channel is used for
  24  *     this 32 bit free-running counter. the second channel is not used.
  25  *
  26  *   - The third channel may be used to provide a 16-bit clockevent
  27  *     source, used in either periodic or oneshot mode.  This runs
  28  *     at 32 KiHZ, and can handle delays of up to two seconds.
  29  *
  30  * A boot clocksource and clockevent source are also currently needed,
  31  * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
  32  * this code can be used when init_timers() is called, well before most
  33  * devices are set up.  (Some low end AT91 parts, which can run uClinux,
  34  * have only the timers in one TC block... they currently don't support
  35  * the tclib code, because of that initialization issue.)
  36  *
  37  * REVISIT behavior during system suspend states... we should disable
  38  * all clocks and save the power.  Easily done for clockevent devices,
  39  * but clocksources won't necessarily get the needed notifications.
  40  * For deeper system sleep states, this will be mandatory...
  41  */
  42
  43 static void __iomem *tcaddr;
  44 static struct
  45 {
  46         u32 cmr;
  47         u32 imr;
  48         u32 rc;
  49         bool clken;
  50 } tcb_cache[3];
  51 static u32 bmr_cache;
  52
  53 static u64 tc_get_cycles(struct clocksource *cs)
  54 {
  55         unsigned long   flags;
  56         u32             lower, upper;
  57
  58         raw_local_irq_save(flags);
  59         do {
  60                 upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
  61                 lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
  62         } while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));
  63
  64         raw_local_irq_restore(flags);
  65         return (upper << 16) | lower;
  66 }
  67
  68 static u64 tc_get_cycles32(struct clocksource *cs)
  69 {
  70         return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
  71 }
  72
  73 void tc_clksrc_suspend(struct clocksource *cs)
  74 {
  75         int i;
  76
  77         for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
  78                 tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
  79                 tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
  80                 tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
  81                 tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
  82                                         ATMEL_TC_CLKSTA);
  83         }
  84
  85         bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
  86 }
  87
  88 void tc_clksrc_resume(struct clocksource *cs)
  89 {
  90         int i;
  91
  92         for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
  93                 /* Restore registers for the channel, RA and RB are not used  */
  94                 writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
  95                 writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
  96                 writel(0, tcaddr + ATMEL_TC_REG(i, RA));
  97                 writel(0, tcaddr + ATMEL_TC_REG(i, RB));
  98                 /* Disable all the interrupts */
  99                 writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
 100                 /* Reenable interrupts that were enabled before suspending */
 101                 writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
 102                 /* Start the clock if it was used */
 103                 if (tcb_cache[i].clken)
 104                         writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
 105         }
 106
 107         /* Dual channel, chain channels */
 108         writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
 109         /* Finally, trigger all the channels*/
 110         writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 111 }
 112
 113 static struct clocksource clksrc = {
 114         .name           = "tcb_clksrc",
 115         .rating         = 200,
 116         .read           = tc_get_cycles,
 117         .mask           = CLOCKSOURCE_MASK(32),
 118         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 119         .suspend        = tc_clksrc_suspend,
 120         .resume         = tc_clksrc_resume,
 121 };
 122
 123 #ifdef CONFIG_GENERIC_CLOCKEVENTS
 124
 125 struct tc_clkevt_device {
 126         struct clock_event_device       clkevt;
 127         struct clk                      *clk;
 128         void __iomem                    *regs;
 129 };
 130
 131 static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
 132 {
 133         return container_of(clkevt, struct tc_clkevt_device, clkevt);
 134 }
 135
 136 /* For now, we always use the 32K clock ... this optimizes for NO_HZ,
 137  * because using one of the divided clocks would usually mean the
 138  * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
 139  *
 140  * A divided clock could be good for high resolution timers, since
 141  * 30.5 usec resolution can seem "low".
 142  */
 143 static u32 timer_clock;
 144
 145 static int tc_shutdown(struct clock_event_device *d)
 146 {
 147         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 148         void __iomem            *regs = tcd->regs;
 149
 150         writel(0xff, regs + ATMEL_TC_REG(2, IDR));
 151         writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
 152         if (!clockevent_state_detached(d))
 153                 clk_disable(tcd->clk);
 154
 155         return 0;
 156 }
 157
 158 static int tc_set_oneshot(struct clock_event_device *d)
 159 {
 160         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 161         void __iomem            *regs = tcd->regs;
 162
 163         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 164                 tc_shutdown(d);
 165
 166         clk_enable(tcd->clk);
 167
 168         /* slow clock, count up to RC, then irq and stop */
 169         writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
 170                      ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
 171         writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 172
 173         /* set_next_event() configures and starts the timer */
 174         return 0;
 175 }
 176
 177 static int tc_set_periodic(struct clock_event_device *d)
 178 {
 179         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 180         void __iomem            *regs = tcd->regs;
 181
 182         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 183                 tc_shutdown(d);
 184
 185         /* By not making the gentime core emulate periodic mode on top
 186          * of oneshot, we get lower overhead and improved accuracy.
 187          */
 188         clk_enable(tcd->clk);
 189
 190         /* slow clock, count up to RC, then irq and restart */
 191         writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 192                      regs + ATMEL_TC_REG(2, CMR));
 193         writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 194
 195         /* Enable clock and interrupts on RC compare */
 196         writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 197
 198         /* go go gadget! */
 199         writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
 200                      ATMEL_TC_REG(2, CCR));
 201         return 0;
 202 }
 203
 204 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 205 {
 206         writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
 207
 208         /* go go gadget! */
 209         writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 210                         tcaddr + ATMEL_TC_REG(2, CCR));
 211         return 0;
 212 }
 213
 214 static struct tc_clkevt_device clkevt = {
 215         .clkevt = {
 216                 .name                   = "tc_clkevt",
 217                 .features               = CLOCK_EVT_FEAT_PERIODIC |
 218                                           CLOCK_EVT_FEAT_ONESHOT,
 219                 /* Should be lower than at91rm9200's system timer */
 220                 .rating                 = 125,
 221                 .set_next_event         = tc_next_event,
 222                 .set_state_shutdown     = tc_shutdown,
 223                 .set_state_periodic     = tc_set_periodic,
 224                 .set_state_oneshot      = tc_set_oneshot,
 225         },
 226 };
 227
 228 static irqreturn_t ch2_irq(int irq, void *handle)
 229 {
 230         struct tc_clkevt_device *dev = handle;
 231         unsigned int            sr;
 232
 233         sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
 234         if (sr & ATMEL_TC_CPCS) {
 235                 dev->clkevt.event_handler(&dev->clkevt);
 236                 return IRQ_HANDLED;
 237         }
 238
 239         return IRQ_NONE;
 240 }
 241
 242 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 243 {
 244         int ret;
 245         struct clk *t2_clk = tc->clk[2];
 246         int irq = tc->irq[2];
 247
 248         ret = clk_prepare_enable(tc->slow_clk);
 249         if (ret)
 250                 return ret;
 251
 252         /* try to enable t2 clk to avoid future errors in mode change */
 253         ret = clk_prepare_enable(t2_clk);
 254         if (ret) {
 255                 clk_disable_unprepare(tc->slow_clk);
 256                 return ret;
 257         }
 258
 259         clk_disable(t2_clk);
 260
 261         clkevt.regs = tc->regs;
 262         clkevt.clk = t2_clk;
 263
 264         timer_clock = clk32k_divisor_idx;
 265
 266         clkevt.clkevt.cpumask = cpumask_of(0);
 267
 268         ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
 269         if (ret) {
 270                 clk_unprepare(t2_clk);
 271                 clk_disable_unprepare(tc->slow_clk);
 272                 return ret;
 273         }
 274
 275         clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
 276
 277         return ret;
 278 }
 279
 280 #else /* !CONFIG_GENERIC_CLOCKEVENTS */
 281
 282 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 283 {
 284         /* NOTHING */
 285         return 0;
 286 }
 287
 288 #endif
 289
 290 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 291 {
 292         /* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
 293         writel(mck_divisor_idx                  /* likely divide-by-8 */
 294                         | ATMEL_TC_WAVE
 295                         | ATMEL_TC_WAVESEL_UP           /* free-run */
 296                         | ATMEL_TC_ACPA_SET             /* TIOA0 rises at 0 */
 297                         | ATMEL_TC_ACPC_CLEAR,          /* (duty cycle 50%) */
 298                         tcaddr + ATMEL_TC_REG(0, CMR));
 299         writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
 300         writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
 301         writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));    /* no irqs */
 302         writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 303
 304         /* channel 1:  waveform mode, input TIOA0 */
 305         writel(ATMEL_TC_XC1                     /* input: TIOA0 */
 306                         | ATMEL_TC_WAVE
 307                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 308                         tcaddr + ATMEL_TC_REG(1, CMR));
 309         writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));    /* no irqs */
 310         writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 311
 312         /* chain channel 0 to channel 1*/
 313         writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 314         /* then reset all the timers */
 315         writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 316 }
 317
 318 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 319 {
 320         /* channel 0:  waveform mode, input mclk/8 */
 321         writel(mck_divisor_idx                  /* likely divide-by-8 */
 322                         | ATMEL_TC_WAVE
 323                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 324                         tcaddr + ATMEL_TC_REG(0, CMR));
 325         writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));    /* no irqs */
 326         writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 327
 328         /* then reset all the timers */
 329         writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 330 }
 331
 332 static int __init tcb_clksrc_init(void)
 333 {
 334         static char bootinfo[] __initdata
 335                 = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
 336
 337         struct platform_device *pdev;
 338         struct atmel_tc *tc;
 339         struct clk *t0_clk;
 340         u32 rate, divided_rate = 0;
 341         int best_divisor_idx = -1;
 342         int clk32k_divisor_idx = -1;
 343         int i;
 344         int ret;
 345
 346         tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
 347         if (!tc) {
 348                 pr_debug("can't alloc TC for clocksource\n");
 349                 return -ENODEV;
 350         }
 351         tcaddr = tc->regs;
 352         pdev = tc->pdev;
 353
 354         t0_clk = tc->clk[0];
 355         ret = clk_prepare_enable(t0_clk);
 356         if (ret) {
 357                 pr_debug("can't enable T0 clk\n");
 358                 goto err_free_tc;
 359         }
 360
 361         /* How fast will we be counting?  Pick something over 5 MHz.  */
 362         rate = (u32) clk_get_rate(t0_clk);
 363         for (i = 0; i < 5; i++) {
 364                 unsigned divisor = atmel_tc_divisors[i];
 365                 unsigned tmp;
 366
 367                 /* remember 32 KiHz clock for later */
 368                 if (!divisor) {
 369                         clk32k_divisor_idx = i;
 370                         continue;
 371                 }
 372
 373                 tmp = rate / divisor;
 374                 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
 375                 if (best_divisor_idx > 0) {
 376                         if (tmp < 5 * 1000 * 1000)
 377                                 continue;
 378                 }
 379                 divided_rate = tmp;
 380                 best_divisor_idx = i;
 381         }
 382
 383
 384         printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
 385                         divided_rate / 1000000,
 386                         ((divided_rate + 500000) % 1000000) / 1000);
 387
 388         if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
 389                 /* use apropriate function to read 32 bit counter */
 390                 clksrc.read = tc_get_cycles32;
 391                 /* setup ony channel 0 */
 392                 tcb_setup_single_chan(tc, best_divisor_idx);
 393         } else {
 394                 /* tclib will give us three clocks no matter what the
 395                  * underlying platform supports.
 396                  */
 397                 ret = clk_prepare_enable(tc->clk[1]);
 398                 if (ret) {
 399                         pr_debug("can't enable T1 clk\n");
 400                         goto err_disable_t0;
 401                 }
 402                 /* setup both channel 0 & 1 */
 403                 tcb_setup_dual_chan(tc, best_divisor_idx);
 404         }
 405
 406         /* and away we go! */
 407         ret = clocksource_register_hz(&clksrc, divided_rate);
 408         if (ret)
 409                 goto err_disable_t1;
 410
 411         /* channel 2:  periodic and oneshot timer support */
 412         ret = setup_clkevents(tc, clk32k_divisor_idx);
 413         if (ret)
 414                 goto err_unregister_clksrc;
 415
 416         return 0;
 417
 418 err_unregister_clksrc:
 419         clocksource_unregister(&clksrc);
 420
 421 err_disable_t1:
 422         if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
 423                 clk_disable_unprepare(tc->clk[1]);
 424
 425 err_disable_t0:
 426         clk_disable_unprepare(t0_clk);
 427
 428 err_free_tc:
 429         atmel_tc_free(tc);
 430         return ret;
 431 }
 432 arch_initcall(tcb_clksrc_init);