drivers/clk/ux500/u8500_clk.c

   1 /*
   2  * Clock definitions for u8500 platform.
   3  *
   4  * Copyright (C) 2012 ST-Ericsson SA
   5  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   6  *
   7  * License terms: GNU General Public License (GPL) version 2
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/mfd/dbx500-prcmu.h>
  14 #include <linux/platform_data/clk-ux500.h>
  15
  16 #include "clk.h"
  17
  18 void u8500_clk_init(void)
  19 {
  20         struct prcmu_fw_version *fw_version;
  21         const char *sgaclk_parent = NULL;
  22         struct clk *clk;
  23
  24         /* Clock sources */
  25         clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  26                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  27         clk_register_clkdev(clk, "soc0_pll", NULL);
  28
  29         clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  30                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  31         clk_register_clkdev(clk, "soc1_pll", NULL);
  32
  33         clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
  34                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  35         clk_register_clkdev(clk, "ddr_pll", NULL);
  36
  37         /* FIXME: Add sys, ulp and int clocks here. */
  38
  39         clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
  40                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
  41                                 32768);
  42         clk_register_clkdev(clk, "clk32k", NULL);
  43         clk_register_clkdev(clk, NULL, "rtc-pl031");
  44
  45         /* PRCMU clocks */
  46         fw_version = prcmu_get_fw_version();
  47         if (fw_version != NULL) {
  48                 switch (fw_version->project) {
  49                 case PRCMU_FW_PROJECT_U8500_C2:
  50                 case PRCMU_FW_PROJECT_U8520:
  51                 case PRCMU_FW_PROJECT_U8420:
  52                         sgaclk_parent = "soc0_pll";
  53                         break;
  54                 default:
  55                         break;
  56                 }
  57         }
  58
  59         if (sgaclk_parent)
  60                 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
  61                                         PRCMU_SGACLK, 0);
  62         else
  63                 clk = clk_reg_prcmu_gate("sgclk", NULL,
  64                                         PRCMU_SGACLK, CLK_IS_ROOT);
  65         clk_register_clkdev(clk, NULL, "mali");
  66
  67         clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
  68         clk_register_clkdev(clk, NULL, "UART");
  69
  70         clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
  71         clk_register_clkdev(clk, NULL, "MSP02");
  72
  73         clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
  74         clk_register_clkdev(clk, NULL, "MSP1");
  75
  76         clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
  77         clk_register_clkdev(clk, NULL, "I2C");
  78
  79         clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
  80         clk_register_clkdev(clk, NULL, "slim");
  81
  82         clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
  83         clk_register_clkdev(clk, NULL, "PERIPH1");
  84
  85         clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
  86         clk_register_clkdev(clk, NULL, "PERIPH2");
  87
  88         clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
  89         clk_register_clkdev(clk, NULL, "PERIPH3");
  90
  91         clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
  92         clk_register_clkdev(clk, NULL, "PERIPH5");
  93
  94         clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
  95         clk_register_clkdev(clk, NULL, "PERIPH6");
  96
  97         clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
  98         clk_register_clkdev(clk, NULL, "PERIPH7");
  99
 100         clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 101                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 102         clk_register_clkdev(clk, NULL, "lcd");
 103         clk_register_clkdev(clk, "lcd", "mcde");
 104
 105         clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
 106         clk_register_clkdev(clk, NULL, "bml");
 107
 108         clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 109                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 110
 111         clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
 112                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 113
 114         clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
 115                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 116         clk_register_clkdev(clk, NULL, "hdmi");
 117         clk_register_clkdev(clk, "hdmi", "mcde");
 118
 119         clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
 120         clk_register_clkdev(clk, NULL, "apeat");
 121
 122         clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
 123                                 CLK_IS_ROOT);
 124         clk_register_clkdev(clk, NULL, "apetrace");
 125
 126         clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
 127         clk_register_clkdev(clk, NULL, "mcde");
 128         clk_register_clkdev(clk, "mcde", "mcde");
 129         clk_register_clkdev(clk, "dsisys", "dsilink.0");
 130         clk_register_clkdev(clk, "dsisys", "dsilink.1");
 131         clk_register_clkdev(clk, "dsisys", "dsilink.2");
 132
 133         clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
 134                                 CLK_IS_ROOT);
 135         clk_register_clkdev(clk, NULL, "ipi2");
 136
 137         clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
 138                                 CLK_IS_ROOT);
 139         clk_register_clkdev(clk, NULL, "dsialt");
 140
 141         clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
 142         clk_register_clkdev(clk, NULL, "dma40.0");
 143
 144         clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
 145         clk_register_clkdev(clk, NULL, "b2r2");
 146         clk_register_clkdev(clk, NULL, "b2r2_core");
 147         clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
 148
 149         clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 150                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 151         clk_register_clkdev(clk, NULL, "tv");
 152         clk_register_clkdev(clk, "tv", "mcde");
 153
 154         clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
 155         clk_register_clkdev(clk, NULL, "SSP");
 156
 157         clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
 158         clk_register_clkdev(clk, NULL, "rngclk");
 159
 160         clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
 161         clk_register_clkdev(clk, NULL, "uicc");
 162
 163         /*
 164          * FIXME: The MTU clocks might need some kind of "parent muxed join"
 165          * and these have no K-clocks. For now, we ignore the missing
 166          * connection to the corresponding P-clocks, p6_mtu0_clk and
 167          * p6_mtu1_clk. Instead timclk is used which is the valid parent.
 168          */
 169         clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
 170         clk_register_clkdev(clk, NULL, "mtu0");
 171         clk_register_clkdev(clk, NULL, "mtu1");
 172
 173         clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);
 174         clk_register_clkdev(clk, NULL, "sdmmc");
 175
 176
 177         clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 178                                 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 179         clk_register_clkdev(clk, "dsihs2", "mcde");
 180         clk_register_clkdev(clk, "dsihs2", "dsilink.2");
 181
 182
 183         clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 184                                 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 185         clk_register_clkdev(clk, "dsihs0", "mcde");
 186         clk_register_clkdev(clk, "dsihs0", "dsilink.0");
 187
 188         clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 189                                 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 190         clk_register_clkdev(clk, "dsihs1", "mcde");
 191         clk_register_clkdev(clk, "dsihs1", "dsilink.1");
 192
 193         clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 194                                 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 195         clk_register_clkdev(clk, "dsilp0", "dsilink.0");
 196         clk_register_clkdev(clk, "dsilp0", "mcde");
 197
 198         clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 199                                 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 200         clk_register_clkdev(clk, "dsilp1", "dsilink.1");
 201         clk_register_clkdev(clk, "dsilp1", "mcde");
 202
 203         clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 204                                 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 205         clk_register_clkdev(clk, "dsilp2", "dsilink.2");
 206         clk_register_clkdev(clk, "dsilp2", "mcde");
 207
 208         clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
 209                                 CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
 210                                 CLK_IGNORE_UNUSED);
 211         clk_register_clkdev(clk, NULL, "smp_twd");
 212
 213         /*
 214          * FIXME: Add special handled PRCMU clocks here:
 215          * 1. clk_arm, use PRCMU_ARMCLK.
 216          * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
 217          * 3. ab9540_clkout1yuv, see clkout0yuv
 218          */
 219
 220         /* PRCC P-clocks */
 221         clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE,
 222                                 BIT(0), 0);
 223         clk_register_clkdev(clk, "apb_pclk", "uart0");
 224
 225         clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE,
 226                                 BIT(1), 0);
 227         clk_register_clkdev(clk, "apb_pclk", "uart1");
 228
 229         clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
 230                                 BIT(2), 0);
 231         clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
 232                                 BIT(3), 0);
 233         clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
 234                                 BIT(4), 0);
 235
 236         clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
 237                                 BIT(5), 0);
 238         clk_register_clkdev(clk, "apb_pclk", "sdi0");
 239
 240         clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
 241                                 BIT(6), 0);
 242
 243         clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
 244                                 BIT(7), 0);
 245         clk_register_clkdev(clk, NULL, "spi3");
 246
 247         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
 248                                 BIT(8), 0);
 249
 250         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
 251                                 BIT(9), 0);
 252         clk_register_clkdev(clk, NULL, "gpio.0");
 253         clk_register_clkdev(clk, NULL, "gpio.1");
 254         clk_register_clkdev(clk, NULL, "gpioblock0");
 255
 256         clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
 257                                 BIT(10), 0);
 258         clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
 259                                 BIT(11), 0);
 260
 261         clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
 262                                 BIT(0), 0);
 263
 264         clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
 265                                 BIT(1), 0);
 266         clk_register_clkdev(clk, NULL, "spi2");
 267
 268         clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE,
 269                                 BIT(2), 0);
 270         clk_register_clkdev(clk, NULL, "spi1");
 271
 272         clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE,
 273                                 BIT(3), 0);
 274         clk_register_clkdev(clk, NULL, "pwl");
 275
 276         clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE,
 277                                 BIT(4), 0);
 278         clk_register_clkdev(clk, "apb_pclk", "sdi4");
 279
 280         clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
 281                                 BIT(5), 0);
 282
 283         clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
 284                                 BIT(6), 0);
 285         clk_register_clkdev(clk, "apb_pclk", "sdi1");
 286
 287
 288         clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
 289                                 BIT(7), 0);
 290         clk_register_clkdev(clk, "apb_pclk", "sdi3");
 291
 292         clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE,
 293                                 BIT(8), 0);
 294         clk_register_clkdev(clk, NULL, "spi0");
 295
 296         clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE,
 297                                 BIT(9), 0);
 298         clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
 299
 300         clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE,
 301                                 BIT(10), 0);
 302         clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
 303
 304         clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE,
 305                                 BIT(11), 0);
 306         clk_register_clkdev(clk, NULL, "gpio.6");
 307         clk_register_clkdev(clk, NULL, "gpio.7");
 308         clk_register_clkdev(clk, NULL, "gpioblock1");
 309
 310         clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
 311                                 BIT(11), 0);
 312
 313         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
 314                                 BIT(0), 0);
 315         clk_register_clkdev(clk, NULL, "fsmc");
 316
 317         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
 318                                 BIT(1), 0);
 319         clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
 320                                 BIT(2), 0);
 321         clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
 322                                 BIT(3), 0);
 323
 324         clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
 325                                 BIT(4), 0);
 326         clk_register_clkdev(clk, "apb_pclk", "sdi2");
 327
 328         clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
 329                                 BIT(5), 0);
 330
 331         clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
 332                                 BIT(6), 0);
 333         clk_register_clkdev(clk, "apb_pclk", "uart2");
 334
 335         clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE,
 336                                 BIT(7), 0);
 337         clk_register_clkdev(clk, "apb_pclk", "sdi5");
 338
 339         clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE,
 340                                 BIT(8), 0);
 341         clk_register_clkdev(clk, NULL, "gpio.2");
 342         clk_register_clkdev(clk, NULL, "gpio.3");
 343         clk_register_clkdev(clk, NULL, "gpio.4");
 344         clk_register_clkdev(clk, NULL, "gpio.5");
 345         clk_register_clkdev(clk, NULL, "gpioblock2");
 346
 347         clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE,
 348                                 BIT(0), 0);
 349         clk_register_clkdev(clk, "usb", "musb-ux500.0");
 350
 351         clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE,
 352                                 BIT(1), 0);
 353         clk_register_clkdev(clk, NULL, "gpio.8");
 354         clk_register_clkdev(clk, NULL, "gpioblock3");
 355
 356         clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
 357                                 BIT(0), 0);
 358
 359         clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
 360                                 BIT(1), 0);
 361         clk_register_clkdev(clk, NULL, "cryp0");
 362         clk_register_clkdev(clk, NULL, "cryp1");
 363
 364         clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE,
 365                                 BIT(2), 0);
 366         clk_register_clkdev(clk, NULL, "hash0");
 367
 368         clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE,
 369                                 BIT(3), 0);
 370         clk_register_clkdev(clk, NULL, "pka");
 371
 372         clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE,
 373                                 BIT(4), 0);
 374         clk_register_clkdev(clk, NULL, "hash1");
 375
 376         clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE,
 377                                 BIT(5), 0);
 378         clk_register_clkdev(clk, NULL, "cfgreg");
 379
 380         clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
 381                                 BIT(6), 0);
 382         clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
 383                                 BIT(7), 0);
 384
 385         /* PRCC K-clocks
 386          *
 387          * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
 388          * by enabling just the K-clock, even if it is not a valid parent to
 389          * the K-clock. Until drivers get fixed we might need some kind of
 390          * "parent muxed join".
 391          */
 392
 393         /* Periph1 */
 394         clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 395                         U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE);
 396         clk_register_clkdev(clk, NULL, "uart0");
 397
 398         clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 399                         U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE);
 400         clk_register_clkdev(clk, NULL, "uart1");
 401
 402         clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 403                         U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
 404         clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 405                         U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
 406         clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 407                         U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
 408
 409         clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 410                         U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
 411         clk_register_clkdev(clk, NULL, "sdi0");
 412
 413         clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 414                         U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
 415         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 416                         U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
 417         /* FIXME: Redefinition of BIT(3). */
 418         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 419                         U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
 420         clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 421                         U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
 422
 423         /* Periph2 */
 424         clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 425                         U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
 426
 427         clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 428                         U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
 429         clk_register_clkdev(clk, NULL, "sdi4");
 430
 431         clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 432                         U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
 433
 434         clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 435                         U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
 436         clk_register_clkdev(clk, NULL, "sdi1");
 437
 438         clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 439                         U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE);
 440         clk_register_clkdev(clk, NULL, "sdi3");
 441
 442         /* Note that rate is received from parent. */
 443         clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 444                         U8500_CLKRST2_BASE, BIT(6),
 445                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 446         clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 447                         U8500_CLKRST2_BASE, BIT(7),
 448                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 449
 450         /* Periph3 */
 451         clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 452                         U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
 453         clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 454                         U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
 455         clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 456                         U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
 457
 458         clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 459                         U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
 460         clk_register_clkdev(clk, NULL, "sdi2");
 461
 462         clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 463                         U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
 464
 465         clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 466                         U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
 467         clk_register_clkdev(clk, NULL, "uart2");
 468
 469         clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 470                         U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE);
 471         clk_register_clkdev(clk, NULL, "sdi5");
 472
 473         /* Periph6 */
 474         clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
 475                         U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
 476
 477 }