2 * Copyright 2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
20 #include <linux/of_address.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
24 #define TCON_CH1_SCLK2_PARENTS 4
26 #define TCON_CH1_SCLK2_GATE_BIT BIT(31)
27 #define TCON_CH1_SCLK2_MUX_MASK 3
28 #define TCON_CH1_SCLK2_MUX_SHIFT 24
29 #define TCON_CH1_SCLK2_DIV_MASK 0xf
30 #define TCON_CH1_SCLK2_DIV_SHIFT 0
32 #define TCON_CH1_SCLK1_GATE_BIT BIT(15)
33 #define TCON_CH1_SCLK1_HALF_BIT BIT(11)
41 #define hw_to_tclk(hw) container_of(hw, struct tcon_ch1_clk, hw)
43 static void tcon_ch1_disable(struct clk_hw *hw)
45 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
49 spin_lock_irqsave(&tclk->lock, flags);
50 reg = readl(tclk->reg);
51 reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
52 writel(reg, tclk->reg);
53 spin_unlock_irqrestore(&tclk->lock, flags);
56 static int tcon_ch1_enable(struct clk_hw *hw)
58 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
62 spin_lock_irqsave(&tclk->lock, flags);
63 reg = readl(tclk->reg);
64 reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT;
65 writel(reg, tclk->reg);
66 spin_unlock_irqrestore(&tclk->lock, flags);
71 static int tcon_ch1_is_enabled(struct clk_hw *hw)
73 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
76 reg = readl(tclk->reg);
77 return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
80 static u8 tcon_ch1_get_parent(struct clk_hw *hw)
82 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
85 reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT;
86 reg &= reg >> TCON_CH1_SCLK2_MUX_MASK;
91 static int tcon_ch1_set_parent(struct clk_hw *hw, u8 index)
93 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
97 spin_lock_irqsave(&tclk->lock, flags);
98 reg = readl(tclk->reg);
99 reg &= ~(TCON_CH1_SCLK2_MUX_MASK << TCON_CH1_SCLK2_MUX_SHIFT);
100 reg |= index << TCON_CH1_SCLK2_MUX_SHIFT;
101 writel(reg, tclk->reg);
102 spin_unlock_irqrestore(&tclk->lock, flags);
107 static unsigned long tcon_ch1_calc_divider(unsigned long rate,
108 unsigned long parent_rate,
112 unsigned long best_rate = 0;
116 for (m = 1; m < 16; m++) {
119 for (d = 1; d < 3; d++) {
120 unsigned long tmp_rate;
122 tmp_rate = parent_rate / m / d;
128 (rate - tmp_rate) < (rate - best_rate)) {
129 best_rate = tmp_rate;
144 static int tcon_ch1_determine_rate(struct clk_hw *hw,
145 struct clk_rate_request *req)
147 long best_rate = -EINVAL;
150 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
151 unsigned long parent_rate;
152 unsigned long tmp_rate;
153 struct clk_hw *parent;
155 parent = clk_hw_get_parent_by_index(hw, i);
159 parent_rate = clk_hw_get_rate(parent);
161 tmp_rate = tcon_ch1_calc_divider(req->rate, parent_rate,
165 (req->rate - tmp_rate) < (req->rate - best_rate)) {
166 best_rate = tmp_rate;
167 req->best_parent_rate = parent_rate;
168 req->best_parent_hw = parent;
175 req->rate = best_rate;
179 static unsigned long tcon_ch1_recalc_rate(struct clk_hw *hw,
180 unsigned long parent_rate)
182 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
185 reg = readl(tclk->reg);
187 parent_rate /= (reg & TCON_CH1_SCLK2_DIV_MASK) + 1;
189 if (reg & TCON_CH1_SCLK1_HALF_BIT)
195 static int tcon_ch1_set_rate(struct clk_hw *hw, unsigned long rate,
196 unsigned long parent_rate)
198 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
204 tcon_ch1_calc_divider(rate, parent_rate, &div_m, &half);
206 spin_lock_irqsave(&tclk->lock, flags);
207 reg = readl(tclk->reg);
208 reg &= ~(TCON_CH1_SCLK2_DIV_MASK | TCON_CH1_SCLK1_HALF_BIT);
209 reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK;
212 reg |= TCON_CH1_SCLK1_HALF_BIT;
214 writel(reg, tclk->reg);
215 spin_unlock_irqrestore(&tclk->lock, flags);
220 static const struct clk_ops tcon_ch1_ops = {
221 .disable = tcon_ch1_disable,
222 .enable = tcon_ch1_enable,
223 .is_enabled = tcon_ch1_is_enabled,
225 .get_parent = tcon_ch1_get_parent,
226 .set_parent = tcon_ch1_set_parent,
228 .determine_rate = tcon_ch1_determine_rate,
229 .recalc_rate = tcon_ch1_recalc_rate,
230 .set_rate = tcon_ch1_set_rate,
233 static void __init tcon_ch1_setup(struct device_node *node)
235 const char *parents[TCON_CH1_SCLK2_PARENTS];
236 const char *clk_name = node->name;
237 struct clk_init_data init;
238 struct tcon_ch1_clk *tclk;
244 of_property_read_string(node, "clock-output-names", &clk_name);
246 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
248 pr_err("%s: Could not map the clock registers\n", clk_name);
252 ret = of_clk_parent_fill(node, parents, TCON_CH1_SCLK2_PARENTS);
253 if (ret != TCON_CH1_SCLK2_PARENTS) {
254 pr_err("%s Could not retrieve the parents\n", clk_name);
258 tclk = kzalloc(sizeof(*tclk), GFP_KERNEL);
262 init.name = clk_name;
263 init.ops = &tcon_ch1_ops;
264 init.parent_names = parents;
265 init.num_parents = TCON_CH1_SCLK2_PARENTS;
266 init.flags = CLK_SET_RATE_PARENT;
269 tclk->hw.init = &init;
270 spin_lock_init(&tclk->lock);
272 clk = clk_register(NULL, &tclk->hw);
274 pr_err("%s: Couldn't register the clock\n", clk_name);
278 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
280 pr_err("%s: Couldn't register our clock provider\n", clk_name);
281 goto err_unregister_clk;
292 of_address_to_resource(node, 0, &res);
293 release_mem_region(res.start, resource_size(&res));
296 CLK_OF_DECLARE(tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",