2 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/platform_device.h>
18 #include "ccu_common.h"
19 #include "ccu_reset.h"
27 #include "ccu_phase.h"
29 #include "ccu-sun8i-a83t.h"
31 #define CCU_SUN8I_A83T_LOCK_REG 0x20c
34 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
35 * P should only be used for output frequencies lower than 228 MHz.
36 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
38 * For now we can just model it as a multiplier clock, and force P to /1.
40 #define SUN8I_A83T_PLL_C0CPUX_REG 0x000
41 #define SUN8I_A83T_PLL_C1CPUX_REG 0x004
43 static struct ccu_mult pll_c0cpux_clk = {
46 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
48 .reg = SUN8I_A83T_PLL_C0CPUX_REG,
49 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
50 .features = CCU_FEATURE_LOCK_REG,
51 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 static struct ccu_mult pll_c1cpux_clk = {
60 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
62 .reg = SUN8I_A83T_PLL_C1CPUX_REG,
63 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
64 .features = CCU_FEATURE_LOCK_REG,
65 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
72 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
73 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
74 * and 24.576 MHz, ignore them for now. Enforce the default for them,
75 * which is d1 = 0, d2 = 1.
77 #define SUN8I_A83T_PLL_AUDIO_REG 0x008
79 /* clock rates doubled for post divider */
80 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
81 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
82 { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
85 static struct ccu_nm pll_audio_clk = {
88 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
89 .m = _SUNXI_CCU_DIV(0, 6),
91 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
94 .reg = SUN8I_A83T_PLL_AUDIO_REG,
95 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
96 .features = CCU_FEATURE_LOCK_REG |
97 CCU_FEATURE_FIXED_POSTDIV |
98 CCU_FEATURE_SIGMA_DELTA_MOD,
99 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
100 &ccu_nm_ops, CLK_SET_RATE_UNGATE),
104 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
105 static struct ccu_nkmp pll_video0_clk = {
108 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
109 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
110 .p = _SUNXI_CCU_DIV(0, 2), /* output divider */
111 .max_rate = 3000000000UL,
114 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
115 .features = CCU_FEATURE_LOCK_REG,
116 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
118 CLK_SET_RATE_UNGATE),
122 static struct ccu_nkmp pll_ve_clk = {
125 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
126 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
127 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
130 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
131 .features = CCU_FEATURE_LOCK_REG,
132 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
134 CLK_SET_RATE_UNGATE),
138 static struct ccu_nkmp pll_ddr_clk = {
141 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
142 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
143 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
146 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
147 .features = CCU_FEATURE_LOCK_REG,
148 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
150 CLK_SET_RATE_UNGATE),
154 static struct ccu_nkmp pll_periph_clk = {
157 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
158 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
159 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
162 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
163 .features = CCU_FEATURE_LOCK_REG,
164 .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
166 CLK_SET_RATE_UNGATE),
170 static struct ccu_nkmp pll_gpu_clk = {
173 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
174 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
175 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
178 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
179 .features = CCU_FEATURE_LOCK_REG,
180 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
182 CLK_SET_RATE_UNGATE),
186 static struct ccu_nkmp pll_hsic_clk = {
189 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
190 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
191 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
194 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
195 .features = CCU_FEATURE_LOCK_REG,
196 .hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
198 CLK_SET_RATE_UNGATE),
202 static struct ccu_nkmp pll_de_clk = {
205 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
206 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
207 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
210 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
211 .features = CCU_FEATURE_LOCK_REG,
212 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
214 CLK_SET_RATE_UNGATE),
218 static struct ccu_nkmp pll_video1_clk = {
221 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
222 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
223 .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
224 .max_rate = 3000000000UL,
227 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
228 .features = CCU_FEATURE_LOCK_REG,
229 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
231 CLK_SET_RATE_UNGATE),
235 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
236 static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents,
237 0x50, 12, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
239 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
240 static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents,
241 0x50, 28, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
243 static SUNXI_CCU_M(axi0_clk, "axi0", "c0cpux", 0x050, 0, 2, 0);
244 static SUNXI_CCU_M(axi1_clk, "axi1", "c1cpux", 0x050, 16, 2, 0);
246 static const char * const ahb1_parents[] = { "osc16M-d512", "osc24M",
249 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
250 { .index = 2, .shift = 6, .width = 2 },
251 { .index = 3, .shift = 6, .width = 2 },
253 static struct ccu_div ahb1_clk = {
254 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
259 .var_predivs = ahb1_predivs,
260 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
264 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
271 static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0);
273 static const char * const apb2_parents[] = { "osc16M-d512", "osc24M",
274 "pll-periph", "pll-periph" };
276 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
282 static const char * const ahb2_parents[] = { "ahb1", "pll-periph" };
283 static const struct ccu_mux_fixed_prediv ahb2_prediv = {
286 static struct ccu_mux ahb2_clk = {
290 .fixed_predivs = &ahb2_prediv,
295 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
302 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
304 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
306 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
308 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
310 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
312 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
314 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
316 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
318 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
320 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
322 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
324 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
326 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
328 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb2",
330 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
332 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb2",
335 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
337 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
339 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
341 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
343 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
345 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
347 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
349 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
351 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
354 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
356 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
358 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
360 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
362 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
364 static SUNXI_CCU_GATE(bus_tdm_clk, "bus-tdm", "apb1",
367 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
369 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
371 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
373 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
375 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
377 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
379 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
381 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
384 static const char * const cci400_parents[] = { "osc24M", "pll-periph",
386 static struct ccu_div cci400_clk = {
387 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, 0),
388 .mux = _SUNXI_CCU_MUX(24, 2),
391 .hw.init = CLK_HW_INIT_PARENTS("cci400",
398 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
400 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents,
408 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
416 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
418 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
421 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
429 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
431 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
434 static SUNXI_CCU_MP_MMC_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
437 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
439 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
442 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents,
450 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents,
458 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents,
466 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
467 0x0b0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
468 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
469 0x0b4, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
470 static SUNXI_CCU_M_WITH_GATE(i2s2_clk, "i2s2", "pll-audio",
471 0x0b8, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
472 static SUNXI_CCU_M_WITH_GATE(tdm_clk, "tdm", "pll-audio",
473 0x0bc, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
474 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
475 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
477 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
479 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
481 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
483 static struct ccu_gate usb_hsic_12m_clk = {
488 .features = CCU_FEATURE_ALL_PREDIV,
489 .hw.init = CLK_HW_INIT("usb-hsic-12m", "osc24M",
493 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
496 /* TODO divider has minimum of 2 */
497 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 0x0f4, 0, 4, CLK_IS_CRITICAL);
499 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
501 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
504 static const char * const tcon0_parents[] = { "pll-video0" };
505 static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
506 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
508 static const char * const tcon1_parents[] = { "pll-video1" };
509 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
510 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
512 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
514 static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0);
516 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-de",
518 static const u8 csi_mclk_table[] = { 0, 3, 5 };
519 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
520 csi_mclk_parents, csi_mclk_table,
527 static const char * const csi_sclk_parents[] = { "pll-periph", "pll-ve" };
528 static const u8 csi_sclk_table[] = { 0, 5 };
529 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
530 csi_sclk_parents, csi_sclk_table,
537 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c,
538 16, 3, BIT(31), CLK_SET_RATE_PARENT);
540 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
542 static const char * const hdmi_parents[] = { "pll-video1" };
543 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
548 CLK_SET_RATE_PARENT);
550 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0);
552 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
554 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
561 static const char * const mipi_dsi0_parents[] = { "pll-video0" };
562 static const u8 mipi_dsi0_table[] = { 8 };
563 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
564 mipi_dsi0_parents, mipi_dsi0_table,
569 CLK_SET_RATE_PARENT);
571 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video0" };
572 static const u8 mipi_dsi1_table[] = { 0, 9 };
573 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
574 mipi_dsi1_parents, mipi_dsi1_table,
579 CLK_SET_RATE_PARENT);
581 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x1a0,
582 0, 3, BIT(31), CLK_SET_RATE_PARENT);
584 static const char * const gpu_memory_parents[] = { "pll-gpu", "pll-ddr" };
585 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_memory_clk, "gpu-memory",
591 CLK_SET_RATE_PARENT);
593 static SUNXI_CCU_M_WITH_GATE(gpu_hyd_clk, "gpu-hyd", "pll-gpu", 0x1a8,
594 0, 3, BIT(31), CLK_SET_RATE_PARENT);
596 static struct ccu_common *sun8i_a83t_ccu_clks[] = {
597 &pll_c0cpux_clk.common,
598 &pll_c1cpux_clk.common,
599 &pll_audio_clk.common,
600 &pll_video0_clk.common,
603 &pll_periph_clk.common,
605 &pll_hsic_clk.common,
607 &pll_video1_clk.common,
616 &bus_mipi_dsi_clk.common,
619 &bus_mmc0_clk.common,
620 &bus_mmc1_clk.common,
621 &bus_mmc2_clk.common,
622 &bus_nand_clk.common,
623 &bus_dram_clk.common,
624 &bus_emac_clk.common,
625 &bus_hstimer_clk.common,
626 &bus_spi0_clk.common,
627 &bus_spi1_clk.common,
629 &bus_ehci0_clk.common,
630 &bus_ehci1_clk.common,
631 &bus_ohci0_clk.common,
633 &bus_tcon0_clk.common,
634 &bus_tcon1_clk.common,
636 &bus_hdmi_clk.common,
639 &bus_msgbox_clk.common,
640 &bus_spinlock_clk.common,
641 &bus_spdif_clk.common,
643 &bus_i2s0_clk.common,
644 &bus_i2s1_clk.common,
645 &bus_i2s2_clk.common,
647 &bus_i2c0_clk.common,
648 &bus_i2c1_clk.common,
649 &bus_i2c2_clk.common,
650 &bus_uart0_clk.common,
651 &bus_uart1_clk.common,
652 &bus_uart2_clk.common,
653 &bus_uart3_clk.common,
654 &bus_uart4_clk.common,
658 &mmc0_sample_clk.common,
659 &mmc0_output_clk.common,
661 &mmc1_sample_clk.common,
662 &mmc1_output_clk.common,
664 &mmc2_sample_clk.common,
665 &mmc2_output_clk.common,
674 &usb_phy0_clk.common,
675 &usb_phy1_clk.common,
676 &usb_hsic_clk.common,
677 &usb_hsic_12m_clk.common,
678 &usb_ohci0_clk.common,
681 &dram_csi_clk.common,
684 &csi_misc_clk.common,
685 &mipi_csi_clk.common,
686 &csi_mclk_clk.common,
687 &csi_sclk_clk.common,
691 &hdmi_slow_clk.common,
693 &mipi_dsi0_clk.common,
694 &mipi_dsi1_clk.common,
695 &gpu_core_clk.common,
696 &gpu_memory_clk.common,
700 static struct clk_hw_onecell_data sun8i_a83t_hw_clks = {
702 [CLK_PLL_C0CPUX] = &pll_c0cpux_clk.common.hw,
703 [CLK_PLL_C1CPUX] = &pll_c1cpux_clk.common.hw,
704 [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
705 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
706 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
707 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
708 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
709 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
710 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
711 [CLK_PLL_DE] = &pll_de_clk.common.hw,
712 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
713 [CLK_C0CPUX] = &c0cpux_clk.common.hw,
714 [CLK_C1CPUX] = &c1cpux_clk.common.hw,
715 [CLK_AXI0] = &axi0_clk.common.hw,
716 [CLK_AXI1] = &axi1_clk.common.hw,
717 [CLK_AHB1] = &ahb1_clk.common.hw,
718 [CLK_AHB2] = &ahb2_clk.common.hw,
719 [CLK_APB1] = &apb1_clk.common.hw,
720 [CLK_APB2] = &apb2_clk.common.hw,
721 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
722 [CLK_BUS_SS] = &bus_ss_clk.common.hw,
723 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
724 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
725 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
726 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
727 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
728 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
729 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
730 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
731 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
732 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
733 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
734 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
735 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
736 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
737 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
738 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
739 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
740 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
741 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
742 [CLK_BUS_DE] = &bus_de_clk.common.hw,
743 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
744 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
745 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
746 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
747 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
748 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
749 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
750 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
751 [CLK_BUS_TDM] = &bus_tdm_clk.common.hw,
752 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
753 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
754 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
755 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
756 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
757 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
758 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
759 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
760 [CLK_CCI400] = &cci400_clk.common.hw,
761 [CLK_NAND] = &nand_clk.common.hw,
762 [CLK_MMC0] = &mmc0_clk.common.hw,
763 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
764 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
765 [CLK_MMC1] = &mmc1_clk.common.hw,
766 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
767 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
768 [CLK_MMC2] = &mmc2_clk.common.hw,
769 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
770 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
771 [CLK_SS] = &ss_clk.common.hw,
772 [CLK_SPI0] = &spi0_clk.common.hw,
773 [CLK_SPI1] = &spi1_clk.common.hw,
774 [CLK_I2S0] = &i2s0_clk.common.hw,
775 [CLK_I2S1] = &i2s1_clk.common.hw,
776 [CLK_I2S2] = &i2s2_clk.common.hw,
777 [CLK_TDM] = &tdm_clk.common.hw,
778 [CLK_SPDIF] = &spdif_clk.common.hw,
779 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
780 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
781 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
782 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
783 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
784 [CLK_DRAM] = &dram_clk.common.hw,
785 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
786 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
787 [CLK_TCON0] = &tcon0_clk.common.hw,
788 [CLK_TCON1] = &tcon1_clk.common.hw,
789 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
790 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
791 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
792 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
793 [CLK_VE] = &ve_clk.common.hw,
794 [CLK_AVS] = &avs_clk.common.hw,
795 [CLK_HDMI] = &hdmi_clk.common.hw,
796 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
797 [CLK_MBUS] = &mbus_clk.common.hw,
798 [CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw,
799 [CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw,
800 [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
801 [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
802 [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
807 static struct ccu_reset_map sun8i_a83t_ccu_resets[] = {
808 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
809 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
810 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
811 [RST_DRAM] = { 0x0f4, BIT(31) },
812 [RST_MBUS] = { 0x0fc, BIT(31) },
813 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
814 [RST_BUS_SS] = { 0x2c0, BIT(5) },
815 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
816 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
817 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
818 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
819 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
820 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
821 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
822 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
823 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
824 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
825 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
826 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
827 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
828 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
829 [RST_BUS_VE] = { 0x2c4, BIT(0) },
830 [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
831 [RST_BUS_TCON1] = { 0x2c4, BIT(5) },
832 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
833 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
834 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
835 [RST_BUS_DE] = { 0x2c4, BIT(12) },
836 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
837 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
838 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
839 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
840 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
841 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
842 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
843 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
844 [RST_BUS_TDM] = { 0x2d0, BIT(15) },
845 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
846 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
847 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
848 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
849 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
850 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
851 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
852 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
855 static const struct sunxi_ccu_desc sun8i_a83t_ccu_desc = {
856 .ccu_clks = sun8i_a83t_ccu_clks,
857 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_ccu_clks),
859 .hw_clks = &sun8i_a83t_hw_clks,
861 .resets = sun8i_a83t_ccu_resets,
862 .num_resets = ARRAY_SIZE(sun8i_a83t_ccu_resets),
865 #define SUN8I_A83T_PLL_P_SHIFT 16
866 #define SUN8I_A83T_PLL_N_SHIFT 8
867 #define SUN8I_A83T_PLL_N_WIDTH 8
869 static void sun8i_a83t_cpu_pll_fixup(void __iomem *reg)
871 u32 val = readl(reg);
873 /* bail out if P divider is not used */
874 if (!(val & BIT(SUN8I_A83T_PLL_P_SHIFT)))
878 * If P is used, output should be less than 288 MHz. When we
879 * set P to 1, we should also decrease the multiplier so the
880 * output doesn't go out of range, but not too much such that
881 * the multiplier stays above 12, the minimal operation value.
883 * To keep it simple, set the multiplier to 17, the reset value.
885 val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1,
886 SUN8I_A83T_PLL_N_SHIFT);
887 val |= 17 << SUN8I_A83T_PLL_N_SHIFT;
890 val &= ~BIT(SUN8I_A83T_PLL_P_SHIFT);
895 static int sun8i_a83t_ccu_probe(struct platform_device *pdev)
897 struct resource *res;
901 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
902 reg = devm_ioremap_resource(&pdev->dev, res);
906 /* Enforce d1 = 0, d2 = 1 for Audio PLL */
907 val = readl(reg + SUN8I_A83T_PLL_AUDIO_REG);
910 writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG);
912 /* Enforce P = 1 for both CPU cluster PLLs */
913 sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C0CPUX_REG);
914 sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C1CPUX_REG);
916 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_a83t_ccu_desc);
919 static const struct of_device_id sun8i_a83t_ccu_ids[] = {
920 { .compatible = "allwinner,sun8i-a83t-ccu" },
924 static struct platform_driver sun8i_a83t_ccu_driver = {
925 .probe = sun8i_a83t_ccu_probe,
927 .name = "sun8i-a83t-ccu",
928 .of_match_table = sun8i_a83t_ccu_ids,
931 builtin_platform_driver(sun8i_a83t_ccu_driver);