drivers/clk/renesas/renesas-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2015 Glider bvba
   6  *
   7  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
   8  *
   9  * Copyright (C) 2013 Ideas On Board SPRL
  10  * Copyright (C) 2015 Renesas Electronics Corp.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/clk/renesas.h>
  16 #include <linux/delay.h>
  17 #include <linux/device.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/mod_devicetable.h>
  21 #include <linux/module.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_clock.h>
  26 #include <linux/pm_domain.h>
  27 #include <linux/psci.h>
  28 #include <linux/reset-controller.h>
  29 #include <linux/slab.h>
  30
  31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  32
  33 #include "renesas-cpg-mssr.h"
  34 #include "clk-div6.h"
  35
  36 #ifdef DEBUG
  37 #define WARN_DEBUG(x)   WARN_ON(x)
  38 #else
  39 #define WARN_DEBUG(x)   do { } while (0)
  40 #endif
  41
  42
  43 /*
  44  * Module Standby and Software Reset register offets.
  45  *
  46  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  47  * R-Car Gen2, R-Car Gen3, and RZ/G1.
  48  * These are NOT valid for R-Car Gen1 and RZ/A1!
  49  */
  50
  51 /*
  52  * Module Stop Status Register offsets
  53  */
  54
  55 static const u16 mstpsr[] = {
  56         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  57         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  58 };
  59
  60 #define MSTPSR(i)       mstpsr[i]
  61
  62
  63 /*
  64  * System Module Stop Control Register offsets
  65  */
  66
  67 static const u16 smstpcr[] = {
  68         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  69         0x990, 0x994, 0x998, 0x99C,
  70 };
  71
  72 #define SMSTPCR(i)      smstpcr[i]
  73
  74 /*
  75  * Standby Control Register offsets (RZ/A)
  76  * Base address is FRQCR register
  77  */
  78
  79 static const u16 stbcr[] = {
  80         0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
  81         0x424, 0x428, 0x42C,
  82 };
  83
  84 #define STBCR(i)        stbcr[i]
  85
  86 /*
  87  * Software Reset Register offsets
  88  */
  89
  90 static const u16 srcr[] = {
  91         0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
  92         0x920, 0x924, 0x928, 0x92C,
  93 };
  94
  95 #define SRCR(i)         srcr[i]
  96
  97
  98 /* Realtime Module Stop Control Register offsets */
  99 #define RMSTPCR(i)      (smstpcr[i] - 0x20)
 100
 101 /* Modem Module Stop Control Register offsets (r8a73a4) */
 102 #define MMSTPCR(i)      (smstpcr[i] + 0x20)
 103
 104 /* Software Reset Clearing Register offsets */
 105 #define SRSTCLR(i)      (0x940 + (i) * 4)
 106
 107
 108 /**
 109  * Clock Pulse Generator / Module Standby and Software Reset Private Data
 110  *
 111  * @rcdev: Optional reset controller entity
 112  * @dev: CPG/MSSR device
 113  * @base: CPG/MSSR register block base address
 114  * @rmw_lock: protects RMW register accesses
 115  * @np: Device node in DT for this CPG/MSSR module
 116  * @num_core_clks: Number of Core Clocks in clks[]
 117  * @num_mod_clks: Number of Module Clocks in clks[]
 118  * @last_dt_core_clk: ID of the last Core Clock exported to DT
 119  * @stbyctrl: This device has Standby Control Registers
 120  * @notifiers: Notifier chain to save/restore clock state for system resume
 121  * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
 122  * @smstpcr_saved[].val: Saved values of SMSTPCR[]
 123  * @clks: Array containing all Core and Module Clocks
 124  */
 125 struct cpg_mssr_priv {
 126 #ifdef CONFIG_RESET_CONTROLLER
 127         struct reset_controller_dev rcdev;
 128 #endif
 129         struct device *dev;
 130         void __iomem *base;
 131         spinlock_t rmw_lock;
 132         struct device_node *np;
 133
 134         unsigned int num_core_clks;
 135         unsigned int num_mod_clks;
 136         unsigned int last_dt_core_clk;
 137         bool stbyctrl;
 138
 139         struct raw_notifier_head notifiers;
 140         struct {
 141                 u32 mask;
 142                 u32 val;
 143         } smstpcr_saved[ARRAY_SIZE(smstpcr)];
 144
 145         struct clk *clks[];
 146 };
 147
 148 static struct cpg_mssr_priv *cpg_mssr_priv;
 149
 150 /**
 151  * struct mstp_clock - MSTP gating clock
 152  * @hw: handle between common and hardware-specific interfaces
 153  * @index: MSTP clock number
 154  * @priv: CPG/MSSR private data
 155  */
 156 struct mstp_clock {
 157         struct clk_hw hw;
 158         u32 index;
 159         struct cpg_mssr_priv *priv;
 160 };
 161
 162 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
 163
 164 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
 165 {
 166         struct mstp_clock *clock = to_mstp_clock(hw);
 167         struct cpg_mssr_priv *priv = clock->priv;
 168         unsigned int reg = clock->index / 32;
 169         unsigned int bit = clock->index % 32;
 170         struct device *dev = priv->dev;
 171         u32 bitmask = BIT(bit);
 172         unsigned long flags;
 173         unsigned int i;
 174         u32 value;
 175
 176         dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
 177                 enable ? "ON" : "OFF");
 178         spin_lock_irqsave(&priv->rmw_lock, flags);
 179
 180         if (priv->stbyctrl) {
 181                 value = readb(priv->base + STBCR(reg));
 182                 if (enable)
 183                         value &= ~bitmask;
 184                 else
 185                         value |= bitmask;
 186                 writeb(value, priv->base + STBCR(reg));
 187
 188                 /* dummy read to ensure write has completed */
 189                 readb(priv->base + STBCR(reg));
 190                 barrier_data(priv->base + STBCR(reg));
 191         } else {
 192                 value = readl(priv->base + SMSTPCR(reg));
 193                 if (enable)
 194                         value &= ~bitmask;
 195                 else
 196                         value |= bitmask;
 197                 writel(value, priv->base + SMSTPCR(reg));
 198         }
 199
 200         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 201
 202         if (!enable || priv->stbyctrl)
 203                 return 0;
 204
 205         for (i = 1000; i > 0; --i) {
 206                 if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
 207                         break;
 208                 cpu_relax();
 209         }
 210
 211         if (!i) {
 212                 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
 213                         priv->base + SMSTPCR(reg), bit);
 214                 return -ETIMEDOUT;
 215         }
 216
 217         return 0;
 218 }
 219
 220 static int cpg_mstp_clock_enable(struct clk_hw *hw)
 221 {
 222         return cpg_mstp_clock_endisable(hw, true);
 223 }
 224
 225 static void cpg_mstp_clock_disable(struct clk_hw *hw)
 226 {
 227         cpg_mstp_clock_endisable(hw, false);
 228 }
 229
 230 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
 231 {
 232         struct mstp_clock *clock = to_mstp_clock(hw);
 233         struct cpg_mssr_priv *priv = clock->priv;
 234         u32 value;
 235
 236         if (priv->stbyctrl)
 237                 value = readb(priv->base + STBCR(clock->index / 32));
 238         else
 239                 value = readl(priv->base + MSTPSR(clock->index / 32));
 240
 241         return !(value & BIT(clock->index % 32));
 242 }
 243
 244 static const struct clk_ops cpg_mstp_clock_ops = {
 245         .enable = cpg_mstp_clock_enable,
 246         .disable = cpg_mstp_clock_disable,
 247         .is_enabled = cpg_mstp_clock_is_enabled,
 248 };
 249
 250 static
 251 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
 252                                          void *data)
 253 {
 254         unsigned int clkidx = clkspec->args[1];
 255         struct cpg_mssr_priv *priv = data;
 256         struct device *dev = priv->dev;
 257         unsigned int idx;
 258         const char *type;
 259         struct clk *clk;
 260         int range_check;
 261
 262         switch (clkspec->args[0]) {
 263         case CPG_CORE:
 264                 type = "core";
 265                 if (clkidx > priv->last_dt_core_clk) {
 266                         dev_err(dev, "Invalid %s clock index %u\n", type,
 267                                clkidx);
 268                         return ERR_PTR(-EINVAL);
 269                 }
 270                 clk = priv->clks[clkidx];
 271                 break;
 272
 273         case CPG_MOD:
 274                 type = "module";
 275                 if (priv->stbyctrl) {
 276                         idx = MOD_CLK_PACK_10(clkidx);
 277                         range_check = 7 - (clkidx % 10);
 278                 } else {
 279                         idx = MOD_CLK_PACK(clkidx);
 280                         range_check = 31 - (clkidx % 100);
 281                 }
 282                 if (range_check < 0 || idx >= priv->num_mod_clks) {
 283                         dev_err(dev, "Invalid %s clock index %u\n", type,
 284                                 clkidx);
 285                         return ERR_PTR(-EINVAL);
 286                 }
 287                 clk = priv->clks[priv->num_core_clks + idx];
 288                 break;
 289
 290         default:
 291                 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
 292                 return ERR_PTR(-EINVAL);
 293         }
 294
 295         if (IS_ERR(clk))
 296                 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
 297                        PTR_ERR(clk));
 298         else
 299                 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
 300                         clkspec->args[0], clkspec->args[1], clk,
 301                         clk_get_rate(clk));
 302         return clk;
 303 }
 304
 305 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 306                                               const struct cpg_mssr_info *info,
 307                                               struct cpg_mssr_priv *priv)
 308 {
 309         struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
 310         struct device *dev = priv->dev;
 311         unsigned int id = core->id, div = core->div;
 312         const char *parent_name;
 313
 314         WARN_DEBUG(id >= priv->num_core_clks);
 315         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 316
 317         if (!core->name) {
 318                 /* Skip NULLified clock */
 319                 return;
 320         }
 321
 322         switch (core->type) {
 323         case CLK_TYPE_IN:
 324                 clk = of_clk_get_by_name(priv->np, core->name);
 325                 break;
 326
 327         case CLK_TYPE_FF:
 328         case CLK_TYPE_DIV6P1:
 329         case CLK_TYPE_DIV6_RO:
 330                 WARN_DEBUG(core->parent >= priv->num_core_clks);
 331                 parent = priv->clks[core->parent];
 332                 if (IS_ERR(parent)) {
 333                         clk = parent;
 334                         goto fail;
 335                 }
 336
 337                 parent_name = __clk_get_name(parent);
 338
 339                 if (core->type == CLK_TYPE_DIV6_RO)
 340                         /* Multiply with the DIV6 register value */
 341                         div *= (readl(priv->base + core->offset) & 0x3f) + 1;
 342
 343                 if (core->type == CLK_TYPE_DIV6P1) {
 344                         clk = cpg_div6_register(core->name, 1, &parent_name,
 345                                                 priv->base + core->offset,
 346                                                 &priv->notifiers);
 347                 } else {
 348                         clk = clk_register_fixed_factor(NULL, core->name,
 349                                                         parent_name, 0,
 350                                                         core->mult, div);
 351                 }
 352                 break;
 353
 354         case CLK_TYPE_FR:
 355                 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
 356                                               core->mult);
 357                 break;
 358
 359         default:
 360                 if (info->cpg_clk_register)
 361                         clk = info->cpg_clk_register(dev, core, info,
 362                                                      priv->clks, priv->base,
 363                                                      &priv->notifiers);
 364                 else
 365                         dev_err(dev, "%s has unsupported core clock type %u\n",
 366                                 core->name, core->type);
 367                 break;
 368         }
 369
 370         if (IS_ERR_OR_NULL(clk))
 371                 goto fail;
 372
 373         dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 374         priv->clks[id] = clk;
 375         return;
 376
 377 fail:
 378         dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
 379                 core->name, PTR_ERR(clk));
 380 }
 381
 382 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
 383                                              const struct cpg_mssr_info *info,
 384                                              struct cpg_mssr_priv *priv)
 385 {
 386         struct mstp_clock *clock = NULL;
 387         struct device *dev = priv->dev;
 388         unsigned int id = mod->id;
 389         struct clk_init_data init;
 390         struct clk *parent, *clk;
 391         const char *parent_name;
 392         unsigned int i;
 393
 394         WARN_DEBUG(id < priv->num_core_clks);
 395         WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
 396         WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
 397         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 398
 399         if (!mod->name) {
 400                 /* Skip NULLified clock */
 401                 return;
 402         }
 403
 404         parent = priv->clks[mod->parent];
 405         if (IS_ERR(parent)) {
 406                 clk = parent;
 407                 goto fail;
 408         }
 409
 410         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 411         if (!clock) {
 412                 clk = ERR_PTR(-ENOMEM);
 413                 goto fail;
 414         }
 415
 416         init.name = mod->name;
 417         init.ops = &cpg_mstp_clock_ops;
 418         init.flags = CLK_SET_RATE_PARENT;
 419         for (i = 0; i < info->num_crit_mod_clks; i++)
 420                 if (id == info->crit_mod_clks[i]) {
 421                         dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
 422                                 mod->name);
 423                         init.flags |= CLK_IS_CRITICAL;
 424                         break;
 425                 }
 426
 427         parent_name = __clk_get_name(parent);
 428         init.parent_names = &parent_name;
 429         init.num_parents = 1;
 430
 431         clock->index = id - priv->num_core_clks;
 432         clock->priv = priv;
 433         clock->hw.init = &init;
 434
 435         clk = clk_register(NULL, &clock->hw);
 436         if (IS_ERR(clk))
 437                 goto fail;
 438
 439         dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 440         priv->clks[id] = clk;
 441         priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
 442         return;
 443
 444 fail:
 445         dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
 446                 mod->name, PTR_ERR(clk));
 447         kfree(clock);
 448 }
 449
 450 struct cpg_mssr_clk_domain {
 451         struct generic_pm_domain genpd;
 452         unsigned int num_core_pm_clks;
 453         unsigned int core_pm_clks[];
 454 };
 455
 456 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
 457
 458 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
 459                                struct cpg_mssr_clk_domain *pd)
 460 {
 461         unsigned int i;
 462
 463         if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
 464                 return false;
 465
 466         switch (clkspec->args[0]) {
 467         case CPG_CORE:
 468                 for (i = 0; i < pd->num_core_pm_clks; i++)
 469                         if (clkspec->args[1] == pd->core_pm_clks[i])
 470                                 return true;
 471                 return false;
 472
 473         case CPG_MOD:
 474                 return true;
 475
 476         default:
 477                 return false;
 478         }
 479 }
 480
 481 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 482 {
 483         struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
 484         struct device_node *np = dev->of_node;
 485         struct of_phandle_args clkspec;
 486         struct clk *clk;
 487         int i = 0;
 488         int error;
 489
 490         if (!pd) {
 491                 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
 492                 return -EPROBE_DEFER;
 493         }
 494
 495         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 496                                            &clkspec)) {
 497                 if (cpg_mssr_is_pm_clk(&clkspec, pd))
 498                         goto found;
 499
 500                 of_node_put(clkspec.np);
 501                 i++;
 502         }
 503
 504         return 0;
 505
 506 found:
 507         clk = of_clk_get_from_provider(&clkspec);
 508         of_node_put(clkspec.np);
 509
 510         if (IS_ERR(clk))
 511                 return PTR_ERR(clk);
 512
 513         error = pm_clk_create(dev);
 514         if (error)
 515                 goto fail_put;
 516
 517         error = pm_clk_add_clk(dev, clk);
 518         if (error)
 519                 goto fail_destroy;
 520
 521         return 0;
 522
 523 fail_destroy:
 524         pm_clk_destroy(dev);
 525 fail_put:
 526         clk_put(clk);
 527         return error;
 528 }
 529
 530 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 531 {
 532         if (!pm_clk_no_clocks(dev))
 533                 pm_clk_destroy(dev);
 534 }
 535
 536 static int __init cpg_mssr_add_clk_domain(struct device *dev,
 537                                           const unsigned int *core_pm_clks,
 538                                           unsigned int num_core_pm_clks)
 539 {
 540         struct device_node *np = dev->of_node;
 541         struct generic_pm_domain *genpd;
 542         struct cpg_mssr_clk_domain *pd;
 543         size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
 544
 545         pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
 546         if (!pd)
 547                 return -ENOMEM;
 548
 549         pd->num_core_pm_clks = num_core_pm_clks;
 550         memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
 551
 552         genpd = &pd->genpd;
 553         genpd->name = np->name;
 554         genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
 555         genpd->attach_dev = cpg_mssr_attach_dev;
 556         genpd->detach_dev = cpg_mssr_detach_dev;
 557         pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
 558         cpg_mssr_clk_domain = pd;
 559
 560         of_genpd_add_provider_simple(np, genpd);
 561         return 0;
 562 }
 563
 564 #ifdef CONFIG_RESET_CONTROLLER
 565
 566 #define rcdev_to_priv(x)        container_of(x, struct cpg_mssr_priv, rcdev)
 567
 568 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
 569                           unsigned long id)
 570 {
 571         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 572         unsigned int reg = id / 32;
 573         unsigned int bit = id % 32;
 574         u32 bitmask = BIT(bit);
 575         unsigned long flags;
 576         u32 value;
 577
 578         dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
 579
 580         /* Reset module */
 581         spin_lock_irqsave(&priv->rmw_lock, flags);
 582         value = readl(priv->base + SRCR(reg));
 583         value |= bitmask;
 584         writel(value, priv->base + SRCR(reg));
 585         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 586
 587         /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
 588         udelay(35);
 589
 590         /* Release module from reset state */
 591         writel(bitmask, priv->base + SRSTCLR(reg));
 592
 593         return 0;
 594 }
 595
 596 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
 597 {
 598         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 599         unsigned int reg = id / 32;
 600         unsigned int bit = id % 32;
 601         u32 bitmask = BIT(bit);
 602         unsigned long flags;
 603         u32 value;
 604
 605         dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
 606
 607         spin_lock_irqsave(&priv->rmw_lock, flags);
 608         value = readl(priv->base + SRCR(reg));
 609         value |= bitmask;
 610         writel(value, priv->base + SRCR(reg));
 611         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 612         return 0;
 613 }
 614
 615 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
 616                              unsigned long id)
 617 {
 618         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 619         unsigned int reg = id / 32;
 620         unsigned int bit = id % 32;
 621         u32 bitmask = BIT(bit);
 622
 623         dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
 624
 625         writel(bitmask, priv->base + SRSTCLR(reg));
 626         return 0;
 627 }
 628
 629 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
 630                            unsigned long id)
 631 {
 632         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 633         unsigned int reg = id / 32;
 634         unsigned int bit = id % 32;
 635         u32 bitmask = BIT(bit);
 636
 637         return !!(readl(priv->base + SRCR(reg)) & bitmask);
 638 }
 639
 640 static const struct reset_control_ops cpg_mssr_reset_ops = {
 641         .reset = cpg_mssr_reset,
 642         .assert = cpg_mssr_assert,
 643         .deassert = cpg_mssr_deassert,
 644         .status = cpg_mssr_status,
 645 };
 646
 647 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
 648                                 const struct of_phandle_args *reset_spec)
 649 {
 650         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 651         unsigned int unpacked = reset_spec->args[0];
 652         unsigned int idx = MOD_CLK_PACK(unpacked);
 653
 654         if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
 655                 dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
 656                 return -EINVAL;
 657         }
 658
 659         return idx;
 660 }
 661
 662 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
 663 {
 664         priv->rcdev.ops = &cpg_mssr_reset_ops;
 665         priv->rcdev.of_node = priv->dev->of_node;
 666         priv->rcdev.of_reset_n_cells = 1;
 667         priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
 668         priv->rcdev.nr_resets = priv->num_mod_clks;
 669         return devm_reset_controller_register(priv->dev, &priv->rcdev);
 670 }
 671
 672 #else /* !CONFIG_RESET_CONTROLLER */
 673 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
 674 {
 675         return 0;
 676 }
 677 #endif /* !CONFIG_RESET_CONTROLLER */
 678
 679
 680 static const struct of_device_id cpg_mssr_match[] = {
 681 #ifdef CONFIG_CLK_R7S9210
 682         {
 683                 .compatible = "renesas,r7s9210-cpg-mssr",
 684                 .data = &r7s9210_cpg_mssr_info,
 685         },
 686 #endif
 687 #ifdef CONFIG_CLK_R8A7743
 688         {
 689                 .compatible = "renesas,r8a7743-cpg-mssr",
 690                 .data = &r8a7743_cpg_mssr_info,
 691         },
 692         /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
 693         {
 694                 .compatible = "renesas,r8a7744-cpg-mssr",
 695                 .data = &r8a7743_cpg_mssr_info,
 696         },
 697 #endif
 698 #ifdef CONFIG_CLK_R8A7745
 699         {
 700                 .compatible = "renesas,r8a7745-cpg-mssr",
 701                 .data = &r8a7745_cpg_mssr_info,
 702         },
 703 #endif
 704 #ifdef CONFIG_CLK_R8A77470
 705         {
 706                 .compatible = "renesas,r8a77470-cpg-mssr",
 707                 .data = &r8a77470_cpg_mssr_info,
 708         },
 709 #endif
 710 #ifdef CONFIG_CLK_R8A774A1
 711         {
 712                 .compatible = "renesas,r8a774a1-cpg-mssr",
 713                 .data = &r8a774a1_cpg_mssr_info,
 714         },
 715 #endif
 716 #ifdef CONFIG_CLK_R8A774C0
 717         {
 718                 .compatible = "renesas,r8a774c0-cpg-mssr",
 719                 .data = &r8a774c0_cpg_mssr_info,
 720         },
 721 #endif
 722 #ifdef CONFIG_CLK_R8A7790
 723         {
 724                 .compatible = "renesas,r8a7790-cpg-mssr",
 725                 .data = &r8a7790_cpg_mssr_info,
 726         },
 727 #endif
 728 #ifdef CONFIG_CLK_R8A7791
 729         {
 730                 .compatible = "renesas,r8a7791-cpg-mssr",
 731                 .data = &r8a7791_cpg_mssr_info,
 732         },
 733         /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
 734         {
 735                 .compatible = "renesas,r8a7793-cpg-mssr",
 736                 .data = &r8a7791_cpg_mssr_info,
 737         },
 738 #endif
 739 #ifdef CONFIG_CLK_R8A7792
 740         {
 741                 .compatible = "renesas,r8a7792-cpg-mssr",
 742                 .data = &r8a7792_cpg_mssr_info,
 743         },
 744 #endif
 745 #ifdef CONFIG_CLK_R8A7794
 746         {
 747                 .compatible = "renesas,r8a7794-cpg-mssr",
 748                 .data = &r8a7794_cpg_mssr_info,
 749         },
 750 #endif
 751 #ifdef CONFIG_CLK_R8A7795
 752         {
 753                 .compatible = "renesas,r8a7795-cpg-mssr",
 754                 .data = &r8a7795_cpg_mssr_info,
 755         },
 756 #endif
 757 #ifdef CONFIG_CLK_R8A7796
 758         {
 759                 .compatible = "renesas,r8a7796-cpg-mssr",
 760                 .data = &r8a7796_cpg_mssr_info,
 761         },
 762 #endif
 763 #ifdef CONFIG_CLK_R8A77965
 764         {
 765                 .compatible = "renesas,r8a77965-cpg-mssr",
 766                 .data = &r8a77965_cpg_mssr_info,
 767         },
 768 #endif
 769 #ifdef CONFIG_CLK_R8A77970
 770         {
 771                 .compatible = "renesas,r8a77970-cpg-mssr",
 772                 .data = &r8a77970_cpg_mssr_info,
 773         },
 774 #endif
 775 #ifdef CONFIG_CLK_R8A77980
 776         {
 777                 .compatible = "renesas,r8a77980-cpg-mssr",
 778                 .data = &r8a77980_cpg_mssr_info,
 779         },
 780 #endif
 781 #ifdef CONFIG_CLK_R8A77990
 782         {
 783                 .compatible = "renesas,r8a77990-cpg-mssr",
 784                 .data = &r8a77990_cpg_mssr_info,
 785         },
 786 #endif
 787 #ifdef CONFIG_CLK_R8A77995
 788         {
 789                 .compatible = "renesas,r8a77995-cpg-mssr",
 790                 .data = &r8a77995_cpg_mssr_info,
 791         },
 792 #endif
 793         { /* sentinel */ }
 794 };
 795
 796 static void cpg_mssr_del_clk_provider(void *data)
 797 {
 798         of_clk_del_provider(data);
 799 }
 800
 801 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
 802 static int cpg_mssr_suspend_noirq(struct device *dev)
 803 {
 804         struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
 805         unsigned int reg;
 806
 807         /* This is the best we can do to check for the presence of PSCI */
 808         if (!psci_ops.cpu_suspend)
 809                 return 0;
 810
 811         /* Save module registers with bits under our control */
 812         for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
 813                 if (priv->smstpcr_saved[reg].mask)
 814                         priv->smstpcr_saved[reg].val =
 815                                 readl(priv->base + SMSTPCR(reg));
 816         }
 817
 818         /* Save core clocks */
 819         raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
 820
 821         return 0;
 822 }
 823
 824 static int cpg_mssr_resume_noirq(struct device *dev)
 825 {
 826         struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
 827         unsigned int reg, i;
 828         u32 mask, oldval, newval;
 829
 830         /* This is the best we can do to check for the presence of PSCI */
 831         if (!psci_ops.cpu_suspend)
 832                 return 0;
 833
 834         /* Restore core clocks */
 835         raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
 836
 837         /* Restore module clocks */
 838         for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
 839                 mask = priv->smstpcr_saved[reg].mask;
 840                 if (!mask)
 841                         continue;
 842
 843                 if (priv->stbyctrl)
 844                         oldval = readb(priv->base + STBCR(reg));
 845                 else
 846                         oldval = readl(priv->base + SMSTPCR(reg));
 847                 newval = oldval & ~mask;
 848                 newval |= priv->smstpcr_saved[reg].val & mask;
 849                 if (newval == oldval)
 850                         continue;
 851
 852                 if (priv->stbyctrl) {
 853                         writeb(newval, priv->base + STBCR(reg));
 854                         /* dummy read to ensure write has completed */
 855                         readb(priv->base + STBCR(reg));
 856                         barrier_data(priv->base + STBCR(reg));
 857                         continue;
 858                 } else
 859                         writel(newval, priv->base + SMSTPCR(reg));
 860
 861                 /* Wait until enabled clocks are really enabled */
 862                 mask &= ~priv->smstpcr_saved[reg].val;
 863                 if (!mask)
 864                         continue;
 865
 866                 for (i = 1000; i > 0; --i) {
 867                         oldval = readl(priv->base + MSTPSR(reg));
 868                         if (!(oldval & mask))
 869                                 break;
 870                         cpu_relax();
 871                 }
 872
 873                 if (!i)
 874                         dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
 875                                  priv->base + SMSTPCR(reg), oldval & mask);
 876         }
 877
 878         return 0;
 879 }
 880
 881 static const struct dev_pm_ops cpg_mssr_pm = {
 882         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
 883                                       cpg_mssr_resume_noirq)
 884 };
 885 #define DEV_PM_OPS      &cpg_mssr_pm
 886 #else
 887 #define DEV_PM_OPS      NULL
 888 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
 889
 890 static int __init cpg_mssr_common_init(struct device *dev,
 891                                        struct device_node *np,
 892                                        const struct cpg_mssr_info *info)
 893 {
 894         struct cpg_mssr_priv *priv;
 895         unsigned int nclks, i;
 896         int error;
 897
 898         if (info->init) {
 899                 error = info->init(dev);
 900                 if (error)
 901                         return error;
 902         }
 903
 904         nclks = info->num_total_core_clks + info->num_hw_mod_clks;
 905         priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
 906         if (!priv)
 907                 return -ENOMEM;
 908
 909         priv->np = np;
 910         priv->dev = dev;
 911         spin_lock_init(&priv->rmw_lock);
 912
 913         priv->base = of_iomap(np, 0);
 914         if (!priv->base) {
 915                 error = -ENOMEM;
 916                 goto out_err;
 917         }
 918
 919         cpg_mssr_priv = priv;
 920         priv->num_core_clks = info->num_total_core_clks;
 921         priv->num_mod_clks = info->num_hw_mod_clks;
 922         priv->last_dt_core_clk = info->last_dt_core_clk;
 923         RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
 924         priv->stbyctrl = info->stbyctrl;
 925
 926         for (i = 0; i < nclks; i++)
 927                 priv->clks[i] = ERR_PTR(-ENOENT);
 928
 929         error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
 930         if (error)
 931                 goto out_err;
 932
 933         return 0;
 934
 935 out_err:
 936         if (priv->base)
 937                 iounmap(priv->base);
 938         kfree(priv);
 939
 940         return error;
 941 }
 942
 943 void __init cpg_mssr_early_init(struct device_node *np,
 944                                 const struct cpg_mssr_info *info)
 945 {
 946         int error;
 947         int i;
 948
 949         error = cpg_mssr_common_init(NULL, np, info);
 950         if (error)
 951                 return;
 952
 953         for (i = 0; i < info->num_early_core_clks; i++)
 954                 cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
 955                                            cpg_mssr_priv);
 956
 957         for (i = 0; i < info->num_early_mod_clks; i++)
 958                 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
 959                                           cpg_mssr_priv);
 960
 961 }
 962
 963 static int __init cpg_mssr_probe(struct platform_device *pdev)
 964 {
 965         struct device *dev = &pdev->dev;
 966         struct device_node *np = dev->of_node;
 967         const struct cpg_mssr_info *info;
 968         struct cpg_mssr_priv *priv;
 969         unsigned int i;
 970         int error;
 971
 972         info = of_device_get_match_data(dev);
 973
 974         if (!cpg_mssr_priv) {
 975                 error = cpg_mssr_common_init(dev, dev->of_node, info);
 976                 if (error)
 977                         return error;
 978         }
 979
 980         priv = cpg_mssr_priv;
 981         priv->dev = dev;
 982         dev_set_drvdata(dev, priv);
 983
 984         for (i = 0; i < info->num_core_clks; i++)
 985                 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
 986
 987         for (i = 0; i < info->num_mod_clks; i++)
 988                 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
 989
 990         error = devm_add_action_or_reset(dev,
 991                                          cpg_mssr_del_clk_provider,
 992                                          np);
 993         if (error)
 994                 return error;
 995
 996         error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
 997                                         info->num_core_pm_clks);
 998         if (error)
 999                 return error;
1000
1001         /* Reset Controller not supported for Standby Control SoCs */
1002         if (info->stbyctrl)
1003                 return 0;
1004
1005         error = cpg_mssr_reset_controller_register(priv);
1006         if (error)
1007                 return error;
1008
1009         return 0;
1010 }
1011
1012 static struct platform_driver cpg_mssr_driver = {
1013         .driver         = {
1014                 .name   = "renesas-cpg-mssr",
1015                 .of_match_table = cpg_mssr_match,
1016                 .pm = DEV_PM_OPS,
1017         },
1018 };
1019
1020 static int __init cpg_mssr_init(void)
1021 {
1022         return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
1023 }
1024
1025 subsys_initcall(cpg_mssr_init);
1026
1027 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
1028                                    unsigned int num_core_clks,
1029                                    unsigned int first_clk,
1030                                    unsigned int last_clk)
1031 {
1032         unsigned int i;
1033
1034         for (i = 0; i < num_core_clks; i++)
1035                 if (core_clks[i].id >= first_clk &&
1036                     core_clks[i].id <= last_clk)
1037                         core_clks[i].name = NULL;
1038 }
1039
1040 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
1041                              unsigned int num_mod_clks,
1042                              const unsigned int *clks, unsigned int n)
1043 {
1044         unsigned int i, j;
1045
1046         for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1047                 if (mod_clks[i].id == clks[j]) {
1048                         mod_clks[i].name = NULL;
1049                         j++;
1050                 }
1051 }
1052
1053 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
1054                               unsigned int num_mod_clks,
1055                               const struct mssr_mod_reparent *clks,
1056                               unsigned int n)
1057 {
1058         unsigned int i, j;
1059
1060         for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1061                 if (mod_clks[i].id == clks[j].clk) {
1062                         mod_clks[i].parent = clks[j].parent;
1063                         j++;
1064                 }
1065 }
1066
1067 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
1068 MODULE_LICENSE("GPL v2");