drivers/clk/renesas/r8a77970-cpg-mssr.c

   1 /*
   2  * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2017 Cogent Embedded Inc.
   5  *
   6  * Based on r8a7795-cpg-mssr.c
   7  *
   8  * Copyright (C) 2015 Glider bvba
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; version 2 of the License.
  13  */
  14
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/soc/renesas/rcar-rst.h>
  19
  20 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
  21
  22 #include "renesas-cpg-mssr.h"
  23 #include "rcar-gen3-cpg.h"
  24
  25 enum clk_ids {
  26         /* Core Clock Outputs exported to DT */
  27         LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
  28
  29         /* External Input Clocks */
  30         CLK_EXTAL,
  31         CLK_EXTALR,
  32
  33         /* Internal Core Clocks */
  34         CLK_MAIN,
  35         CLK_PLL0,
  36         CLK_PLL1,
  37         CLK_PLL3,
  38         CLK_PLL1_DIV2,
  39         CLK_PLL1_DIV4,
  40
  41         /* Module Clocks */
  42         MOD_CLK_BASE
  43 };
  44
  45 static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
  46         /* External Clock Inputs */
  47         DEF_INPUT("extal",      CLK_EXTAL),
  48         DEF_INPUT("extalr",     CLK_EXTALR),
  49
  50         /* Internal Core Clocks */
  51         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  52         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  53         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  54         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  55
  56         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
  57         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,  CLK_PLL1_DIV2,  2, 1),
  58
  59         /* Core Clock Outputs */
  60         DEF_FIXED("ztr",        R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
  61         DEF_FIXED("ztrd2",      R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  62         DEF_FIXED("zt",         R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
  63         DEF_FIXED("zx",         R8A77970_CLK_ZX,    CLK_PLL1_DIV2,  3, 1),
  64         DEF_FIXED("s1d1",       R8A77970_CLK_S1D1,  CLK_PLL1_DIV2,  4, 1),
  65         DEF_FIXED("s1d2",       R8A77970_CLK_S1D2,  CLK_PLL1_DIV2,  8, 1),
  66         DEF_FIXED("s1d4",       R8A77970_CLK_S1D4,  CLK_PLL1_DIV2, 16, 1),
  67         DEF_FIXED("s2d1",       R8A77970_CLK_S2D1,  CLK_PLL1_DIV2,  6, 1),
  68         DEF_FIXED("s2d2",       R8A77970_CLK_S2D2,  CLK_PLL1_DIV2, 12, 1),
  69         DEF_FIXED("s2d4",       R8A77970_CLK_S2D4,  CLK_PLL1_DIV2, 24, 1),
  70
  71         DEF_FIXED("cl",         R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
  72         DEF_FIXED("cp",         R8A77970_CLK_CP,    CLK_EXTAL,      2, 1),
  73
  74         DEF_DIV6P1("canfd",     R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
  75         DEF_DIV6P1("mso",       R8A77970_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
  76         DEF_DIV6P1("csi0",      R8A77970_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
  77
  78         DEF_FIXED("osc",        R8A77970_CLK_OSC,   CLK_PLL1_DIV2, 12*1024, 1),
  79         DEF_FIXED("r",          R8A77970_CLK_R,     CLK_EXTALR,    1, 1),
  80 };
  81
  82 static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
  83         DEF_MOD("ivcp1e",                127,   R8A77970_CLK_S2D1),
  84         DEF_MOD("scif4",                 203,   R8A77970_CLK_S2D4),
  85         DEF_MOD("scif3",                 204,   R8A77970_CLK_S2D4),
  86         DEF_MOD("scif1",                 206,   R8A77970_CLK_S2D4),
  87         DEF_MOD("scif0",                 207,   R8A77970_CLK_S2D4),
  88         DEF_MOD("msiof3",                208,   R8A77970_CLK_MSO),
  89         DEF_MOD("msiof2",                209,   R8A77970_CLK_MSO),
  90         DEF_MOD("msiof1",                210,   R8A77970_CLK_MSO),
  91         DEF_MOD("msiof0",                211,   R8A77970_CLK_MSO),
  92         DEF_MOD("mfis",                  213,   R8A77970_CLK_S2D2),
  93         DEF_MOD("sys-dmac2",             217,   R8A77970_CLK_S2D1),
  94         DEF_MOD("sys-dmac1",             218,   R8A77970_CLK_S2D1),
  95         DEF_MOD("rwdt",                  402,   R8A77970_CLK_R),
  96         DEF_MOD("intc-ex",               407,   R8A77970_CLK_CP),
  97         DEF_MOD("intc-ap",               408,   R8A77970_CLK_S2D1),
  98         DEF_MOD("hscif3",                517,   R8A77970_CLK_S2D1),
  99         DEF_MOD("hscif2",                518,   R8A77970_CLK_S2D1),
 100         DEF_MOD("hscif1",                519,   R8A77970_CLK_S2D1),
 101         DEF_MOD("hscif0",                520,   R8A77970_CLK_S2D1),
 102         DEF_MOD("thermal",               522,   R8A77970_CLK_CP),
 103         DEF_MOD("pwm",                   523,   R8A77970_CLK_S2D4),
 104         DEF_MOD("fcpvd0",                603,   R8A77970_CLK_S2D1),
 105         DEF_MOD("vspd0",                 623,   R8A77970_CLK_S2D1),
 106         DEF_MOD("csi40",                 716,   R8A77970_CLK_CSI0),
 107         DEF_MOD("du0",                   724,   R8A77970_CLK_S2D1),
 108         DEF_MOD("lvds",                  727,   R8A77970_CLK_S2D1),
 109         DEF_MOD("vin3",                  808,   R8A77970_CLK_S2D1),
 110         DEF_MOD("vin2",                  809,   R8A77970_CLK_S2D1),
 111         DEF_MOD("vin1",                  810,   R8A77970_CLK_S2D1),
 112         DEF_MOD("vin0",                  811,   R8A77970_CLK_S2D1),
 113         DEF_MOD("etheravb",              812,   R8A77970_CLK_S2D2),
 114         DEF_MOD("gpio5",                 907,   R8A77970_CLK_CP),
 115         DEF_MOD("gpio4",                 908,   R8A77970_CLK_CP),
 116         DEF_MOD("gpio3",                 909,   R8A77970_CLK_CP),
 117         DEF_MOD("gpio2",                 910,   R8A77970_CLK_CP),
 118         DEF_MOD("gpio1",                 911,   R8A77970_CLK_CP),
 119         DEF_MOD("gpio0",                 912,   R8A77970_CLK_CP),
 120         DEF_MOD("can-fd",                914,   R8A77970_CLK_S2D2),
 121         DEF_MOD("i2c4",                  927,   R8A77970_CLK_S2D2),
 122         DEF_MOD("i2c3",                  928,   R8A77970_CLK_S2D2),
 123         DEF_MOD("i2c2",                  929,   R8A77970_CLK_S2D2),
 124         DEF_MOD("i2c1",                  930,   R8A77970_CLK_S2D2),
 125         DEF_MOD("i2c0",                  931,   R8A77970_CLK_S2D2),
 126 };
 127
 128 static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
 129         MOD_CLK_ID(408),        /* INTC-AP (GIC) */
 130 };
 131
 132
 133 /*
 134  * CPG Clock Data
 135  */
 136
 137 /*
 138  *   MD         EXTAL           PLL0    PLL1    PLL3
 139  * 14 13 19     (MHz)
 140  *-------------------------------------------------
 141  * 0  0  0      16.66 x 1       x192    x192    x96
 142  * 0  0  1      16.66 x 1       x192    x192    x80
 143  * 0  1  0      20    x 1       x160    x160    x80
 144  * 0  1  1      20    x 1       x160    x160    x66
 145  * 1  0  0      27    / 2       x236    x236    x118
 146  * 1  0  1      27    / 2       x236    x236    x98
 147  * 1  1  0      33.33 / 2       x192    x192    x96
 148  * 1  1  1      33.33 / 2       x192    x192    x80
 149  */
 150 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 12) | \
 151                                          (((md) & BIT(13)) >> 12) | \
 152                                          (((md) & BIT(19)) >> 19))
 153
 154 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
 155         /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
 156         { 1,            192,    1,      96,     1,      },
 157         { 1,            192,    1,      80,     1,      },
 158         { 1,            160,    1,      80,     1,      },
 159         { 1,            160,    1,      66,     1,      },
 160         { 2,            236,    1,      118,    1,      },
 161         { 2,            236,    1,      98,     1,      },
 162         { 2,            192,    1,      96,     1,      },
 163         { 2,            192,    1,      80,     1,      },
 164 };
 165
 166 static int __init r8a77970_cpg_mssr_init(struct device *dev)
 167 {
 168         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 169         u32 cpg_mode;
 170         int error;
 171
 172         error = rcar_rst_read_mode_pins(&cpg_mode);
 173         if (error)
 174                 return error;
 175
 176         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 177
 178         return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
 179 }
 180
 181 const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
 182         /* Core Clocks */
 183         .core_clks = r8a77970_core_clks,
 184         .num_core_clks = ARRAY_SIZE(r8a77970_core_clks),
 185         .last_dt_core_clk = LAST_DT_CORE_CLK,
 186         .num_total_core_clks = MOD_CLK_BASE,
 187
 188         /* Module Clocks */
 189         .mod_clks = r8a77970_mod_clks,
 190         .num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks),
 191         .num_hw_mod_clks = 12 * 32,
 192
 193         /* Critical Module Clocks */
 194         .crit_mod_clks = r8a77970_crit_mod_clks,
 195         .num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks),
 196
 197         /* Callbacks */
 198         .init = r8a77970_cpg_mssr_init,
 199         .cpg_clk_register = rcar_gen3_cpg_clk_register,
 200 };