drivers/clk/qcom/mmcc-msm8996.c

   1 /*x
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24 #include <linux/clk.h>
  25
  26 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-regmap-divider.h"
  31 #include "clk-alpha-pll.h"
  32 #include "clk-rcg.h"
  33 #include "clk-branch.h"
  34 #include "reset.h"
  35 #include "gdsc.h"
  36
  37 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  38
  39 enum {
  40         P_XO,
  41         P_MMPLL0,
  42         P_GPLL0,
  43         P_GPLL0_DIV,
  44         P_MMPLL1,
  45         P_MMPLL9,
  46         P_MMPLL2,
  47         P_MMPLL8,
  48         P_MMPLL3,
  49         P_DSI0PLL,
  50         P_DSI1PLL,
  51         P_MMPLL5,
  52         P_HDMIPLL,
  53         P_DSI0PLL_BYTE,
  54         P_DSI1PLL_BYTE,
  55         P_MMPLL4,
  56 };
  57
  58 static const struct parent_map mmss_xo_hdmi_map[] = {
  59         { P_XO, 0 },
  60         { P_HDMIPLL, 1 }
  61 };
  62
  63 static const char * const mmss_xo_hdmi[] = {
  64         "xo",
  65         "hdmipll"
  66 };
  67
  68 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
  69         { P_XO, 0 },
  70         { P_DSI0PLL, 1 },
  71         { P_DSI1PLL, 2 }
  72 };
  73
  74 static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
  75         "xo",
  76         "dsi0pll",
  77         "dsi1pll"
  78 };
  79
  80 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
  81         { P_XO, 0 },
  82         { P_GPLL0, 5 },
  83         { P_GPLL0_DIV, 6 }
  84 };
  85
  86 static const char * const mmss_xo_gpll0_gpll0_div[] = {
  87         "xo",
  88         "gpll0",
  89         "gpll0_div"
  90 };
  91
  92 static const struct parent_map mmss_xo_dsibyte_map[] = {
  93         { P_XO, 0 },
  94         { P_DSI0PLL_BYTE, 1 },
  95         { P_DSI1PLL_BYTE, 2 }
  96 };
  97
  98 static const char * const mmss_xo_dsibyte[] = {
  99         "xo",
 100         "dsi0pllbyte",
 101         "dsi1pllbyte"
 102 };
 103
 104 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
 105         { P_XO, 0 },
 106         { P_MMPLL0, 1 },
 107         { P_GPLL0, 5 },
 108         { P_GPLL0_DIV, 6 }
 109 };
 110
 111 static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = {
 112         "xo",
 113         "mmpll0",
 114         "gpll0",
 115         "gpll0_div"
 116 };
 117
 118 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
 119         { P_XO, 0 },
 120         { P_MMPLL0, 1 },
 121         { P_MMPLL1, 2 },
 122         { P_GPLL0, 5 },
 123         { P_GPLL0_DIV, 6 }
 124 };
 125
 126 static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
 127         "xo",
 128         "mmpll0",
 129         "mmpll1",
 130         "gpll0",
 131         "gpll0_div"
 132 };
 133
 134 static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
 135         { P_XO, 0 },
 136         { P_MMPLL0, 1 },
 137         { P_MMPLL3, 3 },
 138         { P_GPLL0, 5 },
 139         { P_GPLL0_DIV, 6 }
 140 };
 141
 142 static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
 143         "xo",
 144         "mmpll0",
 145         "mmpll3",
 146         "gpll0",
 147         "gpll0_div"
 148 };
 149
 150 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
 151         { P_XO, 0 },
 152         { P_MMPLL0, 1 },
 153         { P_MMPLL5, 2 },
 154         { P_GPLL0, 5 },
 155         { P_GPLL0_DIV, 6 }
 156 };
 157
 158 static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
 159         "xo",
 160         "mmpll0",
 161         "mmpll5",
 162         "gpll0",
 163         "gpll0_div"
 164 };
 165
 166 static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
 167         { P_XO, 0 },
 168         { P_MMPLL0, 1 },
 169         { P_MMPLL4, 3 },
 170         { P_GPLL0, 5 },
 171         { P_GPLL0_DIV, 6 }
 172 };
 173
 174 static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
 175         "xo",
 176         "mmpll0",
 177         "mmpll4",
 178         "gpll0",
 179         "gpll0_div"
 180 };
 181
 182 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
 183         { P_XO, 0 },
 184         { P_MMPLL0, 1 },
 185         { P_MMPLL9, 2 },
 186         { P_MMPLL2, 3 },
 187         { P_MMPLL8, 4 },
 188         { P_GPLL0, 5 }
 189 };
 190
 191 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
 192         "xo",
 193         "mmpll0",
 194         "mmpll9",
 195         "mmpll2",
 196         "mmpll8",
 197         "gpll0"
 198 };
 199
 200 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
 201         { P_XO, 0 },
 202         { P_MMPLL0, 1 },
 203         { P_MMPLL9, 2 },
 204         { P_MMPLL2, 3 },
 205         { P_MMPLL8, 4 },
 206         { P_GPLL0, 5 },
 207         { P_GPLL0_DIV, 6 }
 208 };
 209
 210 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
 211         "xo",
 212         "mmpll0",
 213         "mmpll9",
 214         "mmpll2",
 215         "mmpll8",
 216         "gpll0",
 217         "gpll0_div"
 218 };
 219
 220 static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
 221         { P_XO, 0 },
 222         { P_MMPLL0, 1 },
 223         { P_MMPLL1, 2 },
 224         { P_MMPLL4, 3 },
 225         { P_MMPLL3, 4 },
 226         { P_GPLL0, 5 },
 227         { P_GPLL0_DIV, 6 }
 228 };
 229
 230 static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
 231         "xo",
 232         "mmpll0",
 233         "mmpll1",
 234         "mmpll4",
 235         "mmpll3",
 236         "gpll0",
 237         "gpll0_div"
 238 };
 239
 240 static struct clk_fixed_factor gpll0_div = {
 241         .mult = 1,
 242         .div = 2,
 243         .hw.init = &(struct clk_init_data){
 244                 .name = "gpll0_div",
 245                 .parent_names = (const char *[]){ "gpll0" },
 246                 .num_parents = 1,
 247                 .ops = &clk_fixed_factor_ops,
 248         },
 249 };
 250
 251 static struct pll_vco mmpll_p_vco[] = {
 252         { 250000000, 500000000, 3 },
 253         { 500000000, 1000000000, 2 },
 254         { 1000000000, 1500000000, 1 },
 255         { 1500000000, 2000000000, 0 },
 256 };
 257
 258 static struct pll_vco mmpll_gfx_vco[] = {
 259         { 400000000, 1000000000, 2 },
 260         { 1000000000, 1500000000, 1 },
 261         { 1500000000, 2000000000, 0 },
 262 };
 263
 264 static struct pll_vco mmpll_t_vco[] = {
 265         { 500000000, 1500000000, 0 },
 266 };
 267
 268 static struct clk_alpha_pll mmpll0_early = {
 269         .offset = 0x0,
 270         .vco_table = mmpll_p_vco,
 271         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 272         .clkr = {
 273                 .enable_reg = 0x100,
 274                 .enable_mask = BIT(0),
 275                 .hw.init = &(struct clk_init_data){
 276                         .name = "mmpll0_early",
 277                         .parent_names = (const char *[]){ "xo" },
 278                         .num_parents = 1,
 279                         .ops = &clk_alpha_pll_ops,
 280                 },
 281         },
 282 };
 283
 284 static struct clk_alpha_pll_postdiv mmpll0 = {
 285         .offset = 0x0,
 286         .width = 4,
 287         .clkr.hw.init = &(struct clk_init_data){
 288                 .name = "mmpll0",
 289                 .parent_names = (const char *[]){ "mmpll0_early" },
 290                 .num_parents = 1,
 291                 .ops = &clk_alpha_pll_postdiv_ops,
 292                 .flags = CLK_SET_RATE_PARENT,
 293         },
 294 };
 295
 296 static struct clk_alpha_pll mmpll1_early = {
 297         .offset = 0x30,
 298         .vco_table = mmpll_p_vco,
 299         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 300         .clkr = {
 301                 .enable_reg = 0x100,
 302                 .enable_mask = BIT(1),
 303                 .hw.init = &(struct clk_init_data){
 304                         .name = "mmpll1_early",
 305                         .parent_names = (const char *[]){ "xo" },
 306                         .num_parents = 1,
 307                         .ops = &clk_alpha_pll_ops,
 308                 }
 309         },
 310 };
 311
 312 static struct clk_alpha_pll_postdiv mmpll1 = {
 313         .offset = 0x30,
 314         .width = 4,
 315         .clkr.hw.init = &(struct clk_init_data){
 316                 .name = "mmpll1",
 317                 .parent_names = (const char *[]){ "mmpll1_early" },
 318                 .num_parents = 1,
 319                 .ops = &clk_alpha_pll_postdiv_ops,
 320                 .flags = CLK_SET_RATE_PARENT,
 321         },
 322 };
 323
 324 static struct clk_alpha_pll mmpll2_early = {
 325         .offset = 0x4100,
 326         .vco_table = mmpll_gfx_vco,
 327         .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
 328         .clkr.hw.init = &(struct clk_init_data){
 329                 .name = "mmpll2_early",
 330                 .parent_names = (const char *[]){ "xo" },
 331                 .num_parents = 1,
 332                 .ops = &clk_alpha_pll_ops,
 333         },
 334 };
 335
 336 static struct clk_alpha_pll_postdiv mmpll2 = {
 337         .offset = 0x4100,
 338         .width = 4,
 339         .clkr.hw.init = &(struct clk_init_data){
 340                 .name = "mmpll2",
 341                 .parent_names = (const char *[]){ "mmpll2_early" },
 342                 .num_parents = 1,
 343                 .ops = &clk_alpha_pll_postdiv_ops,
 344                 .flags = CLK_SET_RATE_PARENT,
 345         },
 346 };
 347
 348 static struct clk_alpha_pll mmpll3_early = {
 349         .offset = 0x60,
 350         .vco_table = mmpll_p_vco,
 351         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 352         .clkr.hw.init = &(struct clk_init_data){
 353                 .name = "mmpll3_early",
 354                 .parent_names = (const char *[]){ "xo" },
 355                 .num_parents = 1,
 356                 .ops = &clk_alpha_pll_ops,
 357         },
 358 };
 359
 360 static struct clk_alpha_pll_postdiv mmpll3 = {
 361         .offset = 0x60,
 362         .width = 4,
 363         .clkr.hw.init = &(struct clk_init_data){
 364                 .name = "mmpll3",
 365                 .parent_names = (const char *[]){ "mmpll3_early" },
 366                 .num_parents = 1,
 367                 .ops = &clk_alpha_pll_postdiv_ops,
 368                 .flags = CLK_SET_RATE_PARENT,
 369         },
 370 };
 371
 372 static struct clk_alpha_pll mmpll4_early = {
 373         .offset = 0x90,
 374         .vco_table = mmpll_t_vco,
 375         .num_vco = ARRAY_SIZE(mmpll_t_vco),
 376         .clkr.hw.init = &(struct clk_init_data){
 377                 .name = "mmpll4_early",
 378                 .parent_names = (const char *[]){ "xo" },
 379                 .num_parents = 1,
 380                 .ops = &clk_alpha_pll_ops,
 381         },
 382 };
 383
 384 static struct clk_alpha_pll_postdiv mmpll4 = {
 385         .offset = 0x90,
 386         .width = 2,
 387         .clkr.hw.init = &(struct clk_init_data){
 388                 .name = "mmpll4",
 389                 .parent_names = (const char *[]){ "mmpll4_early" },
 390                 .num_parents = 1,
 391                 .ops = &clk_alpha_pll_postdiv_ops,
 392                 .flags = CLK_SET_RATE_PARENT,
 393         },
 394 };
 395
 396 static struct clk_alpha_pll mmpll5_early = {
 397         .offset = 0xc0,
 398         .vco_table = mmpll_p_vco,
 399         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 400         .clkr.hw.init = &(struct clk_init_data){
 401                 .name = "mmpll5_early",
 402                 .parent_names = (const char *[]){ "xo" },
 403                 .num_parents = 1,
 404                 .ops = &clk_alpha_pll_ops,
 405         },
 406 };
 407
 408 static struct clk_alpha_pll_postdiv mmpll5 = {
 409         .offset = 0xc0,
 410         .width = 4,
 411         .clkr.hw.init = &(struct clk_init_data){
 412                 .name = "mmpll5",
 413                 .parent_names = (const char *[]){ "mmpll5_early" },
 414                 .num_parents = 1,
 415                 .ops = &clk_alpha_pll_postdiv_ops,
 416                 .flags = CLK_SET_RATE_PARENT,
 417         },
 418 };
 419
 420 static struct clk_alpha_pll mmpll8_early = {
 421         .offset = 0x4130,
 422         .vco_table = mmpll_gfx_vco,
 423         .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
 424         .clkr.hw.init = &(struct clk_init_data){
 425                 .name = "mmpll8_early",
 426                 .parent_names = (const char *[]){ "xo" },
 427                 .num_parents = 1,
 428                 .ops = &clk_alpha_pll_ops,
 429         },
 430 };
 431
 432 static struct clk_alpha_pll_postdiv mmpll8 = {
 433         .offset = 0x4130,
 434         .width = 4,
 435         .clkr.hw.init = &(struct clk_init_data){
 436                 .name = "mmpll8",
 437                 .parent_names = (const char *[]){ "mmpll8_early" },
 438                 .num_parents = 1,
 439                 .ops = &clk_alpha_pll_postdiv_ops,
 440                 .flags = CLK_SET_RATE_PARENT,
 441         },
 442 };
 443
 444 static struct clk_alpha_pll mmpll9_early = {
 445         .offset = 0x4200,
 446         .vco_table = mmpll_t_vco,
 447         .num_vco = ARRAY_SIZE(mmpll_t_vco),
 448         .clkr.hw.init = &(struct clk_init_data){
 449                 .name = "mmpll9_early",
 450                 .parent_names = (const char *[]){ "xo" },
 451                 .num_parents = 1,
 452                 .ops = &clk_alpha_pll_ops,
 453         },
 454 };
 455
 456 static struct clk_alpha_pll_postdiv mmpll9 = {
 457         .offset = 0x4200,
 458         .width = 2,
 459         .clkr.hw.init = &(struct clk_init_data){
 460                 .name = "mmpll9",
 461                 .parent_names = (const char *[]){ "mmpll9_early" },
 462                 .num_parents = 1,
 463                 .ops = &clk_alpha_pll_postdiv_ops,
 464                 .flags = CLK_SET_RATE_PARENT,
 465         },
 466 };
 467
 468 static const struct freq_tbl ftbl_ahb_clk_src[] = {
 469         F(19200000, P_XO, 1, 0, 0),
 470         F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
 471         F(80000000, P_MMPLL0, 10, 0, 0),
 472         { }
 473 };
 474
 475 static struct clk_rcg2 ahb_clk_src = {
 476         .cmd_rcgr = 0x5000,
 477         .hid_width = 5,
 478         .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 479         .freq_tbl = ftbl_ahb_clk_src,
 480         .clkr.hw.init = &(struct clk_init_data){
 481                 .name = "ahb_clk_src",
 482                 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
 483                 .num_parents = 4,
 484                 .ops = &clk_rcg2_ops,
 485         },
 486 };
 487
 488 static const struct freq_tbl ftbl_axi_clk_src[] = {
 489         F(19200000, P_XO, 1, 0, 0),
 490         F(75000000, P_GPLL0_DIV, 4, 0, 0),
 491         F(100000000, P_GPLL0, 6, 0, 0),
 492         F(171430000, P_GPLL0, 3.5, 0, 0),
 493         F(200000000, P_GPLL0, 3, 0, 0),
 494         F(320000000, P_MMPLL0, 2.5, 0, 0),
 495         F(400000000, P_MMPLL0, 2, 0, 0),
 496         { }
 497 };
 498
 499 static struct clk_rcg2 axi_clk_src = {
 500         .cmd_rcgr = 0x5040,
 501         .hid_width = 5,
 502         .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
 503         .freq_tbl = ftbl_axi_clk_src,
 504         .clkr.hw.init = &(struct clk_init_data){
 505                 .name = "axi_clk_src",
 506                 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
 507                 .num_parents = 5,
 508                 .ops = &clk_rcg2_ops,
 509         },
 510 };
 511
 512 static struct clk_rcg2 maxi_clk_src = {
 513         .cmd_rcgr = 0x5090,
 514         .hid_width = 5,
 515         .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
 516         .freq_tbl = ftbl_axi_clk_src,
 517         .clkr.hw.init = &(struct clk_init_data){
 518                 .name = "maxi_clk_src",
 519                 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
 520                 .num_parents = 5,
 521                 .ops = &clk_rcg2_ops,
 522         },
 523 };
 524
 525 static struct clk_rcg2 gfx3d_clk_src = {
 526         .cmd_rcgr = 0x4000,
 527         .hid_width = 5,
 528         .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
 529         .clkr.hw.init = &(struct clk_init_data){
 530                 .name = "gfx3d_clk_src",
 531                 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
 532                 .num_parents = 6,
 533                 .ops = &clk_gfx3d_ops,
 534                 .flags = CLK_SET_RATE_PARENT,
 535         },
 536 };
 537
 538 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
 539         F(19200000, P_XO, 1, 0, 0),
 540         { }
 541 };
 542
 543 static struct clk_rcg2 rbbmtimer_clk_src = {
 544         .cmd_rcgr = 0x4090,
 545         .hid_width = 5,
 546         .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 547         .freq_tbl = ftbl_rbbmtimer_clk_src,
 548         .clkr.hw.init = &(struct clk_init_data){
 549                 .name = "rbbmtimer_clk_src",
 550                 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
 551                 .num_parents = 4,
 552                 .ops = &clk_rcg2_ops,
 553         },
 554 };
 555
 556 static struct clk_rcg2 isense_clk_src = {
 557         .cmd_rcgr = 0x4010,
 558         .hid_width = 5,
 559         .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
 560         .clkr.hw.init = &(struct clk_init_data){
 561                 .name = "isense_clk_src",
 562                 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
 563                 .num_parents = 7,
 564                 .ops = &clk_rcg2_ops,
 565         },
 566 };
 567
 568 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
 569         F(19200000, P_XO, 1, 0, 0),
 570         F(50000000, P_GPLL0, 12, 0, 0),
 571         { }
 572 };
 573
 574 static struct clk_rcg2 rbcpr_clk_src = {
 575         .cmd_rcgr = 0x4060,
 576         .hid_width = 5,
 577         .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 578         .freq_tbl = ftbl_rbcpr_clk_src,
 579         .clkr.hw.init = &(struct clk_init_data){
 580                 .name = "rbcpr_clk_src",
 581                 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
 582                 .num_parents = 4,
 583                 .ops = &clk_rcg2_ops,
 584         },
 585 };
 586
 587 static const struct freq_tbl ftbl_video_core_clk_src[] = {
 588         F(75000000, P_GPLL0_DIV, 4, 0, 0),
 589         F(150000000, P_GPLL0, 4, 0, 0),
 590         F(346666667, P_MMPLL3, 3, 0, 0),
 591         F(520000000, P_MMPLL3, 2, 0, 0),
 592         { }
 593 };
 594
 595 static struct clk_rcg2 video_core_clk_src = {
 596         .cmd_rcgr = 0x1000,
 597         .mnd_width = 8,
 598         .hid_width = 5,
 599         .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 600         .freq_tbl = ftbl_video_core_clk_src,
 601         .clkr.hw.init = &(struct clk_init_data){
 602                 .name = "video_core_clk_src",
 603                 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 604                 .num_parents = 5,
 605                 .ops = &clk_rcg2_ops,
 606         },
 607 };
 608
 609 static struct clk_rcg2 video_subcore0_clk_src = {
 610         .cmd_rcgr = 0x1060,
 611         .mnd_width = 8,
 612         .hid_width = 5,
 613         .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 614         .freq_tbl = ftbl_video_core_clk_src,
 615         .clkr.hw.init = &(struct clk_init_data){
 616                 .name = "video_subcore0_clk_src",
 617                 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 618                 .num_parents = 5,
 619                 .ops = &clk_rcg2_ops,
 620         },
 621 };
 622
 623 static struct clk_rcg2 video_subcore1_clk_src = {
 624         .cmd_rcgr = 0x1080,
 625         .mnd_width = 8,
 626         .hid_width = 5,
 627         .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 628         .freq_tbl = ftbl_video_core_clk_src,
 629         .clkr.hw.init = &(struct clk_init_data){
 630                 .name = "video_subcore1_clk_src",
 631                 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 632                 .num_parents = 5,
 633                 .ops = &clk_rcg2_ops,
 634         },
 635 };
 636
 637 static struct clk_rcg2 pclk0_clk_src = {
 638         .cmd_rcgr = 0x2000,
 639         .mnd_width = 8,
 640         .hid_width = 5,
 641         .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
 642         .clkr.hw.init = &(struct clk_init_data){
 643                 .name = "pclk0_clk_src",
 644                 .parent_names = mmss_xo_dsi0pll_dsi1pll,
 645                 .num_parents = 3,
 646                 .ops = &clk_pixel_ops,
 647                 .flags = CLK_SET_RATE_PARENT,
 648         },
 649 };
 650
 651 static struct clk_rcg2 pclk1_clk_src = {
 652         .cmd_rcgr = 0x2020,
 653         .mnd_width = 8,
 654         .hid_width = 5,
 655         .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
 656         .clkr.hw.init = &(struct clk_init_data){
 657                 .name = "pclk1_clk_src",
 658                 .parent_names = mmss_xo_dsi0pll_dsi1pll,
 659                 .num_parents = 3,
 660                 .ops = &clk_pixel_ops,
 661                 .flags = CLK_SET_RATE_PARENT,
 662         },
 663 };
 664
 665 static const struct freq_tbl ftbl_mdp_clk_src[] = {
 666         F(85714286, P_GPLL0, 7, 0, 0),
 667         F(100000000, P_GPLL0, 6, 0, 0),
 668         F(150000000, P_GPLL0, 4, 0, 0),
 669         F(171428571, P_GPLL0, 3.5, 0, 0),
 670         F(200000000, P_GPLL0, 3, 0, 0),
 671         F(275000000, P_MMPLL5, 3, 0, 0),
 672         F(300000000, P_GPLL0, 2, 0, 0),
 673         F(330000000, P_MMPLL5, 2.5, 0, 0),
 674         F(412500000, P_MMPLL5, 2, 0, 0),
 675         { }
 676 };
 677
 678 static struct clk_rcg2 mdp_clk_src = {
 679         .cmd_rcgr = 0x2040,
 680         .hid_width = 5,
 681         .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
 682         .freq_tbl = ftbl_mdp_clk_src,
 683         .clkr.hw.init = &(struct clk_init_data){
 684                 .name = "mdp_clk_src",
 685                 .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
 686                 .num_parents = 5,
 687                 .ops = &clk_rcg2_ops,
 688         },
 689 };
 690
 691 static struct freq_tbl extpclk_freq_tbl[] = {
 692         { .src = P_HDMIPLL },
 693         { }
 694 };
 695
 696 static struct clk_rcg2 extpclk_clk_src = {
 697         .cmd_rcgr = 0x2060,
 698         .hid_width = 5,
 699         .parent_map = mmss_xo_hdmi_map,
 700         .freq_tbl = extpclk_freq_tbl,
 701         .clkr.hw.init = &(struct clk_init_data){
 702                 .name = "extpclk_clk_src",
 703                 .parent_names = mmss_xo_hdmi,
 704                 .num_parents = 2,
 705                 .ops = &clk_byte_ops,
 706                 .flags = CLK_SET_RATE_PARENT,
 707         },
 708 };
 709
 710 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
 711         F(19200000, P_XO, 1, 0, 0),
 712         { }
 713 };
 714
 715 static struct clk_rcg2 vsync_clk_src = {
 716         .cmd_rcgr = 0x2080,
 717         .hid_width = 5,
 718         .parent_map = mmss_xo_gpll0_gpll0_div_map,
 719         .freq_tbl = ftbl_mdss_vsync_clk,
 720         .clkr.hw.init = &(struct clk_init_data){
 721                 .name = "vsync_clk_src",
 722                 .parent_names = mmss_xo_gpll0_gpll0_div,
 723                 .num_parents = 3,
 724                 .ops = &clk_rcg2_ops,
 725         },
 726 };
 727
 728 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 729         F(19200000, P_XO, 1, 0, 0),
 730         { }
 731 };
 732
 733 static struct clk_rcg2 hdmi_clk_src = {
 734         .cmd_rcgr = 0x2100,
 735         .hid_width = 5,
 736         .parent_map = mmss_xo_gpll0_gpll0_div_map,
 737         .freq_tbl = ftbl_mdss_hdmi_clk,
 738         .clkr.hw.init = &(struct clk_init_data){
 739                 .name = "hdmi_clk_src",
 740                 .parent_names = mmss_xo_gpll0_gpll0_div,
 741                 .num_parents = 3,
 742                 .ops = &clk_rcg2_ops,
 743         },
 744 };
 745
 746 static struct clk_rcg2 byte0_clk_src = {
 747         .cmd_rcgr = 0x2120,
 748         .hid_width = 5,
 749         .parent_map = mmss_xo_dsibyte_map,
 750         .clkr.hw.init = &(struct clk_init_data){
 751                 .name = "byte0_clk_src",
 752                 .parent_names = mmss_xo_dsibyte,
 753                 .num_parents = 3,
 754                 .ops = &clk_byte2_ops,
 755                 .flags = CLK_SET_RATE_PARENT,
 756         },
 757 };
 758
 759 static struct clk_rcg2 byte1_clk_src = {
 760         .cmd_rcgr = 0x2140,
 761         .hid_width = 5,
 762         .parent_map = mmss_xo_dsibyte_map,
 763         .clkr.hw.init = &(struct clk_init_data){
 764                 .name = "byte1_clk_src",
 765                 .parent_names = mmss_xo_dsibyte,
 766                 .num_parents = 3,
 767                 .ops = &clk_byte2_ops,
 768                 .flags = CLK_SET_RATE_PARENT,
 769         },
 770 };
 771
 772 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 773         F(19200000, P_XO, 1, 0, 0),
 774         { }
 775 };
 776
 777 static struct clk_rcg2 esc0_clk_src = {
 778         .cmd_rcgr = 0x2160,
 779         .hid_width = 5,
 780         .parent_map = mmss_xo_dsibyte_map,
 781         .freq_tbl = ftbl_mdss_esc0_1_clk,
 782         .clkr.hw.init = &(struct clk_init_data){
 783                 .name = "esc0_clk_src",
 784                 .parent_names = mmss_xo_dsibyte,
 785                 .num_parents = 3,
 786                 .ops = &clk_rcg2_ops,
 787         },
 788 };
 789
 790 static struct clk_rcg2 esc1_clk_src = {
 791         .cmd_rcgr = 0x2180,
 792         .hid_width = 5,
 793         .parent_map = mmss_xo_dsibyte_map,
 794         .freq_tbl = ftbl_mdss_esc0_1_clk,
 795         .clkr.hw.init = &(struct clk_init_data){
 796                 .name = "esc1_clk_src",
 797                 .parent_names = mmss_xo_dsibyte,
 798                 .num_parents = 3,
 799                 .ops = &clk_rcg2_ops,
 800         },
 801 };
 802
 803 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
 804         F(10000, P_XO, 16, 1, 120),
 805         F(24000, P_XO, 16, 1, 50),
 806         F(6000000, P_GPLL0_DIV, 10, 1, 5),
 807         F(12000000, P_GPLL0_DIV, 1, 1, 25),
 808         F(13000000, P_GPLL0_DIV, 2, 13, 150),
 809         F(24000000, P_GPLL0_DIV, 1, 2, 25),
 810         { }
 811 };
 812
 813 static struct clk_rcg2 camss_gp0_clk_src = {
 814         .cmd_rcgr = 0x3420,
 815         .mnd_width = 8,
 816         .hid_width = 5,
 817         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 818         .freq_tbl = ftbl_camss_gp0_clk_src,
 819         .clkr.hw.init = &(struct clk_init_data){
 820                 .name = "camss_gp0_clk_src",
 821                 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 822                 .num_parents = 5,
 823                 .ops = &clk_rcg2_ops,
 824         },
 825 };
 826
 827 static struct clk_rcg2 camss_gp1_clk_src = {
 828         .cmd_rcgr = 0x3450,
 829         .mnd_width = 8,
 830         .hid_width = 5,
 831         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 832         .freq_tbl = ftbl_camss_gp0_clk_src,
 833         .clkr.hw.init = &(struct clk_init_data){
 834                 .name = "camss_gp1_clk_src",
 835                 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 836                 .num_parents = 5,
 837                 .ops = &clk_rcg2_ops,
 838         },
 839 };
 840
 841 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
 842         F(4800000, P_XO, 4, 0, 0),
 843         F(6000000, P_GPLL0_DIV, 10, 1, 5),
 844         F(8000000, P_GPLL0_DIV, 1, 2, 75),
 845         F(9600000, P_XO, 2, 0, 0),
 846         F(16666667, P_GPLL0_DIV, 2, 1, 9),
 847         F(19200000, P_XO, 1, 0, 0),
 848         F(24000000, P_GPLL0_DIV, 1, 2, 25),
 849         F(33333333, P_GPLL0_DIV, 1, 1, 9),
 850         F(48000000, P_GPLL0, 1, 2, 25),
 851         F(66666667, P_GPLL0, 1, 1, 9),
 852         { }
 853 };
 854
 855 static struct clk_rcg2 mclk0_clk_src = {
 856         .cmd_rcgr = 0x3360,
 857         .mnd_width = 8,
 858         .hid_width = 5,
 859         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 860         .freq_tbl = ftbl_mclk0_clk_src,
 861         .clkr.hw.init = &(struct clk_init_data){
 862                 .name = "mclk0_clk_src",
 863                 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 864                 .num_parents = 5,
 865                 .ops = &clk_rcg2_ops,
 866         },
 867 };
 868
 869 static struct clk_rcg2 mclk1_clk_src = {
 870         .cmd_rcgr = 0x3390,
 871         .mnd_width = 8,
 872         .hid_width = 5,
 873         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 874         .freq_tbl = ftbl_mclk0_clk_src,
 875         .clkr.hw.init = &(struct clk_init_data){
 876                 .name = "mclk1_clk_src",
 877                 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 878                 .num_parents = 5,
 879                 .ops = &clk_rcg2_ops,
 880         },
 881 };
 882
 883 static struct clk_rcg2 mclk2_clk_src = {
 884         .cmd_rcgr = 0x33c0,
 885         .mnd_width = 8,
 886         .hid_width = 5,
 887         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 888         .freq_tbl = ftbl_mclk0_clk_src,
 889         .clkr.hw.init = &(struct clk_init_data){
 890                 .name = "mclk2_clk_src",
 891                 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 892                 .num_parents = 5,
 893                 .ops = &clk_rcg2_ops,
 894         },
 895 };
 896
 897 static struct clk_rcg2 mclk3_clk_src = {
 898         .cmd_rcgr = 0x33f0,
 899         .mnd_width = 8,
 900         .hid_width = 5,
 901         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 902         .freq_tbl = ftbl_mclk0_clk_src,
 903         .clkr.hw.init = &(struct clk_init_data){
 904                 .name = "mclk3_clk_src",
 905                 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 906                 .num_parents = 5,
 907                 .ops = &clk_rcg2_ops,
 908         },
 909 };
 910
 911 static const struct freq_tbl ftbl_cci_clk_src[] = {
 912         F(19200000, P_XO, 1, 0, 0),
 913         F(37500000, P_GPLL0, 16, 0, 0),
 914         F(50000000, P_GPLL0, 12, 0, 0),
 915         F(100000000, P_GPLL0, 6, 0, 0),
 916         { }
 917 };
 918
 919 static struct clk_rcg2 cci_clk_src = {
 920         .cmd_rcgr = 0x3300,
 921         .mnd_width = 8,
 922         .hid_width = 5,
 923         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 924         .freq_tbl = ftbl_cci_clk_src,
 925         .clkr.hw.init = &(struct clk_init_data){
 926                 .name = "cci_clk_src",
 927                 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 928                 .num_parents = 5,
 929                 .ops = &clk_rcg2_ops,
 930         },
 931 };
 932
 933 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
 934         F(100000000, P_GPLL0_DIV, 3, 0, 0),
 935         F(200000000, P_GPLL0, 3, 0, 0),
 936         F(266666667, P_MMPLL0, 3, 0, 0),
 937         { }
 938 };
 939
 940 static struct clk_rcg2 csi0phytimer_clk_src = {
 941         .cmd_rcgr = 0x3000,
 942         .hid_width = 5,
 943         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
 944         .freq_tbl = ftbl_csi0phytimer_clk_src,
 945         .clkr.hw.init = &(struct clk_init_data){
 946                 .name = "csi0phytimer_clk_src",
 947                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
 948                 .num_parents = 7,
 949                 .ops = &clk_rcg2_ops,
 950         },
 951 };
 952
 953 static struct clk_rcg2 csi1phytimer_clk_src = {
 954         .cmd_rcgr = 0x3030,
 955         .hid_width = 5,
 956         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
 957         .freq_tbl = ftbl_csi0phytimer_clk_src,
 958         .clkr.hw.init = &(struct clk_init_data){
 959                 .name = "csi1phytimer_clk_src",
 960                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
 961                 .num_parents = 7,
 962                 .ops = &clk_rcg2_ops,
 963         },
 964 };
 965
 966 static struct clk_rcg2 csi2phytimer_clk_src = {
 967         .cmd_rcgr = 0x3060,
 968         .hid_width = 5,
 969         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
 970         .freq_tbl = ftbl_csi0phytimer_clk_src,
 971         .clkr.hw.init = &(struct clk_init_data){
 972                 .name = "csi2phytimer_clk_src",
 973                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
 974                 .num_parents = 7,
 975                 .ops = &clk_rcg2_ops,
 976         },
 977 };
 978
 979 static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
 980         F(100000000, P_GPLL0_DIV, 3, 0, 0),
 981         F(200000000, P_GPLL0, 3, 0, 0),
 982         F(320000000, P_MMPLL4, 3, 0, 0),
 983         F(384000000, P_MMPLL4, 2.5, 0, 0),
 984         { }
 985 };
 986
 987 static struct clk_rcg2 csiphy0_3p_clk_src = {
 988         .cmd_rcgr = 0x3240,
 989         .hid_width = 5,
 990         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
 991         .freq_tbl = ftbl_csiphy0_3p_clk_src,
 992         .clkr.hw.init = &(struct clk_init_data){
 993                 .name = "csiphy0_3p_clk_src",
 994                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
 995                 .num_parents = 7,
 996                 .ops = &clk_rcg2_ops,
 997         },
 998 };
 999
1000 static struct clk_rcg2 csiphy1_3p_clk_src = {
1001         .cmd_rcgr = 0x3260,
1002         .hid_width = 5,
1003         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1004         .freq_tbl = ftbl_csiphy0_3p_clk_src,
1005         .clkr.hw.init = &(struct clk_init_data){
1006                 .name = "csiphy1_3p_clk_src",
1007                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1008                 .num_parents = 7,
1009                 .ops = &clk_rcg2_ops,
1010         },
1011 };
1012
1013 static struct clk_rcg2 csiphy2_3p_clk_src = {
1014         .cmd_rcgr = 0x3280,
1015         .hid_width = 5,
1016         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1017         .freq_tbl = ftbl_csiphy0_3p_clk_src,
1018         .clkr.hw.init = &(struct clk_init_data){
1019                 .name = "csiphy2_3p_clk_src",
1020                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1021                 .num_parents = 7,
1022                 .ops = &clk_rcg2_ops,
1023         },
1024 };
1025
1026 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1027         F(75000000, P_GPLL0_DIV, 4, 0, 0),
1028         F(150000000, P_GPLL0, 4, 0, 0),
1029         F(228571429, P_MMPLL0, 3.5, 0, 0),
1030         F(266666667, P_MMPLL0, 3, 0, 0),
1031         F(320000000, P_MMPLL0, 2.5, 0, 0),
1032         F(480000000, P_MMPLL4, 2, 0, 0),
1033         { }
1034 };
1035
1036 static struct clk_rcg2 jpeg0_clk_src = {
1037         .cmd_rcgr = 0x3500,
1038         .hid_width = 5,
1039         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1040         .freq_tbl = ftbl_jpeg0_clk_src,
1041         .clkr.hw.init = &(struct clk_init_data){
1042                 .name = "jpeg0_clk_src",
1043                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1044                 .num_parents = 7,
1045                 .ops = &clk_rcg2_ops,
1046         },
1047 };
1048
1049 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
1050         F(75000000, P_GPLL0_DIV, 4, 0, 0),
1051         F(150000000, P_GPLL0, 4, 0, 0),
1052         F(228571429, P_MMPLL0, 3.5, 0, 0),
1053         F(266666667, P_MMPLL0, 3, 0, 0),
1054         F(320000000, P_MMPLL0, 2.5, 0, 0),
1055         { }
1056 };
1057
1058 static struct clk_rcg2 jpeg2_clk_src = {
1059         .cmd_rcgr = 0x3540,
1060         .hid_width = 5,
1061         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1062         .freq_tbl = ftbl_jpeg2_clk_src,
1063         .clkr.hw.init = &(struct clk_init_data){
1064                 .name = "jpeg2_clk_src",
1065                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1066                 .num_parents = 7,
1067                 .ops = &clk_rcg2_ops,
1068         },
1069 };
1070
1071 static struct clk_rcg2 jpeg_dma_clk_src = {
1072         .cmd_rcgr = 0x3560,
1073         .hid_width = 5,
1074         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1075         .freq_tbl = ftbl_jpeg0_clk_src,
1076         .clkr.hw.init = &(struct clk_init_data){
1077                 .name = "jpeg_dma_clk_src",
1078                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1079                 .num_parents = 7,
1080                 .ops = &clk_rcg2_ops,
1081         },
1082 };
1083
1084 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1085         F(75000000, P_GPLL0_DIV, 4, 0, 0),
1086         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1087         F(300000000, P_GPLL0, 2, 0, 0),
1088         F(320000000, P_MMPLL0, 2.5, 0, 0),
1089         F(480000000, P_MMPLL4, 2, 0, 0),
1090         F(600000000, P_GPLL0, 1, 0, 0),
1091         { }
1092 };
1093
1094 static struct clk_rcg2 vfe0_clk_src = {
1095         .cmd_rcgr = 0x3600,
1096         .hid_width = 5,
1097         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1098         .freq_tbl = ftbl_vfe0_clk_src,
1099         .clkr.hw.init = &(struct clk_init_data){
1100                 .name = "vfe0_clk_src",
1101                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1102                 .num_parents = 7,
1103                 .ops = &clk_rcg2_ops,
1104         },
1105 };
1106
1107 static struct clk_rcg2 vfe1_clk_src = {
1108         .cmd_rcgr = 0x3620,
1109         .hid_width = 5,
1110         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1111         .freq_tbl = ftbl_vfe0_clk_src,
1112         .clkr.hw.init = &(struct clk_init_data){
1113                 .name = "vfe1_clk_src",
1114                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1115                 .num_parents = 7,
1116                 .ops = &clk_rcg2_ops,
1117         },
1118 };
1119
1120 static const struct freq_tbl ftbl_cpp_clk_src[] = {
1121         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1122         F(200000000, P_GPLL0, 3, 0, 0),
1123         F(320000000, P_MMPLL0, 2.5, 0, 0),
1124         F(480000000, P_MMPLL4, 2, 0, 0),
1125         F(640000000, P_MMPLL4, 1.5, 0, 0),
1126         { }
1127 };
1128
1129 static struct clk_rcg2 cpp_clk_src = {
1130         .cmd_rcgr = 0x3640,
1131         .hid_width = 5,
1132         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1133         .freq_tbl = ftbl_cpp_clk_src,
1134         .clkr.hw.init = &(struct clk_init_data){
1135                 .name = "cpp_clk_src",
1136                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1137                 .num_parents = 7,
1138                 .ops = &clk_rcg2_ops,
1139         },
1140 };
1141
1142 static const struct freq_tbl ftbl_csi0_clk_src[] = {
1143         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1144         F(200000000, P_GPLL0, 3, 0, 0),
1145         F(266666667, P_MMPLL0, 3, 0, 0),
1146         F(480000000, P_MMPLL4, 2, 0, 0),
1147         F(600000000, P_GPLL0, 1, 0, 0),
1148         { }
1149 };
1150
1151 static struct clk_rcg2 csi0_clk_src = {
1152         .cmd_rcgr = 0x3090,
1153         .hid_width = 5,
1154         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1155         .freq_tbl = ftbl_csi0_clk_src,
1156         .clkr.hw.init = &(struct clk_init_data){
1157                 .name = "csi0_clk_src",
1158                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1159                 .num_parents = 7,
1160                 .ops = &clk_rcg2_ops,
1161         },
1162 };
1163
1164 static struct clk_rcg2 csi1_clk_src = {
1165         .cmd_rcgr = 0x3100,
1166         .hid_width = 5,
1167         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1168         .freq_tbl = ftbl_csi0_clk_src,
1169         .clkr.hw.init = &(struct clk_init_data){
1170                 .name = "csi1_clk_src",
1171                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1172                 .num_parents = 7,
1173                 .ops = &clk_rcg2_ops,
1174         },
1175 };
1176
1177 static struct clk_rcg2 csi2_clk_src = {
1178         .cmd_rcgr = 0x3160,
1179         .hid_width = 5,
1180         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1181         .freq_tbl = ftbl_csi0_clk_src,
1182         .clkr.hw.init = &(struct clk_init_data){
1183                 .name = "csi2_clk_src",
1184                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1185                 .num_parents = 7,
1186                 .ops = &clk_rcg2_ops,
1187         },
1188 };
1189
1190 static struct clk_rcg2 csi3_clk_src = {
1191         .cmd_rcgr = 0x31c0,
1192         .hid_width = 5,
1193         .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1194         .freq_tbl = ftbl_csi0_clk_src,
1195         .clkr.hw.init = &(struct clk_init_data){
1196                 .name = "csi3_clk_src",
1197                 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1198                 .num_parents = 7,
1199                 .ops = &clk_rcg2_ops,
1200         },
1201 };
1202
1203 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
1204         F(100000000, P_GPLL0_DIV, 3, 0, 0),
1205         F(200000000, P_GPLL0, 3, 0, 0),
1206         F(400000000, P_MMPLL0, 2, 0, 0),
1207         { }
1208 };
1209
1210 static struct clk_rcg2 fd_core_clk_src = {
1211         .cmd_rcgr = 0x3b00,
1212         .hid_width = 5,
1213         .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
1214         .freq_tbl = ftbl_fd_core_clk_src,
1215         .clkr.hw.init = &(struct clk_init_data){
1216                 .name = "fd_core_clk_src",
1217                 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1218                 .num_parents = 5,
1219                 .ops = &clk_rcg2_ops,
1220         },
1221 };
1222
1223 static struct clk_branch mmss_mmagic_ahb_clk = {
1224         .halt_reg = 0x5024,
1225         .clkr = {
1226                 .enable_reg = 0x5024,
1227                 .enable_mask = BIT(0),
1228                 .hw.init = &(struct clk_init_data){
1229                         .name = "mmss_mmagic_ahb_clk",
1230                         .parent_names = (const char *[]){ "ahb_clk_src" },
1231                         .num_parents = 1,
1232                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1233                         .ops = &clk_branch2_ops,
1234                 },
1235         },
1236 };
1237
1238 static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1239         .halt_reg = 0x5054,
1240         .clkr = {
1241                 .enable_reg = 0x5054,
1242                 .enable_mask = BIT(0),
1243                 .hw.init = &(struct clk_init_data){
1244                         .name = "mmss_mmagic_cfg_ahb_clk",
1245                         .parent_names = (const char *[]){ "ahb_clk_src" },
1246                         .num_parents = 1,
1247                         .flags = CLK_SET_RATE_PARENT,
1248                         .ops = &clk_branch2_ops,
1249                 },
1250         },
1251 };
1252
1253 static struct clk_branch mmss_misc_ahb_clk = {
1254         .halt_reg = 0x5018,
1255         .clkr = {
1256                 .enable_reg = 0x5018,
1257                 .enable_mask = BIT(0),
1258                 .hw.init = &(struct clk_init_data){
1259                         .name = "mmss_misc_ahb_clk",
1260                         .parent_names = (const char *[]){ "ahb_clk_src" },
1261                         .num_parents = 1,
1262                         .flags = CLK_SET_RATE_PARENT,
1263                         .ops = &clk_branch2_ops,
1264                 },
1265         },
1266 };
1267
1268 static struct clk_branch mmss_misc_cxo_clk = {
1269         .halt_reg = 0x5014,
1270         .clkr = {
1271                 .enable_reg = 0x5014,
1272                 .enable_mask = BIT(0),
1273                 .hw.init = &(struct clk_init_data){
1274                         .name = "mmss_misc_cxo_clk",
1275                         .parent_names = (const char *[]){ "xo" },
1276                         .num_parents = 1,
1277                         .ops = &clk_branch2_ops,
1278                 },
1279         },
1280 };
1281
1282 static struct clk_branch mmss_mmagic_maxi_clk = {
1283         .halt_reg = 0x5074,
1284         .clkr = {
1285                 .enable_reg = 0x5074,
1286                 .enable_mask = BIT(0),
1287                 .hw.init = &(struct clk_init_data){
1288                         .name = "mmss_mmagic_maxi_clk",
1289                         .parent_names = (const char *[]){ "maxi_clk_src" },
1290                         .num_parents = 1,
1291                         .flags = CLK_SET_RATE_PARENT,
1292                         .ops = &clk_branch2_ops,
1293                 },
1294         },
1295 };
1296
1297 static struct clk_branch mmagic_camss_axi_clk = {
1298         .halt_reg = 0x3c44,
1299         .clkr = {
1300                 .enable_reg = 0x3c44,
1301                 .enable_mask = BIT(0),
1302                 .hw.init = &(struct clk_init_data){
1303                         .name = "mmagic_camss_axi_clk",
1304                         .parent_names = (const char *[]){ "axi_clk_src" },
1305                         .num_parents = 1,
1306                         .flags = CLK_SET_RATE_PARENT,
1307                         .ops = &clk_branch2_ops,
1308                 },
1309         },
1310 };
1311
1312 static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1313         .halt_reg = 0x3c48,
1314         .clkr = {
1315                 .enable_reg = 0x3c48,
1316                 .enable_mask = BIT(0),
1317                 .hw.init = &(struct clk_init_data){
1318                         .name = "mmagic_camss_noc_cfg_ahb_clk",
1319                         .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1320                         .num_parents = 1,
1321                         .flags = CLK_SET_RATE_PARENT,
1322                         .ops = &clk_branch2_ops,
1323                 },
1324         },
1325 };
1326
1327 static struct clk_branch smmu_vfe_ahb_clk = {
1328         .halt_reg = 0x3c04,
1329         .clkr = {
1330                 .enable_reg = 0x3c04,
1331                 .enable_mask = BIT(0),
1332                 .hw.init = &(struct clk_init_data){
1333                         .name = "smmu_vfe_ahb_clk",
1334                         .parent_names = (const char *[]){ "ahb_clk_src" },
1335                         .num_parents = 1,
1336                         .flags = CLK_SET_RATE_PARENT,
1337                         .ops = &clk_branch2_ops,
1338                 },
1339         },
1340 };
1341
1342 static struct clk_branch smmu_vfe_axi_clk = {
1343         .halt_reg = 0x3c08,
1344         .clkr = {
1345                 .enable_reg = 0x3c08,
1346                 .enable_mask = BIT(0),
1347                 .hw.init = &(struct clk_init_data){
1348                         .name = "smmu_vfe_axi_clk",
1349                         .parent_names = (const char *[]){ "axi_clk_src" },
1350                         .num_parents = 1,
1351                         .flags = CLK_SET_RATE_PARENT,
1352                         .ops = &clk_branch2_ops,
1353                 },
1354         },
1355 };
1356
1357 static struct clk_branch smmu_cpp_ahb_clk = {
1358         .halt_reg = 0x3c14,
1359         .clkr = {
1360                 .enable_reg = 0x3c14,
1361                 .enable_mask = BIT(0),
1362                 .hw.init = &(struct clk_init_data){
1363                         .name = "smmu_cpp_ahb_clk",
1364                         .parent_names = (const char *[]){ "ahb_clk_src" },
1365                         .num_parents = 1,
1366                         .flags = CLK_SET_RATE_PARENT,
1367                         .ops = &clk_branch2_ops,
1368                 },
1369         },
1370 };
1371
1372 static struct clk_branch smmu_cpp_axi_clk = {
1373         .halt_reg = 0x3c18,
1374         .clkr = {
1375                 .enable_reg = 0x3c18,
1376                 .enable_mask = BIT(0),
1377                 .hw.init = &(struct clk_init_data){
1378                         .name = "smmu_cpp_axi_clk",
1379                         .parent_names = (const char *[]){ "axi_clk_src" },
1380                         .num_parents = 1,
1381                         .flags = CLK_SET_RATE_PARENT,
1382                         .ops = &clk_branch2_ops,
1383                 },
1384         },
1385 };
1386
1387 static struct clk_branch smmu_jpeg_ahb_clk = {
1388         .halt_reg = 0x3c24,
1389         .clkr = {
1390                 .enable_reg = 0x3c24,
1391                 .enable_mask = BIT(0),
1392                 .hw.init = &(struct clk_init_data){
1393                         .name = "smmu_jpeg_ahb_clk",
1394                         .parent_names = (const char *[]){ "ahb_clk_src" },
1395                         .num_parents = 1,
1396                         .flags = CLK_SET_RATE_PARENT,
1397                         .ops = &clk_branch2_ops,
1398                 },
1399         },
1400 };
1401
1402 static struct clk_branch smmu_jpeg_axi_clk = {
1403         .halt_reg = 0x3c28,
1404         .clkr = {
1405                 .enable_reg = 0x3c28,
1406                 .enable_mask = BIT(0),
1407                 .hw.init = &(struct clk_init_data){
1408                         .name = "smmu_jpeg_axi_clk",
1409                         .parent_names = (const char *[]){ "axi_clk_src" },
1410                         .num_parents = 1,
1411                         .flags = CLK_SET_RATE_PARENT,
1412                         .ops = &clk_branch2_ops,
1413                 },
1414         },
1415 };
1416
1417 static struct clk_branch mmagic_mdss_axi_clk = {
1418         .halt_reg = 0x2474,
1419         .clkr = {
1420                 .enable_reg = 0x2474,
1421                 .enable_mask = BIT(0),
1422                 .hw.init = &(struct clk_init_data){
1423                         .name = "mmagic_mdss_axi_clk",
1424                         .parent_names = (const char *[]){ "axi_clk_src" },
1425                         .num_parents = 1,
1426                         .flags = CLK_SET_RATE_PARENT,
1427                         .ops = &clk_branch2_ops,
1428                 },
1429         },
1430 };
1431
1432 static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1433         .halt_reg = 0x2478,
1434         .clkr = {
1435                 .enable_reg = 0x2478,
1436                 .enable_mask = BIT(0),
1437                 .hw.init = &(struct clk_init_data){
1438                         .name = "mmagic_mdss_noc_cfg_ahb_clk",
1439                         .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1440                         .num_parents = 1,
1441                         .flags = CLK_SET_RATE_PARENT,
1442                         .ops = &clk_branch2_ops,
1443                 },
1444         },
1445 };
1446
1447 static struct clk_branch smmu_rot_ahb_clk = {
1448         .halt_reg = 0x2444,
1449         .clkr = {
1450                 .enable_reg = 0x2444,
1451                 .enable_mask = BIT(0),
1452                 .hw.init = &(struct clk_init_data){
1453                         .name = "smmu_rot_ahb_clk",
1454                         .parent_names = (const char *[]){ "ahb_clk_src" },
1455                         .num_parents = 1,
1456                         .flags = CLK_SET_RATE_PARENT,
1457                         .ops = &clk_branch2_ops,
1458                 },
1459         },
1460 };
1461
1462 static struct clk_branch smmu_rot_axi_clk = {
1463         .halt_reg = 0x2448,
1464         .clkr = {
1465                 .enable_reg = 0x2448,
1466                 .enable_mask = BIT(0),
1467                 .hw.init = &(struct clk_init_data){
1468                         .name = "smmu_rot_axi_clk",
1469                         .parent_names = (const char *[]){ "axi_clk_src" },
1470                         .num_parents = 1,
1471                         .flags = CLK_SET_RATE_PARENT,
1472                         .ops = &clk_branch2_ops,
1473                 },
1474         },
1475 };
1476
1477 static struct clk_branch smmu_mdp_ahb_clk = {
1478         .halt_reg = 0x2454,
1479         .clkr = {
1480                 .enable_reg = 0x2454,
1481                 .enable_mask = BIT(0),
1482                 .hw.init = &(struct clk_init_data){
1483                         .name = "smmu_mdp_ahb_clk",
1484                         .parent_names = (const char *[]){ "ahb_clk_src" },
1485                         .num_parents = 1,
1486                         .flags = CLK_SET_RATE_PARENT,
1487                         .ops = &clk_branch2_ops,
1488                 },
1489         },
1490 };
1491
1492 static struct clk_branch smmu_mdp_axi_clk = {
1493         .halt_reg = 0x2458,
1494         .clkr = {
1495                 .enable_reg = 0x2458,
1496                 .enable_mask = BIT(0),
1497                 .hw.init = &(struct clk_init_data){
1498                         .name = "smmu_mdp_axi_clk",
1499                         .parent_names = (const char *[]){ "axi_clk_src" },
1500                         .num_parents = 1,
1501                         .flags = CLK_SET_RATE_PARENT,
1502                         .ops = &clk_branch2_ops,
1503                 },
1504         },
1505 };
1506
1507 static struct clk_branch mmagic_video_axi_clk = {
1508         .halt_reg = 0x1194,
1509         .clkr = {
1510                 .enable_reg = 0x1194,
1511                 .enable_mask = BIT(0),
1512                 .hw.init = &(struct clk_init_data){
1513                         .name = "mmagic_video_axi_clk",
1514                         .parent_names = (const char *[]){ "axi_clk_src" },
1515                         .num_parents = 1,
1516                         .flags = CLK_SET_RATE_PARENT,
1517                         .ops = &clk_branch2_ops,
1518                 },
1519         },
1520 };
1521
1522 static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1523         .halt_reg = 0x1198,
1524         .clkr = {
1525                 .enable_reg = 0x1198,
1526                 .enable_mask = BIT(0),
1527                 .hw.init = &(struct clk_init_data){
1528                         .name = "mmagic_video_noc_cfg_ahb_clk",
1529                         .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1530                         .num_parents = 1,
1531                         .flags = CLK_SET_RATE_PARENT,
1532                         .ops = &clk_branch2_ops,
1533                 },
1534         },
1535 };
1536
1537 static struct clk_branch smmu_video_ahb_clk = {
1538         .halt_reg = 0x1174,
1539         .clkr = {
1540                 .enable_reg = 0x1174,
1541                 .enable_mask = BIT(0),
1542                 .hw.init = &(struct clk_init_data){
1543                         .name = "smmu_video_ahb_clk",
1544                         .parent_names = (const char *[]){ "ahb_clk_src" },
1545                         .num_parents = 1,
1546                         .flags = CLK_SET_RATE_PARENT,
1547                         .ops = &clk_branch2_ops,
1548                 },
1549         },
1550 };
1551
1552 static struct clk_branch smmu_video_axi_clk = {
1553         .halt_reg = 0x1178,
1554         .clkr = {
1555                 .enable_reg = 0x1178,
1556                 .enable_mask = BIT(0),
1557                 .hw.init = &(struct clk_init_data){
1558                         .name = "smmu_video_axi_clk",
1559                         .parent_names = (const char *[]){ "axi_clk_src" },
1560                         .num_parents = 1,
1561                         .flags = CLK_SET_RATE_PARENT,
1562                         .ops = &clk_branch2_ops,
1563                 },
1564         },
1565 };
1566
1567 static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
1568         .halt_reg = 0x5298,
1569         .clkr = {
1570                 .enable_reg = 0x5298,
1571                 .enable_mask = BIT(0),
1572                 .hw.init = &(struct clk_init_data){
1573                         .name = "mmagic_bimc_noc_cfg_ahb_clk",
1574                         .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1575                         .num_parents = 1,
1576                         .flags = CLK_SET_RATE_PARENT,
1577                         .ops = &clk_branch2_ops,
1578                 },
1579         },
1580 };
1581
1582 static struct clk_branch gpu_gx_gfx3d_clk = {
1583         .halt_reg = 0x4028,
1584         .clkr = {
1585                 .enable_reg = 0x4028,
1586                 .enable_mask = BIT(0),
1587                 .hw.init = &(struct clk_init_data){
1588                         .name = "gpu_gx_gfx3d_clk",
1589                         .parent_names = (const char *[]){ "gfx3d_clk_src" },
1590                         .num_parents = 1,
1591                         .flags = CLK_SET_RATE_PARENT,
1592                         .ops = &clk_branch2_ops,
1593                 },
1594         },
1595 };
1596
1597 static struct clk_branch gpu_gx_rbbmtimer_clk = {
1598         .halt_reg = 0x40b0,
1599         .clkr = {
1600                 .enable_reg = 0x40b0,
1601                 .enable_mask = BIT(0),
1602                 .hw.init = &(struct clk_init_data){
1603                         .name = "gpu_gx_rbbmtimer_clk",
1604                         .parent_names = (const char *[]){ "rbbmtimer_clk_src" },
1605                         .num_parents = 1,
1606                         .flags = CLK_SET_RATE_PARENT,
1607                         .ops = &clk_branch2_ops,
1608                 },
1609         },
1610 };
1611
1612 static struct clk_branch gpu_ahb_clk = {
1613         .halt_reg = 0x403c,
1614         .clkr = {
1615                 .enable_reg = 0x403c,
1616                 .enable_mask = BIT(0),
1617                 .hw.init = &(struct clk_init_data){
1618                         .name = "gpu_ahb_clk",
1619                         .parent_names = (const char *[]){ "ahb_clk_src" },
1620                         .num_parents = 1,
1621                         .flags = CLK_SET_RATE_PARENT,
1622                         .ops = &clk_branch2_ops,
1623                 },
1624         },
1625 };
1626
1627 static struct clk_branch gpu_aon_isense_clk = {
1628         .halt_reg = 0x4044,
1629         .clkr = {
1630                 .enable_reg = 0x4044,
1631                 .enable_mask = BIT(0),
1632                 .hw.init = &(struct clk_init_data){
1633                         .name = "gpu_aon_isense_clk",
1634                         .parent_names = (const char *[]){ "isense_clk_src" },
1635                         .num_parents = 1,
1636                         .flags = CLK_SET_RATE_PARENT,
1637                         .ops = &clk_branch2_ops,
1638                 },
1639         },
1640 };
1641
1642 static struct clk_branch vmem_maxi_clk = {
1643         .halt_reg = 0x1204,
1644         .clkr = {
1645                 .enable_reg = 0x1204,
1646                 .enable_mask = BIT(0),
1647                 .hw.init = &(struct clk_init_data){
1648                         .name = "vmem_maxi_clk",
1649                         .parent_names = (const char *[]){ "maxi_clk_src" },
1650                         .num_parents = 1,
1651                         .flags = CLK_SET_RATE_PARENT,
1652                         .ops = &clk_branch2_ops,
1653                 },
1654         },
1655 };
1656
1657 static struct clk_branch vmem_ahb_clk = {
1658         .halt_reg = 0x1208,
1659         .clkr = {
1660                 .enable_reg = 0x1208,
1661                 .enable_mask = BIT(0),
1662                 .hw.init = &(struct clk_init_data){
1663                         .name = "vmem_ahb_clk",
1664                         .parent_names = (const char *[]){ "ahb_clk_src" },
1665                         .num_parents = 1,
1666                         .flags = CLK_SET_RATE_PARENT,
1667                         .ops = &clk_branch2_ops,
1668                 },
1669         },
1670 };
1671
1672 static struct clk_branch mmss_rbcpr_clk = {
1673         .halt_reg = 0x4084,
1674         .clkr = {
1675                 .enable_reg = 0x4084,
1676                 .enable_mask = BIT(0),
1677                 .hw.init = &(struct clk_init_data){
1678                         .name = "mmss_rbcpr_clk",
1679                         .parent_names = (const char *[]){ "rbcpr_clk_src" },
1680                         .num_parents = 1,
1681                         .flags = CLK_SET_RATE_PARENT,
1682                         .ops = &clk_branch2_ops,
1683                 },
1684         },
1685 };
1686
1687 static struct clk_branch mmss_rbcpr_ahb_clk = {
1688         .halt_reg = 0x4088,
1689         .clkr = {
1690                 .enable_reg = 0x4088,
1691                 .enable_mask = BIT(0),
1692                 .hw.init = &(struct clk_init_data){
1693                         .name = "mmss_rbcpr_ahb_clk",
1694                         .parent_names = (const char *[]){ "ahb_clk_src" },
1695                         .num_parents = 1,
1696                         .flags = CLK_SET_RATE_PARENT,
1697                         .ops = &clk_branch2_ops,
1698                 },
1699         },
1700 };
1701
1702 static struct clk_branch video_core_clk = {
1703         .halt_reg = 0x1028,
1704         .clkr = {
1705                 .enable_reg = 0x1028,
1706                 .enable_mask = BIT(0),
1707                 .hw.init = &(struct clk_init_data){
1708                         .name = "video_core_clk",
1709                         .parent_names = (const char *[]){ "video_core_clk_src" },
1710                         .num_parents = 1,
1711                         .flags = CLK_SET_RATE_PARENT,
1712                         .ops = &clk_branch2_ops,
1713                 },
1714         },
1715 };
1716
1717 static struct clk_branch video_axi_clk = {
1718         .halt_reg = 0x1034,
1719         .clkr = {
1720                 .enable_reg = 0x1034,
1721                 .enable_mask = BIT(0),
1722                 .hw.init = &(struct clk_init_data){
1723                         .name = "video_axi_clk",
1724                         .parent_names = (const char *[]){ "axi_clk_src" },
1725                         .num_parents = 1,
1726                         .flags = CLK_SET_RATE_PARENT,
1727                         .ops = &clk_branch2_ops,
1728                 },
1729         },
1730 };
1731
1732 static struct clk_branch video_maxi_clk = {
1733         .halt_reg = 0x1038,
1734         .clkr = {
1735                 .enable_reg = 0x1038,
1736                 .enable_mask = BIT(0),
1737                 .hw.init = &(struct clk_init_data){
1738                         .name = "video_maxi_clk",
1739                         .parent_names = (const char *[]){ "maxi_clk_src" },
1740                         .num_parents = 1,
1741                         .flags = CLK_SET_RATE_PARENT,
1742                         .ops = &clk_branch2_ops,
1743                 },
1744         },
1745 };
1746
1747 static struct clk_branch video_ahb_clk = {
1748         .halt_reg = 0x1030,
1749         .clkr = {
1750                 .enable_reg = 0x1030,
1751                 .enable_mask = BIT(0),
1752                 .hw.init = &(struct clk_init_data){
1753                         .name = "video_ahb_clk",
1754                         .parent_names = (const char *[]){ "ahb_clk_src" },
1755                         .num_parents = 1,
1756                         .flags = CLK_SET_RATE_PARENT,
1757                         .ops = &clk_branch2_ops,
1758                 },
1759         },
1760 };
1761
1762 static struct clk_branch video_subcore0_clk = {
1763         .halt_reg = 0x1048,
1764         .clkr = {
1765                 .enable_reg = 0x1048,
1766                 .enable_mask = BIT(0),
1767                 .hw.init = &(struct clk_init_data){
1768                         .name = "video_subcore0_clk",
1769                         .parent_names = (const char *[]){ "video_subcore0_clk_src" },
1770                         .num_parents = 1,
1771                         .flags = CLK_SET_RATE_PARENT,
1772                         .ops = &clk_branch2_ops,
1773                 },
1774         },
1775 };
1776
1777 static struct clk_branch video_subcore1_clk = {
1778         .halt_reg = 0x104c,
1779         .clkr = {
1780                 .enable_reg = 0x104c,
1781                 .enable_mask = BIT(0),
1782                 .hw.init = &(struct clk_init_data){
1783                         .name = "video_subcore1_clk",
1784                         .parent_names = (const char *[]){ "video_subcore1_clk_src" },
1785                         .num_parents = 1,
1786                         .flags = CLK_SET_RATE_PARENT,
1787                         .ops = &clk_branch2_ops,
1788                 },
1789         },
1790 };
1791
1792 static struct clk_branch mdss_ahb_clk = {
1793         .halt_reg = 0x2308,
1794         .clkr = {
1795                 .enable_reg = 0x2308,
1796                 .enable_mask = BIT(0),
1797                 .hw.init = &(struct clk_init_data){
1798                         .name = "mdss_ahb_clk",
1799                         .parent_names = (const char *[]){ "ahb_clk_src" },
1800                         .num_parents = 1,
1801                         .flags = CLK_SET_RATE_PARENT,
1802                         .ops = &clk_branch2_ops,
1803                 },
1804         },
1805 };
1806
1807 static struct clk_branch mdss_hdmi_ahb_clk = {
1808         .halt_reg = 0x230c,
1809         .clkr = {
1810                 .enable_reg = 0x230c,
1811                 .enable_mask = BIT(0),
1812                 .hw.init = &(struct clk_init_data){
1813                         .name = "mdss_hdmi_ahb_clk",
1814                         .parent_names = (const char *[]){ "ahb_clk_src" },
1815                         .num_parents = 1,
1816                         .flags = CLK_SET_RATE_PARENT,
1817                         .ops = &clk_branch2_ops,
1818                 },
1819         },
1820 };
1821
1822 static struct clk_branch mdss_axi_clk = {
1823         .halt_reg = 0x2310,
1824         .clkr = {
1825                 .enable_reg = 0x2310,
1826                 .enable_mask = BIT(0),
1827                 .hw.init = &(struct clk_init_data){
1828                         .name = "mdss_axi_clk",
1829                         .parent_names = (const char *[]){ "axi_clk_src" },
1830                         .num_parents = 1,
1831                         .flags = CLK_SET_RATE_PARENT,
1832                         .ops = &clk_branch2_ops,
1833                 },
1834         },
1835 };
1836
1837 static struct clk_branch mdss_pclk0_clk = {
1838         .halt_reg = 0x2314,
1839         .clkr = {
1840                 .enable_reg = 0x2314,
1841                 .enable_mask = BIT(0),
1842                 .hw.init = &(struct clk_init_data){
1843                         .name = "mdss_pclk0_clk",
1844                         .parent_names = (const char *[]){ "pclk0_clk_src" },
1845                         .num_parents = 1,
1846                         .flags = CLK_SET_RATE_PARENT,
1847                         .ops = &clk_branch2_ops,
1848                 },
1849         },
1850 };
1851
1852 static struct clk_branch mdss_pclk1_clk = {
1853         .halt_reg = 0x2318,
1854         .clkr = {
1855                 .enable_reg = 0x2318,
1856                 .enable_mask = BIT(0),
1857                 .hw.init = &(struct clk_init_data){
1858                         .name = "mdss_pclk1_clk",
1859                         .parent_names = (const char *[]){ "pclk1_clk_src" },
1860                         .num_parents = 1,
1861                         .flags = CLK_SET_RATE_PARENT,
1862                         .ops = &clk_branch2_ops,
1863                 },
1864         },
1865 };
1866
1867 static struct clk_branch mdss_mdp_clk = {
1868         .halt_reg = 0x231c,
1869         .clkr = {
1870                 .enable_reg = 0x231c,
1871                 .enable_mask = BIT(0),
1872                 .hw.init = &(struct clk_init_data){
1873                         .name = "mdss_mdp_clk",
1874                         .parent_names = (const char *[]){ "mdp_clk_src" },
1875                         .num_parents = 1,
1876                         .flags = CLK_SET_RATE_PARENT,
1877                         .ops = &clk_branch2_ops,
1878                 },
1879         },
1880 };
1881
1882 static struct clk_branch mdss_extpclk_clk = {
1883         .halt_reg = 0x2324,
1884         .clkr = {
1885                 .enable_reg = 0x2324,
1886                 .enable_mask = BIT(0),
1887                 .hw.init = &(struct clk_init_data){
1888                         .name = "mdss_extpclk_clk",
1889                         .parent_names = (const char *[]){ "extpclk_clk_src" },
1890                         .num_parents = 1,
1891                         .flags = CLK_SET_RATE_PARENT,
1892                         .ops = &clk_branch2_ops,
1893                 },
1894         },
1895 };
1896
1897 static struct clk_branch mdss_vsync_clk = {
1898         .halt_reg = 0x2328,
1899         .clkr = {
1900                 .enable_reg = 0x2328,
1901                 .enable_mask = BIT(0),
1902                 .hw.init = &(struct clk_init_data){
1903                         .name = "mdss_vsync_clk",
1904                         .parent_names = (const char *[]){ "vsync_clk_src" },
1905                         .num_parents = 1,
1906                         .flags = CLK_SET_RATE_PARENT,
1907                         .ops = &clk_branch2_ops,
1908                 },
1909         },
1910 };
1911
1912 static struct clk_branch mdss_hdmi_clk = {
1913         .halt_reg = 0x2338,
1914         .clkr = {
1915                 .enable_reg = 0x2338,
1916                 .enable_mask = BIT(0),
1917                 .hw.init = &(struct clk_init_data){
1918                         .name = "mdss_hdmi_clk",
1919                         .parent_names = (const char *[]){ "hdmi_clk_src" },
1920                         .num_parents = 1,
1921                         .flags = CLK_SET_RATE_PARENT,
1922                         .ops = &clk_branch2_ops,
1923                 },
1924         },
1925 };
1926
1927 static struct clk_branch mdss_byte0_clk = {
1928         .halt_reg = 0x233c,
1929         .clkr = {
1930                 .enable_reg = 0x233c,
1931                 .enable_mask = BIT(0),
1932                 .hw.init = &(struct clk_init_data){
1933                         .name = "mdss_byte0_clk",
1934                         .parent_names = (const char *[]){ "byte0_clk_src" },
1935                         .num_parents = 1,
1936                         .flags = CLK_SET_RATE_PARENT,
1937                         .ops = &clk_branch2_ops,
1938                 },
1939         },
1940 };
1941
1942 static struct clk_branch mdss_byte1_clk = {
1943         .halt_reg = 0x2340,
1944         .clkr = {
1945                 .enable_reg = 0x2340,
1946                 .enable_mask = BIT(0),
1947                 .hw.init = &(struct clk_init_data){
1948                         .name = "mdss_byte1_clk",
1949                         .parent_names = (const char *[]){ "byte1_clk_src" },
1950                         .num_parents = 1,
1951                         .flags = CLK_SET_RATE_PARENT,
1952                         .ops = &clk_branch2_ops,
1953                 },
1954         },
1955 };
1956
1957 static struct clk_branch mdss_esc0_clk = {
1958         .halt_reg = 0x2344,
1959         .clkr = {
1960                 .enable_reg = 0x2344,
1961                 .enable_mask = BIT(0),
1962                 .hw.init = &(struct clk_init_data){
1963                         .name = "mdss_esc0_clk",
1964                         .parent_names = (const char *[]){ "esc0_clk_src" },
1965                         .num_parents = 1,
1966                         .flags = CLK_SET_RATE_PARENT,
1967                         .ops = &clk_branch2_ops,
1968                 },
1969         },
1970 };
1971
1972 static struct clk_branch mdss_esc1_clk = {
1973         .halt_reg = 0x2348,
1974         .clkr = {
1975                 .enable_reg = 0x2348,
1976                 .enable_mask = BIT(0),
1977                 .hw.init = &(struct clk_init_data){
1978                         .name = "mdss_esc1_clk",
1979                         .parent_names = (const char *[]){ "esc1_clk_src" },
1980                         .num_parents = 1,
1981                         .flags = CLK_SET_RATE_PARENT,
1982                         .ops = &clk_branch2_ops,
1983                 },
1984         },
1985 };
1986
1987 static struct clk_branch camss_top_ahb_clk = {
1988         .halt_reg = 0x3484,
1989         .clkr = {
1990                 .enable_reg = 0x3484,
1991                 .enable_mask = BIT(0),
1992                 .hw.init = &(struct clk_init_data){
1993                         .name = "camss_top_ahb_clk",
1994                         .parent_names = (const char *[]){ "ahb_clk_src" },
1995                         .num_parents = 1,
1996                         .flags = CLK_SET_RATE_PARENT,
1997                         .ops = &clk_branch2_ops,
1998                 },
1999         },
2000 };
2001
2002 static struct clk_branch camss_ahb_clk = {
2003         .halt_reg = 0x348c,
2004         .clkr = {
2005                 .enable_reg = 0x348c,
2006                 .enable_mask = BIT(0),
2007                 .hw.init = &(struct clk_init_data){
2008                         .name = "camss_ahb_clk",
2009                         .parent_names = (const char *[]){ "ahb_clk_src" },
2010                         .num_parents = 1,
2011                         .flags = CLK_SET_RATE_PARENT,
2012                         .ops = &clk_branch2_ops,
2013                 },
2014         },
2015 };
2016
2017 static struct clk_branch camss_micro_ahb_clk = {
2018         .halt_reg = 0x3494,
2019         .clkr = {
2020                 .enable_reg = 0x3494,
2021                 .enable_mask = BIT(0),
2022                 .hw.init = &(struct clk_init_data){
2023                         .name = "camss_micro_ahb_clk",
2024                         .parent_names = (const char *[]){ "ahb_clk_src" },
2025                         .num_parents = 1,
2026                         .flags = CLK_SET_RATE_PARENT,
2027                         .ops = &clk_branch2_ops,
2028                 },
2029         },
2030 };
2031
2032 static struct clk_branch camss_gp0_clk = {
2033         .halt_reg = 0x3444,
2034         .clkr = {
2035                 .enable_reg = 0x3444,
2036                 .enable_mask = BIT(0),
2037                 .hw.init = &(struct clk_init_data){
2038                         .name = "camss_gp0_clk",
2039                         .parent_names = (const char *[]){ "camss_gp0_clk_src" },
2040                         .num_parents = 1,
2041                         .flags = CLK_SET_RATE_PARENT,
2042                         .ops = &clk_branch2_ops,
2043                 },
2044         },
2045 };
2046
2047 static struct clk_branch camss_gp1_clk = {
2048         .halt_reg = 0x3474,
2049         .clkr = {
2050                 .enable_reg = 0x3474,
2051                 .enable_mask = BIT(0),
2052                 .hw.init = &(struct clk_init_data){
2053                         .name = "camss_gp1_clk",
2054                         .parent_names = (const char *[]){ "camss_gp1_clk_src" },
2055                         .num_parents = 1,
2056                         .flags = CLK_SET_RATE_PARENT,
2057                         .ops = &clk_branch2_ops,
2058                 },
2059         },
2060 };
2061
2062 static struct clk_branch camss_mclk0_clk = {
2063         .halt_reg = 0x3384,
2064         .clkr = {
2065                 .enable_reg = 0x3384,
2066                 .enable_mask = BIT(0),
2067                 .hw.init = &(struct clk_init_data){
2068                         .name = "camss_mclk0_clk",
2069                         .parent_names = (const char *[]){ "mclk0_clk_src" },
2070                         .num_parents = 1,
2071                         .flags = CLK_SET_RATE_PARENT,
2072                         .ops = &clk_branch2_ops,
2073                 },
2074         },
2075 };
2076
2077 static struct clk_branch camss_mclk1_clk = {
2078         .halt_reg = 0x33b4,
2079         .clkr = {
2080                 .enable_reg = 0x33b4,
2081                 .enable_mask = BIT(0),
2082                 .hw.init = &(struct clk_init_data){
2083                         .name = "camss_mclk1_clk",
2084                         .parent_names = (const char *[]){ "mclk1_clk_src" },
2085                         .num_parents = 1,
2086                         .flags = CLK_SET_RATE_PARENT,
2087                         .ops = &clk_branch2_ops,
2088                 },
2089         },
2090 };
2091
2092 static struct clk_branch camss_mclk2_clk = {
2093         .halt_reg = 0x33e4,
2094         .clkr = {
2095                 .enable_reg = 0x33e4,
2096                 .enable_mask = BIT(0),
2097                 .hw.init = &(struct clk_init_data){
2098                         .name = "camss_mclk2_clk",
2099                         .parent_names = (const char *[]){ "mclk2_clk_src" },
2100                         .num_parents = 1,
2101                         .flags = CLK_SET_RATE_PARENT,
2102                         .ops = &clk_branch2_ops,
2103                 },
2104         },
2105 };
2106
2107 static struct clk_branch camss_mclk3_clk = {
2108         .halt_reg = 0x3414,
2109         .clkr = {
2110                 .enable_reg = 0x3414,
2111                 .enable_mask = BIT(0),
2112                 .hw.init = &(struct clk_init_data){
2113                         .name = "camss_mclk3_clk",
2114                         .parent_names = (const char *[]){ "mclk3_clk_src" },
2115                         .num_parents = 1,
2116                         .flags = CLK_SET_RATE_PARENT,
2117                         .ops = &clk_branch2_ops,
2118                 },
2119         },
2120 };
2121
2122 static struct clk_branch camss_cci_clk = {
2123         .halt_reg = 0x3344,
2124         .clkr = {
2125                 .enable_reg = 0x3344,
2126                 .enable_mask = BIT(0),
2127                 .hw.init = &(struct clk_init_data){
2128                         .name = "camss_cci_clk",
2129                         .parent_names = (const char *[]){ "cci_clk_src" },
2130                         .num_parents = 1,
2131                         .flags = CLK_SET_RATE_PARENT,
2132                         .ops = &clk_branch2_ops,
2133                 },
2134         },
2135 };
2136
2137 static struct clk_branch camss_cci_ahb_clk = {
2138         .halt_reg = 0x3348,
2139         .clkr = {
2140                 .enable_reg = 0x3348,
2141                 .enable_mask = BIT(0),
2142                 .hw.init = &(struct clk_init_data){
2143                         .name = "camss_cci_ahb_clk",
2144                         .parent_names = (const char *[]){ "ahb_clk_src" },
2145                         .num_parents = 1,
2146                         .flags = CLK_SET_RATE_PARENT,
2147                         .ops = &clk_branch2_ops,
2148                 },
2149         },
2150 };
2151
2152 static struct clk_branch camss_csi0phytimer_clk = {
2153         .halt_reg = 0x3024,
2154         .clkr = {
2155                 .enable_reg = 0x3024,
2156                 .enable_mask = BIT(0),
2157                 .hw.init = &(struct clk_init_data){
2158                         .name = "camss_csi0phytimer_clk",
2159                         .parent_names = (const char *[]){ "csi0phytimer_clk_src" },
2160                         .num_parents = 1,
2161                         .flags = CLK_SET_RATE_PARENT,
2162                         .ops = &clk_branch2_ops,
2163                 },
2164         },
2165 };
2166
2167 static struct clk_branch camss_csi1phytimer_clk = {
2168         .halt_reg = 0x3054,
2169         .clkr = {
2170                 .enable_reg = 0x3054,
2171                 .enable_mask = BIT(0),
2172                 .hw.init = &(struct clk_init_data){
2173                         .name = "camss_csi1phytimer_clk",
2174                         .parent_names = (const char *[]){ "csi1phytimer_clk_src" },
2175                         .num_parents = 1,
2176                         .flags = CLK_SET_RATE_PARENT,
2177                         .ops = &clk_branch2_ops,
2178                 },
2179         },
2180 };
2181
2182 static struct clk_branch camss_csi2phytimer_clk = {
2183         .halt_reg = 0x3084,
2184         .clkr = {
2185                 .enable_reg = 0x3084,
2186                 .enable_mask = BIT(0),
2187                 .hw.init = &(struct clk_init_data){
2188                         .name = "camss_csi2phytimer_clk",
2189                         .parent_names = (const char *[]){ "csi2phytimer_clk_src" },
2190                         .num_parents = 1,
2191                         .flags = CLK_SET_RATE_PARENT,
2192                         .ops = &clk_branch2_ops,
2193                 },
2194         },
2195 };
2196
2197 static struct clk_branch camss_csiphy0_3p_clk = {
2198         .halt_reg = 0x3234,
2199         .clkr = {
2200                 .enable_reg = 0x3234,
2201                 .enable_mask = BIT(0),
2202                 .hw.init = &(struct clk_init_data){
2203                         .name = "camss_csiphy0_3p_clk",
2204                         .parent_names = (const char *[]){ "csiphy0_3p_clk_src" },
2205                         .num_parents = 1,
2206                         .flags = CLK_SET_RATE_PARENT,
2207                         .ops = &clk_branch2_ops,
2208                 },
2209         },
2210 };
2211
2212 static struct clk_branch camss_csiphy1_3p_clk = {
2213         .halt_reg = 0x3254,
2214         .clkr = {
2215                 .enable_reg = 0x3254,
2216                 .enable_mask = BIT(0),
2217                 .hw.init = &(struct clk_init_data){
2218                         .name = "camss_csiphy1_3p_clk",
2219                         .parent_names = (const char *[]){ "csiphy1_3p_clk_src" },
2220                         .num_parents = 1,
2221                         .flags = CLK_SET_RATE_PARENT,
2222                         .ops = &clk_branch2_ops,
2223                 },
2224         },
2225 };
2226
2227 static struct clk_branch camss_csiphy2_3p_clk = {
2228         .halt_reg = 0x3274,
2229         .clkr = {
2230                 .enable_reg = 0x3274,
2231                 .enable_mask = BIT(0),
2232                 .hw.init = &(struct clk_init_data){
2233                         .name = "camss_csiphy2_3p_clk",
2234                         .parent_names = (const char *[]){ "csiphy2_3p_clk_src" },
2235                         .num_parents = 1,
2236                         .flags = CLK_SET_RATE_PARENT,
2237                         .ops = &clk_branch2_ops,
2238                 },
2239         },
2240 };
2241
2242 static struct clk_branch camss_jpeg0_clk = {
2243         .halt_reg = 0x35a8,
2244         .clkr = {
2245                 .enable_reg = 0x35a8,
2246                 .enable_mask = BIT(0),
2247                 .hw.init = &(struct clk_init_data){
2248                         .name = "camss_jpeg0_clk",
2249                         .parent_names = (const char *[]){ "jpeg0_clk_src" },
2250                         .num_parents = 1,
2251                         .flags = CLK_SET_RATE_PARENT,
2252                         .ops = &clk_branch2_ops,
2253                 },
2254         },
2255 };
2256
2257 static struct clk_branch camss_jpeg2_clk = {
2258         .halt_reg = 0x35b0,
2259         .clkr = {
2260                 .enable_reg = 0x35b0,
2261                 .enable_mask = BIT(0),
2262                 .hw.init = &(struct clk_init_data){
2263                         .name = "camss_jpeg2_clk",
2264                         .parent_names = (const char *[]){ "jpeg2_clk_src" },
2265                         .num_parents = 1,
2266                         .flags = CLK_SET_RATE_PARENT,
2267                         .ops = &clk_branch2_ops,
2268                 },
2269         },
2270 };
2271
2272 static struct clk_branch camss_jpeg_dma_clk = {
2273         .halt_reg = 0x35c0,
2274         .clkr = {
2275                 .enable_reg = 0x35c0,
2276                 .enable_mask = BIT(0),
2277                 .hw.init = &(struct clk_init_data){
2278                         .name = "camss_jpeg_dma_clk",
2279                         .parent_names = (const char *[]){ "jpeg_dma_clk_src" },
2280                         .num_parents = 1,
2281                         .flags = CLK_SET_RATE_PARENT,
2282                         .ops = &clk_branch2_ops,
2283                 },
2284         },
2285 };
2286
2287 static struct clk_branch camss_jpeg_ahb_clk = {
2288         .halt_reg = 0x35b4,
2289         .clkr = {
2290                 .enable_reg = 0x35b4,
2291                 .enable_mask = BIT(0),
2292                 .hw.init = &(struct clk_init_data){
2293                         .name = "camss_jpeg_ahb_clk",
2294                         .parent_names = (const char *[]){ "ahb_clk_src" },
2295                         .num_parents = 1,
2296                         .flags = CLK_SET_RATE_PARENT,
2297                         .ops = &clk_branch2_ops,
2298                 },
2299         },
2300 };
2301
2302 static struct clk_branch camss_jpeg_axi_clk = {
2303         .halt_reg = 0x35b8,
2304         .clkr = {
2305                 .enable_reg = 0x35b8,
2306                 .enable_mask = BIT(0),
2307                 .hw.init = &(struct clk_init_data){
2308                         .name = "camss_jpeg_axi_clk",
2309                         .parent_names = (const char *[]){ "axi_clk_src" },
2310                         .num_parents = 1,
2311                         .flags = CLK_SET_RATE_PARENT,
2312                         .ops = &clk_branch2_ops,
2313                 },
2314         },
2315 };
2316
2317 static struct clk_branch camss_vfe_ahb_clk = {
2318         .halt_reg = 0x36b8,
2319         .clkr = {
2320                 .enable_reg = 0x36b8,
2321                 .enable_mask = BIT(0),
2322                 .hw.init = &(struct clk_init_data){
2323                         .name = "camss_vfe_ahb_clk",
2324                         .parent_names = (const char *[]){ "ahb_clk_src" },
2325                         .num_parents = 1,
2326                         .flags = CLK_SET_RATE_PARENT,
2327                         .ops = &clk_branch2_ops,
2328                 },
2329         },
2330 };
2331
2332 static struct clk_branch camss_vfe_axi_clk = {
2333         .halt_reg = 0x36bc,
2334         .clkr = {
2335                 .enable_reg = 0x36bc,
2336                 .enable_mask = BIT(0),
2337                 .hw.init = &(struct clk_init_data){
2338                         .name = "camss_vfe_axi_clk",
2339                         .parent_names = (const char *[]){ "axi_clk_src" },
2340                         .num_parents = 1,
2341                         .flags = CLK_SET_RATE_PARENT,
2342                         .ops = &clk_branch2_ops,
2343                 },
2344         },
2345 };
2346
2347 static struct clk_branch camss_vfe0_clk = {
2348         .halt_reg = 0x36a8,
2349         .clkr = {
2350                 .enable_reg = 0x36a8,
2351                 .enable_mask = BIT(0),
2352                 .hw.init = &(struct clk_init_data){
2353                         .name = "camss_vfe0_clk",
2354                         .parent_names = (const char *[]){ "vfe0_clk_src" },
2355                         .num_parents = 1,
2356                         .flags = CLK_SET_RATE_PARENT,
2357                         .ops = &clk_branch2_ops,
2358                 },
2359         },
2360 };
2361
2362 static struct clk_branch camss_vfe0_stream_clk = {
2363         .halt_reg = 0x3720,
2364         .clkr = {
2365                 .enable_reg = 0x3720,
2366                 .enable_mask = BIT(0),
2367                 .hw.init = &(struct clk_init_data){
2368                         .name = "camss_vfe0_stream_clk",
2369                         .parent_names = (const char *[]){ "vfe0_clk_src" },
2370                         .num_parents = 1,
2371                         .flags = CLK_SET_RATE_PARENT,
2372                         .ops = &clk_branch2_ops,
2373                 },
2374         },
2375 };
2376
2377 static struct clk_branch camss_vfe0_ahb_clk = {
2378         .halt_reg = 0x3668,
2379         .clkr = {
2380                 .enable_reg = 0x3668,
2381                 .enable_mask = BIT(0),
2382                 .hw.init = &(struct clk_init_data){
2383                         .name = "camss_vfe0_ahb_clk",
2384                         .parent_names = (const char *[]){ "ahb_clk_src" },
2385                         .num_parents = 1,
2386                         .flags = CLK_SET_RATE_PARENT,
2387                         .ops = &clk_branch2_ops,
2388                 },
2389         },
2390 };
2391
2392 static struct clk_branch camss_vfe1_clk = {
2393         .halt_reg = 0x36ac,
2394         .clkr = {
2395                 .enable_reg = 0x36ac,
2396                 .enable_mask = BIT(0),
2397                 .hw.init = &(struct clk_init_data){
2398                         .name = "camss_vfe1_clk",
2399                         .parent_names = (const char *[]){ "vfe1_clk_src" },
2400                         .num_parents = 1,
2401                         .flags = CLK_SET_RATE_PARENT,
2402                         .ops = &clk_branch2_ops,
2403                 },
2404         },
2405 };
2406
2407 static struct clk_branch camss_vfe1_stream_clk = {
2408         .halt_reg = 0x3724,
2409         .clkr = {
2410                 .enable_reg = 0x3724,
2411                 .enable_mask = BIT(0),
2412                 .hw.init = &(struct clk_init_data){
2413                         .name = "camss_vfe1_stream_clk",
2414                         .parent_names = (const char *[]){ "vfe1_clk_src" },
2415                         .num_parents = 1,
2416                         .flags = CLK_SET_RATE_PARENT,
2417                         .ops = &clk_branch2_ops,
2418                 },
2419         },
2420 };
2421
2422 static struct clk_branch camss_vfe1_ahb_clk = {
2423         .halt_reg = 0x3678,
2424         .clkr = {
2425                 .enable_reg = 0x3678,
2426                 .enable_mask = BIT(0),
2427                 .hw.init = &(struct clk_init_data){
2428                         .name = "camss_vfe1_ahb_clk",
2429                         .parent_names = (const char *[]){ "ahb_clk_src" },
2430                         .num_parents = 1,
2431                         .flags = CLK_SET_RATE_PARENT,
2432                         .ops = &clk_branch2_ops,
2433                 },
2434         },
2435 };
2436
2437 static struct clk_branch camss_csi_vfe0_clk = {
2438         .halt_reg = 0x3704,
2439         .clkr = {
2440                 .enable_reg = 0x3704,
2441                 .enable_mask = BIT(0),
2442                 .hw.init = &(struct clk_init_data){
2443                         .name = "camss_csi_vfe0_clk",
2444                         .parent_names = (const char *[]){ "vfe0_clk_src" },
2445                         .num_parents = 1,
2446                         .flags = CLK_SET_RATE_PARENT,
2447                         .ops = &clk_branch2_ops,
2448                 },
2449         },
2450 };
2451
2452 static struct clk_branch camss_csi_vfe1_clk = {
2453         .halt_reg = 0x3714,
2454         .clkr = {
2455                 .enable_reg = 0x3714,
2456                 .enable_mask = BIT(0),
2457                 .hw.init = &(struct clk_init_data){
2458                         .name = "camss_csi_vfe1_clk",
2459                         .parent_names = (const char *[]){ "vfe1_clk_src" },
2460                         .num_parents = 1,
2461                         .flags = CLK_SET_RATE_PARENT,
2462                         .ops = &clk_branch2_ops,
2463                 },
2464         },
2465 };
2466
2467 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2468         .halt_reg = 0x36c8,
2469         .clkr = {
2470                 .enable_reg = 0x36c8,
2471                 .enable_mask = BIT(0),
2472                 .hw.init = &(struct clk_init_data){
2473                         .name = "camss_cpp_vbif_ahb_clk",
2474                         .parent_names = (const char *[]){ "ahb_clk_src" },
2475                         .num_parents = 1,
2476                         .flags = CLK_SET_RATE_PARENT,
2477                         .ops = &clk_branch2_ops,
2478                 },
2479         },
2480 };
2481
2482 static struct clk_branch camss_cpp_axi_clk = {
2483         .halt_reg = 0x36c4,
2484         .clkr = {
2485                 .enable_reg = 0x36c4,
2486                 .enable_mask = BIT(0),
2487                 .hw.init = &(struct clk_init_data){
2488                         .name = "camss_cpp_axi_clk",
2489                         .parent_names = (const char *[]){ "axi_clk_src" },
2490                         .num_parents = 1,
2491                         .flags = CLK_SET_RATE_PARENT,
2492                         .ops = &clk_branch2_ops,
2493                 },
2494         },
2495 };
2496
2497 static struct clk_branch camss_cpp_clk = {
2498         .halt_reg = 0x36b0,
2499         .clkr = {
2500                 .enable_reg = 0x36b0,
2501                 .enable_mask = BIT(0),
2502                 .hw.init = &(struct clk_init_data){
2503                         .name = "camss_cpp_clk",
2504                         .parent_names = (const char *[]){ "cpp_clk_src" },
2505                         .num_parents = 1,
2506                         .flags = CLK_SET_RATE_PARENT,
2507                         .ops = &clk_branch2_ops,
2508                 },
2509         },
2510 };
2511
2512 static struct clk_branch camss_cpp_ahb_clk = {
2513         .halt_reg = 0x36b4,
2514         .clkr = {
2515                 .enable_reg = 0x36b4,
2516                 .enable_mask = BIT(0),
2517                 .hw.init = &(struct clk_init_data){
2518                         .name = "camss_cpp_ahb_clk",
2519                         .parent_names = (const char *[]){ "ahb_clk_src" },
2520                         .num_parents = 1,
2521                         .flags = CLK_SET_RATE_PARENT,
2522                         .ops = &clk_branch2_ops,
2523                 },
2524         },
2525 };
2526
2527 static struct clk_branch camss_csi0_clk = {
2528         .halt_reg = 0x30b4,
2529         .clkr = {
2530                 .enable_reg = 0x30b4,
2531                 .enable_mask = BIT(0),
2532                 .hw.init = &(struct clk_init_data){
2533                         .name = "camss_csi0_clk",
2534                         .parent_names = (const char *[]){ "csi0_clk_src" },
2535                         .num_parents = 1,
2536                         .flags = CLK_SET_RATE_PARENT,
2537                         .ops = &clk_branch2_ops,
2538                 },
2539         },
2540 };
2541
2542 static struct clk_branch camss_csi0_ahb_clk = {
2543         .halt_reg = 0x30bc,
2544         .clkr = {
2545                 .enable_reg = 0x30bc,
2546                 .enable_mask = BIT(0),
2547                 .hw.init = &(struct clk_init_data){
2548                         .name = "camss_csi0_ahb_clk",
2549                         .parent_names = (const char *[]){ "ahb_clk_src" },
2550                         .num_parents = 1,
2551                         .flags = CLK_SET_RATE_PARENT,
2552                         .ops = &clk_branch2_ops,
2553                 },
2554         },
2555 };
2556
2557 static struct clk_branch camss_csi0phy_clk = {
2558         .halt_reg = 0x30c4,
2559         .clkr = {
2560                 .enable_reg = 0x30c4,
2561                 .enable_mask = BIT(0),
2562                 .hw.init = &(struct clk_init_data){
2563                         .name = "camss_csi0phy_clk",
2564                         .parent_names = (const char *[]){ "csi0_clk_src" },
2565                         .num_parents = 1,
2566                         .flags = CLK_SET_RATE_PARENT,
2567                         .ops = &clk_branch2_ops,
2568                 },
2569         },
2570 };
2571
2572 static struct clk_branch camss_csi0rdi_clk = {
2573         .halt_reg = 0x30d4,
2574         .clkr = {
2575                 .enable_reg = 0x30d4,
2576                 .enable_mask = BIT(0),
2577                 .hw.init = &(struct clk_init_data){
2578                         .name = "camss_csi0rdi_clk",
2579                         .parent_names = (const char *[]){ "csi0_clk_src" },
2580                         .num_parents = 1,
2581                         .flags = CLK_SET_RATE_PARENT,
2582                         .ops = &clk_branch2_ops,
2583                 },
2584         },
2585 };
2586
2587 static struct clk_branch camss_csi0pix_clk = {
2588         .halt_reg = 0x30e4,
2589         .clkr = {
2590                 .enable_reg = 0x30e4,
2591                 .enable_mask = BIT(0),
2592                 .hw.init = &(struct clk_init_data){
2593                         .name = "camss_csi0pix_clk",
2594                         .parent_names = (const char *[]){ "csi0_clk_src" },
2595                         .num_parents = 1,
2596                         .flags = CLK_SET_RATE_PARENT,
2597                         .ops = &clk_branch2_ops,
2598                 },
2599         },
2600 };
2601
2602 static struct clk_branch camss_csi1_clk = {
2603         .halt_reg = 0x3124,
2604         .clkr = {
2605                 .enable_reg = 0x3124,
2606                 .enable_mask = BIT(0),
2607                 .hw.init = &(struct clk_init_data){
2608                         .name = "camss_csi1_clk",
2609                         .parent_names = (const char *[]){ "csi1_clk_src" },
2610                         .num_parents = 1,
2611                         .flags = CLK_SET_RATE_PARENT,
2612                         .ops = &clk_branch2_ops,
2613                 },
2614         },
2615 };
2616
2617 static struct clk_branch camss_csi1_ahb_clk = {
2618         .halt_reg = 0x3128,
2619         .clkr = {
2620                 .enable_reg = 0x3128,
2621                 .enable_mask = BIT(0),
2622                 .hw.init = &(struct clk_init_data){
2623                         .name = "camss_csi1_ahb_clk",
2624                         .parent_names = (const char *[]){ "ahb_clk_src" },
2625                         .num_parents = 1,
2626                         .flags = CLK_SET_RATE_PARENT,
2627                         .ops = &clk_branch2_ops,
2628                 },
2629         },
2630 };
2631
2632 static struct clk_branch camss_csi1phy_clk = {
2633         .halt_reg = 0x3134,
2634         .clkr = {
2635                 .enable_reg = 0x3134,
2636                 .enable_mask = BIT(0),
2637                 .hw.init = &(struct clk_init_data){
2638                         .name = "camss_csi1phy_clk",
2639                         .parent_names = (const char *[]){ "csi1_clk_src" },
2640                         .num_parents = 1,
2641                         .flags = CLK_SET_RATE_PARENT,
2642                         .ops = &clk_branch2_ops,
2643                 },
2644         },
2645 };
2646
2647 static struct clk_branch camss_csi1rdi_clk = {
2648         .halt_reg = 0x3144,
2649         .clkr = {
2650                 .enable_reg = 0x3144,
2651                 .enable_mask = BIT(0),
2652                 .hw.init = &(struct clk_init_data){
2653                         .name = "camss_csi1rdi_clk",
2654                         .parent_names = (const char *[]){ "csi1_clk_src" },
2655                         .num_parents = 1,
2656                         .flags = CLK_SET_RATE_PARENT,
2657                         .ops = &clk_branch2_ops,
2658                 },
2659         },
2660 };
2661
2662 static struct clk_branch camss_csi1pix_clk = {
2663         .halt_reg = 0x3154,
2664         .clkr = {
2665                 .enable_reg = 0x3154,
2666                 .enable_mask = BIT(0),
2667                 .hw.init = &(struct clk_init_data){
2668                         .name = "camss_csi1pix_clk",
2669                         .parent_names = (const char *[]){ "csi1_clk_src" },
2670                         .num_parents = 1,
2671                         .flags = CLK_SET_RATE_PARENT,
2672                         .ops = &clk_branch2_ops,
2673                 },
2674         },
2675 };
2676
2677 static struct clk_branch camss_csi2_clk = {
2678         .halt_reg = 0x3184,
2679         .clkr = {
2680                 .enable_reg = 0x3184,
2681                 .enable_mask = BIT(0),
2682                 .hw.init = &(struct clk_init_data){
2683                         .name = "camss_csi2_clk",
2684                         .parent_names = (const char *[]){ "csi2_clk_src" },
2685                         .num_parents = 1,
2686                         .flags = CLK_SET_RATE_PARENT,
2687                         .ops = &clk_branch2_ops,
2688                 },
2689         },
2690 };
2691
2692 static struct clk_branch camss_csi2_ahb_clk = {
2693         .halt_reg = 0x3188,
2694         .clkr = {
2695                 .enable_reg = 0x3188,
2696                 .enable_mask = BIT(0),
2697                 .hw.init = &(struct clk_init_data){
2698                         .name = "camss_csi2_ahb_clk",
2699                         .parent_names = (const char *[]){ "ahb_clk_src" },
2700                         .num_parents = 1,
2701                         .flags = CLK_SET_RATE_PARENT,
2702                         .ops = &clk_branch2_ops,
2703                 },
2704         },
2705 };
2706
2707 static struct clk_branch camss_csi2phy_clk = {
2708         .halt_reg = 0x3194,
2709         .clkr = {
2710                 .enable_reg = 0x3194,
2711                 .enable_mask = BIT(0),
2712                 .hw.init = &(struct clk_init_data){
2713                         .name = "camss_csi2phy_clk",
2714                         .parent_names = (const char *[]){ "csi2_clk_src" },
2715                         .num_parents = 1,
2716                         .flags = CLK_SET_RATE_PARENT,
2717                         .ops = &clk_branch2_ops,
2718                 },
2719         },
2720 };
2721
2722 static struct clk_branch camss_csi2rdi_clk = {
2723         .halt_reg = 0x31a4,
2724         .clkr = {
2725                 .enable_reg = 0x31a4,
2726                 .enable_mask = BIT(0),
2727                 .hw.init = &(struct clk_init_data){
2728                         .name = "camss_csi2rdi_clk",
2729                         .parent_names = (const char *[]){ "csi2_clk_src" },
2730                         .num_parents = 1,
2731                         .flags = CLK_SET_RATE_PARENT,
2732                         .ops = &clk_branch2_ops,
2733                 },
2734         },
2735 };
2736
2737 static struct clk_branch camss_csi2pix_clk = {
2738         .halt_reg = 0x31b4,
2739         .clkr = {
2740                 .enable_reg = 0x31b4,
2741                 .enable_mask = BIT(0),
2742                 .hw.init = &(struct clk_init_data){
2743                         .name = "camss_csi2pix_clk",
2744                         .parent_names = (const char *[]){ "csi2_clk_src" },
2745                         .num_parents = 1,
2746                         .flags = CLK_SET_RATE_PARENT,
2747                         .ops = &clk_branch2_ops,
2748                 },
2749         },
2750 };
2751
2752 static struct clk_branch camss_csi3_clk = {
2753         .halt_reg = 0x31e4,
2754         .clkr = {
2755                 .enable_reg = 0x31e4,
2756                 .enable_mask = BIT(0),
2757                 .hw.init = &(struct clk_init_data){
2758                         .name = "camss_csi3_clk",
2759                         .parent_names = (const char *[]){ "csi3_clk_src" },
2760                         .num_parents = 1,
2761                         .flags = CLK_SET_RATE_PARENT,
2762                         .ops = &clk_branch2_ops,
2763                 },
2764         },
2765 };
2766
2767 static struct clk_branch camss_csi3_ahb_clk = {
2768         .halt_reg = 0x31e8,
2769         .clkr = {
2770                 .enable_reg = 0x31e8,
2771                 .enable_mask = BIT(0),
2772                 .hw.init = &(struct clk_init_data){
2773                         .name = "camss_csi3_ahb_clk",
2774                         .parent_names = (const char *[]){ "ahb_clk_src" },
2775                         .num_parents = 1,
2776                         .flags = CLK_SET_RATE_PARENT,
2777                         .ops = &clk_branch2_ops,
2778                 },
2779         },
2780 };
2781
2782 static struct clk_branch camss_csi3phy_clk = {
2783         .halt_reg = 0x31f4,
2784         .clkr = {
2785                 .enable_reg = 0x31f4,
2786                 .enable_mask = BIT(0),
2787                 .hw.init = &(struct clk_init_data){
2788                         .name = "camss_csi3phy_clk",
2789                         .parent_names = (const char *[]){ "csi3_clk_src" },
2790                         .num_parents = 1,
2791                         .flags = CLK_SET_RATE_PARENT,
2792                         .ops = &clk_branch2_ops,
2793                 },
2794         },
2795 };
2796
2797 static struct clk_branch camss_csi3rdi_clk = {
2798         .halt_reg = 0x3204,
2799         .clkr = {
2800                 .enable_reg = 0x3204,
2801                 .enable_mask = BIT(0),
2802                 .hw.init = &(struct clk_init_data){
2803                         .name = "camss_csi3rdi_clk",
2804                         .parent_names = (const char *[]){ "csi3_clk_src" },
2805                         .num_parents = 1,
2806                         .flags = CLK_SET_RATE_PARENT,
2807                         .ops = &clk_branch2_ops,
2808                 },
2809         },
2810 };
2811
2812 static struct clk_branch camss_csi3pix_clk = {
2813         .halt_reg = 0x3214,
2814         .clkr = {
2815                 .enable_reg = 0x3214,
2816                 .enable_mask = BIT(0),
2817                 .hw.init = &(struct clk_init_data){
2818                         .name = "camss_csi3pix_clk",
2819                         .parent_names = (const char *[]){ "csi3_clk_src" },
2820                         .num_parents = 1,
2821                         .flags = CLK_SET_RATE_PARENT,
2822                         .ops = &clk_branch2_ops,
2823                 },
2824         },
2825 };
2826
2827 static struct clk_branch camss_ispif_ahb_clk = {
2828         .halt_reg = 0x3224,
2829         .clkr = {
2830                 .enable_reg = 0x3224,
2831                 .enable_mask = BIT(0),
2832                 .hw.init = &(struct clk_init_data){
2833                         .name = "camss_ispif_ahb_clk",
2834                         .parent_names = (const char *[]){ "ahb_clk_src" },
2835                         .num_parents = 1,
2836                         .flags = CLK_SET_RATE_PARENT,
2837                         .ops = &clk_branch2_ops,
2838                 },
2839         },
2840 };
2841
2842 static struct clk_branch fd_core_clk = {
2843         .halt_reg = 0x3b68,
2844         .clkr = {
2845                 .enable_reg = 0x3b68,
2846                 .enable_mask = BIT(0),
2847                 .hw.init = &(struct clk_init_data){
2848                         .name = "fd_core_clk",
2849                         .parent_names = (const char *[]){ "fd_core_clk_src" },
2850                         .num_parents = 1,
2851                         .flags = CLK_SET_RATE_PARENT,
2852                         .ops = &clk_branch2_ops,
2853                 },
2854         },
2855 };
2856
2857 static struct clk_branch fd_core_uar_clk = {
2858         .halt_reg = 0x3b6c,
2859         .clkr = {
2860                 .enable_reg = 0x3b6c,
2861                 .enable_mask = BIT(0),
2862                 .hw.init = &(struct clk_init_data){
2863                         .name = "fd_core_uar_clk",
2864                         .parent_names = (const char *[]){ "fd_core_clk_src" },
2865                         .num_parents = 1,
2866                         .flags = CLK_SET_RATE_PARENT,
2867                         .ops = &clk_branch2_ops,
2868                 },
2869         },
2870 };
2871
2872 static struct clk_branch fd_ahb_clk = {
2873         .halt_reg = 0x3ba74,
2874         .clkr = {
2875                 .enable_reg = 0x3ba74,
2876                 .enable_mask = BIT(0),
2877                 .hw.init = &(struct clk_init_data){
2878                         .name = "fd_ahb_clk",
2879                         .parent_names = (const char *[]){ "ahb_clk_src" },
2880                         .num_parents = 1,
2881                         .flags = CLK_SET_RATE_PARENT,
2882                         .ops = &clk_branch2_ops,
2883                 },
2884         },
2885 };
2886
2887 static struct clk_hw *mmcc_msm8996_hws[] = {
2888         &gpll0_div.hw,
2889 };
2890
2891 static struct gdsc mmagic_bimc_gdsc = {
2892         .gdscr = 0x529c,
2893         .pd = {
2894                 .name = "mmagic_bimc",
2895         },
2896         .pwrsts = PWRSTS_OFF_ON,
2897 };
2898
2899 static struct gdsc mmagic_video_gdsc = {
2900         .gdscr = 0x119c,
2901         .gds_hw_ctrl = 0x120c,
2902         .pd = {
2903                 .name = "mmagic_video",
2904         },
2905         .pwrsts = PWRSTS_OFF_ON,
2906         .flags = VOTABLE,
2907 };
2908
2909 static struct gdsc mmagic_mdss_gdsc = {
2910         .gdscr = 0x247c,
2911         .gds_hw_ctrl = 0x2480,
2912         .pd = {
2913                 .name = "mmagic_mdss",
2914         },
2915         .pwrsts = PWRSTS_OFF_ON,
2916         .flags = VOTABLE,
2917 };
2918
2919 static struct gdsc mmagic_camss_gdsc = {
2920         .gdscr = 0x3c4c,
2921         .gds_hw_ctrl = 0x3c50,
2922         .pd = {
2923                 .name = "mmagic_camss",
2924         },
2925         .pwrsts = PWRSTS_OFF_ON,
2926         .flags = VOTABLE,
2927 };
2928
2929 static struct gdsc venus_gdsc = {
2930         .gdscr = 0x1024,
2931         .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2932         .cxc_count = 3,
2933         .pd = {
2934                 .name = "venus",
2935         },
2936         .parent = &mmagic_video_gdsc.pd,
2937         .pwrsts = PWRSTS_OFF_ON,
2938 };
2939
2940 static struct gdsc venus_core0_gdsc = {
2941         .gdscr = 0x1040,
2942         .cxcs = (unsigned int []){ 0x1048 },
2943         .cxc_count = 1,
2944         .pd = {
2945                 .name = "venus_core0",
2946         },
2947         .parent = &venus_gdsc.pd,
2948         .pwrsts = PWRSTS_OFF_ON,
2949         .flags = HW_CTRL,
2950 };
2951
2952 static struct gdsc venus_core1_gdsc = {
2953         .gdscr = 0x1044,
2954         .cxcs = (unsigned int []){ 0x104c },
2955         .cxc_count = 1,
2956         .pd = {
2957                 .name = "venus_core1",
2958         },
2959         .parent = &venus_gdsc.pd,
2960         .pwrsts = PWRSTS_OFF_ON,
2961         .flags = HW_CTRL,
2962 };
2963
2964 static struct gdsc camss_gdsc = {
2965         .gdscr = 0x34a0,
2966         .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
2967         .cxc_count = 2,
2968         .pd = {
2969                 .name = "camss",
2970         },
2971         .parent = &mmagic_camss_gdsc.pd,
2972         .pwrsts = PWRSTS_OFF_ON,
2973 };
2974
2975 static struct gdsc vfe0_gdsc = {
2976         .gdscr = 0x3664,
2977         .cxcs = (unsigned int []){ 0x36a8 },
2978         .cxc_count = 1,
2979         .pd = {
2980                 .name = "vfe0",
2981         },
2982         .parent = &camss_gdsc.pd,
2983         .pwrsts = PWRSTS_OFF_ON,
2984 };
2985
2986 static struct gdsc vfe1_gdsc = {
2987         .gdscr = 0x3674,
2988         .cxcs = (unsigned int []){ 0x36ac },
2989         .cxc_count = 1,
2990         .pd = {
2991                 .name = "vfe1",
2992         },
2993         .parent = &camss_gdsc.pd,
2994         .pwrsts = PWRSTS_OFF_ON,
2995 };
2996
2997 static struct gdsc jpeg_gdsc = {
2998         .gdscr = 0x35a4,
2999         .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3000         .cxc_count = 4,
3001         .pd = {
3002                 .name = "jpeg",
3003         },
3004         .parent = &camss_gdsc.pd,
3005         .pwrsts = PWRSTS_OFF_ON,
3006 };
3007
3008 static struct gdsc cpp_gdsc = {
3009         .gdscr = 0x36d4,
3010         .cxcs = (unsigned int []){ 0x36b0 },
3011         .cxc_count = 1,
3012         .pd = {
3013                 .name = "cpp",
3014         },
3015         .parent = &camss_gdsc.pd,
3016         .pwrsts = PWRSTS_OFF_ON,
3017 };
3018
3019 static struct gdsc fd_gdsc = {
3020         .gdscr = 0x3b64,
3021         .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3022         .cxc_count = 2,
3023         .pd = {
3024                 .name = "fd",
3025         },
3026         .parent = &camss_gdsc.pd,
3027         .pwrsts = PWRSTS_OFF_ON,
3028 };
3029
3030 static struct gdsc mdss_gdsc = {
3031         .gdscr = 0x2304,
3032         .cxcs = (unsigned int []){ 0x2310, 0x231c },
3033         .cxc_count = 2,
3034         .pd = {
3035                 .name = "mdss",
3036         },
3037         .parent = &mmagic_mdss_gdsc.pd,
3038         .pwrsts = PWRSTS_OFF_ON,
3039 };
3040
3041 static struct gdsc gpu_gdsc = {
3042         .gdscr = 0x4034,
3043         .gds_hw_ctrl = 0x4038,
3044         .pd = {
3045                 .name = "gpu",
3046         },
3047         .pwrsts = PWRSTS_OFF_ON,
3048         .flags = VOTABLE,
3049 };
3050
3051 static struct gdsc gpu_gx_gdsc = {
3052         .gdscr = 0x4024,
3053         .clamp_io_ctrl = 0x4300,
3054         .cxcs = (unsigned int []){ 0x4028 },
3055         .cxc_count = 1,
3056         .pd = {
3057                 .name = "gpu_gx",
3058         },
3059         .pwrsts = PWRSTS_OFF_ON,
3060         .flags = CLAMP_IO,
3061 };
3062
3063 static struct clk_regmap *mmcc_msm8996_clocks[] = {
3064         [MMPLL0_EARLY] = &mmpll0_early.clkr,
3065         [MMPLL0_PLL] = &mmpll0.clkr,
3066         [MMPLL1_EARLY] = &mmpll1_early.clkr,
3067         [MMPLL1_PLL] = &mmpll1.clkr,
3068         [MMPLL2_EARLY] = &mmpll2_early.clkr,
3069         [MMPLL2_PLL] = &mmpll2.clkr,
3070         [MMPLL3_EARLY] = &mmpll3_early.clkr,
3071         [MMPLL3_PLL] = &mmpll3.clkr,
3072         [MMPLL4_EARLY] = &mmpll4_early.clkr,
3073         [MMPLL4_PLL] = &mmpll4.clkr,
3074         [MMPLL5_EARLY] = &mmpll5_early.clkr,
3075         [MMPLL5_PLL] = &mmpll5.clkr,
3076         [MMPLL8_EARLY] = &mmpll8_early.clkr,
3077         [MMPLL8_PLL] = &mmpll8.clkr,
3078         [MMPLL9_EARLY] = &mmpll9_early.clkr,
3079         [MMPLL9_PLL] = &mmpll9.clkr,
3080         [AHB_CLK_SRC] = &ahb_clk_src.clkr,
3081         [AXI_CLK_SRC] = &axi_clk_src.clkr,
3082         [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
3083         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3084         [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3085         [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
3086         [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3087         [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
3088         [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
3089         [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
3090         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3091         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3092         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3093         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3094         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3095         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3096         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3097         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3098         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3099         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3100         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3101         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3102         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3103         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3104         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3105         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3106         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3107         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3108         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3109         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3110         [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
3111         [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
3112         [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
3113         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3114         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3115         [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
3116         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3117         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3118         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3119         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3120         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3121         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3122         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3123         [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
3124         [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
3125         [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
3126         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3127         [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
3128         [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
3129         [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
3130         [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
3131         [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
3132         [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
3133         [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
3134         [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
3135         [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
3136         [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
3137         [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
3138         [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
3139         [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
3140         [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
3141         [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
3142         [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
3143         [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
3144         [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
3145         [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
3146         [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
3147         [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
3148         [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
3149         [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
3150         [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
3151         [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
3152         [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
3153         [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
3154         [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3155         [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3156         [VIDEO_CORE_CLK] = &video_core_clk.clkr,
3157         [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
3158         [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
3159         [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
3160         [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
3161         [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
3162         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3163         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3164         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3165         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3166         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3167         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3168         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3169         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3170         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3171         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3172         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3173         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3174         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3175         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3176         [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3177         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3178         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3179         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3180         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3181         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3182         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3183         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3184         [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
3185         [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
3186         [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
3187         [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
3188         [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
3189         [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
3190         [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
3191         [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
3192         [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
3193         [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
3194         [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
3195         [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
3196         [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
3197         [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
3198         [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
3199         [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
3200         [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
3201         [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
3202         [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
3203         [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
3204         [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
3205         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3206         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3207         [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
3208         [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
3209         [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
3210         [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
3211         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3212         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3213         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3214         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3215         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3216         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3217         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3218         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3219         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3220         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3221         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3222         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3223         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3224         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3225         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3226         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3227         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3228         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3229         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3230         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3231         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3232         [FD_CORE_CLK] = &fd_core_clk.clkr,
3233         [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
3234         [FD_AHB_CLK] = &fd_ahb_clk.clkr,
3235 };
3236
3237 static struct gdsc *mmcc_msm8996_gdscs[] = {
3238         [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc,
3239         [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc,
3240         [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc,
3241         [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc,
3242         [VENUS_GDSC] = &venus_gdsc,
3243         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3244         [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3245         [CAMSS_GDSC] = &camss_gdsc,
3246         [VFE0_GDSC] = &vfe0_gdsc,
3247         [VFE1_GDSC] = &vfe1_gdsc,
3248         [JPEG_GDSC] = &jpeg_gdsc,
3249         [CPP_GDSC] = &cpp_gdsc,
3250         [FD_GDSC] = &fd_gdsc,
3251         [MDSS_GDSC] = &mdss_gdsc,
3252         [GPU_GDSC] = &gpu_gdsc,
3253         [GPU_GX_GDSC] = &gpu_gx_gdsc,
3254 };
3255
3256 static const struct qcom_reset_map mmcc_msm8996_resets[] = {
3257         [MMAGICAHB_BCR] = { 0x5020 },
3258         [MMAGIC_CFG_BCR] = { 0x5050 },
3259         [MISC_BCR] = { 0x5010 },
3260         [BTO_BCR] = { 0x5030 },
3261         [MMAGICAXI_BCR] = { 0x5060 },
3262         [MMAGICMAXI_BCR] = { 0x5070 },
3263         [DSA_BCR] = { 0x50a0 },
3264         [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3265         [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3266         [SMMU_VFE_BCR] = { 0x3c00 },
3267         [SMMU_CPP_BCR] = { 0x3c10 },
3268         [SMMU_JPEG_BCR] = { 0x3c20 },
3269         [MMAGIC_MDSS_BCR] = { 0x2470 },
3270         [THROTTLE_MDSS_BCR] = { 0x2460 },
3271         [SMMU_ROT_BCR] = { 0x2440 },
3272         [SMMU_MDP_BCR] = { 0x2450 },
3273         [MMAGIC_VIDEO_BCR] = { 0x1190 },
3274         [THROTTLE_VIDEO_BCR] = { 0x1180 },
3275         [SMMU_VIDEO_BCR] = { 0x1170 },
3276         [MMAGIC_BIMC_BCR] = { 0x5290 },
3277         [GPU_GX_BCR] = { 0x4020 },
3278         [GPU_BCR] = { 0x4030 },
3279         [GPU_AON_BCR] = { 0x4040 },
3280         [VMEM_BCR] = { 0x1200 },
3281         [MMSS_RBCPR_BCR] = { 0x4080 },
3282         [VIDEO_BCR] = { 0x1020 },
3283         [MDSS_BCR] = { 0x2300 },
3284         [CAMSS_TOP_BCR] = { 0x3480 },
3285         [CAMSS_AHB_BCR] = { 0x3488 },
3286         [CAMSS_MICRO_BCR] = { 0x3490 },
3287         [CAMSS_CCI_BCR] = { 0x3340 },
3288         [CAMSS_PHY0_BCR] = { 0x3020 },
3289         [CAMSS_PHY1_BCR] = { 0x3050 },
3290         [CAMSS_PHY2_BCR] = { 0x3080 },
3291         [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3292         [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3293         [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3294         [CAMSS_JPEG_BCR] = { 0x35a0 },
3295         [CAMSS_VFE_BCR] = { 0x36a0 },
3296         [CAMSS_VFE0_BCR] = { 0x3660 },
3297         [CAMSS_VFE1_BCR] = { 0x3670 },
3298         [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3299         [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3300         [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3301         [CAMSS_CPP_BCR] = { 0x36d0 },
3302         [CAMSS_CSI0_BCR] = { 0x30b0 },
3303         [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3304         [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3305         [CAMSS_CSI1_BCR] = { 0x3120 },
3306         [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3307         [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3308         [CAMSS_CSI2_BCR] = { 0x3180 },
3309         [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3310         [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3311         [CAMSS_CSI3_BCR] = { 0x31e0 },
3312         [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3313         [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3314         [CAMSS_ISPIF_BCR] = { 0x3220 },
3315         [FD_BCR] = { 0x3b60 },
3316         [MMSS_SPDM_RM_BCR] = { 0x300 },
3317 };
3318
3319 static const struct regmap_config mmcc_msm8996_regmap_config = {
3320         .reg_bits       = 32,
3321         .reg_stride     = 4,
3322         .val_bits       = 32,
3323         .max_register   = 0xb008,
3324         .fast_io        = true,
3325 };
3326
3327 static const struct qcom_cc_desc mmcc_msm8996_desc = {
3328         .config = &mmcc_msm8996_regmap_config,
3329         .clks = mmcc_msm8996_clocks,
3330         .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
3331         .resets = mmcc_msm8996_resets,
3332         .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
3333         .gdscs = mmcc_msm8996_gdscs,
3334         .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
3335 };
3336
3337 static const struct of_device_id mmcc_msm8996_match_table[] = {
3338         { .compatible = "qcom,mmcc-msm8996" },
3339         { }
3340 };
3341 MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
3342
3343 static int mmcc_msm8996_probe(struct platform_device *pdev)
3344 {
3345         struct device *dev = &pdev->dev;
3346         int i, ret;
3347         struct regmap *regmap;
3348
3349         regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
3350         if (IS_ERR(regmap))
3351                 return PTR_ERR(regmap);
3352
3353         /* Disable the AHB DCD */
3354         regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3355         /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
3356         regmap_update_bits(regmap, 0x5054, BIT(15), 0);
3357
3358         for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) {
3359                 ret = devm_clk_hw_register(dev, mmcc_msm8996_hws[i]);
3360                 if (ret)
3361                         return ret;
3362         }
3363
3364         return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
3365 }
3366
3367 static struct platform_driver mmcc_msm8996_driver = {
3368         .probe          = mmcc_msm8996_probe,
3369         .driver         = {
3370                 .name   = "mmcc-msm8996",
3371                 .of_match_table = mmcc_msm8996_match_table,
3372         },
3373 };
3374 module_platform_driver(mmcc_msm8996_driver);
3375
3376 MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
3377 MODULE_LICENSE("GPL v2");
3378 MODULE_ALIAS("platform:mmcc-msm8996");