drivers/clk/qcom/gcc-msm8998.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_AUD_REF_CLK,
  30         P_CORE_BI_PLL_TEST_SE,
  31         P_GPLL0_OUT_MAIN,
  32         P_GPLL4_OUT_MAIN,
  33         P_PLL0_EARLY_DIV_CLK_SRC,
  34         P_SLEEP_CLK,
  35         P_XO,
  36 };
  37
  38 static const struct parent_map gcc_parent_map_0[] = {
  39         { P_XO, 0 },
  40         { P_GPLL0_OUT_MAIN, 1 },
  41         { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  42         { P_CORE_BI_PLL_TEST_SE, 7 },
  43 };
  44
  45 static const char * const gcc_parent_names_0[] = {
  46         "xo",
  47         "gpll0_out_main",
  48         "gpll0_out_main",
  49         "core_bi_pll_test_se",
  50 };
  51
  52 static const struct parent_map gcc_parent_map_1[] = {
  53         { P_XO, 0 },
  54         { P_GPLL0_OUT_MAIN, 1 },
  55         { P_CORE_BI_PLL_TEST_SE, 7 },
  56 };
  57
  58 static const char * const gcc_parent_names_1[] = {
  59         "xo",
  60         "gpll0_out_main",
  61         "core_bi_pll_test_se",
  62 };
  63
  64 static const struct parent_map gcc_parent_map_2[] = {
  65         { P_XO, 0 },
  66         { P_GPLL0_OUT_MAIN, 1 },
  67         { P_SLEEP_CLK, 5 },
  68         { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  69         { P_CORE_BI_PLL_TEST_SE, 7 },
  70 };
  71
  72 static const char * const gcc_parent_names_2[] = {
  73         "xo",
  74         "gpll0_out_main",
  75         "core_pi_sleep_clk",
  76         "gpll0_out_main",
  77         "core_bi_pll_test_se",
  78 };
  79
  80 static const struct parent_map gcc_parent_map_3[] = {
  81         { P_XO, 0 },
  82         { P_SLEEP_CLK, 5 },
  83         { P_CORE_BI_PLL_TEST_SE, 7 },
  84 };
  85
  86 static const char * const gcc_parent_names_3[] = {
  87         "xo",
  88         "core_pi_sleep_clk",
  89         "core_bi_pll_test_se",
  90 };
  91
  92 static const struct parent_map gcc_parent_map_4[] = {
  93         { P_XO, 0 },
  94         { P_GPLL0_OUT_MAIN, 1 },
  95         { P_GPLL4_OUT_MAIN, 5 },
  96         { P_CORE_BI_PLL_TEST_SE, 7 },
  97 };
  98
  99 static const char * const gcc_parent_names_4[] = {
 100         "xo",
 101         "gpll0_out_main",
 102         "gpll4_out_main",
 103         "core_bi_pll_test_se",
 104 };
 105
 106 static const struct parent_map gcc_parent_map_5[] = {
 107         { P_XO, 0 },
 108         { P_GPLL0_OUT_MAIN, 1 },
 109         { P_AUD_REF_CLK, 2 },
 110         { P_CORE_BI_PLL_TEST_SE, 7 },
 111 };
 112
 113 static const char * const gcc_parent_names_5[] = {
 114         "xo",
 115         "gpll0_out_main",
 116         "aud_ref_clk",
 117         "core_bi_pll_test_se",
 118 };
 119
 120 static struct pll_vco fabia_vco[] = {
 121         { 250000000, 2000000000, 0 },
 122         { 125000000, 1000000000, 1 },
 123 };
 124
 125 static struct clk_alpha_pll gpll0 = {
 126         .offset = 0x0,
 127         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 128         .vco_table = fabia_vco,
 129         .num_vco = ARRAY_SIZE(fabia_vco),
 130         .clkr = {
 131                 .enable_reg = 0x52000,
 132                 .enable_mask = BIT(0),
 133                 .hw.init = &(struct clk_init_data){
 134                         .name = "gpll0",
 135                         .parent_names = (const char *[]){ "xo" },
 136                         .num_parents = 1,
 137                         .ops = &clk_alpha_pll_ops,
 138                 }
 139         },
 140 };
 141
 142 static struct clk_alpha_pll_postdiv gpll0_out_even = {
 143         .offset = 0x0,
 144         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 145         .clkr.hw.init = &(struct clk_init_data){
 146                 .name = "gpll0_out_even",
 147                 .parent_names = (const char *[]){ "gpll0" },
 148                 .num_parents = 1,
 149                 .ops = &clk_alpha_pll_postdiv_ops,
 150         },
 151 };
 152
 153 static struct clk_alpha_pll_postdiv gpll0_out_main = {
 154         .offset = 0x0,
 155         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 156         .clkr.hw.init = &(struct clk_init_data){
 157                 .name = "gpll0_out_main",
 158                 .parent_names = (const char *[]){ "gpll0" },
 159                 .num_parents = 1,
 160                 .ops = &clk_alpha_pll_postdiv_ops,
 161         },
 162 };
 163
 164 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
 165         .offset = 0x0,
 166         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 167         .clkr.hw.init = &(struct clk_init_data){
 168                 .name = "gpll0_out_odd",
 169                 .parent_names = (const char *[]){ "gpll0" },
 170                 .num_parents = 1,
 171                 .ops = &clk_alpha_pll_postdiv_ops,
 172         },
 173 };
 174
 175 static struct clk_alpha_pll_postdiv gpll0_out_test = {
 176         .offset = 0x0,
 177         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 178         .clkr.hw.init = &(struct clk_init_data){
 179                 .name = "gpll0_out_test",
 180                 .parent_names = (const char *[]){ "gpll0" },
 181                 .num_parents = 1,
 182                 .ops = &clk_alpha_pll_postdiv_ops,
 183         },
 184 };
 185
 186 static struct clk_alpha_pll gpll1 = {
 187         .offset = 0x1000,
 188         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 189         .vco_table = fabia_vco,
 190         .num_vco = ARRAY_SIZE(fabia_vco),
 191         .clkr = {
 192                 .enable_reg = 0x52000,
 193                 .enable_mask = BIT(1),
 194                 .hw.init = &(struct clk_init_data){
 195                         .name = "gpll1",
 196                         .parent_names = (const char *[]){ "xo" },
 197                         .num_parents = 1,
 198                         .ops = &clk_alpha_pll_ops,
 199                 }
 200         },
 201 };
 202
 203 static struct clk_alpha_pll_postdiv gpll1_out_even = {
 204         .offset = 0x1000,
 205         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 206         .clkr.hw.init = &(struct clk_init_data){
 207                 .name = "gpll1_out_even",
 208                 .parent_names = (const char *[]){ "gpll1" },
 209                 .num_parents = 1,
 210                 .ops = &clk_alpha_pll_postdiv_ops,
 211         },
 212 };
 213
 214 static struct clk_alpha_pll_postdiv gpll1_out_main = {
 215         .offset = 0x1000,
 216         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 217         .clkr.hw.init = &(struct clk_init_data){
 218                 .name = "gpll1_out_main",
 219                 .parent_names = (const char *[]){ "gpll1" },
 220                 .num_parents = 1,
 221                 .ops = &clk_alpha_pll_postdiv_ops,
 222         },
 223 };
 224
 225 static struct clk_alpha_pll_postdiv gpll1_out_odd = {
 226         .offset = 0x1000,
 227         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 228         .clkr.hw.init = &(struct clk_init_data){
 229                 .name = "gpll1_out_odd",
 230                 .parent_names = (const char *[]){ "gpll1" },
 231                 .num_parents = 1,
 232                 .ops = &clk_alpha_pll_postdiv_ops,
 233         },
 234 };
 235
 236 static struct clk_alpha_pll_postdiv gpll1_out_test = {
 237         .offset = 0x1000,
 238         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 239         .clkr.hw.init = &(struct clk_init_data){
 240                 .name = "gpll1_out_test",
 241                 .parent_names = (const char *[]){ "gpll1" },
 242                 .num_parents = 1,
 243                 .ops = &clk_alpha_pll_postdiv_ops,
 244         },
 245 };
 246
 247 static struct clk_alpha_pll gpll2 = {
 248         .offset = 0x2000,
 249         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 250         .vco_table = fabia_vco,
 251         .num_vco = ARRAY_SIZE(fabia_vco),
 252         .clkr = {
 253                 .enable_reg = 0x52000,
 254                 .enable_mask = BIT(2),
 255                 .hw.init = &(struct clk_init_data){
 256                         .name = "gpll2",
 257                         .parent_names = (const char *[]){ "xo" },
 258                         .num_parents = 1,
 259                         .ops = &clk_alpha_pll_ops,
 260                 }
 261         },
 262 };
 263
 264 static struct clk_alpha_pll_postdiv gpll2_out_even = {
 265         .offset = 0x2000,
 266         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 267         .clkr.hw.init = &(struct clk_init_data){
 268                 .name = "gpll2_out_even",
 269                 .parent_names = (const char *[]){ "gpll2" },
 270                 .num_parents = 1,
 271                 .ops = &clk_alpha_pll_postdiv_ops,
 272         },
 273 };
 274
 275 static struct clk_alpha_pll_postdiv gpll2_out_main = {
 276         .offset = 0x2000,
 277         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "gpll2_out_main",
 280                 .parent_names = (const char *[]){ "gpll2" },
 281                 .num_parents = 1,
 282                 .ops = &clk_alpha_pll_postdiv_ops,
 283         },
 284 };
 285
 286 static struct clk_alpha_pll_postdiv gpll2_out_odd = {
 287         .offset = 0x2000,
 288         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 289         .clkr.hw.init = &(struct clk_init_data){
 290                 .name = "gpll2_out_odd",
 291                 .parent_names = (const char *[]){ "gpll2" },
 292                 .num_parents = 1,
 293                 .ops = &clk_alpha_pll_postdiv_ops,
 294         },
 295 };
 296
 297 static struct clk_alpha_pll_postdiv gpll2_out_test = {
 298         .offset = 0x2000,
 299         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 300         .clkr.hw.init = &(struct clk_init_data){
 301                 .name = "gpll2_out_test",
 302                 .parent_names = (const char *[]){ "gpll2" },
 303                 .num_parents = 1,
 304                 .ops = &clk_alpha_pll_postdiv_ops,
 305         },
 306 };
 307
 308 static struct clk_alpha_pll gpll3 = {
 309         .offset = 0x3000,
 310         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 311         .vco_table = fabia_vco,
 312         .num_vco = ARRAY_SIZE(fabia_vco),
 313         .clkr = {
 314                 .enable_reg = 0x52000,
 315                 .enable_mask = BIT(3),
 316                 .hw.init = &(struct clk_init_data){
 317                         .name = "gpll3",
 318                         .parent_names = (const char *[]){ "xo" },
 319                         .num_parents = 1,
 320                         .ops = &clk_alpha_pll_ops,
 321                 }
 322         },
 323 };
 324
 325 static struct clk_alpha_pll_postdiv gpll3_out_even = {
 326         .offset = 0x3000,
 327         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 328         .clkr.hw.init = &(struct clk_init_data){
 329                 .name = "gpll3_out_even",
 330                 .parent_names = (const char *[]){ "gpll3" },
 331                 .num_parents = 1,
 332                 .ops = &clk_alpha_pll_postdiv_ops,
 333         },
 334 };
 335
 336 static struct clk_alpha_pll_postdiv gpll3_out_main = {
 337         .offset = 0x3000,
 338         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 339         .clkr.hw.init = &(struct clk_init_data){
 340                 .name = "gpll3_out_main",
 341                 .parent_names = (const char *[]){ "gpll3" },
 342                 .num_parents = 1,
 343                 .ops = &clk_alpha_pll_postdiv_ops,
 344         },
 345 };
 346
 347 static struct clk_alpha_pll_postdiv gpll3_out_odd = {
 348         .offset = 0x3000,
 349         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 350         .clkr.hw.init = &(struct clk_init_data){
 351                 .name = "gpll3_out_odd",
 352                 .parent_names = (const char *[]){ "gpll3" },
 353                 .num_parents = 1,
 354                 .ops = &clk_alpha_pll_postdiv_ops,
 355         },
 356 };
 357
 358 static struct clk_alpha_pll_postdiv gpll3_out_test = {
 359         .offset = 0x3000,
 360         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 361         .clkr.hw.init = &(struct clk_init_data){
 362                 .name = "gpll3_out_test",
 363                 .parent_names = (const char *[]){ "gpll3" },
 364                 .num_parents = 1,
 365                 .ops = &clk_alpha_pll_postdiv_ops,
 366         },
 367 };
 368
 369 static struct clk_alpha_pll gpll4 = {
 370         .offset = 0x77000,
 371         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 372         .vco_table = fabia_vco,
 373         .num_vco = ARRAY_SIZE(fabia_vco),
 374         .clkr = {
 375                 .enable_reg = 0x52000,
 376                 .enable_mask = BIT(4),
 377                 .hw.init = &(struct clk_init_data){
 378                         .name = "gpll4",
 379                         .parent_names = (const char *[]){ "xo" },
 380                         .num_parents = 1,
 381                         .ops = &clk_alpha_pll_ops,
 382                 }
 383         },
 384 };
 385
 386 static struct clk_alpha_pll_postdiv gpll4_out_even = {
 387         .offset = 0x77000,
 388         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 389         .clkr.hw.init = &(struct clk_init_data){
 390                 .name = "gpll4_out_even",
 391                 .parent_names = (const char *[]){ "gpll4" },
 392                 .num_parents = 1,
 393                 .ops = &clk_alpha_pll_postdiv_ops,
 394         },
 395 };
 396
 397 static struct clk_alpha_pll_postdiv gpll4_out_main = {
 398         .offset = 0x77000,
 399         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 400         .clkr.hw.init = &(struct clk_init_data){
 401                 .name = "gpll4_out_main",
 402                 .parent_names = (const char *[]){ "gpll4" },
 403                 .num_parents = 1,
 404                 .ops = &clk_alpha_pll_postdiv_ops,
 405         },
 406 };
 407
 408 static struct clk_alpha_pll_postdiv gpll4_out_odd = {
 409         .offset = 0x77000,
 410         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 411         .clkr.hw.init = &(struct clk_init_data){
 412                 .name = "gpll4_out_odd",
 413                 .parent_names = (const char *[]){ "gpll4" },
 414                 .num_parents = 1,
 415                 .ops = &clk_alpha_pll_postdiv_ops,
 416         },
 417 };
 418
 419 static struct clk_alpha_pll_postdiv gpll4_out_test = {
 420         .offset = 0x77000,
 421         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 422         .clkr.hw.init = &(struct clk_init_data){
 423                 .name = "gpll4_out_test",
 424                 .parent_names = (const char *[]){ "gpll4" },
 425                 .num_parents = 1,
 426                 .ops = &clk_alpha_pll_postdiv_ops,
 427         },
 428 };
 429
 430 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 431         F(19200000, P_XO, 1, 0, 0),
 432         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 433         { }
 434 };
 435
 436 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 437         .cmd_rcgr = 0x19020,
 438         .mnd_width = 0,
 439         .hid_width = 5,
 440         .parent_map = gcc_parent_map_1,
 441         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 442         .clkr.hw.init = &(struct clk_init_data){
 443                 .name = "blsp1_qup1_i2c_apps_clk_src",
 444                 .parent_names = gcc_parent_names_1,
 445                 .num_parents = 3,
 446                 .ops = &clk_rcg2_ops,
 447         },
 448 };
 449
 450 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 451         F(960000, P_XO, 10, 1, 2),
 452         F(4800000, P_XO, 4, 0, 0),
 453         F(9600000, P_XO, 2, 0, 0),
 454         F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
 455         F(19200000, P_XO, 1, 0, 0),
 456         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 457         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 458         { }
 459 };
 460
 461 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 462         .cmd_rcgr = 0x1900c,
 463         .mnd_width = 8,
 464         .hid_width = 5,
 465         .parent_map = gcc_parent_map_0,
 466         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 467         .clkr.hw.init = &(struct clk_init_data){
 468                 .name = "blsp1_qup1_spi_apps_clk_src",
 469                 .parent_names = gcc_parent_names_0,
 470                 .num_parents = 4,
 471                 .ops = &clk_rcg2_ops,
 472         },
 473 };
 474
 475 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 476         .cmd_rcgr = 0x1b020,
 477         .mnd_width = 0,
 478         .hid_width = 5,
 479         .parent_map = gcc_parent_map_1,
 480         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 481         .clkr.hw.init = &(struct clk_init_data){
 482                 .name = "blsp1_qup2_i2c_apps_clk_src",
 483                 .parent_names = gcc_parent_names_1,
 484                 .num_parents = 3,
 485                 .ops = &clk_rcg2_ops,
 486         },
 487 };
 488
 489 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 490         .cmd_rcgr = 0x1b00c,
 491         .mnd_width = 8,
 492         .hid_width = 5,
 493         .parent_map = gcc_parent_map_0,
 494         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 495         .clkr.hw.init = &(struct clk_init_data){
 496                 .name = "blsp1_qup2_spi_apps_clk_src",
 497                 .parent_names = gcc_parent_names_0,
 498                 .num_parents = 4,
 499                 .ops = &clk_rcg2_ops,
 500         },
 501 };
 502
 503 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 504         .cmd_rcgr = 0x1d020,
 505         .mnd_width = 0,
 506         .hid_width = 5,
 507         .parent_map = gcc_parent_map_1,
 508         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 509         .clkr.hw.init = &(struct clk_init_data){
 510                 .name = "blsp1_qup3_i2c_apps_clk_src",
 511                 .parent_names = gcc_parent_names_1,
 512                 .num_parents = 3,
 513                 .ops = &clk_rcg2_ops,
 514         },
 515 };
 516
 517 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 518         .cmd_rcgr = 0x1d00c,
 519         .mnd_width = 8,
 520         .hid_width = 5,
 521         .parent_map = gcc_parent_map_0,
 522         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 523         .clkr.hw.init = &(struct clk_init_data){
 524                 .name = "blsp1_qup3_spi_apps_clk_src",
 525                 .parent_names = gcc_parent_names_0,
 526                 .num_parents = 4,
 527                 .ops = &clk_rcg2_ops,
 528         },
 529 };
 530
 531 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 532         .cmd_rcgr = 0x1f020,
 533         .mnd_width = 0,
 534         .hid_width = 5,
 535         .parent_map = gcc_parent_map_1,
 536         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 537         .clkr.hw.init = &(struct clk_init_data){
 538                 .name = "blsp1_qup4_i2c_apps_clk_src",
 539                 .parent_names = gcc_parent_names_1,
 540                 .num_parents = 3,
 541                 .ops = &clk_rcg2_ops,
 542         },
 543 };
 544
 545 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 546         .cmd_rcgr = 0x1f00c,
 547         .mnd_width = 8,
 548         .hid_width = 5,
 549         .parent_map = gcc_parent_map_0,
 550         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 551         .clkr.hw.init = &(struct clk_init_data){
 552                 .name = "blsp1_qup4_spi_apps_clk_src",
 553                 .parent_names = gcc_parent_names_0,
 554                 .num_parents = 4,
 555                 .ops = &clk_rcg2_ops,
 556         },
 557 };
 558
 559 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 560         .cmd_rcgr = 0x21020,
 561         .mnd_width = 0,
 562         .hid_width = 5,
 563         .parent_map = gcc_parent_map_1,
 564         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 565         .clkr.hw.init = &(struct clk_init_data){
 566                 .name = "blsp1_qup5_i2c_apps_clk_src",
 567                 .parent_names = gcc_parent_names_1,
 568                 .num_parents = 3,
 569                 .ops = &clk_rcg2_ops,
 570         },
 571 };
 572
 573 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 574         .cmd_rcgr = 0x2100c,
 575         .mnd_width = 8,
 576         .hid_width = 5,
 577         .parent_map = gcc_parent_map_0,
 578         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 579         .clkr.hw.init = &(struct clk_init_data){
 580                 .name = "blsp1_qup5_spi_apps_clk_src",
 581                 .parent_names = gcc_parent_names_0,
 582                 .num_parents = 4,
 583                 .ops = &clk_rcg2_ops,
 584         },
 585 };
 586
 587 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 588         .cmd_rcgr = 0x23020,
 589         .mnd_width = 0,
 590         .hid_width = 5,
 591         .parent_map = gcc_parent_map_1,
 592         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 593         .clkr.hw.init = &(struct clk_init_data){
 594                 .name = "blsp1_qup6_i2c_apps_clk_src",
 595                 .parent_names = gcc_parent_names_1,
 596                 .num_parents = 3,
 597                 .ops = &clk_rcg2_ops,
 598         },
 599 };
 600
 601 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 602         .cmd_rcgr = 0x2300c,
 603         .mnd_width = 8,
 604         .hid_width = 5,
 605         .parent_map = gcc_parent_map_0,
 606         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 607         .clkr.hw.init = &(struct clk_init_data){
 608                 .name = "blsp1_qup6_spi_apps_clk_src",
 609                 .parent_names = gcc_parent_names_0,
 610                 .num_parents = 4,
 611                 .ops = &clk_rcg2_ops,
 612         },
 613 };
 614
 615 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 616         F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
 617         F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
 618         F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
 619         F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
 620         F(19200000, P_XO, 1, 0, 0),
 621         F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
 622         F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
 623         F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
 624         F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
 625         F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 626         F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
 627         F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
 628         F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
 629         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 630         F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
 631         { }
 632 };
 633
 634 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 635         .cmd_rcgr = 0x1a00c,
 636         .mnd_width = 16,
 637         .hid_width = 5,
 638         .parent_map = gcc_parent_map_0,
 639         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 640         .clkr.hw.init = &(struct clk_init_data){
 641                 .name = "blsp1_uart1_apps_clk_src",
 642                 .parent_names = gcc_parent_names_0,
 643                 .num_parents = 4,
 644                 .ops = &clk_rcg2_ops,
 645         },
 646 };
 647
 648 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 649         .cmd_rcgr = 0x1c00c,
 650         .mnd_width = 16,
 651         .hid_width = 5,
 652         .parent_map = gcc_parent_map_0,
 653         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 654         .clkr.hw.init = &(struct clk_init_data){
 655                 .name = "blsp1_uart2_apps_clk_src",
 656                 .parent_names = gcc_parent_names_0,
 657                 .num_parents = 4,
 658                 .ops = &clk_rcg2_ops,
 659         },
 660 };
 661
 662 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 663         .cmd_rcgr = 0x1e00c,
 664         .mnd_width = 16,
 665         .hid_width = 5,
 666         .parent_map = gcc_parent_map_0,
 667         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 668         .clkr.hw.init = &(struct clk_init_data){
 669                 .name = "blsp1_uart3_apps_clk_src",
 670                 .parent_names = gcc_parent_names_0,
 671                 .num_parents = 4,
 672                 .ops = &clk_rcg2_ops,
 673         },
 674 };
 675
 676 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 677         .cmd_rcgr = 0x26020,
 678         .mnd_width = 0,
 679         .hid_width = 5,
 680         .parent_map = gcc_parent_map_1,
 681         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 682         .clkr.hw.init = &(struct clk_init_data){
 683                 .name = "blsp2_qup1_i2c_apps_clk_src",
 684                 .parent_names = gcc_parent_names_1,
 685                 .num_parents = 3,
 686                 .ops = &clk_rcg2_ops,
 687         },
 688 };
 689
 690 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 691         .cmd_rcgr = 0x2600c,
 692         .mnd_width = 8,
 693         .hid_width = 5,
 694         .parent_map = gcc_parent_map_0,
 695         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 696         .clkr.hw.init = &(struct clk_init_data){
 697                 .name = "blsp2_qup1_spi_apps_clk_src",
 698                 .parent_names = gcc_parent_names_0,
 699                 .num_parents = 4,
 700                 .ops = &clk_rcg2_ops,
 701         },
 702 };
 703
 704 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 705         .cmd_rcgr = 0x28020,
 706         .mnd_width = 0,
 707         .hid_width = 5,
 708         .parent_map = gcc_parent_map_1,
 709         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 710         .clkr.hw.init = &(struct clk_init_data){
 711                 .name = "blsp2_qup2_i2c_apps_clk_src",
 712                 .parent_names = gcc_parent_names_1,
 713                 .num_parents = 3,
 714                 .ops = &clk_rcg2_ops,
 715         },
 716 };
 717
 718 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 719         .cmd_rcgr = 0x2800c,
 720         .mnd_width = 8,
 721         .hid_width = 5,
 722         .parent_map = gcc_parent_map_0,
 723         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 724         .clkr.hw.init = &(struct clk_init_data){
 725                 .name = "blsp2_qup2_spi_apps_clk_src",
 726                 .parent_names = gcc_parent_names_0,
 727                 .num_parents = 4,
 728                 .ops = &clk_rcg2_ops,
 729         },
 730 };
 731
 732 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 733         .cmd_rcgr = 0x2a020,
 734         .mnd_width = 0,
 735         .hid_width = 5,
 736         .parent_map = gcc_parent_map_1,
 737         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 738         .clkr.hw.init = &(struct clk_init_data){
 739                 .name = "blsp2_qup3_i2c_apps_clk_src",
 740                 .parent_names = gcc_parent_names_1,
 741                 .num_parents = 3,
 742                 .ops = &clk_rcg2_ops,
 743         },
 744 };
 745
 746 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 747         .cmd_rcgr = 0x2a00c,
 748         .mnd_width = 8,
 749         .hid_width = 5,
 750         .parent_map = gcc_parent_map_0,
 751         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 752         .clkr.hw.init = &(struct clk_init_data){
 753                 .name = "blsp2_qup3_spi_apps_clk_src",
 754                 .parent_names = gcc_parent_names_0,
 755                 .num_parents = 4,
 756                 .ops = &clk_rcg2_ops,
 757         },
 758 };
 759
 760 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 761         .cmd_rcgr = 0x2c020,
 762         .mnd_width = 0,
 763         .hid_width = 5,
 764         .parent_map = gcc_parent_map_1,
 765         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 766         .clkr.hw.init = &(struct clk_init_data){
 767                 .name = "blsp2_qup4_i2c_apps_clk_src",
 768                 .parent_names = gcc_parent_names_1,
 769                 .num_parents = 3,
 770                 .ops = &clk_rcg2_ops,
 771         },
 772 };
 773
 774 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 775         .cmd_rcgr = 0x2c00c,
 776         .mnd_width = 8,
 777         .hid_width = 5,
 778         .parent_map = gcc_parent_map_0,
 779         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 780         .clkr.hw.init = &(struct clk_init_data){
 781                 .name = "blsp2_qup4_spi_apps_clk_src",
 782                 .parent_names = gcc_parent_names_0,
 783                 .num_parents = 4,
 784                 .ops = &clk_rcg2_ops,
 785         },
 786 };
 787
 788 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 789         .cmd_rcgr = 0x2e020,
 790         .mnd_width = 0,
 791         .hid_width = 5,
 792         .parent_map = gcc_parent_map_1,
 793         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 794         .clkr.hw.init = &(struct clk_init_data){
 795                 .name = "blsp2_qup5_i2c_apps_clk_src",
 796                 .parent_names = gcc_parent_names_1,
 797                 .num_parents = 3,
 798                 .ops = &clk_rcg2_ops,
 799         },
 800 };
 801
 802 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 803         .cmd_rcgr = 0x2e00c,
 804         .mnd_width = 8,
 805         .hid_width = 5,
 806         .parent_map = gcc_parent_map_0,
 807         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 808         .clkr.hw.init = &(struct clk_init_data){
 809                 .name = "blsp2_qup5_spi_apps_clk_src",
 810                 .parent_names = gcc_parent_names_0,
 811                 .num_parents = 4,
 812                 .ops = &clk_rcg2_ops,
 813         },
 814 };
 815
 816 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 817         .cmd_rcgr = 0x30020,
 818         .mnd_width = 0,
 819         .hid_width = 5,
 820         .parent_map = gcc_parent_map_1,
 821         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 822         .clkr.hw.init = &(struct clk_init_data){
 823                 .name = "blsp2_qup6_i2c_apps_clk_src",
 824                 .parent_names = gcc_parent_names_1,
 825                 .num_parents = 3,
 826                 .ops = &clk_rcg2_ops,
 827         },
 828 };
 829
 830 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 831         .cmd_rcgr = 0x3000c,
 832         .mnd_width = 8,
 833         .hid_width = 5,
 834         .parent_map = gcc_parent_map_0,
 835         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 836         .clkr.hw.init = &(struct clk_init_data){
 837                 .name = "blsp2_qup6_spi_apps_clk_src",
 838                 .parent_names = gcc_parent_names_0,
 839                 .num_parents = 4,
 840                 .ops = &clk_rcg2_ops,
 841         },
 842 };
 843
 844 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 845         .cmd_rcgr = 0x2700c,
 846         .mnd_width = 16,
 847         .hid_width = 5,
 848         .parent_map = gcc_parent_map_0,
 849         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 850         .clkr.hw.init = &(struct clk_init_data){
 851                 .name = "blsp2_uart1_apps_clk_src",
 852                 .parent_names = gcc_parent_names_0,
 853                 .num_parents = 4,
 854                 .ops = &clk_rcg2_ops,
 855         },
 856 };
 857
 858 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 859         .cmd_rcgr = 0x2900c,
 860         .mnd_width = 16,
 861         .hid_width = 5,
 862         .parent_map = gcc_parent_map_0,
 863         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 864         .clkr.hw.init = &(struct clk_init_data){
 865                 .name = "blsp2_uart2_apps_clk_src",
 866                 .parent_names = gcc_parent_names_0,
 867                 .num_parents = 4,
 868                 .ops = &clk_rcg2_ops,
 869         },
 870 };
 871
 872 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 873         .cmd_rcgr = 0x2b00c,
 874         .mnd_width = 16,
 875         .hid_width = 5,
 876         .parent_map = gcc_parent_map_0,
 877         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 878         .clkr.hw.init = &(struct clk_init_data){
 879                 .name = "blsp2_uart3_apps_clk_src",
 880                 .parent_names = gcc_parent_names_0,
 881                 .num_parents = 4,
 882                 .ops = &clk_rcg2_ops,
 883         },
 884 };
 885
 886 static const struct freq_tbl ftbl_gp1_clk_src[] = {
 887         F(19200000, P_XO, 1, 0, 0),
 888         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 889         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 890         { }
 891 };
 892
 893 static struct clk_rcg2 gp1_clk_src = {
 894         .cmd_rcgr = 0x64004,
 895         .mnd_width = 8,
 896         .hid_width = 5,
 897         .parent_map = gcc_parent_map_2,
 898         .freq_tbl = ftbl_gp1_clk_src,
 899         .clkr.hw.init = &(struct clk_init_data){
 900                 .name = "gp1_clk_src",
 901                 .parent_names = gcc_parent_names_2,
 902                 .num_parents = 5,
 903                 .ops = &clk_rcg2_ops,
 904         },
 905 };
 906
 907 static struct clk_rcg2 gp2_clk_src = {
 908         .cmd_rcgr = 0x65004,
 909         .mnd_width = 8,
 910         .hid_width = 5,
 911         .parent_map = gcc_parent_map_2,
 912         .freq_tbl = ftbl_gp1_clk_src,
 913         .clkr.hw.init = &(struct clk_init_data){
 914                 .name = "gp2_clk_src",
 915                 .parent_names = gcc_parent_names_2,
 916                 .num_parents = 5,
 917                 .ops = &clk_rcg2_ops,
 918         },
 919 };
 920
 921 static struct clk_rcg2 gp3_clk_src = {
 922         .cmd_rcgr = 0x66004,
 923         .mnd_width = 8,
 924         .hid_width = 5,
 925         .parent_map = gcc_parent_map_2,
 926         .freq_tbl = ftbl_gp1_clk_src,
 927         .clkr.hw.init = &(struct clk_init_data){
 928                 .name = "gp3_clk_src",
 929                 .parent_names = gcc_parent_names_2,
 930                 .num_parents = 5,
 931                 .ops = &clk_rcg2_ops,
 932         },
 933 };
 934
 935 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
 936         F(19200000, P_XO, 1, 0, 0),
 937         F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 938         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 939         { }
 940 };
 941
 942 static struct clk_rcg2 hmss_ahb_clk_src = {
 943         .cmd_rcgr = 0x48014,
 944         .mnd_width = 0,
 945         .hid_width = 5,
 946         .parent_map = gcc_parent_map_1,
 947         .freq_tbl = ftbl_hmss_ahb_clk_src,
 948         .clkr.hw.init = &(struct clk_init_data){
 949                 .name = "hmss_ahb_clk_src",
 950                 .parent_names = gcc_parent_names_1,
 951                 .num_parents = 3,
 952                 .ops = &clk_rcg2_ops,
 953         },
 954 };
 955
 956 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
 957         F(19200000, P_XO, 1, 0, 0),
 958         { }
 959 };
 960
 961 static struct clk_rcg2 hmss_rbcpr_clk_src = {
 962         .cmd_rcgr = 0x48044,
 963         .mnd_width = 0,
 964         .hid_width = 5,
 965         .parent_map = gcc_parent_map_1,
 966         .freq_tbl = ftbl_hmss_rbcpr_clk_src,
 967         .clkr.hw.init = &(struct clk_init_data){
 968                 .name = "hmss_rbcpr_clk_src",
 969                 .parent_names = gcc_parent_names_1,
 970                 .num_parents = 3,
 971                 .ops = &clk_rcg2_ops,
 972         },
 973 };
 974
 975 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 976         F(1010526, P_XO, 1, 1, 19),
 977         { }
 978 };
 979
 980 static struct clk_rcg2 pcie_aux_clk_src = {
 981         .cmd_rcgr = 0x6c000,
 982         .mnd_width = 16,
 983         .hid_width = 5,
 984         .parent_map = gcc_parent_map_3,
 985         .freq_tbl = ftbl_pcie_aux_clk_src,
 986         .clkr.hw.init = &(struct clk_init_data){
 987                 .name = "pcie_aux_clk_src",
 988                 .parent_names = gcc_parent_names_3,
 989                 .num_parents = 3,
 990                 .ops = &clk_rcg2_ops,
 991         },
 992 };
 993
 994 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
 995         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 996         { }
 997 };
 998
 999 static struct clk_rcg2 pdm2_clk_src = {
1000         .cmd_rcgr = 0x33010,
1001         .mnd_width = 0,
1002         .hid_width = 5,
1003         .parent_map = gcc_parent_map_1,
1004         .freq_tbl = ftbl_pdm2_clk_src,
1005         .clkr.hw.init = &(struct clk_init_data){
1006                 .name = "pdm2_clk_src",
1007                 .parent_names = gcc_parent_names_1,
1008                 .num_parents = 3,
1009                 .ops = &clk_rcg2_ops,
1010         },
1011 };
1012
1013 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1014         F(144000, P_XO, 16, 3, 25),
1015         F(400000, P_XO, 12, 1, 4),
1016         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1017         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1018         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1019         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1020         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1021         { }
1022 };
1023
1024 static struct clk_rcg2 sdcc2_apps_clk_src = {
1025         .cmd_rcgr = 0x14010,
1026         .mnd_width = 8,
1027         .hid_width = 5,
1028         .parent_map = gcc_parent_map_4,
1029         .freq_tbl = ftbl_sdcc2_apps_clk_src,
1030         .clkr.hw.init = &(struct clk_init_data){
1031                 .name = "sdcc2_apps_clk_src",
1032                 .parent_names = gcc_parent_names_4,
1033                 .num_parents = 4,
1034                 .ops = &clk_rcg2_ops,
1035         },
1036 };
1037
1038 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
1039         F(144000, P_XO, 16, 3, 25),
1040         F(400000, P_XO, 12, 1, 4),
1041         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1042         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1043         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1044         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1045         { }
1046 };
1047
1048 static struct clk_rcg2 sdcc4_apps_clk_src = {
1049         .cmd_rcgr = 0x16010,
1050         .mnd_width = 8,
1051         .hid_width = 5,
1052         .parent_map = gcc_parent_map_1,
1053         .freq_tbl = ftbl_sdcc4_apps_clk_src,
1054         .clkr.hw.init = &(struct clk_init_data){
1055                 .name = "sdcc4_apps_clk_src",
1056                 .parent_names = gcc_parent_names_1,
1057                 .num_parents = 3,
1058                 .ops = &clk_rcg2_ops,
1059         },
1060 };
1061
1062 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1063         F(105495, P_XO, 1, 1, 182),
1064         { }
1065 };
1066
1067 static struct clk_rcg2 tsif_ref_clk_src = {
1068         .cmd_rcgr = 0x36010,
1069         .mnd_width = 8,
1070         .hid_width = 5,
1071         .parent_map = gcc_parent_map_5,
1072         .freq_tbl = ftbl_tsif_ref_clk_src,
1073         .clkr.hw.init = &(struct clk_init_data){
1074                 .name = "tsif_ref_clk_src",
1075                 .parent_names = gcc_parent_names_5,
1076                 .num_parents = 4,
1077                 .ops = &clk_rcg2_ops,
1078         },
1079 };
1080
1081 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1082         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1083         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1084         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1085         { }
1086 };
1087
1088 static struct clk_rcg2 ufs_axi_clk_src = {
1089         .cmd_rcgr = 0x75018,
1090         .mnd_width = 8,
1091         .hid_width = 5,
1092         .parent_map = gcc_parent_map_0,
1093         .freq_tbl = ftbl_ufs_axi_clk_src,
1094         .clkr.hw.init = &(struct clk_init_data){
1095                 .name = "ufs_axi_clk_src",
1096                 .parent_names = gcc_parent_names_0,
1097                 .num_parents = 4,
1098                 .ops = &clk_rcg2_ops,
1099         },
1100 };
1101
1102 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1103         F(19200000, P_XO, 1, 0, 0),
1104         F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1105         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1106         { }
1107 };
1108
1109 static struct clk_rcg2 usb30_master_clk_src = {
1110         .cmd_rcgr = 0xf014,
1111         .mnd_width = 8,
1112         .hid_width = 5,
1113         .parent_map = gcc_parent_map_0,
1114         .freq_tbl = ftbl_usb30_master_clk_src,
1115         .clkr.hw.init = &(struct clk_init_data){
1116                 .name = "usb30_master_clk_src",
1117                 .parent_names = gcc_parent_names_0,
1118                 .num_parents = 4,
1119                 .ops = &clk_rcg2_ops,
1120         },
1121 };
1122
1123 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1124         .cmd_rcgr = 0xf028,
1125         .mnd_width = 0,
1126         .hid_width = 5,
1127         .parent_map = gcc_parent_map_0,
1128         .freq_tbl = ftbl_hmss_rbcpr_clk_src,
1129         .clkr.hw.init = &(struct clk_init_data){
1130                 .name = "usb30_mock_utmi_clk_src",
1131                 .parent_names = gcc_parent_names_0,
1132                 .num_parents = 4,
1133                 .ops = &clk_rcg2_ops,
1134         },
1135 };
1136
1137 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1138         F(1200000, P_XO, 16, 0, 0),
1139         { }
1140 };
1141
1142 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1143         .cmd_rcgr = 0x5000c,
1144         .mnd_width = 0,
1145         .hid_width = 5,
1146         .parent_map = gcc_parent_map_3,
1147         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "usb3_phy_aux_clk_src",
1150                 .parent_names = gcc_parent_names_3,
1151                 .num_parents = 3,
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static struct clk_branch gcc_aggre1_noc_xo_clk = {
1157         .halt_reg = 0x8202c,
1158         .halt_check = BRANCH_HALT,
1159         .clkr = {
1160                 .enable_reg = 0x8202c,
1161                 .enable_mask = BIT(0),
1162                 .hw.init = &(struct clk_init_data){
1163                         .name = "gcc_aggre1_noc_xo_clk",
1164                         .ops = &clk_branch2_ops,
1165                 },
1166         },
1167 };
1168
1169 static struct clk_branch gcc_aggre1_ufs_axi_clk = {
1170         .halt_reg = 0x82028,
1171         .halt_check = BRANCH_HALT,
1172         .clkr = {
1173                 .enable_reg = 0x82028,
1174                 .enable_mask = BIT(0),
1175                 .hw.init = &(struct clk_init_data){
1176                         .name = "gcc_aggre1_ufs_axi_clk",
1177                         .parent_names = (const char *[]){
1178                                 "ufs_axi_clk_src",
1179                         },
1180                         .num_parents = 1,
1181                         .ops = &clk_branch2_ops,
1182                 },
1183         },
1184 };
1185
1186 static struct clk_branch gcc_aggre1_usb3_axi_clk = {
1187         .halt_reg = 0x82024,
1188         .halt_check = BRANCH_HALT,
1189         .clkr = {
1190                 .enable_reg = 0x82024,
1191                 .enable_mask = BIT(0),
1192                 .hw.init = &(struct clk_init_data){
1193                         .name = "gcc_aggre1_usb3_axi_clk",
1194                         .parent_names = (const char *[]){
1195                                 "usb30_master_clk_src",
1196                         },
1197                         .num_parents = 1,
1198                         .ops = &clk_branch2_ops,
1199                 },
1200         },
1201 };
1202
1203 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
1204         .halt_reg = 0x48090,
1205         .halt_check = BRANCH_HALT,
1206         .clkr = {
1207                 .enable_reg = 0x48090,
1208                 .enable_mask = BIT(0),
1209                 .hw.init = &(struct clk_init_data){
1210                         .name = "gcc_apss_qdss_tsctr_div2_clk",
1211                         .ops = &clk_branch2_ops,
1212                 },
1213         },
1214 };
1215
1216 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
1217         .halt_reg = 0x48094,
1218         .halt_check = BRANCH_HALT,
1219         .clkr = {
1220                 .enable_reg = 0x48094,
1221                 .enable_mask = BIT(0),
1222                 .hw.init = &(struct clk_init_data){
1223                         .name = "gcc_apss_qdss_tsctr_div8_clk",
1224                         .ops = &clk_branch2_ops,
1225                 },
1226         },
1227 };
1228
1229 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1230         .halt_reg = 0x48004,
1231         .halt_check = BRANCH_HALT_VOTED,
1232         .clkr = {
1233                 .enable_reg = 0x52004,
1234                 .enable_mask = BIT(22),
1235                 .hw.init = &(struct clk_init_data){
1236                         .name = "gcc_bimc_hmss_axi_clk",
1237                         .ops = &clk_branch2_ops,
1238                 },
1239         },
1240 };
1241
1242 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1243         .halt_reg = 0x4401c,
1244         .halt_check = BRANCH_HALT,
1245         .clkr = {
1246                 .enable_reg = 0x4401c,
1247                 .enable_mask = BIT(0),
1248                 .hw.init = &(struct clk_init_data){
1249                         .name = "gcc_bimc_mss_q6_axi_clk",
1250                         .ops = &clk_branch2_ops,
1251                 },
1252         },
1253 };
1254
1255 static struct clk_branch gcc_blsp1_ahb_clk = {
1256         .halt_reg = 0x17004,
1257         .halt_check = BRANCH_HALT_VOTED,
1258         .clkr = {
1259                 .enable_reg = 0x52004,
1260                 .enable_mask = BIT(17),
1261                 .hw.init = &(struct clk_init_data){
1262                         .name = "gcc_blsp1_ahb_clk",
1263                         .ops = &clk_branch2_ops,
1264                 },
1265         },
1266 };
1267
1268 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1269         .halt_reg = 0x19008,
1270         .halt_check = BRANCH_HALT,
1271         .clkr = {
1272                 .enable_reg = 0x19008,
1273                 .enable_mask = BIT(0),
1274                 .hw.init = &(struct clk_init_data){
1275                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1276                         .parent_names = (const char *[]){
1277                                 "blsp1_qup1_i2c_apps_clk_src",
1278                         },
1279                         .num_parents = 1,
1280                         .ops = &clk_branch2_ops,
1281                 },
1282         },
1283 };
1284
1285 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1286         .halt_reg = 0x19004,
1287         .halt_check = BRANCH_HALT,
1288         .clkr = {
1289                 .enable_reg = 0x19004,
1290                 .enable_mask = BIT(0),
1291                 .hw.init = &(struct clk_init_data){
1292                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1293                         .parent_names = (const char *[]){
1294                                 "blsp1_qup1_spi_apps_clk_src",
1295                         },
1296                         .num_parents = 1,
1297                         .ops = &clk_branch2_ops,
1298                 },
1299         },
1300 };
1301
1302 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1303         .halt_reg = 0x1b008,
1304         .halt_check = BRANCH_HALT,
1305         .clkr = {
1306                 .enable_reg = 0x1b008,
1307                 .enable_mask = BIT(0),
1308                 .hw.init = &(struct clk_init_data){
1309                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1310                         .parent_names = (const char *[]){
1311                                 "blsp1_qup2_i2c_apps_clk_src",
1312                         },
1313                         .num_parents = 1,
1314                         .ops = &clk_branch2_ops,
1315                 },
1316         },
1317 };
1318
1319 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1320         .halt_reg = 0x1b004,
1321         .halt_check = BRANCH_HALT,
1322         .clkr = {
1323                 .enable_reg = 0x1b004,
1324                 .enable_mask = BIT(0),
1325                 .hw.init = &(struct clk_init_data){
1326                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1327                         .parent_names = (const char *[]){
1328                                 "blsp1_qup2_spi_apps_clk_src",
1329                         },
1330                         .num_parents = 1,
1331                         .ops = &clk_branch2_ops,
1332                 },
1333         },
1334 };
1335
1336 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1337         .halt_reg = 0x1d008,
1338         .halt_check = BRANCH_HALT,
1339         .clkr = {
1340                 .enable_reg = 0x1d008,
1341                 .enable_mask = BIT(0),
1342                 .hw.init = &(struct clk_init_data){
1343                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1344                         .parent_names = (const char *[]){
1345                                 "blsp1_qup3_i2c_apps_clk_src",
1346                         },
1347                         .num_parents = 1,
1348                         .ops = &clk_branch2_ops,
1349                 },
1350         },
1351 };
1352
1353 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1354         .halt_reg = 0x1d004,
1355         .halt_check = BRANCH_HALT,
1356         .clkr = {
1357                 .enable_reg = 0x1d004,
1358                 .enable_mask = BIT(0),
1359                 .hw.init = &(struct clk_init_data){
1360                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1361                         .parent_names = (const char *[]){
1362                                 "blsp1_qup3_spi_apps_clk_src",
1363                         },
1364                         .num_parents = 1,
1365                         .ops = &clk_branch2_ops,
1366                 },
1367         },
1368 };
1369
1370 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1371         .halt_reg = 0x1f008,
1372         .halt_check = BRANCH_HALT,
1373         .clkr = {
1374                 .enable_reg = 0x1f008,
1375                 .enable_mask = BIT(0),
1376                 .hw.init = &(struct clk_init_data){
1377                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1378                         .parent_names = (const char *[]){
1379                                 "blsp1_qup4_i2c_apps_clk_src",
1380                         },
1381                         .num_parents = 1,
1382                         .ops = &clk_branch2_ops,
1383                 },
1384         },
1385 };
1386
1387 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1388         .halt_reg = 0x1f004,
1389         .halt_check = BRANCH_HALT,
1390         .clkr = {
1391                 .enable_reg = 0x1f004,
1392                 .enable_mask = BIT(0),
1393                 .hw.init = &(struct clk_init_data){
1394                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1395                         .parent_names = (const char *[]){
1396                                 "blsp1_qup4_spi_apps_clk_src",
1397                         },
1398                         .num_parents = 1,
1399                         .ops = &clk_branch2_ops,
1400                 },
1401         },
1402 };
1403
1404 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1405         .halt_reg = 0x21008,
1406         .halt_check = BRANCH_HALT,
1407         .clkr = {
1408                 .enable_reg = 0x21008,
1409                 .enable_mask = BIT(0),
1410                 .hw.init = &(struct clk_init_data){
1411                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1412                         .parent_names = (const char *[]){
1413                                 "blsp1_qup5_i2c_apps_clk_src",
1414                         },
1415                         .num_parents = 1,
1416                         .ops = &clk_branch2_ops,
1417                 },
1418         },
1419 };
1420
1421 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1422         .halt_reg = 0x21004,
1423         .halt_check = BRANCH_HALT,
1424         .clkr = {
1425                 .enable_reg = 0x21004,
1426                 .enable_mask = BIT(0),
1427                 .hw.init = &(struct clk_init_data){
1428                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1429                         .parent_names = (const char *[]){
1430                                 "blsp1_qup5_spi_apps_clk_src",
1431                         },
1432                         .num_parents = 1,
1433                         .ops = &clk_branch2_ops,
1434                 },
1435         },
1436 };
1437
1438 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1439         .halt_reg = 0x23008,
1440         .halt_check = BRANCH_HALT,
1441         .clkr = {
1442                 .enable_reg = 0x23008,
1443                 .enable_mask = BIT(0),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1446                         .parent_names = (const char *[]){
1447                                 "blsp1_qup6_i2c_apps_clk_src",
1448                         },
1449                         .num_parents = 1,
1450                         .ops = &clk_branch2_ops,
1451                 },
1452         },
1453 };
1454
1455 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1456         .halt_reg = 0x23004,
1457         .halt_check = BRANCH_HALT,
1458         .clkr = {
1459                 .enable_reg = 0x23004,
1460                 .enable_mask = BIT(0),
1461                 .hw.init = &(struct clk_init_data){
1462                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1463                         .parent_names = (const char *[]){
1464                                 "blsp1_qup6_spi_apps_clk_src",
1465                         },
1466                         .num_parents = 1,
1467                         .ops = &clk_branch2_ops,
1468                 },
1469         },
1470 };
1471
1472 static struct clk_branch gcc_blsp1_sleep_clk = {
1473         .halt_reg = 0x17008,
1474         .halt_check = BRANCH_HALT_VOTED,
1475         .clkr = {
1476                 .enable_reg = 0x52004,
1477                 .enable_mask = BIT(16),
1478                 .hw.init = &(struct clk_init_data){
1479                         .name = "gcc_blsp1_sleep_clk",
1480                         .ops = &clk_branch2_ops,
1481                 },
1482         },
1483 };
1484
1485 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1486         .halt_reg = 0x1a004,
1487         .halt_check = BRANCH_HALT,
1488         .clkr = {
1489                 .enable_reg = 0x1a004,
1490                 .enable_mask = BIT(0),
1491                 .hw.init = &(struct clk_init_data){
1492                         .name = "gcc_blsp1_uart1_apps_clk",
1493                         .parent_names = (const char *[]){
1494                                 "blsp1_uart1_apps_clk_src",
1495                         },
1496                         .num_parents = 1,
1497                         .ops = &clk_branch2_ops,
1498                 },
1499         },
1500 };
1501
1502 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1503         .halt_reg = 0x1c004,
1504         .halt_check = BRANCH_HALT,
1505         .clkr = {
1506                 .enable_reg = 0x1c004,
1507                 .enable_mask = BIT(0),
1508                 .hw.init = &(struct clk_init_data){
1509                         .name = "gcc_blsp1_uart2_apps_clk",
1510                         .parent_names = (const char *[]){
1511                                 "blsp1_uart2_apps_clk_src",
1512                         },
1513                         .num_parents = 1,
1514                         .ops = &clk_branch2_ops,
1515                 },
1516         },
1517 };
1518
1519 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1520         .halt_reg = 0x1e004,
1521         .halt_check = BRANCH_HALT,
1522         .clkr = {
1523                 .enable_reg = 0x1e004,
1524                 .enable_mask = BIT(0),
1525                 .hw.init = &(struct clk_init_data){
1526                         .name = "gcc_blsp1_uart3_apps_clk",
1527                         .parent_names = (const char *[]){
1528                                 "blsp1_uart3_apps_clk_src",
1529                         },
1530                         .num_parents = 1,
1531                         .ops = &clk_branch2_ops,
1532                 },
1533         },
1534 };
1535
1536 static struct clk_branch gcc_blsp2_ahb_clk = {
1537         .halt_reg = 0x25004,
1538         .halt_check = BRANCH_HALT_VOTED,
1539         .clkr = {
1540                 .enable_reg = 0x52004,
1541                 .enable_mask = BIT(15),
1542                 .hw.init = &(struct clk_init_data){
1543                         .name = "gcc_blsp2_ahb_clk",
1544                         .ops = &clk_branch2_ops,
1545                 },
1546         },
1547 };
1548
1549 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1550         .halt_reg = 0x26008,
1551         .halt_check = BRANCH_HALT,
1552         .clkr = {
1553                 .enable_reg = 0x26008,
1554                 .enable_mask = BIT(0),
1555                 .hw.init = &(struct clk_init_data){
1556                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1557                         .parent_names = (const char *[]){
1558                                 "blsp2_qup1_i2c_apps_clk_src",
1559                         },
1560                         .num_parents = 1,
1561                         .ops = &clk_branch2_ops,
1562                 },
1563         },
1564 };
1565
1566 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1567         .halt_reg = 0x26004,
1568         .halt_check = BRANCH_HALT,
1569         .clkr = {
1570                 .enable_reg = 0x26004,
1571                 .enable_mask = BIT(0),
1572                 .hw.init = &(struct clk_init_data){
1573                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1574                         .parent_names = (const char *[]){
1575                                 "blsp2_qup1_spi_apps_clk_src",
1576                         },
1577                         .num_parents = 1,
1578                         .ops = &clk_branch2_ops,
1579                 },
1580         },
1581 };
1582
1583 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1584         .halt_reg = 0x28008,
1585         .halt_check = BRANCH_HALT,
1586         .clkr = {
1587                 .enable_reg = 0x28008,
1588                 .enable_mask = BIT(0),
1589                 .hw.init = &(struct clk_init_data){
1590                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1591                         .parent_names = (const char *[]){
1592                                 "blsp2_qup2_i2c_apps_clk_src",
1593                         },
1594                         .num_parents = 1,
1595                         .ops = &clk_branch2_ops,
1596                 },
1597         },
1598 };
1599
1600 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1601         .halt_reg = 0x28004,
1602         .halt_check = BRANCH_HALT,
1603         .clkr = {
1604                 .enable_reg = 0x28004,
1605                 .enable_mask = BIT(0),
1606                 .hw.init = &(struct clk_init_data){
1607                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1608                         .parent_names = (const char *[]){
1609                                 "blsp2_qup2_spi_apps_clk_src",
1610                         },
1611                         .num_parents = 1,
1612                         .ops = &clk_branch2_ops,
1613                 },
1614         },
1615 };
1616
1617 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1618         .halt_reg = 0x2a008,
1619         .halt_check = BRANCH_HALT,
1620         .clkr = {
1621                 .enable_reg = 0x2a008,
1622                 .enable_mask = BIT(0),
1623                 .hw.init = &(struct clk_init_data){
1624                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1625                         .parent_names = (const char *[]){
1626                                 "blsp2_qup3_i2c_apps_clk_src",
1627                         },
1628                         .num_parents = 1,
1629                         .ops = &clk_branch2_ops,
1630                 },
1631         },
1632 };
1633
1634 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1635         .halt_reg = 0x2a004,
1636         .halt_check = BRANCH_HALT,
1637         .clkr = {
1638                 .enable_reg = 0x2a004,
1639                 .enable_mask = BIT(0),
1640                 .hw.init = &(struct clk_init_data){
1641                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1642                         .parent_names = (const char *[]){
1643                                 "blsp2_qup3_spi_apps_clk_src",
1644                         },
1645                         .num_parents = 1,
1646                         .ops = &clk_branch2_ops,
1647                 },
1648         },
1649 };
1650
1651 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1652         .halt_reg = 0x2c008,
1653         .halt_check = BRANCH_HALT,
1654         .clkr = {
1655                 .enable_reg = 0x2c008,
1656                 .enable_mask = BIT(0),
1657                 .hw.init = &(struct clk_init_data){
1658                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1659                         .parent_names = (const char *[]){
1660                                 "blsp2_qup4_i2c_apps_clk_src",
1661                         },
1662                         .num_parents = 1,
1663                         .ops = &clk_branch2_ops,
1664                 },
1665         },
1666 };
1667
1668 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1669         .halt_reg = 0x2c004,
1670         .halt_check = BRANCH_HALT,
1671         .clkr = {
1672                 .enable_reg = 0x2c004,
1673                 .enable_mask = BIT(0),
1674                 .hw.init = &(struct clk_init_data){
1675                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1676                         .parent_names = (const char *[]){
1677                                 "blsp2_qup4_spi_apps_clk_src",
1678                         },
1679                         .num_parents = 1,
1680                         .ops = &clk_branch2_ops,
1681                 },
1682         },
1683 };
1684
1685 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1686         .halt_reg = 0x2e008,
1687         .halt_check = BRANCH_HALT,
1688         .clkr = {
1689                 .enable_reg = 0x2e008,
1690                 .enable_mask = BIT(0),
1691                 .hw.init = &(struct clk_init_data){
1692                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1693                         .parent_names = (const char *[]){
1694                                 "blsp2_qup5_i2c_apps_clk_src",
1695                         },
1696                         .num_parents = 1,
1697                         .ops = &clk_branch2_ops,
1698                 },
1699         },
1700 };
1701
1702 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1703         .halt_reg = 0x2e004,
1704         .halt_check = BRANCH_HALT,
1705         .clkr = {
1706                 .enable_reg = 0x2e004,
1707                 .enable_mask = BIT(0),
1708                 .hw.init = &(struct clk_init_data){
1709                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1710                         .parent_names = (const char *[]){
1711                                 "blsp2_qup5_spi_apps_clk_src",
1712                         },
1713                         .num_parents = 1,
1714                         .ops = &clk_branch2_ops,
1715                 },
1716         },
1717 };
1718
1719 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1720         .halt_reg = 0x30008,
1721         .halt_check = BRANCH_HALT,
1722         .clkr = {
1723                 .enable_reg = 0x30008,
1724                 .enable_mask = BIT(0),
1725                 .hw.init = &(struct clk_init_data){
1726                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1727                         .parent_names = (const char *[]){
1728                                 "blsp2_qup6_i2c_apps_clk_src",
1729                         },
1730                         .num_parents = 1,
1731                         .ops = &clk_branch2_ops,
1732                 },
1733         },
1734 };
1735
1736 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1737         .halt_reg = 0x30004,
1738         .halt_check = BRANCH_HALT,
1739         .clkr = {
1740                 .enable_reg = 0x30004,
1741                 .enable_mask = BIT(0),
1742                 .hw.init = &(struct clk_init_data){
1743                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1744                         .parent_names = (const char *[]){
1745                                 "blsp2_qup6_spi_apps_clk_src",
1746                         },
1747                         .num_parents = 1,
1748                         .ops = &clk_branch2_ops,
1749                 },
1750         },
1751 };
1752
1753 static struct clk_branch gcc_blsp2_sleep_clk = {
1754         .halt_reg = 0x25008,
1755         .halt_check = BRANCH_HALT_VOTED,
1756         .clkr = {
1757                 .enable_reg = 0x52004,
1758                 .enable_mask = BIT(14),
1759                 .hw.init = &(struct clk_init_data){
1760                         .name = "gcc_blsp2_sleep_clk",
1761                         .ops = &clk_branch2_ops,
1762                 },
1763         },
1764 };
1765
1766 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1767         .halt_reg = 0x27004,
1768         .halt_check = BRANCH_HALT,
1769         .clkr = {
1770                 .enable_reg = 0x27004,
1771                 .enable_mask = BIT(0),
1772                 .hw.init = &(struct clk_init_data){
1773                         .name = "gcc_blsp2_uart1_apps_clk",
1774                         .parent_names = (const char *[]){
1775                                 "blsp2_uart1_apps_clk_src",
1776                         },
1777                         .num_parents = 1,
1778                         .ops = &clk_branch2_ops,
1779                 },
1780         },
1781 };
1782
1783 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1784         .halt_reg = 0x29004,
1785         .halt_check = BRANCH_HALT,
1786         .clkr = {
1787                 .enable_reg = 0x29004,
1788                 .enable_mask = BIT(0),
1789                 .hw.init = &(struct clk_init_data){
1790                         .name = "gcc_blsp2_uart2_apps_clk",
1791                         .parent_names = (const char *[]){
1792                                 "blsp2_uart2_apps_clk_src",
1793                         },
1794                         .num_parents = 1,
1795                         .ops = &clk_branch2_ops,
1796                 },
1797         },
1798 };
1799
1800 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1801         .halt_reg = 0x2b004,
1802         .halt_check = BRANCH_HALT,
1803         .clkr = {
1804                 .enable_reg = 0x2b004,
1805                 .enable_mask = BIT(0),
1806                 .hw.init = &(struct clk_init_data){
1807                         .name = "gcc_blsp2_uart3_apps_clk",
1808                         .parent_names = (const char *[]){
1809                                 "blsp2_uart3_apps_clk_src",
1810                         },
1811                         .num_parents = 1,
1812                         .ops = &clk_branch2_ops,
1813                 },
1814         },
1815 };
1816
1817 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1818         .halt_reg = 0x5018,
1819         .halt_check = BRANCH_HALT,
1820         .clkr = {
1821                 .enable_reg = 0x5018,
1822                 .enable_mask = BIT(0),
1823                 .hw.init = &(struct clk_init_data){
1824                         .name = "gcc_cfg_noc_usb3_axi_clk",
1825                         .parent_names = (const char *[]){
1826                                 "usb30_master_clk_src",
1827                         },
1828                         .num_parents = 1,
1829                         .ops = &clk_branch2_ops,
1830                 },
1831         },
1832 };
1833
1834 static struct clk_branch gcc_gp1_clk = {
1835         .halt_reg = 0x64000,
1836         .halt_check = BRANCH_HALT,
1837         .clkr = {
1838                 .enable_reg = 0x64000,
1839                 .enable_mask = BIT(0),
1840                 .hw.init = &(struct clk_init_data){
1841                         .name = "gcc_gp1_clk",
1842                         .parent_names = (const char *[]){
1843                                 "gp1_clk_src",
1844                         },
1845                         .num_parents = 1,
1846                         .ops = &clk_branch2_ops,
1847                 },
1848         },
1849 };
1850
1851 static struct clk_branch gcc_gp2_clk = {
1852         .halt_reg = 0x65000,
1853         .halt_check = BRANCH_HALT,
1854         .clkr = {
1855                 .enable_reg = 0x65000,
1856                 .enable_mask = BIT(0),
1857                 .hw.init = &(struct clk_init_data){
1858                         .name = "gcc_gp2_clk",
1859                         .parent_names = (const char *[]){
1860                                 "gp2_clk_src",
1861                         },
1862                         .num_parents = 1,
1863                         .ops = &clk_branch2_ops,
1864                 },
1865         },
1866 };
1867
1868 static struct clk_branch gcc_gp3_clk = {
1869         .halt_reg = 0x66000,
1870         .halt_check = BRANCH_HALT,
1871         .clkr = {
1872                 .enable_reg = 0x66000,
1873                 .enable_mask = BIT(0),
1874                 .hw.init = &(struct clk_init_data){
1875                         .name = "gcc_gp3_clk",
1876                         .parent_names = (const char *[]){
1877                                 "gp3_clk_src",
1878                         },
1879                         .num_parents = 1,
1880                         .ops = &clk_branch2_ops,
1881                 },
1882         },
1883 };
1884
1885 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1886         .halt_reg = 0x71010,
1887         .halt_check = BRANCH_HALT,
1888         .clkr = {
1889                 .enable_reg = 0x71010,
1890                 .enable_mask = BIT(0),
1891                 .hw.init = &(struct clk_init_data){
1892                         .name = "gcc_gpu_bimc_gfx_clk",
1893                         .ops = &clk_branch2_ops,
1894                 },
1895         },
1896 };
1897
1898 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
1899         .halt_reg = 0x7100c,
1900         .halt_check = BRANCH_HALT,
1901         .clkr = {
1902                 .enable_reg = 0x7100c,
1903                 .enable_mask = BIT(0),
1904                 .hw.init = &(struct clk_init_data){
1905                         .name = "gcc_gpu_bimc_gfx_src_clk",
1906                         .ops = &clk_branch2_ops,
1907                 },
1908         },
1909 };
1910
1911 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1912         .halt_reg = 0x71004,
1913         .halt_check = BRANCH_HALT,
1914         .clkr = {
1915                 .enable_reg = 0x71004,
1916                 .enable_mask = BIT(0),
1917                 .hw.init = &(struct clk_init_data){
1918                         .name = "gcc_gpu_cfg_ahb_clk",
1919                         .ops = &clk_branch2_ops,
1920                 },
1921         },
1922 };
1923
1924 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1925         .halt_reg = 0x71018,
1926         .halt_check = BRANCH_HALT,
1927         .clkr = {
1928                 .enable_reg = 0x71018,
1929                 .enable_mask = BIT(0),
1930                 .hw.init = &(struct clk_init_data){
1931                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1932                         .ops = &clk_branch2_ops,
1933                 },
1934         },
1935 };
1936
1937 static struct clk_branch gcc_hmss_ahb_clk = {
1938         .halt_reg = 0x48000,
1939         .halt_check = BRANCH_HALT_VOTED,
1940         .clkr = {
1941                 .enable_reg = 0x52004,
1942                 .enable_mask = BIT(21),
1943                 .hw.init = &(struct clk_init_data){
1944                         .name = "gcc_hmss_ahb_clk",
1945                         .parent_names = (const char *[]){
1946                                 "hmss_ahb_clk_src",
1947                         },
1948                         .num_parents = 1,
1949                         .ops = &clk_branch2_ops,
1950                 },
1951         },
1952 };
1953
1954 static struct clk_branch gcc_hmss_at_clk = {
1955         .halt_reg = 0x48010,
1956         .halt_check = BRANCH_HALT,
1957         .clkr = {
1958                 .enable_reg = 0x48010,
1959                 .enable_mask = BIT(0),
1960                 .hw.init = &(struct clk_init_data){
1961                         .name = "gcc_hmss_at_clk",
1962                         .ops = &clk_branch2_ops,
1963                 },
1964         },
1965 };
1966
1967 static struct clk_branch gcc_hmss_dvm_bus_clk = {
1968         .halt_reg = 0x4808c,
1969         .halt_check = BRANCH_HALT,
1970         .clkr = {
1971                 .enable_reg = 0x4808c,
1972                 .enable_mask = BIT(0),
1973                 .hw.init = &(struct clk_init_data){
1974                         .name = "gcc_hmss_dvm_bus_clk",
1975                         .ops = &clk_branch2_ops,
1976                 },
1977         },
1978 };
1979
1980 static struct clk_branch gcc_hmss_rbcpr_clk = {
1981         .halt_reg = 0x48008,
1982         .halt_check = BRANCH_HALT,
1983         .clkr = {
1984                 .enable_reg = 0x48008,
1985                 .enable_mask = BIT(0),
1986                 .hw.init = &(struct clk_init_data){
1987                         .name = "gcc_hmss_rbcpr_clk",
1988                         .parent_names = (const char *[]){
1989                                 "hmss_rbcpr_clk_src",
1990                         },
1991                         .num_parents = 1,
1992                         .ops = &clk_branch2_ops,
1993                 },
1994         },
1995 };
1996
1997 static struct clk_branch gcc_hmss_trig_clk = {
1998         .halt_reg = 0x4800c,
1999         .halt_check = BRANCH_HALT,
2000         .clkr = {
2001                 .enable_reg = 0x4800c,
2002                 .enable_mask = BIT(0),
2003                 .hw.init = &(struct clk_init_data){
2004                         .name = "gcc_hmss_trig_clk",
2005                         .ops = &clk_branch2_ops,
2006                 },
2007         },
2008 };
2009
2010 static struct clk_branch gcc_lpass_at_clk = {
2011         .halt_reg = 0x47020,
2012         .halt_check = BRANCH_HALT,
2013         .clkr = {
2014                 .enable_reg = 0x47020,
2015                 .enable_mask = BIT(0),
2016                 .hw.init = &(struct clk_init_data){
2017                         .name = "gcc_lpass_at_clk",
2018                         .ops = &clk_branch2_ops,
2019                 },
2020         },
2021 };
2022
2023 static struct clk_branch gcc_lpass_trig_clk = {
2024         .halt_reg = 0x4701c,
2025         .halt_check = BRANCH_HALT,
2026         .clkr = {
2027                 .enable_reg = 0x4701c,
2028                 .enable_mask = BIT(0),
2029                 .hw.init = &(struct clk_init_data){
2030                         .name = "gcc_lpass_trig_clk",
2031                         .ops = &clk_branch2_ops,
2032                 },
2033         },
2034 };
2035
2036 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
2037         .halt_reg = 0x9004,
2038         .halt_check = BRANCH_HALT,
2039         .clkr = {
2040                 .enable_reg = 0x9004,
2041                 .enable_mask = BIT(0),
2042                 .hw.init = &(struct clk_init_data){
2043                         .name = "gcc_mmss_noc_cfg_ahb_clk",
2044                         .ops = &clk_branch2_ops,
2045                 },
2046         },
2047 };
2048
2049 static struct clk_branch gcc_mmss_qm_ahb_clk = {
2050         .halt_reg = 0x9030,
2051         .halt_check = BRANCH_HALT,
2052         .clkr = {
2053                 .enable_reg = 0x9030,
2054                 .enable_mask = BIT(0),
2055                 .hw.init = &(struct clk_init_data){
2056                         .name = "gcc_mmss_qm_ahb_clk",
2057                         .ops = &clk_branch2_ops,
2058                 },
2059         },
2060 };
2061
2062 static struct clk_branch gcc_mmss_qm_core_clk = {
2063         .halt_reg = 0x900c,
2064         .halt_check = BRANCH_HALT,
2065         .clkr = {
2066                 .enable_reg = 0x900c,
2067                 .enable_mask = BIT(0),
2068                 .hw.init = &(struct clk_init_data){
2069                         .name = "gcc_mmss_qm_core_clk",
2070                         .ops = &clk_branch2_ops,
2071                 },
2072         },
2073 };
2074
2075 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
2076         .halt_reg = 0x9000,
2077         .halt_check = BRANCH_HALT,
2078         .clkr = {
2079                 .enable_reg = 0x9000,
2080                 .enable_mask = BIT(0),
2081                 .hw.init = &(struct clk_init_data){
2082                         .name = "gcc_mmss_sys_noc_axi_clk",
2083                         .ops = &clk_branch2_ops,
2084                 },
2085         },
2086 };
2087
2088 static struct clk_branch gcc_mss_at_clk = {
2089         .halt_reg = 0x8a00c,
2090         .halt_check = BRANCH_HALT,
2091         .clkr = {
2092                 .enable_reg = 0x8a00c,
2093                 .enable_mask = BIT(0),
2094                 .hw.init = &(struct clk_init_data){
2095                         .name = "gcc_mss_at_clk",
2096                         .ops = &clk_branch2_ops,
2097                 },
2098         },
2099 };
2100
2101 static struct clk_branch gcc_pcie_0_aux_clk = {
2102         .halt_reg = 0x6b014,
2103         .halt_check = BRANCH_HALT,
2104         .clkr = {
2105                 .enable_reg = 0x6b014,
2106                 .enable_mask = BIT(0),
2107                 .hw.init = &(struct clk_init_data){
2108                         .name = "gcc_pcie_0_aux_clk",
2109                         .parent_names = (const char *[]){
2110                                 "pcie_aux_clk_src",
2111                         },
2112                         .num_parents = 1,
2113                         .ops = &clk_branch2_ops,
2114                 },
2115         },
2116 };
2117
2118 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2119         .halt_reg = 0x6b010,
2120         .halt_check = BRANCH_HALT,
2121         .clkr = {
2122                 .enable_reg = 0x6b010,
2123                 .enable_mask = BIT(0),
2124                 .hw.init = &(struct clk_init_data){
2125                         .name = "gcc_pcie_0_cfg_ahb_clk",
2126                         .ops = &clk_branch2_ops,
2127                 },
2128         },
2129 };
2130
2131 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2132         .halt_reg = 0x6b00c,
2133         .halt_check = BRANCH_HALT,
2134         .clkr = {
2135                 .enable_reg = 0x6b00c,
2136                 .enable_mask = BIT(0),
2137                 .hw.init = &(struct clk_init_data){
2138                         .name = "gcc_pcie_0_mstr_axi_clk",
2139                         .ops = &clk_branch2_ops,
2140                 },
2141         },
2142 };
2143
2144 static struct clk_branch gcc_pcie_0_pipe_clk = {
2145         .halt_reg = 0x6b018,
2146         .halt_check = BRANCH_HALT,
2147         .clkr = {
2148                 .enable_reg = 0x6b018,
2149                 .enable_mask = BIT(0),
2150                 .hw.init = &(struct clk_init_data){
2151                         .name = "gcc_pcie_0_pipe_clk",
2152                         .ops = &clk_branch2_ops,
2153                 },
2154         },
2155 };
2156
2157 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2158         .halt_reg = 0x6b008,
2159         .halt_check = BRANCH_HALT,
2160         .clkr = {
2161                 .enable_reg = 0x6b008,
2162                 .enable_mask = BIT(0),
2163                 .hw.init = &(struct clk_init_data){
2164                         .name = "gcc_pcie_0_slv_axi_clk",
2165                         .ops = &clk_branch2_ops,
2166                 },
2167         },
2168 };
2169
2170 static struct clk_branch gcc_pcie_phy_aux_clk = {
2171         .halt_reg = 0x6f004,
2172         .halt_check = BRANCH_HALT,
2173         .clkr = {
2174                 .enable_reg = 0x6f004,
2175                 .enable_mask = BIT(0),
2176                 .hw.init = &(struct clk_init_data){
2177                         .name = "gcc_pcie_phy_aux_clk",
2178                         .parent_names = (const char *[]){
2179                                 "pcie_aux_clk_src",
2180                         },
2181                         .num_parents = 1,
2182                         .ops = &clk_branch2_ops,
2183                 },
2184         },
2185 };
2186
2187 static struct clk_branch gcc_pdm2_clk = {
2188         .halt_reg = 0x3300c,
2189         .halt_check = BRANCH_HALT,
2190         .clkr = {
2191                 .enable_reg = 0x3300c,
2192                 .enable_mask = BIT(0),
2193                 .hw.init = &(struct clk_init_data){
2194                         .name = "gcc_pdm2_clk",
2195                         .parent_names = (const char *[]){
2196                                 "pdm2_clk_src",
2197                         },
2198                         .num_parents = 1,
2199                         .ops = &clk_branch2_ops,
2200                 },
2201         },
2202 };
2203
2204 static struct clk_branch gcc_pdm_ahb_clk = {
2205         .halt_reg = 0x33004,
2206         .halt_check = BRANCH_HALT,
2207         .clkr = {
2208                 .enable_reg = 0x33004,
2209                 .enable_mask = BIT(0),
2210                 .hw.init = &(struct clk_init_data){
2211                         .name = "gcc_pdm_ahb_clk",
2212                         .ops = &clk_branch2_ops,
2213                 },
2214         },
2215 };
2216
2217 static struct clk_branch gcc_pdm_xo4_clk = {
2218         .halt_reg = 0x33008,
2219         .halt_check = BRANCH_HALT,
2220         .clkr = {
2221                 .enable_reg = 0x33008,
2222                 .enable_mask = BIT(0),
2223                 .hw.init = &(struct clk_init_data){
2224                         .name = "gcc_pdm_xo4_clk",
2225                         .ops = &clk_branch2_ops,
2226                 },
2227         },
2228 };
2229
2230 static struct clk_branch gcc_prng_ahb_clk = {
2231         .halt_reg = 0x34004,
2232         .halt_check = BRANCH_HALT_VOTED,
2233         .clkr = {
2234                 .enable_reg = 0x52004,
2235                 .enable_mask = BIT(13),
2236                 .hw.init = &(struct clk_init_data){
2237                         .name = "gcc_prng_ahb_clk",
2238                         .ops = &clk_branch2_ops,
2239                 },
2240         },
2241 };
2242
2243 static struct clk_branch gcc_sdcc2_ahb_clk = {
2244         .halt_reg = 0x14008,
2245         .halt_check = BRANCH_HALT,
2246         .clkr = {
2247                 .enable_reg = 0x14008,
2248                 .enable_mask = BIT(0),
2249                 .hw.init = &(struct clk_init_data){
2250                         .name = "gcc_sdcc2_ahb_clk",
2251                         .ops = &clk_branch2_ops,
2252                 },
2253         },
2254 };
2255
2256 static struct clk_branch gcc_sdcc2_apps_clk = {
2257         .halt_reg = 0x14004,
2258         .halt_check = BRANCH_HALT,
2259         .clkr = {
2260                 .enable_reg = 0x14004,
2261                 .enable_mask = BIT(0),
2262                 .hw.init = &(struct clk_init_data){
2263                         .name = "gcc_sdcc2_apps_clk",
2264                         .parent_names = (const char *[]){
2265                                 "sdcc2_apps_clk_src",
2266                         },
2267                         .num_parents = 1,
2268                         .ops = &clk_branch2_ops,
2269                 },
2270         },
2271 };
2272
2273 static struct clk_branch gcc_sdcc4_ahb_clk = {
2274         .halt_reg = 0x16008,
2275         .halt_check = BRANCH_HALT,
2276         .clkr = {
2277                 .enable_reg = 0x16008,
2278                 .enable_mask = BIT(0),
2279                 .hw.init = &(struct clk_init_data){
2280                         .name = "gcc_sdcc4_ahb_clk",
2281                         .ops = &clk_branch2_ops,
2282                 },
2283         },
2284 };
2285
2286 static struct clk_branch gcc_sdcc4_apps_clk = {
2287         .halt_reg = 0x16004,
2288         .halt_check = BRANCH_HALT,
2289         .clkr = {
2290                 .enable_reg = 0x16004,
2291                 .enable_mask = BIT(0),
2292                 .hw.init = &(struct clk_init_data){
2293                         .name = "gcc_sdcc4_apps_clk",
2294                         .parent_names = (const char *[]){
2295                                 "sdcc4_apps_clk_src",
2296                         },
2297                         .num_parents = 1,
2298                         .ops = &clk_branch2_ops,
2299                 },
2300         },
2301 };
2302
2303 static struct clk_branch gcc_tsif_ahb_clk = {
2304         .halt_reg = 0x36004,
2305         .halt_check = BRANCH_HALT,
2306         .clkr = {
2307                 .enable_reg = 0x36004,
2308                 .enable_mask = BIT(0),
2309                 .hw.init = &(struct clk_init_data){
2310                         .name = "gcc_tsif_ahb_clk",
2311                         .ops = &clk_branch2_ops,
2312                 },
2313         },
2314 };
2315
2316 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2317         .halt_reg = 0x3600c,
2318         .halt_check = BRANCH_HALT,
2319         .clkr = {
2320                 .enable_reg = 0x3600c,
2321                 .enable_mask = BIT(0),
2322                 .hw.init = &(struct clk_init_data){
2323                         .name = "gcc_tsif_inactivity_timers_clk",
2324                         .ops = &clk_branch2_ops,
2325                 },
2326         },
2327 };
2328
2329 static struct clk_branch gcc_tsif_ref_clk = {
2330         .halt_reg = 0x36008,
2331         .halt_check = BRANCH_HALT,
2332         .clkr = {
2333                 .enable_reg = 0x36008,
2334                 .enable_mask = BIT(0),
2335                 .hw.init = &(struct clk_init_data){
2336                         .name = "gcc_tsif_ref_clk",
2337                         .parent_names = (const char *[]){
2338                                 "tsif_ref_clk_src",
2339                         },
2340                         .num_parents = 1,
2341                         .ops = &clk_branch2_ops,
2342                 },
2343         },
2344 };
2345
2346 static struct clk_branch gcc_ufs_ahb_clk = {
2347         .halt_reg = 0x7500c,
2348         .halt_check = BRANCH_HALT,
2349         .clkr = {
2350                 .enable_reg = 0x7500c,
2351                 .enable_mask = BIT(0),
2352                 .hw.init = &(struct clk_init_data){
2353                         .name = "gcc_ufs_ahb_clk",
2354                         .ops = &clk_branch2_ops,
2355                 },
2356         },
2357 };
2358
2359 static struct clk_branch gcc_ufs_axi_clk = {
2360         .halt_reg = 0x75008,
2361         .halt_check = BRANCH_HALT,
2362         .clkr = {
2363                 .enable_reg = 0x75008,
2364                 .enable_mask = BIT(0),
2365                 .hw.init = &(struct clk_init_data){
2366                         .name = "gcc_ufs_axi_clk",
2367                         .parent_names = (const char *[]){
2368                                 "ufs_axi_clk_src",
2369                         },
2370                         .num_parents = 1,
2371                         .ops = &clk_branch2_ops,
2372                 },
2373         },
2374 };
2375
2376 static struct clk_branch gcc_ufs_ice_core_clk = {
2377         .halt_reg = 0x7600c,
2378         .halt_check = BRANCH_HALT,
2379         .clkr = {
2380                 .enable_reg = 0x7600c,
2381                 .enable_mask = BIT(0),
2382                 .hw.init = &(struct clk_init_data){
2383                         .name = "gcc_ufs_ice_core_clk",
2384                         .ops = &clk_branch2_ops,
2385                 },
2386         },
2387 };
2388
2389 static struct clk_branch gcc_ufs_phy_aux_clk = {
2390         .halt_reg = 0x76040,
2391         .halt_check = BRANCH_HALT,
2392         .clkr = {
2393                 .enable_reg = 0x76040,
2394                 .enable_mask = BIT(0),
2395                 .hw.init = &(struct clk_init_data){
2396                         .name = "gcc_ufs_phy_aux_clk",
2397                         .ops = &clk_branch2_ops,
2398                 },
2399         },
2400 };
2401
2402 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2403         .halt_reg = 0x75014,
2404         .halt_check = BRANCH_HALT,
2405         .clkr = {
2406                 .enable_reg = 0x75014,
2407                 .enable_mask = BIT(0),
2408                 .hw.init = &(struct clk_init_data){
2409                         .name = "gcc_ufs_rx_symbol_0_clk",
2410                         .ops = &clk_branch2_ops,
2411                 },
2412         },
2413 };
2414
2415 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2416         .halt_reg = 0x7605c,
2417         .halt_check = BRANCH_HALT,
2418         .clkr = {
2419                 .enable_reg = 0x7605c,
2420                 .enable_mask = BIT(0),
2421                 .hw.init = &(struct clk_init_data){
2422                         .name = "gcc_ufs_rx_symbol_1_clk",
2423                         .ops = &clk_branch2_ops,
2424                 },
2425         },
2426 };
2427
2428 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2429         .halt_reg = 0x75010,
2430         .halt_check = BRANCH_HALT,
2431         .clkr = {
2432                 .enable_reg = 0x75010,
2433                 .enable_mask = BIT(0),
2434                 .hw.init = &(struct clk_init_data){
2435                         .name = "gcc_ufs_tx_symbol_0_clk",
2436                         .ops = &clk_branch2_ops,
2437                 },
2438         },
2439 };
2440
2441 static struct clk_branch gcc_ufs_unipro_core_clk = {
2442         .halt_reg = 0x76008,
2443         .halt_check = BRANCH_HALT,
2444         .clkr = {
2445                 .enable_reg = 0x76008,
2446                 .enable_mask = BIT(0),
2447                 .hw.init = &(struct clk_init_data){
2448                         .name = "gcc_ufs_unipro_core_clk",
2449                         .ops = &clk_branch2_ops,
2450                 },
2451         },
2452 };
2453
2454 static struct clk_branch gcc_usb30_master_clk = {
2455         .halt_reg = 0xf008,
2456         .halt_check = BRANCH_HALT,
2457         .clkr = {
2458                 .enable_reg = 0xf008,
2459                 .enable_mask = BIT(0),
2460                 .hw.init = &(struct clk_init_data){
2461                         .name = "gcc_usb30_master_clk",
2462                         .parent_names = (const char *[]){
2463                                 "usb30_master_clk_src",
2464                         },
2465                         .num_parents = 1,
2466                         .ops = &clk_branch2_ops,
2467                 },
2468         },
2469 };
2470
2471 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2472         .halt_reg = 0xf010,
2473         .halt_check = BRANCH_HALT,
2474         .clkr = {
2475                 .enable_reg = 0xf010,
2476                 .enable_mask = BIT(0),
2477                 .hw.init = &(struct clk_init_data){
2478                         .name = "gcc_usb30_mock_utmi_clk",
2479                         .parent_names = (const char *[]){
2480                                 "usb30_mock_utmi_clk_src",
2481                         },
2482                         .num_parents = 1,
2483                         .ops = &clk_branch2_ops,
2484                 },
2485         },
2486 };
2487
2488 static struct clk_branch gcc_usb30_sleep_clk = {
2489         .halt_reg = 0xf00c,
2490         .halt_check = BRANCH_HALT,
2491         .clkr = {
2492                 .enable_reg = 0xf00c,
2493                 .enable_mask = BIT(0),
2494                 .hw.init = &(struct clk_init_data){
2495                         .name = "gcc_usb30_sleep_clk",
2496                         .ops = &clk_branch2_ops,
2497                 },
2498         },
2499 };
2500
2501 static struct clk_branch gcc_usb3_phy_aux_clk = {
2502         .halt_reg = 0x50000,
2503         .halt_check = BRANCH_HALT,
2504         .clkr = {
2505                 .enable_reg = 0x50000,
2506                 .enable_mask = BIT(0),
2507                 .hw.init = &(struct clk_init_data){
2508                         .name = "gcc_usb3_phy_aux_clk",
2509                         .parent_names = (const char *[]){
2510                                 "usb3_phy_aux_clk_src",
2511                         },
2512                         .num_parents = 1,
2513                         .ops = &clk_branch2_ops,
2514                 },
2515         },
2516 };
2517
2518 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2519         .halt_reg = 0x50004,
2520         .halt_check = BRANCH_HALT,
2521         .clkr = {
2522                 .enable_reg = 0x50004,
2523                 .enable_mask = BIT(0),
2524                 .hw.init = &(struct clk_init_data){
2525                         .name = "gcc_usb3_phy_pipe_clk",
2526                         .ops = &clk_branch2_ops,
2527                 },
2528         },
2529 };
2530
2531 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2532         .halt_reg = 0x6a004,
2533         .halt_check = BRANCH_HALT,
2534         .clkr = {
2535                 .enable_reg = 0x6a004,
2536                 .enable_mask = BIT(0),
2537                 .hw.init = &(struct clk_init_data){
2538                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2539                         .ops = &clk_branch2_ops,
2540                 },
2541         },
2542 };
2543
2544 static struct gdsc pcie_0_gdsc = {
2545         .gdscr = 0x6b004,
2546         .gds_hw_ctrl = 0x0,
2547         .pd = {
2548                 .name = "pcie_0_gdsc",
2549         },
2550         .pwrsts = PWRSTS_OFF_ON,
2551         .flags = VOTABLE,
2552 };
2553
2554 static struct gdsc ufs_gdsc = {
2555         .gdscr = 0x75004,
2556         .gds_hw_ctrl = 0x0,
2557         .pd = {
2558                 .name = "ufs_gdsc",
2559         },
2560         .pwrsts = PWRSTS_OFF_ON,
2561         .flags = VOTABLE,
2562 };
2563
2564 static struct gdsc usb_30_gdsc = {
2565         .gdscr = 0xf004,
2566         .gds_hw_ctrl = 0x0,
2567         .pd = {
2568                 .name = "usb_30_gdsc",
2569         },
2570         .pwrsts = PWRSTS_OFF_ON,
2571         .flags = VOTABLE,
2572 };
2573
2574 static struct clk_regmap *gcc_msm8998_clocks[] = {
2575         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2576         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2577         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2578         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2579         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2580         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2581         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2582         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2583         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2584         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2585         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2586         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2587         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2588         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2589         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2590         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2591         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2592         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2593         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2594         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2595         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2596         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2597         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2598         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2599         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2600         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2601         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2602         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2603         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2604         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2605         [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
2606         [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
2607         [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
2608         [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
2609         [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
2610         [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2611         [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2612         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2613         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2614         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2615         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2616         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2617         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2618         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2619         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2620         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2621         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2622         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2623         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2624         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2625         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2626         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2627         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2628         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2629         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2630         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2631         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2632         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2633         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2634         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2635         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2636         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2637         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2638         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2639         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2640         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2641         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2642         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
2643         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2644         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2645         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2646         [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2647         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2648         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2649         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2650         [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2651         [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
2652         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2653         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2654         [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
2655         [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
2656         [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2657         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2658         [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
2659         [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,
2660         [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,
2661         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2662         [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
2663         [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
2664         [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2665         [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
2666         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2667         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2668         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2669         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2670         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2671         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2672         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2673         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2674         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2675         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2676         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2677         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2678         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2679         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2680         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2681         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2682         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2683         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2684         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2685         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2686         [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2687         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2688         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2689         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2690         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2691         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2692         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2693         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2694         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2695         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2696         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2697         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2698         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2699         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2700         [GPLL0] = &gpll0.clkr,
2701         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2702         [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2703         [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2704         [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
2705         [GPLL1] = &gpll1.clkr,
2706         [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
2707         [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2708         [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
2709         [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
2710         [GPLL2] = &gpll2.clkr,
2711         [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
2712         [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2713         [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
2714         [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
2715         [GPLL3] = &gpll3.clkr,
2716         [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
2717         [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2718         [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
2719         [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
2720         [GPLL4] = &gpll4.clkr,
2721         [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
2722         [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2723         [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
2724         [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
2725         [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
2726         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2727         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
2728         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2729         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2730         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2731         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2732         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2733         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2734         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2735         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2736 };
2737
2738 static struct gdsc *gcc_msm8998_gdscs[] = {
2739         [PCIE_0_GDSC] = &pcie_0_gdsc,
2740         [UFS_GDSC] = &ufs_gdsc,
2741         [USB_30_GDSC] = &usb_30_gdsc,
2742 };
2743
2744 static const struct qcom_reset_map gcc_msm8998_resets[] = {
2745         [GCC_BLSP1_QUP1_BCR] = { 0x102400 },
2746         [GCC_BLSP1_QUP2_BCR] = { 0x110592 },
2747         [GCC_BLSP1_QUP3_BCR] = { 0x118784 },
2748         [GCC_BLSP1_QUP4_BCR] = { 0x126976 },
2749         [GCC_BLSP1_QUP5_BCR] = { 0x135168 },
2750         [GCC_BLSP1_QUP6_BCR] = { 0x143360 },
2751         [GCC_BLSP2_QUP1_BCR] = { 0x155648 },
2752         [GCC_BLSP2_QUP2_BCR] = { 0x163840 },
2753         [GCC_BLSP2_QUP3_BCR] = { 0x172032 },
2754         [GCC_BLSP2_QUP4_BCR] = { 0x180224 },
2755         [GCC_BLSP2_QUP5_BCR] = { 0x188416 },
2756         [GCC_BLSP2_QUP6_BCR] = { 0x196608 },
2757         [GCC_PCIE_0_BCR] = { 0x438272 },
2758         [GCC_PDM_BCR] = { 0x208896 },
2759         [GCC_SDCC2_BCR] = { 0x81920 },
2760         [GCC_SDCC4_BCR] = { 0x90112 },
2761         [GCC_TSIF_BCR] = { 0x221184 },
2762         [GCC_UFS_BCR] = { 0x479232 },
2763         [GCC_USB_30_BCR] = { 0x61440 },
2764 };
2765
2766 static const struct regmap_config gcc_msm8998_regmap_config = {
2767         .reg_bits       = 32,
2768         .reg_stride     = 4,
2769         .val_bits       = 32,
2770         .max_register   = 0x8f000,
2771         .fast_io        = true,
2772 };
2773
2774 static const struct qcom_cc_desc gcc_msm8998_desc = {
2775         .config = &gcc_msm8998_regmap_config,
2776         .clks = gcc_msm8998_clocks,
2777         .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
2778         .resets = gcc_msm8998_resets,
2779         .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
2780         .gdscs = gcc_msm8998_gdscs,
2781         .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
2782 };
2783
2784 static int gcc_msm8998_probe(struct platform_device *pdev)
2785 {
2786         struct regmap *regmap;
2787         int ret;
2788
2789         regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
2790         if (IS_ERR(regmap))
2791                 return PTR_ERR(regmap);
2792
2793         /*
2794          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2795          * turned off by hardware during certain apps low power modes.
2796          */
2797         ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2798         if (ret)
2799                 return ret;
2800
2801         return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
2802 }
2803
2804 static const struct of_device_id gcc_msm8998_match_table[] = {
2805         { .compatible = "qcom,gcc-msm8998" },
2806         { }
2807 };
2808 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
2809
2810 static struct platform_driver gcc_msm8998_driver = {
2811         .probe          = gcc_msm8998_probe,
2812         .driver         = {
2813                 .name   = "gcc-msm8998",
2814                 .of_match_table = gcc_msm8998_match_table,
2815         },
2816 };
2817
2818 static int __init gcc_msm8998_init(void)
2819 {
2820         return platform_driver_register(&gcc_msm8998_driver);
2821 }
2822 core_initcall(gcc_msm8998_init);
2823
2824 static void __exit gcc_msm8998_exit(void)
2825 {
2826         platform_driver_unregister(&gcc_msm8998_driver);
2827 }
2828 module_exit(gcc_msm8998_exit);
2829
2830 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
2831 MODULE_LICENSE("GPL v2");
2832 MODULE_ALIAS("platform:gcc-msm8998");