drivers/clk/qcom/gcc-msm8916.c

   1 /*
   2  * Copyright 2015 Linaro Limited
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  26 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 enum {
  36         P_XO,
  37         P_GPLL0,
  38         P_GPLL0_AUX,
  39         P_BIMC,
  40         P_GPLL1,
  41         P_GPLL1_AUX,
  42         P_GPLL2,
  43         P_GPLL2_AUX,
  44         P_SLEEP_CLK,
  45         P_DSI0_PHYPLL_BYTE,
  46         P_DSI0_PHYPLL_DSI,
  47 };
  48
  49 static const struct parent_map gcc_xo_gpll0_map[] = {
  50         { P_XO, 0 },
  51         { P_GPLL0, 1 },
  52 };
  53
  54 static const char *gcc_xo_gpll0[] = {
  55         "xo",
  56         "gpll0_vote",
  57 };
  58
  59 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
  60         { P_XO, 0 },
  61         { P_GPLL0, 1 },
  62         { P_BIMC, 2 },
  63 };
  64
  65 static const char *gcc_xo_gpll0_bimc[] = {
  66         "xo",
  67         "gpll0_vote",
  68         "bimc_pll_vote",
  69 };
  70
  71 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
  72         { P_XO, 0 },
  73         { P_GPLL0_AUX, 3 },
  74         { P_GPLL2_AUX, 2 },
  75         { P_GPLL1, 1 },
  76 };
  77
  78 static const char *gcc_xo_gpll0a_gpll1_gpll2a[] = {
  79         "xo",
  80         "gpll0_vote",
  81         "gpll1_vote",
  82         "gpll2_vote",
  83 };
  84
  85 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
  86         { P_XO, 0 },
  87         { P_GPLL0, 1 },
  88         { P_GPLL2, 2 },
  89 };
  90
  91 static const char *gcc_xo_gpll0_gpll2[] = {
  92         "xo",
  93         "gpll0_vote",
  94         "gpll2_vote",
  95 };
  96
  97 static const struct parent_map gcc_xo_gpll0a_map[] = {
  98         { P_XO, 0 },
  99         { P_GPLL0_AUX, 2 },
 100 };
 101
 102 static const char *gcc_xo_gpll0a[] = {
 103         "xo",
 104         "gpll0_vote",
 105 };
 106
 107 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 108         { P_XO, 0 },
 109         { P_GPLL0, 1 },
 110         { P_GPLL1_AUX, 2 },
 111         { P_SLEEP_CLK, 6 },
 112 };
 113
 114 static const char *gcc_xo_gpll0_gpll1a_sleep[] = {
 115         "xo",
 116         "gpll0_vote",
 117         "gpll1_vote",
 118         "sleep_clk",
 119 };
 120
 121 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 122         { P_XO, 0 },
 123         { P_GPLL0, 1 },
 124         { P_GPLL1_AUX, 2 },
 125 };
 126
 127 static const char *gcc_xo_gpll0_gpll1a[] = {
 128         "xo",
 129         "gpll0_vote",
 130         "gpll1_vote",
 131 };
 132
 133 static const struct parent_map gcc_xo_dsibyte_map[] = {
 134         { P_XO, 0, },
 135         { P_DSI0_PHYPLL_BYTE, 2 },
 136 };
 137
 138 static const char *gcc_xo_dsibyte[] = {
 139         "xo",
 140         "dsi0pllbyte",
 141 };
 142
 143 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 144         { P_XO, 0 },
 145         { P_GPLL0_AUX, 2 },
 146         { P_DSI0_PHYPLL_BYTE, 1 },
 147 };
 148
 149 static const char *gcc_xo_gpll0a_dsibyte[] = {
 150         "xo",
 151         "gpll0_vote",
 152         "dsi0pllbyte",
 153 };
 154
 155 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
 156         { P_XO, 0 },
 157         { P_GPLL0, 1 },
 158         { P_DSI0_PHYPLL_DSI, 2 },
 159 };
 160
 161 static const char *gcc_xo_gpll0_dsiphy[] = {
 162         "xo",
 163         "gpll0_vote",
 164         "dsi0pll",
 165 };
 166
 167 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 168         { P_XO, 0 },
 169         { P_GPLL0_AUX, 2 },
 170         { P_DSI0_PHYPLL_DSI, 1 },
 171 };
 172
 173 static const char *gcc_xo_gpll0a_dsiphy[] = {
 174         "xo",
 175         "gpll0_vote",
 176         "dsi0pll",
 177 };
 178
 179 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
 180         { P_XO, 0 },
 181         { P_GPLL0_AUX, 1 },
 182         { P_GPLL1, 3 },
 183         { P_GPLL2, 2 },
 184 };
 185
 186 static const char *gcc_xo_gpll0a_gpll1_gpll2[] = {
 187         "xo",
 188         "gpll0_vote",
 189         "gpll1_vote",
 190         "gpll2_vote",
 191 };
 192
 193 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 194
 195 static struct clk_pll gpll0 = {
 196         .l_reg = 0x21004,
 197         .m_reg = 0x21008,
 198         .n_reg = 0x2100c,
 199         .config_reg = 0x21014,
 200         .mode_reg = 0x21000,
 201         .status_reg = 0x2101c,
 202         .status_bit = 17,
 203         .clkr.hw.init = &(struct clk_init_data){
 204                 .name = "gpll0",
 205                 .parent_names = (const char *[]){ "xo" },
 206                 .num_parents = 1,
 207                 .ops = &clk_pll_ops,
 208         },
 209 };
 210
 211 static struct clk_regmap gpll0_vote = {
 212         .enable_reg = 0x45000,
 213         .enable_mask = BIT(0),
 214         .hw.init = &(struct clk_init_data){
 215                 .name = "gpll0_vote",
 216                 .parent_names = (const char *[]){ "gpll0" },
 217                 .num_parents = 1,
 218                 .ops = &clk_pll_vote_ops,
 219         },
 220 };
 221
 222 static struct clk_pll gpll1 = {
 223         .l_reg = 0x20004,
 224         .m_reg = 0x20008,
 225         .n_reg = 0x2000c,
 226         .config_reg = 0x20014,
 227         .mode_reg = 0x20000,
 228         .status_reg = 0x2001c,
 229         .status_bit = 17,
 230         .clkr.hw.init = &(struct clk_init_data){
 231                 .name = "gpll1",
 232                 .parent_names = (const char *[]){ "xo" },
 233                 .num_parents = 1,
 234                 .ops = &clk_pll_ops,
 235         },
 236 };
 237
 238 static struct clk_regmap gpll1_vote = {
 239         .enable_reg = 0x45000,
 240         .enable_mask = BIT(1),
 241         .hw.init = &(struct clk_init_data){
 242                 .name = "gpll1_vote",
 243                 .parent_names = (const char *[]){ "gpll1" },
 244                 .num_parents = 1,
 245                 .ops = &clk_pll_vote_ops,
 246         },
 247 };
 248
 249 static struct clk_pll gpll2 = {
 250         .l_reg = 0x4a004,
 251         .m_reg = 0x4a008,
 252         .n_reg = 0x4a00c,
 253         .config_reg = 0x4a014,
 254         .mode_reg = 0x4a000,
 255         .status_reg = 0x4a01c,
 256         .status_bit = 17,
 257         .clkr.hw.init = &(struct clk_init_data){
 258                 .name = "gpll2",
 259                 .parent_names = (const char *[]){ "xo" },
 260                 .num_parents = 1,
 261                 .ops = &clk_pll_ops,
 262         },
 263 };
 264
 265 static struct clk_regmap gpll2_vote = {
 266         .enable_reg = 0x45000,
 267         .enable_mask = BIT(2),
 268         .hw.init = &(struct clk_init_data){
 269                 .name = "gpll2_vote",
 270                 .parent_names = (const char *[]){ "gpll2" },
 271                 .num_parents = 1,
 272                 .ops = &clk_pll_vote_ops,
 273         },
 274 };
 275
 276 static struct clk_pll bimc_pll = {
 277         .l_reg = 0x23004,
 278         .m_reg = 0x23008,
 279         .n_reg = 0x2300c,
 280         .config_reg = 0x23014,
 281         .mode_reg = 0x23000,
 282         .status_reg = 0x2301c,
 283         .status_bit = 17,
 284         .clkr.hw.init = &(struct clk_init_data){
 285                 .name = "bimc_pll",
 286                 .parent_names = (const char *[]){ "xo" },
 287                 .num_parents = 1,
 288                 .ops = &clk_pll_ops,
 289         },
 290 };
 291
 292 static struct clk_regmap bimc_pll_vote = {
 293         .enable_reg = 0x45000,
 294         .enable_mask = BIT(3),
 295         .hw.init = &(struct clk_init_data){
 296                 .name = "bimc_pll_vote",
 297                 .parent_names = (const char *[]){ "bimc_pll" },
 298                 .num_parents = 1,
 299                 .ops = &clk_pll_vote_ops,
 300         },
 301 };
 302
 303 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 304         .cmd_rcgr = 0x27000,
 305         .hid_width = 5,
 306         .parent_map = gcc_xo_gpll0_bimc_map,
 307         .clkr.hw.init = &(struct clk_init_data){
 308                 .name = "pcnoc_bfdcd_clk_src",
 309                 .parent_names = gcc_xo_gpll0_bimc,
 310                 .num_parents = 3,
 311                 .ops = &clk_rcg2_ops,
 312         },
 313 };
 314
 315 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 316         .cmd_rcgr = 0x26004,
 317         .hid_width = 5,
 318         .parent_map = gcc_xo_gpll0_bimc_map,
 319         .clkr.hw.init = &(struct clk_init_data){
 320                 .name = "system_noc_bfdcd_clk_src",
 321                 .parent_names = gcc_xo_gpll0_bimc,
 322                 .num_parents = 3,
 323                 .ops = &clk_rcg2_ops,
 324         },
 325 };
 326
 327 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 328         F(40000000, P_GPLL0, 10, 1, 2),
 329         F(80000000, P_GPLL0, 10, 0, 0),
 330         { }
 331 };
 332
 333 static struct clk_rcg2 camss_ahb_clk_src = {
 334         .cmd_rcgr = 0x5a000,
 335         .mnd_width = 8,
 336         .hid_width = 5,
 337         .parent_map = gcc_xo_gpll0_map,
 338         .freq_tbl = ftbl_gcc_camss_ahb_clk,
 339         .clkr.hw.init = &(struct clk_init_data){
 340                 .name = "camss_ahb_clk_src",
 341                 .parent_names = gcc_xo_gpll0,
 342                 .num_parents = 2,
 343                 .ops = &clk_rcg2_ops,
 344         },
 345 };
 346
 347 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 348         F(19200000, P_XO, 1, 0, 0),
 349         F(50000000, P_GPLL0, 16, 0, 0),
 350         F(100000000, P_GPLL0, 8, 0, 0),
 351         F(133330000, P_GPLL0, 6, 0, 0),
 352         { }
 353 };
 354
 355 static struct clk_rcg2 apss_ahb_clk_src = {
 356         .cmd_rcgr = 0x46000,
 357         .hid_width = 5,
 358         .parent_map = gcc_xo_gpll0_map,
 359         .freq_tbl = ftbl_apss_ahb_clk,
 360         .clkr.hw.init = &(struct clk_init_data){
 361                 .name = "apss_ahb_clk_src",
 362                 .parent_names = gcc_xo_gpll0,
 363                 .num_parents = 2,
 364                 .ops = &clk_rcg2_ops,
 365         },
 366 };
 367
 368 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 369         F(100000000, P_GPLL0, 8, 0,     0),
 370         F(200000000, P_GPLL0, 4, 0,     0),
 371         { }
 372 };
 373
 374 static struct clk_rcg2 csi0_clk_src = {
 375         .cmd_rcgr = 0x4e020,
 376         .hid_width = 5,
 377         .parent_map = gcc_xo_gpll0_map,
 378         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 379         .clkr.hw.init = &(struct clk_init_data){
 380                 .name = "csi0_clk_src",
 381                 .parent_names = gcc_xo_gpll0,
 382                 .num_parents = 2,
 383                 .ops = &clk_rcg2_ops,
 384         },
 385 };
 386
 387 static struct clk_rcg2 csi1_clk_src = {
 388         .cmd_rcgr = 0x4f020,
 389         .hid_width = 5,
 390         .parent_map = gcc_xo_gpll0_map,
 391         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 392         .clkr.hw.init = &(struct clk_init_data){
 393                 .name = "csi1_clk_src",
 394                 .parent_names = gcc_xo_gpll0,
 395                 .num_parents = 2,
 396                 .ops = &clk_rcg2_ops,
 397         },
 398 };
 399
 400 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 401         F(19200000, P_XO, 1, 0, 0),
 402         F(50000000, P_GPLL0_AUX, 16, 0, 0),
 403         F(80000000, P_GPLL0_AUX, 10, 0, 0),
 404         F(100000000, P_GPLL0_AUX, 8, 0, 0),
 405         F(160000000, P_GPLL0_AUX, 5, 0, 0),
 406         F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
 407         F(200000000, P_GPLL0_AUX, 4, 0, 0),
 408         F(266670000, P_GPLL0_AUX, 3, 0, 0),
 409         F(294912000, P_GPLL1, 3, 0, 0),
 410         F(310000000, P_GPLL2, 3, 0, 0),
 411         F(400000000, P_GPLL0_AUX, 2, 0, 0),
 412         { }
 413 };
 414
 415 static struct clk_rcg2 gfx3d_clk_src = {
 416         .cmd_rcgr = 0x59000,
 417         .hid_width = 5,
 418         .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
 419         .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 420         .clkr.hw.init = &(struct clk_init_data){
 421                 .name = "gfx3d_clk_src",
 422                 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
 423                 .num_parents = 4,
 424                 .ops = &clk_rcg2_ops,
 425         },
 426 };
 427
 428 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 429         F(50000000, P_GPLL0, 16, 0, 0),
 430         F(80000000, P_GPLL0, 10, 0, 0),
 431         F(100000000, P_GPLL0, 8, 0, 0),
 432         F(160000000, P_GPLL0, 5, 0, 0),
 433         F(177780000, P_GPLL0, 4.5, 0, 0),
 434         F(200000000, P_GPLL0, 4, 0, 0),
 435         F(266670000, P_GPLL0, 3, 0, 0),
 436         F(320000000, P_GPLL0, 2.5, 0, 0),
 437         F(400000000, P_GPLL0, 2, 0, 0),
 438         F(465000000, P_GPLL2, 2, 0, 0),
 439         { }
 440 };
 441
 442 static struct clk_rcg2 vfe0_clk_src = {
 443         .cmd_rcgr = 0x58000,
 444         .hid_width = 5,
 445         .parent_map = gcc_xo_gpll0_gpll2_map,
 446         .freq_tbl = ftbl_gcc_camss_vfe0_clk,
 447         .clkr.hw.init = &(struct clk_init_data){
 448                 .name = "vfe0_clk_src",
 449                 .parent_names = gcc_xo_gpll0_gpll2,
 450                 .num_parents = 3,
 451                 .ops = &clk_rcg2_ops,
 452         },
 453 };
 454
 455 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 456         F(19200000, P_XO, 1, 0, 0),
 457         F(50000000, P_GPLL0, 16, 0, 0),
 458         { }
 459 };
 460
 461 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 462         .cmd_rcgr = 0x0200c,
 463         .hid_width = 5,
 464         .parent_map = gcc_xo_gpll0_map,
 465         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 466         .clkr.hw.init = &(struct clk_init_data){
 467                 .name = "blsp1_qup1_i2c_apps_clk_src",
 468                 .parent_names = gcc_xo_gpll0,
 469                 .num_parents = 2,
 470                 .ops = &clk_rcg2_ops,
 471         },
 472 };
 473
 474 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 475         F(960000, P_XO, 10, 1, 2),
 476         F(4800000, P_XO, 4, 0, 0),
 477         F(9600000, P_XO, 2, 0, 0),
 478         F(16000000, P_GPLL0, 10, 1, 5),
 479         F(19200000, P_XO, 1, 0, 0),
 480         F(25000000, P_GPLL0, 16, 1, 2),
 481         F(50000000, P_GPLL0, 16, 0, 0),
 482         { }
 483 };
 484
 485 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 486         .cmd_rcgr = 0x02024,
 487         .mnd_width = 8,
 488         .hid_width = 5,
 489         .parent_map = gcc_xo_gpll0_map,
 490         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 491         .clkr.hw.init = &(struct clk_init_data){
 492                 .name = "blsp1_qup1_spi_apps_clk_src",
 493                 .parent_names = gcc_xo_gpll0,
 494                 .num_parents = 2,
 495                 .ops = &clk_rcg2_ops,
 496         },
 497 };
 498
 499 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 500         .cmd_rcgr = 0x03000,
 501         .hid_width = 5,
 502         .parent_map = gcc_xo_gpll0_map,
 503         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 504         .clkr.hw.init = &(struct clk_init_data){
 505                 .name = "blsp1_qup2_i2c_apps_clk_src",
 506                 .parent_names = gcc_xo_gpll0,
 507                 .num_parents = 2,
 508                 .ops = &clk_rcg2_ops,
 509         },
 510 };
 511
 512 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 513         .cmd_rcgr = 0x03014,
 514         .mnd_width = 8,
 515         .hid_width = 5,
 516         .parent_map = gcc_xo_gpll0_map,
 517         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 518         .clkr.hw.init = &(struct clk_init_data){
 519                 .name = "blsp1_qup2_spi_apps_clk_src",
 520                 .parent_names = gcc_xo_gpll0,
 521                 .num_parents = 2,
 522                 .ops = &clk_rcg2_ops,
 523         },
 524 };
 525
 526 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 527         .cmd_rcgr = 0x04000,
 528         .hid_width = 5,
 529         .parent_map = gcc_xo_gpll0_map,
 530         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 531         .clkr.hw.init = &(struct clk_init_data){
 532                 .name = "blsp1_qup3_i2c_apps_clk_src",
 533                 .parent_names = gcc_xo_gpll0,
 534                 .num_parents = 2,
 535                 .ops = &clk_rcg2_ops,
 536         },
 537 };
 538
 539 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 540         .cmd_rcgr = 0x04024,
 541         .mnd_width = 8,
 542         .hid_width = 5,
 543         .parent_map = gcc_xo_gpll0_map,
 544         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 545         .clkr.hw.init = &(struct clk_init_data){
 546                 .name = "blsp1_qup3_spi_apps_clk_src",
 547                 .parent_names = gcc_xo_gpll0,
 548                 .num_parents = 2,
 549                 .ops = &clk_rcg2_ops,
 550         },
 551 };
 552
 553 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 554         .cmd_rcgr = 0x05000,
 555         .hid_width = 5,
 556         .parent_map = gcc_xo_gpll0_map,
 557         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 558         .clkr.hw.init = &(struct clk_init_data){
 559                 .name = "blsp1_qup4_i2c_apps_clk_src",
 560                 .parent_names = gcc_xo_gpll0,
 561                 .num_parents = 2,
 562                 .ops = &clk_rcg2_ops,
 563         },
 564 };
 565
 566 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 567         .cmd_rcgr = 0x05024,
 568         .mnd_width = 8,
 569         .hid_width = 5,
 570         .parent_map = gcc_xo_gpll0_map,
 571         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 572         .clkr.hw.init = &(struct clk_init_data){
 573                 .name = "blsp1_qup4_spi_apps_clk_src",
 574                 .parent_names = gcc_xo_gpll0,
 575                 .num_parents = 2,
 576                 .ops = &clk_rcg2_ops,
 577         },
 578 };
 579
 580 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 581         .cmd_rcgr = 0x06000,
 582         .hid_width = 5,
 583         .parent_map = gcc_xo_gpll0_map,
 584         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 585         .clkr.hw.init = &(struct clk_init_data){
 586                 .name = "blsp1_qup5_i2c_apps_clk_src",
 587                 .parent_names = gcc_xo_gpll0,
 588                 .num_parents = 2,
 589                 .ops = &clk_rcg2_ops,
 590         },
 591 };
 592
 593 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 594         .cmd_rcgr = 0x06024,
 595         .mnd_width = 8,
 596         .hid_width = 5,
 597         .parent_map = gcc_xo_gpll0_map,
 598         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 599         .clkr.hw.init = &(struct clk_init_data){
 600                 .name = "blsp1_qup5_spi_apps_clk_src",
 601                 .parent_names = gcc_xo_gpll0,
 602                 .num_parents = 2,
 603                 .ops = &clk_rcg2_ops,
 604         },
 605 };
 606
 607 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 608         .cmd_rcgr = 0x07000,
 609         .hid_width = 5,
 610         .parent_map = gcc_xo_gpll0_map,
 611         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 612         .clkr.hw.init = &(struct clk_init_data){
 613                 .name = "blsp1_qup6_i2c_apps_clk_src",
 614                 .parent_names = gcc_xo_gpll0,
 615                 .num_parents = 2,
 616                 .ops = &clk_rcg2_ops,
 617         },
 618 };
 619
 620 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 621         .cmd_rcgr = 0x07024,
 622         .mnd_width = 8,
 623         .hid_width = 5,
 624         .parent_map = gcc_xo_gpll0_map,
 625         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 626         .clkr.hw.init = &(struct clk_init_data){
 627                 .name = "blsp1_qup6_spi_apps_clk_src",
 628                 .parent_names = gcc_xo_gpll0,
 629                 .num_parents = 2,
 630                 .ops = &clk_rcg2_ops,
 631         },
 632 };
 633
 634 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 635         F(3686400, P_GPLL0, 1, 72, 15625),
 636         F(7372800, P_GPLL0, 1, 144, 15625),
 637         F(14745600, P_GPLL0, 1, 288, 15625),
 638         F(16000000, P_GPLL0, 10, 1, 5),
 639         F(19200000, P_XO, 1, 0, 0),
 640         F(24000000, P_GPLL0, 1, 3, 100),
 641         F(25000000, P_GPLL0, 16, 1, 2),
 642         F(32000000, P_GPLL0, 1, 1, 25),
 643         F(40000000, P_GPLL0, 1, 1, 20),
 644         F(46400000, P_GPLL0, 1, 29, 500),
 645         F(48000000, P_GPLL0, 1, 3, 50),
 646         F(51200000, P_GPLL0, 1, 8, 125),
 647         F(56000000, P_GPLL0, 1, 7, 100),
 648         F(58982400, P_GPLL0, 1, 1152, 15625),
 649         F(60000000, P_GPLL0, 1, 3, 40),
 650         { }
 651 };
 652
 653 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 654         .cmd_rcgr = 0x02044,
 655         .mnd_width = 16,
 656         .hid_width = 5,
 657         .parent_map = gcc_xo_gpll0_map,
 658         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 659         .clkr.hw.init = &(struct clk_init_data){
 660                 .name = "blsp1_uart1_apps_clk_src",
 661                 .parent_names = gcc_xo_gpll0,
 662                 .num_parents = 2,
 663                 .ops = &clk_rcg2_ops,
 664         },
 665 };
 666
 667 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 668         .cmd_rcgr = 0x03034,
 669         .mnd_width = 16,
 670         .hid_width = 5,
 671         .parent_map = gcc_xo_gpll0_map,
 672         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 673         .clkr.hw.init = &(struct clk_init_data){
 674                 .name = "blsp1_uart2_apps_clk_src",
 675                 .parent_names = gcc_xo_gpll0,
 676                 .num_parents = 2,
 677                 .ops = &clk_rcg2_ops,
 678         },
 679 };
 680
 681 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
 682         F(19200000,     P_XO, 1, 0,     0),
 683         { }
 684 };
 685
 686 static struct clk_rcg2 cci_clk_src = {
 687         .cmd_rcgr = 0x51000,
 688         .mnd_width = 8,
 689         .hid_width = 5,
 690         .parent_map = gcc_xo_gpll0a_map,
 691         .freq_tbl = ftbl_gcc_camss_cci_clk,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "cci_clk_src",
 694                 .parent_names = gcc_xo_gpll0a,
 695                 .num_parents = 2,
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
 701         F(100000000, P_GPLL0, 8, 0, 0),
 702         F(200000000, P_GPLL0, 4, 0, 0),
 703         { }
 704 };
 705
 706 static struct clk_rcg2 camss_gp0_clk_src = {
 707         .cmd_rcgr = 0x54000,
 708         .mnd_width = 8,
 709         .hid_width = 5,
 710         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 711         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 712         .clkr.hw.init = &(struct clk_init_data){
 713                 .name = "camss_gp0_clk_src",
 714                 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 715                 .num_parents = 4,
 716                 .ops = &clk_rcg2_ops,
 717         },
 718 };
 719
 720 static struct clk_rcg2 camss_gp1_clk_src = {
 721         .cmd_rcgr = 0x55000,
 722         .mnd_width = 8,
 723         .hid_width = 5,
 724         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 725         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 726         .clkr.hw.init = &(struct clk_init_data){
 727                 .name = "camss_gp1_clk_src",
 728                 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 729                 .num_parents = 4,
 730                 .ops = &clk_rcg2_ops,
 731         },
 732 };
 733
 734 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
 735         F(133330000, P_GPLL0, 6, 0,     0),
 736         F(266670000, P_GPLL0, 3, 0,     0),
 737         F(320000000, P_GPLL0, 2.5, 0, 0),
 738         { }
 739 };
 740
 741 static struct clk_rcg2 jpeg0_clk_src = {
 742         .cmd_rcgr = 0x57000,
 743         .hid_width = 5,
 744         .parent_map = gcc_xo_gpll0_map,
 745         .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
 746         .clkr.hw.init = &(struct clk_init_data){
 747                 .name = "jpeg0_clk_src",
 748                 .parent_names = gcc_xo_gpll0,
 749                 .num_parents = 2,
 750                 .ops = &clk_rcg2_ops,
 751         },
 752 };
 753
 754 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
 755         F(9600000, P_XO, 2, 0, 0),
 756         F(23880000, P_GPLL0, 1, 2, 67),
 757         F(66670000, P_GPLL0, 12, 0, 0),
 758         { }
 759 };
 760
 761 static struct clk_rcg2 mclk0_clk_src = {
 762         .cmd_rcgr = 0x52000,
 763         .mnd_width = 8,
 764         .hid_width = 5,
 765         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 766         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 767         .clkr.hw.init = &(struct clk_init_data){
 768                 .name = "mclk0_clk_src",
 769                 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 770                 .num_parents = 4,
 771                 .ops = &clk_rcg2_ops,
 772         },
 773 };
 774
 775 static struct clk_rcg2 mclk1_clk_src = {
 776         .cmd_rcgr = 0x53000,
 777         .mnd_width = 8,
 778         .hid_width = 5,
 779         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 780         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 781         .clkr.hw.init = &(struct clk_init_data){
 782                 .name = "mclk1_clk_src",
 783                 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 784                 .num_parents = 4,
 785                 .ops = &clk_rcg2_ops,
 786         },
 787 };
 788
 789 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
 790         F(100000000, P_GPLL0, 8, 0,     0),
 791         F(200000000, P_GPLL0, 4, 0,     0),
 792         { }
 793 };
 794
 795 static struct clk_rcg2 csi0phytimer_clk_src = {
 796         .cmd_rcgr = 0x4e000,
 797         .hid_width = 5,
 798         .parent_map = gcc_xo_gpll0_gpll1a_map,
 799         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 800         .clkr.hw.init = &(struct clk_init_data){
 801                 .name = "csi0phytimer_clk_src",
 802                 .parent_names = gcc_xo_gpll0_gpll1a,
 803                 .num_parents = 3,
 804                 .ops = &clk_rcg2_ops,
 805         },
 806 };
 807
 808 static struct clk_rcg2 csi1phytimer_clk_src = {
 809         .cmd_rcgr = 0x4f000,
 810         .hid_width = 5,
 811         .parent_map = gcc_xo_gpll0_gpll1a_map,
 812         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 813         .clkr.hw.init = &(struct clk_init_data){
 814                 .name = "csi1phytimer_clk_src",
 815                 .parent_names = gcc_xo_gpll0_gpll1a,
 816                 .num_parents = 3,
 817                 .ops = &clk_rcg2_ops,
 818         },
 819 };
 820
 821 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
 822         F(160000000, P_GPLL0, 5, 0, 0),
 823         F(320000000, P_GPLL0, 2.5, 0, 0),
 824         F(465000000, P_GPLL2, 2, 0, 0),
 825         { }
 826 };
 827
 828 static struct clk_rcg2 cpp_clk_src = {
 829         .cmd_rcgr = 0x58018,
 830         .hid_width = 5,
 831         .parent_map = gcc_xo_gpll0_gpll2_map,
 832         .freq_tbl = ftbl_gcc_camss_cpp_clk,
 833         .clkr.hw.init = &(struct clk_init_data){
 834                 .name = "cpp_clk_src",
 835                 .parent_names = gcc_xo_gpll0_gpll2,
 836                 .num_parents = 3,
 837                 .ops = &clk_rcg2_ops,
 838         },
 839 };
 840
 841 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
 842         F(50000000, P_GPLL0, 16, 0, 0),
 843         F(80000000, P_GPLL0, 10, 0, 0),
 844         F(100000000, P_GPLL0, 8, 0, 0),
 845         F(160000000, P_GPLL0, 5, 0, 0),
 846         { }
 847 };
 848
 849 static struct clk_rcg2 crypto_clk_src = {
 850         .cmd_rcgr = 0x16004,
 851         .hid_width = 5,
 852         .parent_map = gcc_xo_gpll0_map,
 853         .freq_tbl = ftbl_gcc_crypto_clk,
 854         .clkr.hw.init = &(struct clk_init_data){
 855                 .name = "crypto_clk_src",
 856                 .parent_names = gcc_xo_gpll0,
 857                 .num_parents = 2,
 858                 .ops = &clk_rcg2_ops,
 859         },
 860 };
 861
 862 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
 863         F(19200000, P_XO, 1, 0, 0),
 864         { }
 865 };
 866
 867 static struct clk_rcg2 gp1_clk_src = {
 868         .cmd_rcgr = 0x08004,
 869         .mnd_width = 8,
 870         .hid_width = 5,
 871         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 872         .freq_tbl = ftbl_gcc_gp1_3_clk,
 873         .clkr.hw.init = &(struct clk_init_data){
 874                 .name = "gp1_clk_src",
 875                 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 876                 .num_parents = 3,
 877                 .ops = &clk_rcg2_ops,
 878         },
 879 };
 880
 881 static struct clk_rcg2 gp2_clk_src = {
 882         .cmd_rcgr = 0x09004,
 883         .mnd_width = 8,
 884         .hid_width = 5,
 885         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 886         .freq_tbl = ftbl_gcc_gp1_3_clk,
 887         .clkr.hw.init = &(struct clk_init_data){
 888                 .name = "gp2_clk_src",
 889                 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 890                 .num_parents = 3,
 891                 .ops = &clk_rcg2_ops,
 892         },
 893 };
 894
 895 static struct clk_rcg2 gp3_clk_src = {
 896         .cmd_rcgr = 0x0a004,
 897         .mnd_width = 8,
 898         .hid_width = 5,
 899         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 900         .freq_tbl = ftbl_gcc_gp1_3_clk,
 901         .clkr.hw.init = &(struct clk_init_data){
 902                 .name = "gp3_clk_src",
 903                 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 904                 .num_parents = 3,
 905                 .ops = &clk_rcg2_ops,
 906         },
 907 };
 908
 909 static struct freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
 910         { .src = P_DSI0_PHYPLL_BYTE },
 911         { }
 912 };
 913
 914 static struct clk_rcg2 byte0_clk_src = {
 915         .cmd_rcgr = 0x4d044,
 916         .hid_width = 5,
 917         .parent_map = gcc_xo_gpll0a_dsibyte_map,
 918         .freq_tbl = ftbl_gcc_mdss_byte0_clk,
 919         .clkr.hw.init = &(struct clk_init_data){
 920                 .name = "byte0_clk_src",
 921                 .parent_names = gcc_xo_gpll0a_dsibyte,
 922                 .num_parents = 3,
 923                 .ops = &clk_byte_ops,
 924                 .flags = CLK_SET_RATE_PARENT,
 925         },
 926 };
 927
 928 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
 929         F(19200000, P_XO, 1, 0, 0),
 930         { }
 931 };
 932
 933 static struct clk_rcg2 esc0_clk_src = {
 934         .cmd_rcgr = 0x4d05c,
 935         .hid_width = 5,
 936         .parent_map = gcc_xo_dsibyte_map,
 937         .freq_tbl = ftbl_gcc_mdss_esc0_clk,
 938         .clkr.hw.init = &(struct clk_init_data){
 939                 .name = "esc0_clk_src",
 940                 .parent_names = gcc_xo_dsibyte,
 941                 .num_parents = 2,
 942                 .ops = &clk_rcg2_ops,
 943         },
 944 };
 945
 946 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
 947         F(50000000, P_GPLL0, 16, 0, 0),
 948         F(80000000, P_GPLL0, 10, 0, 0),
 949         F(100000000, P_GPLL0, 8, 0, 0),
 950         F(160000000, P_GPLL0, 5, 0, 0),
 951         F(177780000, P_GPLL0, 4.5, 0, 0),
 952         F(200000000, P_GPLL0, 4, 0, 0),
 953         F(266670000, P_GPLL0, 3, 0, 0),
 954         F(320000000, P_GPLL0, 2.5, 0, 0),
 955         { }
 956 };
 957
 958 static struct clk_rcg2 mdp_clk_src = {
 959         .cmd_rcgr = 0x4d014,
 960         .hid_width = 5,
 961         .parent_map = gcc_xo_gpll0_dsiphy_map,
 962         .freq_tbl = ftbl_gcc_mdss_mdp_clk,
 963         .clkr.hw.init = &(struct clk_init_data){
 964                 .name = "mdp_clk_src",
 965                 .parent_names = gcc_xo_gpll0_dsiphy,
 966                 .num_parents = 3,
 967                 .ops = &clk_rcg2_ops,
 968         },
 969 };
 970
 971 static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
 972         { .src = P_DSI0_PHYPLL_DSI },
 973         { }
 974 };
 975
 976 static struct clk_rcg2 pclk0_clk_src = {
 977         .cmd_rcgr = 0x4d000,
 978         .mnd_width = 8,
 979         .hid_width = 5,
 980         .parent_map = gcc_xo_gpll0a_dsiphy_map,
 981         .freq_tbl = ftbl_gcc_mdss_pclk,
 982         .clkr.hw.init = &(struct clk_init_data){
 983                 .name = "pclk0_clk_src",
 984                 .parent_names = gcc_xo_gpll0a_dsiphy,
 985                 .num_parents = 3,
 986                 .ops = &clk_pixel_ops,
 987                 .flags = CLK_SET_RATE_PARENT,
 988         },
 989 };
 990
 991 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
 992         F(19200000, P_XO, 1, 0, 0),
 993         { }
 994 };
 995
 996 static struct clk_rcg2 vsync_clk_src = {
 997         .cmd_rcgr = 0x4d02c,
 998         .hid_width = 5,
 999         .parent_map = gcc_xo_gpll0a_map,
1000         .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1001         .clkr.hw.init = &(struct clk_init_data){
1002                 .name = "vsync_clk_src",
1003                 .parent_names = gcc_xo_gpll0a,
1004                 .num_parents = 2,
1005                 .ops = &clk_rcg2_ops,
1006         },
1007 };
1008
1009 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1010         F(64000000, P_GPLL0, 12.5, 0, 0),
1011         { }
1012 };
1013
1014 static struct clk_rcg2 pdm2_clk_src = {
1015         .cmd_rcgr = 0x44010,
1016         .hid_width = 5,
1017         .parent_map = gcc_xo_gpll0_map,
1018         .freq_tbl = ftbl_gcc_pdm2_clk,
1019         .clkr.hw.init = &(struct clk_init_data){
1020                 .name = "pdm2_clk_src",
1021                 .parent_names = gcc_xo_gpll0,
1022                 .num_parents = 2,
1023                 .ops = &clk_rcg2_ops,
1024         },
1025 };
1026
1027 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1028         F(144000, P_XO, 16, 3, 25),
1029         F(400000, P_XO, 12, 1, 4),
1030         F(20000000, P_GPLL0, 10, 1, 4),
1031         F(25000000, P_GPLL0, 16, 1, 2),
1032         F(50000000, P_GPLL0, 16, 0, 0),
1033         F(100000000, P_GPLL0, 8, 0, 0),
1034         F(177770000, P_GPLL0, 4.5, 0, 0),
1035         { }
1036 };
1037
1038 static struct clk_rcg2 sdcc1_apps_clk_src = {
1039         .cmd_rcgr = 0x42004,
1040         .mnd_width = 8,
1041         .hid_width = 5,
1042         .parent_map = gcc_xo_gpll0_map,
1043         .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1044         .clkr.hw.init = &(struct clk_init_data){
1045                 .name = "sdcc1_apps_clk_src",
1046                 .parent_names = gcc_xo_gpll0,
1047                 .num_parents = 2,
1048                 .ops = &clk_rcg2_ops,
1049         },
1050 };
1051
1052 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1053         F(144000, P_XO, 16, 3, 25),
1054         F(400000, P_XO, 12, 1, 4),
1055         F(20000000, P_GPLL0, 10, 1, 4),
1056         F(25000000, P_GPLL0, 16, 1, 2),
1057         F(50000000, P_GPLL0, 16, 0, 0),
1058         F(100000000, P_GPLL0, 8, 0, 0),
1059         F(200000000, P_GPLL0, 4, 0, 0),
1060         { }
1061 };
1062
1063 static struct clk_rcg2 sdcc2_apps_clk_src = {
1064         .cmd_rcgr = 0x43004,
1065         .mnd_width = 8,
1066         .hid_width = 5,
1067         .parent_map = gcc_xo_gpll0_map,
1068         .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1069         .clkr.hw.init = &(struct clk_init_data){
1070                 .name = "sdcc2_apps_clk_src",
1071                 .parent_names = gcc_xo_gpll0,
1072                 .num_parents = 2,
1073                 .ops = &clk_rcg2_ops,
1074         },
1075 };
1076
1077 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1078         F(155000000, P_GPLL2, 6, 0, 0),
1079         F(310000000, P_GPLL2, 3, 0, 0),
1080         F(400000000, P_GPLL0, 2, 0, 0),
1081         { }
1082 };
1083
1084 static struct clk_rcg2 apss_tcu_clk_src = {
1085         .cmd_rcgr = 0x1207c,
1086         .hid_width = 5,
1087         .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1088         .freq_tbl = ftbl_gcc_apss_tcu_clk,
1089         .clkr.hw.init = &(struct clk_init_data){
1090                 .name = "apss_tcu_clk_src",
1091                 .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1092                 .num_parents = 4,
1093                 .ops = &clk_rcg2_ops,
1094         },
1095 };
1096
1097 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1098         F(80000000, P_GPLL0, 10, 0, 0),
1099         { }
1100 };
1101
1102 static struct clk_rcg2 usb_hs_system_clk_src = {
1103         .cmd_rcgr = 0x41010,
1104         .hid_width = 5,
1105         .parent_map = gcc_xo_gpll0_map,
1106         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1107         .clkr.hw.init = &(struct clk_init_data){
1108                 .name = "usb_hs_system_clk_src",
1109                 .parent_names = gcc_xo_gpll0,
1110                 .num_parents = 2,
1111                 .ops = &clk_rcg2_ops,
1112         },
1113 };
1114
1115 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1116         F(100000000, P_GPLL0, 8, 0, 0),
1117         F(160000000, P_GPLL0, 5, 0, 0),
1118         F(228570000, P_GPLL0, 5, 0, 0),
1119         { }
1120 };
1121
1122 static struct clk_rcg2 vcodec0_clk_src = {
1123         .cmd_rcgr = 0x4C000,
1124         .mnd_width = 8,
1125         .hid_width = 5,
1126         .parent_map = gcc_xo_gpll0_map,
1127         .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1128         .clkr.hw.init = &(struct clk_init_data){
1129                 .name = "vcodec0_clk_src",
1130                 .parent_names = gcc_xo_gpll0,
1131                 .num_parents = 2,
1132                 .ops = &clk_rcg2_ops,
1133         },
1134 };
1135
1136 static struct clk_branch gcc_blsp1_ahb_clk = {
1137         .halt_reg = 0x01008,
1138         .halt_check = BRANCH_HALT_VOTED,
1139         .clkr = {
1140                 .enable_reg = 0x45004,
1141                 .enable_mask = BIT(10),
1142                 .hw.init = &(struct clk_init_data){
1143                         .name = "gcc_blsp1_ahb_clk",
1144                         .parent_names = (const char *[]){
1145                                 "pcnoc_bfdcd_clk_src",
1146                         },
1147                         .num_parents = 1,
1148                         .ops = &clk_branch2_ops,
1149                 },
1150         },
1151 };
1152
1153 static struct clk_branch gcc_blsp1_sleep_clk = {
1154         .halt_reg = 0x01004,
1155         .clkr = {
1156                 .enable_reg = 0x01004,
1157                 .enable_mask = BIT(0),
1158                 .hw.init = &(struct clk_init_data){
1159                         .name = "gcc_blsp1_sleep_clk",
1160                         .parent_names = (const char *[]){
1161                                 "sleep_clk_src",
1162                         },
1163                         .num_parents = 1,
1164                         .flags = CLK_SET_RATE_PARENT,
1165                         .ops = &clk_branch2_ops,
1166                 },
1167         },
1168 };
1169
1170 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1171         .halt_reg = 0x02008,
1172         .clkr = {
1173                 .enable_reg = 0x02008,
1174                 .enable_mask = BIT(0),
1175                 .hw.init = &(struct clk_init_data){
1176                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1177                         .parent_names = (const char *[]){
1178                                 "blsp1_qup1_i2c_apps_clk_src",
1179                         },
1180                         .num_parents = 1,
1181                         .flags = CLK_SET_RATE_PARENT,
1182                         .ops = &clk_branch2_ops,
1183                 },
1184         },
1185 };
1186
1187 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1188         .halt_reg = 0x02004,
1189         .clkr = {
1190                 .enable_reg = 0x02004,
1191                 .enable_mask = BIT(0),
1192                 .hw.init = &(struct clk_init_data){
1193                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1194                         .parent_names = (const char *[]){
1195                                 "blsp1_qup1_spi_apps_clk_src",
1196                         },
1197                         .num_parents = 1,
1198                         .flags = CLK_SET_RATE_PARENT,
1199                         .ops = &clk_branch2_ops,
1200                 },
1201         },
1202 };
1203
1204 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1205         .halt_reg = 0x03010,
1206         .clkr = {
1207                 .enable_reg = 0x03010,
1208                 .enable_mask = BIT(0),
1209                 .hw.init = &(struct clk_init_data){
1210                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1211                         .parent_names = (const char *[]){
1212                                 "blsp1_qup2_i2c_apps_clk_src",
1213                         },
1214                         .num_parents = 1,
1215                         .flags = CLK_SET_RATE_PARENT,
1216                         .ops = &clk_branch2_ops,
1217                 },
1218         },
1219 };
1220
1221 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1222         .halt_reg = 0x0300c,
1223         .clkr = {
1224                 .enable_reg = 0x0300c,
1225                 .enable_mask = BIT(0),
1226                 .hw.init = &(struct clk_init_data){
1227                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1228                         .parent_names = (const char *[]){
1229                                 "blsp1_qup2_spi_apps_clk_src",
1230                         },
1231                         .num_parents = 1,
1232                         .flags = CLK_SET_RATE_PARENT,
1233                         .ops = &clk_branch2_ops,
1234                 },
1235         },
1236 };
1237
1238 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1239         .halt_reg = 0x04020,
1240         .clkr = {
1241                 .enable_reg = 0x04020,
1242                 .enable_mask = BIT(0),
1243                 .hw.init = &(struct clk_init_data){
1244                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1245                         .parent_names = (const char *[]){
1246                                 "blsp1_qup3_i2c_apps_clk_src",
1247                         },
1248                         .num_parents = 1,
1249                         .flags = CLK_SET_RATE_PARENT,
1250                         .ops = &clk_branch2_ops,
1251                 },
1252         },
1253 };
1254
1255 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1256         .halt_reg = 0x0401c,
1257         .clkr = {
1258                 .enable_reg = 0x0401c,
1259                 .enable_mask = BIT(0),
1260                 .hw.init = &(struct clk_init_data){
1261                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1262                         .parent_names = (const char *[]){
1263                                 "blsp1_qup3_spi_apps_clk_src",
1264                         },
1265                         .num_parents = 1,
1266                         .flags = CLK_SET_RATE_PARENT,
1267                         .ops = &clk_branch2_ops,
1268                 },
1269         },
1270 };
1271
1272 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1273         .halt_reg = 0x05020,
1274         .clkr = {
1275                 .enable_reg = 0x05020,
1276                 .enable_mask = BIT(0),
1277                 .hw.init = &(struct clk_init_data){
1278                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1279                         .parent_names = (const char *[]){
1280                                 "blsp1_qup4_i2c_apps_clk_src",
1281                         },
1282                         .num_parents = 1,
1283                         .flags = CLK_SET_RATE_PARENT,
1284                         .ops = &clk_branch2_ops,
1285                 },
1286         },
1287 };
1288
1289 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1290         .halt_reg = 0x0501c,
1291         .clkr = {
1292                 .enable_reg = 0x0501c,
1293                 .enable_mask = BIT(0),
1294                 .hw.init = &(struct clk_init_data){
1295                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1296                         .parent_names = (const char *[]){
1297                                 "blsp1_qup4_spi_apps_clk_src",
1298                         },
1299                         .num_parents = 1,
1300                         .flags = CLK_SET_RATE_PARENT,
1301                         .ops = &clk_branch2_ops,
1302                 },
1303         },
1304 };
1305
1306 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1307         .halt_reg = 0x06020,
1308         .clkr = {
1309                 .enable_reg = 0x06020,
1310                 .enable_mask = BIT(0),
1311                 .hw.init = &(struct clk_init_data){
1312                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1313                         .parent_names = (const char *[]){
1314                                 "blsp1_qup5_i2c_apps_clk_src",
1315                         },
1316                         .num_parents = 1,
1317                         .flags = CLK_SET_RATE_PARENT,
1318                         .ops = &clk_branch2_ops,
1319                 },
1320         },
1321 };
1322
1323 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1324         .halt_reg = 0x0601c,
1325         .clkr = {
1326                 .enable_reg = 0x0601c,
1327                 .enable_mask = BIT(0),
1328                 .hw.init = &(struct clk_init_data){
1329                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1330                         .parent_names = (const char *[]){
1331                                 "blsp1_qup5_spi_apps_clk_src",
1332                         },
1333                         .num_parents = 1,
1334                         .flags = CLK_SET_RATE_PARENT,
1335                         .ops = &clk_branch2_ops,
1336                 },
1337         },
1338 };
1339
1340 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1341         .halt_reg = 0x07020,
1342         .clkr = {
1343                 .enable_reg = 0x07020,
1344                 .enable_mask = BIT(0),
1345                 .hw.init = &(struct clk_init_data){
1346                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1347                         .parent_names = (const char *[]){
1348                                 "blsp1_qup6_i2c_apps_clk_src",
1349                         },
1350                         .num_parents = 1,
1351                         .flags = CLK_SET_RATE_PARENT,
1352                         .ops = &clk_branch2_ops,
1353                 },
1354         },
1355 };
1356
1357 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1358         .halt_reg = 0x0701c,
1359         .clkr = {
1360                 .enable_reg = 0x0701c,
1361                 .enable_mask = BIT(0),
1362                 .hw.init = &(struct clk_init_data){
1363                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1364                         .parent_names = (const char *[]){
1365                                 "blsp1_qup6_spi_apps_clk_src",
1366                         },
1367                         .num_parents = 1,
1368                         .flags = CLK_SET_RATE_PARENT,
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1375         .halt_reg = 0x0203c,
1376         .clkr = {
1377                 .enable_reg = 0x0203c,
1378                 .enable_mask = BIT(0),
1379                 .hw.init = &(struct clk_init_data){
1380                         .name = "gcc_blsp1_uart1_apps_clk",
1381                         .parent_names = (const char *[]){
1382                                 "blsp1_uart1_apps_clk_src",
1383                         },
1384                         .num_parents = 1,
1385                         .flags = CLK_SET_RATE_PARENT,
1386                         .ops = &clk_branch2_ops,
1387                 },
1388         },
1389 };
1390
1391 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1392         .halt_reg = 0x0302c,
1393         .clkr = {
1394                 .enable_reg = 0x0302c,
1395                 .enable_mask = BIT(0),
1396                 .hw.init = &(struct clk_init_data){
1397                         .name = "gcc_blsp1_uart2_apps_clk",
1398                         .parent_names = (const char *[]){
1399                                 "blsp1_uart2_apps_clk_src",
1400                         },
1401                         .num_parents = 1,
1402                         .flags = CLK_SET_RATE_PARENT,
1403                         .ops = &clk_branch2_ops,
1404                 },
1405         },
1406 };
1407
1408 static struct clk_branch gcc_boot_rom_ahb_clk = {
1409         .halt_reg = 0x1300c,
1410         .halt_check = BRANCH_HALT_VOTED,
1411         .clkr = {
1412                 .enable_reg = 0x45004,
1413                 .enable_mask = BIT(7),
1414                 .hw.init = &(struct clk_init_data){
1415                         .name = "gcc_boot_rom_ahb_clk",
1416                         .parent_names = (const char *[]){
1417                                 "pcnoc_bfdcd_clk_src",
1418                         },
1419                         .num_parents = 1,
1420                         .ops = &clk_branch2_ops,
1421                 },
1422         },
1423 };
1424
1425 static struct clk_branch gcc_camss_cci_ahb_clk = {
1426         .halt_reg = 0x5101c,
1427         .clkr = {
1428                 .enable_reg = 0x5101c,
1429                 .enable_mask = BIT(0),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "gcc_camss_cci_ahb_clk",
1432                         .parent_names = (const char *[]){
1433                                 "camss_ahb_clk_src",
1434                         },
1435                         .num_parents = 1,
1436                         .flags = CLK_SET_RATE_PARENT,
1437                         .ops = &clk_branch2_ops,
1438                 },
1439         },
1440 };
1441
1442 static struct clk_branch gcc_camss_cci_clk = {
1443         .halt_reg = 0x51018,
1444         .clkr = {
1445                 .enable_reg = 0x51018,
1446                 .enable_mask = BIT(0),
1447                 .hw.init = &(struct clk_init_data){
1448                         .name = "gcc_camss_cci_clk",
1449                         .parent_names = (const char *[]){
1450                                 "cci_clk_src",
1451                         },
1452                         .num_parents = 1,
1453                         .flags = CLK_SET_RATE_PARENT,
1454                         .ops = &clk_branch2_ops,
1455                 },
1456         },
1457 };
1458
1459 static struct clk_branch gcc_camss_csi0_ahb_clk = {
1460         .halt_reg = 0x4e040,
1461         .clkr = {
1462                 .enable_reg = 0x4e040,
1463                 .enable_mask = BIT(0),
1464                 .hw.init = &(struct clk_init_data){
1465                         .name = "gcc_camss_csi0_ahb_clk",
1466                         .parent_names = (const char *[]){
1467                                 "camss_ahb_clk_src",
1468                         },
1469                         .num_parents = 1,
1470                         .flags = CLK_SET_RATE_PARENT,
1471                         .ops = &clk_branch2_ops,
1472                 },
1473         },
1474 };
1475
1476 static struct clk_branch gcc_camss_csi0_clk = {
1477         .halt_reg = 0x4e03c,
1478         .clkr = {
1479                 .enable_reg = 0x4e03c,
1480                 .enable_mask = BIT(0),
1481                 .hw.init = &(struct clk_init_data){
1482                         .name = "gcc_camss_csi0_clk",
1483                         .parent_names = (const char *[]){
1484                                 "csi0_clk_src",
1485                         },
1486                         .num_parents = 1,
1487                         .flags = CLK_SET_RATE_PARENT,
1488                         .ops = &clk_branch2_ops,
1489                 },
1490         },
1491 };
1492
1493 static struct clk_branch gcc_camss_csi0phy_clk = {
1494         .halt_reg = 0x4e048,
1495         .clkr = {
1496                 .enable_reg = 0x4e048,
1497                 .enable_mask = BIT(0),
1498                 .hw.init = &(struct clk_init_data){
1499                         .name = "gcc_camss_csi0phy_clk",
1500                         .parent_names = (const char *[]){
1501                                 "csi0_clk_src",
1502                         },
1503                         .num_parents = 1,
1504                         .flags = CLK_SET_RATE_PARENT,
1505                         .ops = &clk_branch2_ops,
1506                 },
1507         },
1508 };
1509
1510 static struct clk_branch gcc_camss_csi0pix_clk = {
1511         .halt_reg = 0x4e058,
1512         .clkr = {
1513                 .enable_reg = 0x4e058,
1514                 .enable_mask = BIT(0),
1515                 .hw.init = &(struct clk_init_data){
1516                         .name = "gcc_camss_csi0pix_clk",
1517                         .parent_names = (const char *[]){
1518                                 "csi0_clk_src",
1519                         },
1520                         .num_parents = 1,
1521                         .flags = CLK_SET_RATE_PARENT,
1522                         .ops = &clk_branch2_ops,
1523                 },
1524         },
1525 };
1526
1527 static struct clk_branch gcc_camss_csi0rdi_clk = {
1528         .halt_reg = 0x4e050,
1529         .clkr = {
1530                 .enable_reg = 0x4e050,
1531                 .enable_mask = BIT(0),
1532                 .hw.init = &(struct clk_init_data){
1533                         .name = "gcc_camss_csi0rdi_clk",
1534                         .parent_names = (const char *[]){
1535                                 "csi0_clk_src",
1536                         },
1537                         .num_parents = 1,
1538                         .flags = CLK_SET_RATE_PARENT,
1539                         .ops = &clk_branch2_ops,
1540                 },
1541         },
1542 };
1543
1544 static struct clk_branch gcc_camss_csi1_ahb_clk = {
1545         .halt_reg = 0x4f040,
1546         .clkr = {
1547                 .enable_reg = 0x4f040,
1548                 .enable_mask = BIT(0),
1549                 .hw.init = &(struct clk_init_data){
1550                         .name = "gcc_camss_csi1_ahb_clk",
1551                         .parent_names = (const char *[]){
1552                                 "camss_ahb_clk_src",
1553                         },
1554                         .num_parents = 1,
1555                         .flags = CLK_SET_RATE_PARENT,
1556                         .ops = &clk_branch2_ops,
1557                 },
1558         },
1559 };
1560
1561 static struct clk_branch gcc_camss_csi1_clk = {
1562         .halt_reg = 0x4f03c,
1563         .clkr = {
1564                 .enable_reg = 0x4f03c,
1565                 .enable_mask = BIT(0),
1566                 .hw.init = &(struct clk_init_data){
1567                         .name = "gcc_camss_csi1_clk",
1568                         .parent_names = (const char *[]){
1569                                 "csi1_clk_src",
1570                         },
1571                         .num_parents = 1,
1572                         .flags = CLK_SET_RATE_PARENT,
1573                         .ops = &clk_branch2_ops,
1574                 },
1575         },
1576 };
1577
1578 static struct clk_branch gcc_camss_csi1phy_clk = {
1579         .halt_reg = 0x4f048,
1580         .clkr = {
1581                 .enable_reg = 0x4f048,
1582                 .enable_mask = BIT(0),
1583                 .hw.init = &(struct clk_init_data){
1584                         .name = "gcc_camss_csi1phy_clk",
1585                         .parent_names = (const char *[]){
1586                                 "csi1_clk_src",
1587                         },
1588                         .num_parents = 1,
1589                         .flags = CLK_SET_RATE_PARENT,
1590                         .ops = &clk_branch2_ops,
1591                 },
1592         },
1593 };
1594
1595 static struct clk_branch gcc_camss_csi1pix_clk = {
1596         .halt_reg = 0x4f058,
1597         .clkr = {
1598                 .enable_reg = 0x4f058,
1599                 .enable_mask = BIT(0),
1600                 .hw.init = &(struct clk_init_data){
1601                         .name = "gcc_camss_csi1pix_clk",
1602                         .parent_names = (const char *[]){
1603                                 "csi1_clk_src",
1604                         },
1605                         .num_parents = 1,
1606                         .flags = CLK_SET_RATE_PARENT,
1607                         .ops = &clk_branch2_ops,
1608                 },
1609         },
1610 };
1611
1612 static struct clk_branch gcc_camss_csi1rdi_clk = {
1613         .halt_reg = 0x4f050,
1614         .clkr = {
1615                 .enable_reg = 0x4f050,
1616                 .enable_mask = BIT(0),
1617                 .hw.init = &(struct clk_init_data){
1618                         .name = "gcc_camss_csi1rdi_clk",
1619                         .parent_names = (const char *[]){
1620                                 "csi1_clk_src",
1621                         },
1622                         .num_parents = 1,
1623                         .flags = CLK_SET_RATE_PARENT,
1624                         .ops = &clk_branch2_ops,
1625                 },
1626         },
1627 };
1628
1629 static struct clk_branch gcc_camss_csi_vfe0_clk = {
1630         .halt_reg = 0x58050,
1631         .clkr = {
1632                 .enable_reg = 0x58050,
1633                 .enable_mask = BIT(0),
1634                 .hw.init = &(struct clk_init_data){
1635                         .name = "gcc_camss_csi_vfe0_clk",
1636                         .parent_names = (const char *[]){
1637                                 "vfe0_clk_src",
1638                         },
1639                         .num_parents = 1,
1640                         .flags = CLK_SET_RATE_PARENT,
1641                         .ops = &clk_branch2_ops,
1642                 },
1643         },
1644 };
1645
1646 static struct clk_branch gcc_camss_gp0_clk = {
1647         .halt_reg = 0x54018,
1648         .clkr = {
1649                 .enable_reg = 0x54018,
1650                 .enable_mask = BIT(0),
1651                 .hw.init = &(struct clk_init_data){
1652                         .name = "gcc_camss_gp0_clk",
1653                         .parent_names = (const char *[]){
1654                                 "camss_gp0_clk_src",
1655                         },
1656                         .num_parents = 1,
1657                         .flags = CLK_SET_RATE_PARENT,
1658                         .ops = &clk_branch2_ops,
1659                 },
1660         },
1661 };
1662
1663 static struct clk_branch gcc_camss_gp1_clk = {
1664         .halt_reg = 0x55018,
1665         .clkr = {
1666                 .enable_reg = 0x55018,
1667                 .enable_mask = BIT(0),
1668                 .hw.init = &(struct clk_init_data){
1669                         .name = "gcc_camss_gp1_clk",
1670                         .parent_names = (const char *[]){
1671                                 "camss_gp1_clk_src",
1672                         },
1673                         .num_parents = 1,
1674                         .flags = CLK_SET_RATE_PARENT,
1675                         .ops = &clk_branch2_ops,
1676                 },
1677         },
1678 };
1679
1680 static struct clk_branch gcc_camss_ispif_ahb_clk = {
1681         .halt_reg = 0x50004,
1682         .clkr = {
1683                 .enable_reg = 0x50004,
1684                 .enable_mask = BIT(0),
1685                 .hw.init = &(struct clk_init_data){
1686                         .name = "gcc_camss_ispif_ahb_clk",
1687                         .parent_names = (const char *[]){
1688                                 "camss_ahb_clk_src",
1689                         },
1690                         .num_parents = 1,
1691                         .flags = CLK_SET_RATE_PARENT,
1692                         .ops = &clk_branch2_ops,
1693                 },
1694         },
1695 };
1696
1697 static struct clk_branch gcc_camss_jpeg0_clk = {
1698         .halt_reg = 0x57020,
1699         .clkr = {
1700                 .enable_reg = 0x57020,
1701                 .enable_mask = BIT(0),
1702                 .hw.init = &(struct clk_init_data){
1703                         .name = "gcc_camss_jpeg0_clk",
1704                         .parent_names = (const char *[]){
1705                                 "jpeg0_clk_src",
1706                         },
1707                         .num_parents = 1,
1708                         .flags = CLK_SET_RATE_PARENT,
1709                         .ops = &clk_branch2_ops,
1710                 },
1711         },
1712 };
1713
1714 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
1715         .halt_reg = 0x57024,
1716         .clkr = {
1717                 .enable_reg = 0x57024,
1718                 .enable_mask = BIT(0),
1719                 .hw.init = &(struct clk_init_data){
1720                         .name = "gcc_camss_jpeg_ahb_clk",
1721                         .parent_names = (const char *[]){
1722                                 "camss_ahb_clk_src",
1723                         },
1724                         .num_parents = 1,
1725                         .flags = CLK_SET_RATE_PARENT,
1726                         .ops = &clk_branch2_ops,
1727                 },
1728         },
1729 };
1730
1731 static struct clk_branch gcc_camss_jpeg_axi_clk = {
1732         .halt_reg = 0x57028,
1733         .clkr = {
1734                 .enable_reg = 0x57028,
1735                 .enable_mask = BIT(0),
1736                 .hw.init = &(struct clk_init_data){
1737                         .name = "gcc_camss_jpeg_axi_clk",
1738                         .parent_names = (const char *[]){
1739                                 "system_noc_bfdcd_clk_src",
1740                         },
1741                         .num_parents = 1,
1742                         .flags = CLK_SET_RATE_PARENT,
1743                         .ops = &clk_branch2_ops,
1744                 },
1745         },
1746 };
1747
1748 static struct clk_branch gcc_camss_mclk0_clk = {
1749         .halt_reg = 0x52018,
1750         .clkr = {
1751                 .enable_reg = 0x52018,
1752                 .enable_mask = BIT(0),
1753                 .hw.init = &(struct clk_init_data){
1754                         .name = "gcc_camss_mclk0_clk",
1755                         .parent_names = (const char *[]){
1756                                 "mclk0_clk_src",
1757                         },
1758                         .num_parents = 1,
1759                         .flags = CLK_SET_RATE_PARENT,
1760                         .ops = &clk_branch2_ops,
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch gcc_camss_mclk1_clk = {
1766         .halt_reg = 0x53018,
1767         .clkr = {
1768                 .enable_reg = 0x53018,
1769                 .enable_mask = BIT(0),
1770                 .hw.init = &(struct clk_init_data){
1771                         .name = "gcc_camss_mclk1_clk",
1772                         .parent_names = (const char *[]){
1773                                 "mclk1_clk_src",
1774                         },
1775                         .num_parents = 1,
1776                         .flags = CLK_SET_RATE_PARENT,
1777                         .ops = &clk_branch2_ops,
1778                 },
1779         },
1780 };
1781
1782 static struct clk_branch gcc_camss_micro_ahb_clk = {
1783         .halt_reg = 0x5600c,
1784         .clkr = {
1785                 .enable_reg = 0x5600c,
1786                 .enable_mask = BIT(0),
1787                 .hw.init = &(struct clk_init_data){
1788                         .name = "gcc_camss_micro_ahb_clk",
1789                         .parent_names = (const char *[]){
1790                                 "camss_ahb_clk_src",
1791                         },
1792                         .num_parents = 1,
1793                         .flags = CLK_SET_RATE_PARENT,
1794                         .ops = &clk_branch2_ops,
1795                 },
1796         },
1797 };
1798
1799 static struct clk_branch gcc_camss_csi0phytimer_clk = {
1800         .halt_reg = 0x4e01c,
1801         .clkr = {
1802                 .enable_reg = 0x4e01c,
1803                 .enable_mask = BIT(0),
1804                 .hw.init = &(struct clk_init_data){
1805                         .name = "gcc_camss_csi0phytimer_clk",
1806                         .parent_names = (const char *[]){
1807                                 "csi0phytimer_clk_src",
1808                         },
1809                         .num_parents = 1,
1810                         .flags = CLK_SET_RATE_PARENT,
1811                         .ops = &clk_branch2_ops,
1812                 },
1813         },
1814 };
1815
1816 static struct clk_branch gcc_camss_csi1phytimer_clk = {
1817         .halt_reg = 0x4f01c,
1818         .clkr = {
1819                 .enable_reg = 0x4f01c,
1820                 .enable_mask = BIT(0),
1821                 .hw.init = &(struct clk_init_data){
1822                         .name = "gcc_camss_csi1phytimer_clk",
1823                         .parent_names = (const char *[]){
1824                                 "csi1phytimer_clk_src",
1825                         },
1826                         .num_parents = 1,
1827                         .flags = CLK_SET_RATE_PARENT,
1828                         .ops = &clk_branch2_ops,
1829                 },
1830         },
1831 };
1832
1833 static struct clk_branch gcc_camss_ahb_clk = {
1834         .halt_reg = 0x5a014,
1835         .clkr = {
1836                 .enable_reg = 0x5a014,
1837                 .enable_mask = BIT(0),
1838                 .hw.init = &(struct clk_init_data){
1839                         .name = "gcc_camss_ahb_clk",
1840                         .parent_names = (const char *[]){
1841                                 "camss_ahb_clk_src",
1842                         },
1843                         .num_parents = 1,
1844                         .flags = CLK_SET_RATE_PARENT,
1845                         .ops = &clk_branch2_ops,
1846                 },
1847         },
1848 };
1849
1850 static struct clk_branch gcc_camss_top_ahb_clk = {
1851         .halt_reg = 0x56004,
1852         .clkr = {
1853                 .enable_reg = 0x56004,
1854                 .enable_mask = BIT(0),
1855                 .hw.init = &(struct clk_init_data){
1856                         .name = "gcc_camss_top_ahb_clk",
1857                         .parent_names = (const char *[]){
1858                                 "pcnoc_bfdcd_clk_src",
1859                         },
1860                         .num_parents = 1,
1861                         .flags = CLK_SET_RATE_PARENT,
1862                         .ops = &clk_branch2_ops,
1863                 },
1864         },
1865 };
1866
1867 static struct clk_branch gcc_camss_cpp_ahb_clk = {
1868         .halt_reg = 0x58040,
1869         .clkr = {
1870                 .enable_reg = 0x58040,
1871                 .enable_mask = BIT(0),
1872                 .hw.init = &(struct clk_init_data){
1873                         .name = "gcc_camss_cpp_ahb_clk",
1874                         .parent_names = (const char *[]){
1875                                 "camss_ahb_clk_src",
1876                         },
1877                         .num_parents = 1,
1878                         .flags = CLK_SET_RATE_PARENT,
1879                         .ops = &clk_branch2_ops,
1880                 },
1881         },
1882 };
1883
1884 static struct clk_branch gcc_camss_cpp_clk = {
1885         .halt_reg = 0x5803c,
1886         .clkr = {
1887                 .enable_reg = 0x5803c,
1888                 .enable_mask = BIT(0),
1889                 .hw.init = &(struct clk_init_data){
1890                         .name = "gcc_camss_cpp_clk",
1891                         .parent_names = (const char *[]){
1892                                 "cpp_clk_src",
1893                         },
1894                         .num_parents = 1,
1895                         .flags = CLK_SET_RATE_PARENT,
1896                         .ops = &clk_branch2_ops,
1897                 },
1898         },
1899 };
1900
1901 static struct clk_branch gcc_camss_vfe0_clk = {
1902         .halt_reg = 0x58038,
1903         .clkr = {
1904                 .enable_reg = 0x58038,
1905                 .enable_mask = BIT(0),
1906                 .hw.init = &(struct clk_init_data){
1907                         .name = "gcc_camss_vfe0_clk",
1908                         .parent_names = (const char *[]){
1909                                 "vfe0_clk_src",
1910                         },
1911                         .num_parents = 1,
1912                         .flags = CLK_SET_RATE_PARENT,
1913                         .ops = &clk_branch2_ops,
1914                 },
1915         },
1916 };
1917
1918 static struct clk_branch gcc_camss_vfe_ahb_clk = {
1919         .halt_reg = 0x58044,
1920         .clkr = {
1921                 .enable_reg = 0x58044,
1922                 .enable_mask = BIT(0),
1923                 .hw.init = &(struct clk_init_data){
1924                         .name = "gcc_camss_vfe_ahb_clk",
1925                         .parent_names = (const char *[]){
1926                                 "camss_ahb_clk_src",
1927                         },
1928                         .num_parents = 1,
1929                         .flags = CLK_SET_RATE_PARENT,
1930                         .ops = &clk_branch2_ops,
1931                 },
1932         },
1933 };
1934
1935 static struct clk_branch gcc_camss_vfe_axi_clk = {
1936         .halt_reg = 0x58048,
1937         .clkr = {
1938                 .enable_reg = 0x58048,
1939                 .enable_mask = BIT(0),
1940                 .hw.init = &(struct clk_init_data){
1941                         .name = "gcc_camss_vfe_axi_clk",
1942                         .parent_names = (const char *[]){
1943                                 "system_noc_bfdcd_clk_src",
1944                         },
1945                         .num_parents = 1,
1946                         .flags = CLK_SET_RATE_PARENT,
1947                         .ops = &clk_branch2_ops,
1948                 },
1949         },
1950 };
1951
1952 static struct clk_branch gcc_crypto_ahb_clk = {
1953         .halt_reg = 0x16024,
1954         .halt_check = BRANCH_HALT_VOTED,
1955         .clkr = {
1956                 .enable_reg = 0x45004,
1957                 .enable_mask = BIT(0),
1958                 .hw.init = &(struct clk_init_data){
1959                         .name = "gcc_crypto_ahb_clk",
1960                         .parent_names = (const char *[]){
1961                                 "pcnoc_bfdcd_clk_src",
1962                         },
1963                         .num_parents = 1,
1964                         .ops = &clk_branch2_ops,
1965                 },
1966         },
1967 };
1968
1969 static struct clk_branch gcc_crypto_axi_clk = {
1970         .halt_reg = 0x16020,
1971         .halt_check = BRANCH_HALT_VOTED,
1972         .clkr = {
1973                 .enable_reg = 0x45004,
1974                 .enable_mask = BIT(1),
1975                 .hw.init = &(struct clk_init_data){
1976                         .name = "gcc_crypto_axi_clk",
1977                         .parent_names = (const char *[]){
1978                                 "pcnoc_bfdcd_clk_src",
1979                         },
1980                         .num_parents = 1,
1981                         .flags = CLK_SET_RATE_PARENT,
1982                         .ops = &clk_branch2_ops,
1983                 },
1984         },
1985 };
1986
1987 static struct clk_branch gcc_crypto_clk = {
1988         .halt_reg = 0x1601c,
1989         .halt_check = BRANCH_HALT_VOTED,
1990         .clkr = {
1991                 .enable_reg = 0x45004,
1992                 .enable_mask = BIT(2),
1993                 .hw.init = &(struct clk_init_data){
1994                         .name = "gcc_crypto_clk",
1995                         .parent_names = (const char *[]){
1996                                 "crypto_clk_src",
1997                         },
1998                         .num_parents = 1,
1999                         .ops = &clk_branch2_ops,
2000                 },
2001         },
2002 };
2003
2004 static struct clk_branch gcc_oxili_gmem_clk = {
2005         .halt_reg = 0x59024,
2006         .clkr = {
2007                 .enable_reg = 0x59024,
2008                 .enable_mask = BIT(0),
2009                 .hw.init = &(struct clk_init_data){
2010                         .name = "gcc_oxili_gmem_clk",
2011                         .parent_names = (const char *[]){
2012                                 "gfx3d_clk_src",
2013                         },
2014                         .num_parents = 1,
2015                         .flags = CLK_SET_RATE_PARENT,
2016                         .ops = &clk_branch2_ops,
2017                 },
2018         },
2019 };
2020
2021 static struct clk_branch gcc_gp1_clk = {
2022         .halt_reg = 0x08000,
2023         .clkr = {
2024                 .enable_reg = 0x08000,
2025                 .enable_mask = BIT(0),
2026                 .hw.init = &(struct clk_init_data){
2027                         .name = "gcc_gp1_clk",
2028                         .parent_names = (const char *[]){
2029                                 "gp1_clk_src",
2030                         },
2031                         .num_parents = 1,
2032                         .flags = CLK_SET_RATE_PARENT,
2033                         .ops = &clk_branch2_ops,
2034                 },
2035         },
2036 };
2037
2038 static struct clk_branch gcc_gp2_clk = {
2039         .halt_reg = 0x09000,
2040         .clkr = {
2041                 .enable_reg = 0x09000,
2042                 .enable_mask = BIT(0),
2043                 .hw.init = &(struct clk_init_data){
2044                         .name = "gcc_gp2_clk",
2045                         .parent_names = (const char *[]){
2046                                 "gp2_clk_src",
2047                         },
2048                         .num_parents = 1,
2049                         .flags = CLK_SET_RATE_PARENT,
2050                         .ops = &clk_branch2_ops,
2051                 },
2052         },
2053 };
2054
2055 static struct clk_branch gcc_gp3_clk = {
2056         .halt_reg = 0x0a000,
2057         .clkr = {
2058                 .enable_reg = 0x0a000,
2059                 .enable_mask = BIT(0),
2060                 .hw.init = &(struct clk_init_data){
2061                         .name = "gcc_gp3_clk",
2062                         .parent_names = (const char *[]){
2063                                 "gp3_clk_src",
2064                         },
2065                         .num_parents = 1,
2066                         .flags = CLK_SET_RATE_PARENT,
2067                         .ops = &clk_branch2_ops,
2068                 },
2069         },
2070 };
2071
2072 static struct clk_branch gcc_mdss_ahb_clk = {
2073         .halt_reg = 0x4d07c,
2074         .clkr = {
2075                 .enable_reg = 0x4d07c,
2076                 .enable_mask = BIT(0),
2077                 .hw.init = &(struct clk_init_data){
2078                         .name = "gcc_mdss_ahb_clk",
2079                         .parent_names = (const char *[]){
2080                                 "pcnoc_bfdcd_clk_src",
2081                         },
2082                         .num_parents = 1,
2083                         .flags = CLK_SET_RATE_PARENT,
2084                         .ops = &clk_branch2_ops,
2085                 },
2086         },
2087 };
2088
2089 static struct clk_branch gcc_mdss_axi_clk = {
2090         .halt_reg = 0x4d080,
2091         .clkr = {
2092                 .enable_reg = 0x4d080,
2093                 .enable_mask = BIT(0),
2094                 .hw.init = &(struct clk_init_data){
2095                         .name = "gcc_mdss_axi_clk",
2096                         .parent_names = (const char *[]){
2097                                 "system_noc_bfdcd_clk_src",
2098                         },
2099                         .num_parents = 1,
2100                         .flags = CLK_SET_RATE_PARENT,
2101                         .ops = &clk_branch2_ops,
2102                 },
2103         },
2104 };
2105
2106 static struct clk_branch gcc_mdss_byte0_clk = {
2107         .halt_reg = 0x4d094,
2108         .clkr = {
2109                 .enable_reg = 0x4d094,
2110                 .enable_mask = BIT(0),
2111                 .hw.init = &(struct clk_init_data){
2112                         .name = "gcc_mdss_byte0_clk",
2113                         .parent_names = (const char *[]){
2114                                 "byte0_clk_src",
2115                         },
2116                         .num_parents = 1,
2117                         .flags = CLK_SET_RATE_PARENT,
2118                         .ops = &clk_branch2_ops,
2119                 },
2120         },
2121 };
2122
2123 static struct clk_branch gcc_mdss_esc0_clk = {
2124         .halt_reg = 0x4d098,
2125         .clkr = {
2126                 .enable_reg = 0x4d098,
2127                 .enable_mask = BIT(0),
2128                 .hw.init = &(struct clk_init_data){
2129                         .name = "gcc_mdss_esc0_clk",
2130                         .parent_names = (const char *[]){
2131                                 "esc0_clk_src",
2132                         },
2133                         .num_parents = 1,
2134                         .flags = CLK_SET_RATE_PARENT,
2135                         .ops = &clk_branch2_ops,
2136                 },
2137         },
2138 };
2139
2140 static struct clk_branch gcc_mdss_mdp_clk = {
2141         .halt_reg = 0x4D088,
2142         .clkr = {
2143                 .enable_reg = 0x4D088,
2144                 .enable_mask = BIT(0),
2145                 .hw.init = &(struct clk_init_data){
2146                         .name = "gcc_mdss_mdp_clk",
2147                         .parent_names = (const char *[]){
2148                                 "mdp_clk_src",
2149                         },
2150                         .num_parents = 1,
2151                         .flags = CLK_SET_RATE_PARENT,
2152                         .ops = &clk_branch2_ops,
2153                 },
2154         },
2155 };
2156
2157 static struct clk_branch gcc_mdss_pclk0_clk = {
2158         .halt_reg = 0x4d084,
2159         .clkr = {
2160                 .enable_reg = 0x4d084,
2161                 .enable_mask = BIT(0),
2162                 .hw.init = &(struct clk_init_data){
2163                         .name = "gcc_mdss_pclk0_clk",
2164                         .parent_names = (const char *[]){
2165                                 "pclk0_clk_src",
2166                         },
2167                         .num_parents = 1,
2168                         .flags = CLK_SET_RATE_PARENT,
2169                         .ops = &clk_branch2_ops,
2170                 },
2171         },
2172 };
2173
2174 static struct clk_branch gcc_mdss_vsync_clk = {
2175         .halt_reg = 0x4d090,
2176         .clkr = {
2177                 .enable_reg = 0x4d090,
2178                 .enable_mask = BIT(0),
2179                 .hw.init = &(struct clk_init_data){
2180                         .name = "gcc_mdss_vsync_clk",
2181                         .parent_names = (const char *[]){
2182                                 "vsync_clk_src",
2183                         },
2184                         .num_parents = 1,
2185                         .flags = CLK_SET_RATE_PARENT,
2186                         .ops = &clk_branch2_ops,
2187                 },
2188         },
2189 };
2190
2191 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2192         .halt_reg = 0x49000,
2193         .clkr = {
2194                 .enable_reg = 0x49000,
2195                 .enable_mask = BIT(0),
2196                 .hw.init = &(struct clk_init_data){
2197                         .name = "gcc_mss_cfg_ahb_clk",
2198                         .parent_names = (const char *[]){
2199                                 "pcnoc_bfdcd_clk_src",
2200                         },
2201                         .num_parents = 1,
2202                         .flags = CLK_SET_RATE_PARENT,
2203                         .ops = &clk_branch2_ops,
2204                 },
2205         },
2206 };
2207
2208 static struct clk_branch gcc_oxili_ahb_clk = {
2209         .halt_reg = 0x59028,
2210         .clkr = {
2211                 .enable_reg = 0x59028,
2212                 .enable_mask = BIT(0),
2213                 .hw.init = &(struct clk_init_data){
2214                         .name = "gcc_oxili_ahb_clk",
2215                         .parent_names = (const char *[]){
2216                                 "pcnoc_bfdcd_clk_src",
2217                         },
2218                         .num_parents = 1,
2219                         .flags = CLK_SET_RATE_PARENT,
2220                         .ops = &clk_branch2_ops,
2221                 },
2222         },
2223 };
2224
2225 static struct clk_branch gcc_oxili_gfx3d_clk = {
2226         .halt_reg = 0x59020,
2227         .clkr = {
2228                 .enable_reg = 0x59020,
2229                 .enable_mask = BIT(0),
2230                 .hw.init = &(struct clk_init_data){
2231                         .name = "gcc_oxili_gfx3d_clk",
2232                         .parent_names = (const char *[]){
2233                                 "gfx3d_clk_src",
2234                         },
2235                         .num_parents = 1,
2236                         .flags = CLK_SET_RATE_PARENT,
2237                         .ops = &clk_branch2_ops,
2238                 },
2239         },
2240 };
2241
2242 static struct clk_branch gcc_pdm2_clk = {
2243         .halt_reg = 0x4400c,
2244         .clkr = {
2245                 .enable_reg = 0x4400c,
2246                 .enable_mask = BIT(0),
2247                 .hw.init = &(struct clk_init_data){
2248                         .name = "gcc_pdm2_clk",
2249                         .parent_names = (const char *[]){
2250                                 "pdm2_clk_src",
2251                         },
2252                         .num_parents = 1,
2253                         .flags = CLK_SET_RATE_PARENT,
2254                         .ops = &clk_branch2_ops,
2255                 },
2256         },
2257 };
2258
2259 static struct clk_branch gcc_pdm_ahb_clk = {
2260         .halt_reg = 0x44004,
2261         .clkr = {
2262                 .enable_reg = 0x44004,
2263                 .enable_mask = BIT(0),
2264                 .hw.init = &(struct clk_init_data){
2265                         .name = "gcc_pdm_ahb_clk",
2266                         .parent_names = (const char *[]){
2267                                 "pcnoc_bfdcd_clk_src",
2268                         },
2269                         .num_parents = 1,
2270                         .flags = CLK_SET_RATE_PARENT,
2271                         .ops = &clk_branch2_ops,
2272                 },
2273         },
2274 };
2275
2276 static struct clk_branch gcc_prng_ahb_clk = {
2277         .halt_reg = 0x13004,
2278         .halt_check = BRANCH_HALT_VOTED,
2279         .clkr = {
2280                 .enable_reg = 0x45004,
2281                 .enable_mask = BIT(0),
2282                 .hw.init = &(struct clk_init_data){
2283                         .name = "gcc_prng_ahb_clk",
2284                         .parent_names = (const char *[]){
2285                                 "pcnoc_bfdcd_clk_src",
2286                         },
2287                         .num_parents = 1,
2288                         .ops = &clk_branch2_ops,
2289                 },
2290         },
2291 };
2292
2293 static struct clk_branch gcc_sdcc1_ahb_clk = {
2294         .halt_reg = 0x4201c,
2295         .clkr = {
2296                 .enable_reg = 0x4201c,
2297                 .enable_mask = BIT(0),
2298                 .hw.init = &(struct clk_init_data){
2299                         .name = "gcc_sdcc1_ahb_clk",
2300                         .parent_names = (const char *[]){
2301                                 "pcnoc_bfdcd_clk_src",
2302                         },
2303                         .num_parents = 1,
2304                         .flags = CLK_SET_RATE_PARENT,
2305                         .ops = &clk_branch2_ops,
2306                 },
2307         },
2308 };
2309
2310 static struct clk_branch gcc_sdcc1_apps_clk = {
2311         .halt_reg = 0x42018,
2312         .clkr = {
2313                 .enable_reg = 0x42018,
2314                 .enable_mask = BIT(0),
2315                 .hw.init = &(struct clk_init_data){
2316                         .name = "gcc_sdcc1_apps_clk",
2317                         .parent_names = (const char *[]){
2318                                 "sdcc1_apps_clk_src",
2319                         },
2320                         .num_parents = 1,
2321                         .flags = CLK_SET_RATE_PARENT,
2322                         .ops = &clk_branch2_ops,
2323                 },
2324         },
2325 };
2326
2327 static struct clk_branch gcc_sdcc2_ahb_clk = {
2328         .halt_reg = 0x4301c,
2329         .clkr = {
2330                 .enable_reg = 0x4301c,
2331                 .enable_mask = BIT(0),
2332                 .hw.init = &(struct clk_init_data){
2333                         .name = "gcc_sdcc2_ahb_clk",
2334                         .parent_names = (const char *[]){
2335                                 "pcnoc_bfdcd_clk_src",
2336                         },
2337                         .num_parents = 1,
2338                         .flags = CLK_SET_RATE_PARENT,
2339                         .ops = &clk_branch2_ops,
2340                 },
2341         },
2342 };
2343
2344 static struct clk_branch gcc_sdcc2_apps_clk = {
2345         .halt_reg = 0x43018,
2346         .clkr = {
2347                 .enable_reg = 0x43018,
2348                 .enable_mask = BIT(0),
2349                 .hw.init = &(struct clk_init_data){
2350                         .name = "gcc_sdcc2_apps_clk",
2351                         .parent_names = (const char *[]){
2352                                 "sdcc2_apps_clk_src",
2353                         },
2354                         .num_parents = 1,
2355                         .flags = CLK_SET_RATE_PARENT,
2356                         .ops = &clk_branch2_ops,
2357                 },
2358         },
2359 };
2360
2361 static struct clk_branch gcc_gtcu_ahb_clk = {
2362         .halt_reg = 0x12044,
2363         .clkr = {
2364                 .enable_reg = 0x4500c,
2365                 .enable_mask = BIT(13),
2366                 .hw.init = &(struct clk_init_data){
2367                         .name = "gcc_gtcu_ahb_clk",
2368                         .parent_names = (const char *[]){
2369                                 "pcnoc_bfdcd_clk_src",
2370                         },
2371                         .num_parents = 1,
2372                         .flags = CLK_SET_RATE_PARENT,
2373                         .ops = &clk_branch2_ops,
2374                 },
2375         },
2376 };
2377
2378 static struct clk_branch gcc_jpeg_tbu_clk = {
2379         .halt_reg = 0x12034,
2380         .clkr = {
2381                 .enable_reg = 0x4500c,
2382                 .enable_mask = BIT(10),
2383                 .hw.init = &(struct clk_init_data){
2384                         .name = "gcc_jpeg_tbu_clk",
2385                         .parent_names = (const char *[]){
2386                                 "system_noc_bfdcd_clk_src",
2387                         },
2388                         .num_parents = 1,
2389                         .flags = CLK_SET_RATE_PARENT,
2390                         .ops = &clk_branch2_ops,
2391                 },
2392         },
2393 };
2394
2395 static struct clk_branch gcc_mdp_tbu_clk = {
2396         .halt_reg = 0x1201c,
2397         .clkr = {
2398                 .enable_reg = 0x4500c,
2399                 .enable_mask = BIT(4),
2400                 .hw.init = &(struct clk_init_data){
2401                         .name = "gcc_mdp_tbu_clk",
2402                         .parent_names = (const char *[]){
2403                                 "system_noc_bfdcd_clk_src",
2404                         },
2405                         .num_parents = 1,
2406                         .flags = CLK_SET_RATE_PARENT,
2407                         .ops = &clk_branch2_ops,
2408                 },
2409         },
2410 };
2411
2412 static struct clk_branch gcc_smmu_cfg_clk = {
2413         .halt_reg = 0x12038,
2414         .clkr = {
2415                 .enable_reg = 0x4500c,
2416                 .enable_mask = BIT(12),
2417                 .hw.init = &(struct clk_init_data){
2418                         .name = "gcc_smmu_cfg_clk",
2419                         .parent_names = (const char *[]){
2420                                 "pcnoc_bfdcd_clk_src",
2421                         },
2422                         .num_parents = 1,
2423                         .flags = CLK_SET_RATE_PARENT,
2424                         .ops = &clk_branch2_ops,
2425                 },
2426         },
2427 };
2428
2429 static struct clk_branch gcc_venus_tbu_clk = {
2430         .halt_reg = 0x12014,
2431         .clkr = {
2432                 .enable_reg = 0x4500c,
2433                 .enable_mask = BIT(5),
2434                 .hw.init = &(struct clk_init_data){
2435                         .name = "gcc_venus_tbu_clk",
2436                         .parent_names = (const char *[]){
2437                                 "system_noc_bfdcd_clk_src",
2438                         },
2439                         .num_parents = 1,
2440                         .flags = CLK_SET_RATE_PARENT,
2441                         .ops = &clk_branch2_ops,
2442                 },
2443         },
2444 };
2445
2446 static struct clk_branch gcc_vfe_tbu_clk = {
2447         .halt_reg = 0x1203c,
2448         .clkr = {
2449                 .enable_reg = 0x4500c,
2450                 .enable_mask = BIT(9),
2451                 .hw.init = &(struct clk_init_data){
2452                         .name = "gcc_vfe_tbu_clk",
2453                         .parent_names = (const char *[]){
2454                                 "system_noc_bfdcd_clk_src",
2455                         },
2456                         .num_parents = 1,
2457                         .flags = CLK_SET_RATE_PARENT,
2458                         .ops = &clk_branch2_ops,
2459                 },
2460         },
2461 };
2462
2463 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2464         .halt_reg = 0x4102c,
2465         .clkr = {
2466                 .enable_reg = 0x4102c,
2467                 .enable_mask = BIT(0),
2468                 .hw.init = &(struct clk_init_data){
2469                         .name = "gcc_usb2a_phy_sleep_clk",
2470                         .parent_names = (const char *[]){
2471                                 "sleep_clk_src",
2472                         },
2473                         .num_parents = 1,
2474                         .flags = CLK_SET_RATE_PARENT,
2475                         .ops = &clk_branch2_ops,
2476                 },
2477         },
2478 };
2479
2480 static struct clk_branch gcc_usb_hs_ahb_clk = {
2481         .halt_reg = 0x41008,
2482         .clkr = {
2483                 .enable_reg = 0x41008,
2484                 .enable_mask = BIT(0),
2485                 .hw.init = &(struct clk_init_data){
2486                         .name = "gcc_usb_hs_ahb_clk",
2487                         .parent_names = (const char *[]){
2488                                 "pcnoc_bfdcd_clk_src",
2489                         },
2490                         .num_parents = 1,
2491                         .flags = CLK_SET_RATE_PARENT,
2492                         .ops = &clk_branch2_ops,
2493                 },
2494         },
2495 };
2496
2497 static struct clk_branch gcc_usb_hs_system_clk = {
2498         .halt_reg = 0x41004,
2499         .clkr = {
2500                 .enable_reg = 0x41004,
2501                 .enable_mask = BIT(0),
2502                 .hw.init = &(struct clk_init_data){
2503                         .name = "gcc_usb_hs_system_clk",
2504                         .parent_names = (const char *[]){
2505                                 "usb_hs_system_clk_src",
2506                         },
2507                         .num_parents = 1,
2508                         .flags = CLK_SET_RATE_PARENT,
2509                         .ops = &clk_branch2_ops,
2510                 },
2511         },
2512 };
2513
2514 static struct clk_branch gcc_venus0_ahb_clk = {
2515         .halt_reg = 0x4c020,
2516         .clkr = {
2517                 .enable_reg = 0x4c020,
2518                 .enable_mask = BIT(0),
2519                 .hw.init = &(struct clk_init_data){
2520                         .name = "gcc_venus0_ahb_clk",
2521                         .parent_names = (const char *[]){
2522                                 "pcnoc_bfdcd_clk_src",
2523                         },
2524                         .num_parents = 1,
2525                         .flags = CLK_SET_RATE_PARENT,
2526                         .ops = &clk_branch2_ops,
2527                 },
2528         },
2529 };
2530
2531 static struct clk_branch gcc_venus0_axi_clk = {
2532         .halt_reg = 0x4c024,
2533         .clkr = {
2534                 .enable_reg = 0x4c024,
2535                 .enable_mask = BIT(0),
2536                 .hw.init = &(struct clk_init_data){
2537                         .name = "gcc_venus0_axi_clk",
2538                         .parent_names = (const char *[]){
2539                                 "system_noc_bfdcd_clk_src",
2540                         },
2541                         .num_parents = 1,
2542                         .flags = CLK_SET_RATE_PARENT,
2543                         .ops = &clk_branch2_ops,
2544                 },
2545         },
2546 };
2547
2548 static struct clk_branch gcc_venus0_vcodec0_clk = {
2549         .halt_reg = 0x4c01c,
2550         .clkr = {
2551                 .enable_reg = 0x4c01c,
2552                 .enable_mask = BIT(0),
2553                 .hw.init = &(struct clk_init_data){
2554                         .name = "gcc_venus0_vcodec0_clk",
2555                         .parent_names = (const char *[]){
2556                                 "vcodec0_clk_src",
2557                         },
2558                         .num_parents = 1,
2559                         .flags = CLK_SET_RATE_PARENT,
2560                         .ops = &clk_branch2_ops,
2561                 },
2562         },
2563 };
2564
2565 static struct clk_regmap *gcc_msm8916_clocks[] = {
2566         [GPLL0] = &gpll0.clkr,
2567         [GPLL0_VOTE] = &gpll0_vote,
2568         [BIMC_PLL] = &bimc_pll.clkr,
2569         [BIMC_PLL_VOTE] = &bimc_pll_vote,
2570         [GPLL1] = &gpll1.clkr,
2571         [GPLL1_VOTE] = &gpll1_vote,
2572         [GPLL2] = &gpll2.clkr,
2573         [GPLL2_VOTE] = &gpll2_vote,
2574         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
2575         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
2576         [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
2577         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2578         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2579         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2580         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2581         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2582         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2583         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2584         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2585         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2586         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2587         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2588         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2589         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2590         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2591         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2592         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2593         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2594         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2595         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2596         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2597         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2598         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2599         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2600         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2601         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2602         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2603         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2604         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2605         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
2606         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2607         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2608         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2609         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2610         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2611         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2612         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2613         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2614         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2615         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2616         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2617         [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
2618         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2619         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2620         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2621         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2622         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2623         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2624         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2625         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2626         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2627         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2628         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2629         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2630         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2631         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2632         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2633         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2634         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2635         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2636         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2637         [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
2638         [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
2639         [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
2640         [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
2641         [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
2642         [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
2643         [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
2644         [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
2645         [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
2646         [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
2647         [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
2648         [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
2649         [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
2650         [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
2651         [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
2652         [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
2653         [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
2654         [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
2655         [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
2656         [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
2657         [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
2658         [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
2659         [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
2660         [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
2661         [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
2662         [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
2663         [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
2664         [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
2665         [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
2666         [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
2667         [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
2668         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2669         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2670         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2671         [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
2672         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2673         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2674         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2675         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2676         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2677         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2678         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2679         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2680         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2681         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2682         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2683         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2684         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2685         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2686         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2687         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2688         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2689         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2690         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2691         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2692         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2693         [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
2694         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2695         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2696         [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
2697         [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
2698         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2699         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2700         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2701         [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
2702         [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
2703         [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
2704 };
2705
2706 static const struct qcom_reset_map gcc_msm8916_resets[] = {
2707         [GCC_BLSP1_BCR] = { 0x01000 },
2708         [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
2709         [GCC_BLSP1_UART1_BCR] = { 0x02038 },
2710         [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
2711         [GCC_BLSP1_UART2_BCR] = { 0x03028 },
2712         [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
2713         [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
2714         [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
2715         [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
2716         [GCC_IMEM_BCR] = { 0x0e000 },
2717         [GCC_SMMU_BCR] = { 0x12000 },
2718         [GCC_APSS_TCU_BCR] = { 0x12050 },
2719         [GCC_SMMU_XPU_BCR] = { 0x12054 },
2720         [GCC_PCNOC_TBU_BCR] = { 0x12058 },
2721         [GCC_PRNG_BCR] = { 0x13000 },
2722         [GCC_BOOT_ROM_BCR] = { 0x13008 },
2723         [GCC_CRYPTO_BCR] = { 0x16000 },
2724         [GCC_SEC_CTRL_BCR] = { 0x1a000 },
2725         [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
2726         [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
2727         [GCC_DEHR_BCR] = { 0x1f000 },
2728         [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
2729         [GCC_PCNOC_BCR] = { 0x27018 },
2730         [GCC_TCSR_BCR] = { 0x28000 },
2731         [GCC_QDSS_BCR] = { 0x29000 },
2732         [GCC_DCD_BCR] = { 0x2a000 },
2733         [GCC_MSG_RAM_BCR] = { 0x2b000 },
2734         [GCC_MPM_BCR] = { 0x2c000 },
2735         [GCC_SPMI_BCR] = { 0x2e000 },
2736         [GCC_SPDM_BCR] = { 0x2f000 },
2737         [GCC_MM_SPDM_BCR] = { 0x2f024 },
2738         [GCC_BIMC_BCR] = { 0x31000 },
2739         [GCC_RBCPR_BCR] = { 0x33000 },
2740         [GCC_TLMM_BCR] = { 0x34000 },
2741         [GCC_USB_HS_BCR] = { 0x41000 },
2742         [GCC_USB2A_PHY_BCR] = { 0x41028 },
2743         [GCC_SDCC1_BCR] = { 0x42000 },
2744         [GCC_SDCC2_BCR] = { 0x43000 },
2745         [GCC_PDM_BCR] = { 0x44000 },
2746         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
2747         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
2748         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
2749         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
2750         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
2751         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
2752         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
2753         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
2754         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
2755         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
2756         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
2757         [GCC_MMSS_BCR] = { 0x4b000 },
2758         [GCC_VENUS0_BCR] = { 0x4c014 },
2759         [GCC_MDSS_BCR] = { 0x4d074 },
2760         [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
2761         [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
2762         [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
2763         [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
2764         [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
2765         [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
2766         [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
2767         [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
2768         [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
2769         [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
2770         [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
2771         [GCC_CAMSS_CCI_BCR] = { 0x51014 },
2772         [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
2773         [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
2774         [GCC_CAMSS_GP0_BCR] = { 0x54014 },
2775         [GCC_CAMSS_GP1_BCR] = { 0x55014 },
2776         [GCC_CAMSS_TOP_BCR] = { 0x56000 },
2777         [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
2778         [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
2779         [GCC_CAMSS_VFE_BCR] = { 0x58030 },
2780         [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
2781         [GCC_OXILI_BCR] = { 0x59018 },
2782         [GCC_GMEM_BCR] = { 0x5902c },
2783         [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
2784         [GCC_MDP_TBU_BCR] = { 0x62000 },
2785         [GCC_GFX_TBU_BCR] = { 0x63000 },
2786         [GCC_GFX_TCU_BCR] = { 0x64000 },
2787         [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
2788         [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
2789         [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
2790         [GCC_GTCU_AHB_BCR] = { 0x68000 },
2791         [GCC_SMMU_CFG_BCR] = { 0x69000 },
2792         [GCC_VFE_TBU_BCR] = { 0x6a000 },
2793         [GCC_VENUS_TBU_BCR] = { 0x6b000 },
2794         [GCC_JPEG_TBU_BCR] = { 0x6c000 },
2795         [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
2796         [GCC_SMMU_CATS_BCR] = { 0x7c000 },
2797 };
2798
2799 static const struct regmap_config gcc_msm8916_regmap_config = {
2800         .reg_bits       = 32,
2801         .reg_stride     = 4,
2802         .val_bits       = 32,
2803         .max_register   = 0x80000,
2804         .fast_io        = true,
2805 };
2806
2807 static const struct qcom_cc_desc gcc_msm8916_desc = {
2808         .config = &gcc_msm8916_regmap_config,
2809         .clks = gcc_msm8916_clocks,
2810         .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
2811         .resets = gcc_msm8916_resets,
2812         .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
2813 };
2814
2815 static const struct of_device_id gcc_msm8916_match_table[] = {
2816         { .compatible = "qcom,gcc-msm8916" },
2817         { }
2818 };
2819 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
2820
2821 static int gcc_msm8916_probe(struct platform_device *pdev)
2822 {
2823         struct clk *clk;
2824         struct device *dev = &pdev->dev;
2825
2826         /* Temporary until RPM clocks supported */
2827         clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2828         if (IS_ERR(clk))
2829                 return PTR_ERR(clk);
2830
2831         clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2832                                       CLK_IS_ROOT, 32768);
2833         if (IS_ERR(clk))
2834                 return PTR_ERR(clk);
2835
2836         return qcom_cc_probe(pdev, &gcc_msm8916_desc);
2837 }
2838
2839 static int gcc_msm8916_remove(struct platform_device *pdev)
2840 {
2841         qcom_cc_remove(pdev);
2842         return 0;
2843 }
2844
2845 static struct platform_driver gcc_msm8916_driver = {
2846         .probe          = gcc_msm8916_probe,
2847         .remove         = gcc_msm8916_remove,
2848         .driver         = {
2849                 .name   = "gcc-msm8916",
2850                 .of_match_table = gcc_msm8916_match_table,
2851         },
2852 };
2853
2854 static int __init gcc_msm8916_init(void)
2855 {
2856         return platform_driver_register(&gcc_msm8916_driver);
2857 }
2858 core_initcall(gcc_msm8916_init);
2859
2860 static void __exit gcc_msm8916_exit(void)
2861 {
2862         platform_driver_unregister(&gcc_msm8916_driver);
2863 }
2864 module_exit(gcc_msm8916_exit);
2865
2866 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
2867 MODULE_LICENSE("GPL v2");
2868 MODULE_ALIAS("platform:gcc-msm8916");