drivers/clk/meson/meson8b.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 Endless Mobile, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  *
   6  * Copyright (c) 2016 BayLibre, Inc.
   7  * Michael Turquette <mturquette@baylibre.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/init.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of_address.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/slab.h>
  17 #include <linux/regmap.h>
  18
  19 #include "meson8b.h"
  20 #include "clk-regmap.h"
  21 #include "clk-pll.h"
  22 #include "clk-mpll.h"
  23
  24 static DEFINE_SPINLOCK(meson_clk_lock);
  25
  26 struct meson8b_clk_reset {
  27         struct reset_controller_dev reset;
  28         struct regmap *regmap;
  29 };
  30
  31 static const struct pll_params_table sys_pll_params_table[] = {
  32         PLL_PARAMS(50, 1),
  33         PLL_PARAMS(51, 1),
  34         PLL_PARAMS(52, 1),
  35         PLL_PARAMS(53, 1),
  36         PLL_PARAMS(54, 1),
  37         PLL_PARAMS(55, 1),
  38         PLL_PARAMS(56, 1),
  39         PLL_PARAMS(57, 1),
  40         PLL_PARAMS(58, 1),
  41         PLL_PARAMS(59, 1),
  42         PLL_PARAMS(60, 1),
  43         PLL_PARAMS(61, 1),
  44         PLL_PARAMS(62, 1),
  45         PLL_PARAMS(63, 1),
  46         PLL_PARAMS(64, 1),
  47         PLL_PARAMS(65, 1),
  48         PLL_PARAMS(66, 1),
  49         PLL_PARAMS(67, 1),
  50         PLL_PARAMS(68, 1),
  51         PLL_PARAMS(84, 1),
  52         { /* sentinel */ },
  53 };
  54
  55 static struct clk_fixed_rate meson8b_xtal = {
  56         .fixed_rate = 24000000,
  57         .hw.init = &(struct clk_init_data){
  58                 .name = "xtal",
  59                 .num_parents = 0,
  60                 .ops = &clk_fixed_rate_ops,
  61         },
  62 };
  63
  64 static struct clk_regmap meson8b_fixed_pll_dco = {
  65         .data = &(struct meson_clk_pll_data){
  66                 .en = {
  67                         .reg_off = HHI_MPLL_CNTL,
  68                         .shift   = 30,
  69                         .width   = 1,
  70                 },
  71                 .m = {
  72                         .reg_off = HHI_MPLL_CNTL,
  73                         .shift   = 0,
  74                         .width   = 9,
  75                 },
  76                 .n = {
  77                         .reg_off = HHI_MPLL_CNTL,
  78                         .shift   = 9,
  79                         .width   = 5,
  80                 },
  81                 .frac = {
  82                         .reg_off = HHI_MPLL_CNTL2,
  83                         .shift   = 0,
  84                         .width   = 12,
  85                 },
  86                 .l = {
  87                         .reg_off = HHI_MPLL_CNTL,
  88                         .shift   = 31,
  89                         .width   = 1,
  90                 },
  91                 .rst = {
  92                         .reg_off = HHI_MPLL_CNTL,
  93                         .shift   = 29,
  94                         .width   = 1,
  95                 },
  96         },
  97         .hw.init = &(struct clk_init_data){
  98                 .name = "fixed_pll_dco",
  99                 .ops = &meson_clk_pll_ro_ops,
 100                 .parent_names = (const char *[]){ "xtal" },
 101                 .num_parents = 1,
 102         },
 103 };
 104
 105 static struct clk_regmap meson8b_fixed_pll = {
 106         .data = &(struct clk_regmap_div_data){
 107                 .offset = HHI_MPLL_CNTL,
 108                 .shift = 16,
 109                 .width = 2,
 110                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 111         },
 112         .hw.init = &(struct clk_init_data){
 113                 .name = "fixed_pll",
 114                 .ops = &clk_regmap_divider_ro_ops,
 115                 .parent_names = (const char *[]){ "fixed_pll_dco" },
 116                 .num_parents = 1,
 117                 /*
 118                  * This clock won't ever change at runtime so
 119                  * CLK_SET_RATE_PARENT is not required
 120                  */
 121         },
 122 };
 123
 124 static struct clk_regmap meson8b_hdmi_pll_dco = {
 125         .data = &(struct meson_clk_pll_data){
 126                 .en = {
 127                         .reg_off = HHI_VID_PLL_CNTL,
 128                         .shift   = 30,
 129                         .width   = 1,
 130                 },
 131                 .m = {
 132                         .reg_off = HHI_VID_PLL_CNTL,
 133                         .shift   = 0,
 134                         .width   = 9,
 135                 },
 136                 .n = {
 137                         .reg_off = HHI_VID_PLL_CNTL,
 138                         .shift   = 10,
 139                         .width   = 5,
 140                 },
 141                 .frac = {
 142                         .reg_off = HHI_VID_PLL_CNTL2,
 143                         .shift   = 0,
 144                         .width   = 12,
 145                 },
 146                 .l = {
 147                         .reg_off = HHI_VID_PLL_CNTL,
 148                         .shift   = 31,
 149                         .width   = 1,
 150                 },
 151                 .rst = {
 152                         .reg_off = HHI_VID_PLL_CNTL,
 153                         .shift   = 29,
 154                         .width   = 1,
 155                 },
 156         },
 157         .hw.init = &(struct clk_init_data){
 158                 /* sometimes also called "HPLL" or "HPLL PLL" */
 159                 .name = "hdmi_pll_dco",
 160                 .ops = &meson_clk_pll_ro_ops,
 161                 .parent_names = (const char *[]){ "xtal" },
 162                 .num_parents = 1,
 163         },
 164 };
 165
 166 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
 167         .data = &(struct clk_regmap_div_data){
 168                 .offset = HHI_VID_PLL_CNTL,
 169                 .shift = 16,
 170                 .width = 2,
 171                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 172         },
 173         .hw.init = &(struct clk_init_data){
 174                 .name = "hdmi_pll_lvds_out",
 175                 .ops = &clk_regmap_divider_ro_ops,
 176                 .parent_names = (const char *[]){ "hdmi_pll_dco" },
 177                 .num_parents = 1,
 178                 .flags = CLK_SET_RATE_PARENT,
 179         },
 180 };
 181
 182 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
 183         .data = &(struct clk_regmap_div_data){
 184                 .offset = HHI_VID_PLL_CNTL,
 185                 .shift = 18,
 186                 .width = 2,
 187                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 188         },
 189         .hw.init = &(struct clk_init_data){
 190                 .name = "hdmi_pll_hdmi_out",
 191                 .ops = &clk_regmap_divider_ro_ops,
 192                 .parent_names = (const char *[]){ "hdmi_pll_dco" },
 193                 .num_parents = 1,
 194                 .flags = CLK_SET_RATE_PARENT,
 195         },
 196 };
 197
 198 static struct clk_regmap meson8b_sys_pll_dco = {
 199         .data = &(struct meson_clk_pll_data){
 200                 .en = {
 201                         .reg_off = HHI_SYS_PLL_CNTL,
 202                         .shift   = 30,
 203                         .width   = 1,
 204                 },
 205                 .m = {
 206                         .reg_off = HHI_SYS_PLL_CNTL,
 207                         .shift   = 0,
 208                         .width   = 9,
 209                 },
 210                 .n = {
 211                         .reg_off = HHI_SYS_PLL_CNTL,
 212                         .shift   = 9,
 213                         .width   = 5,
 214                 },
 215                 .l = {
 216                         .reg_off = HHI_SYS_PLL_CNTL,
 217                         .shift   = 31,
 218                         .width   = 1,
 219                 },
 220                 .rst = {
 221                         .reg_off = HHI_SYS_PLL_CNTL,
 222                         .shift   = 29,
 223                         .width   = 1,
 224                 },
 225                 .table = sys_pll_params_table,
 226         },
 227         .hw.init = &(struct clk_init_data){
 228                 .name = "sys_pll_dco",
 229                 .ops = &meson_clk_pll_ops,
 230                 .parent_names = (const char *[]){ "xtal" },
 231                 .num_parents = 1,
 232         },
 233 };
 234
 235 static struct clk_regmap meson8b_sys_pll = {
 236         .data = &(struct clk_regmap_div_data){
 237                 .offset = HHI_SYS_PLL_CNTL,
 238                 .shift = 16,
 239                 .width = 2,
 240                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 241         },
 242         .hw.init = &(struct clk_init_data){
 243                 .name = "sys_pll",
 244                 .ops = &clk_regmap_divider_ops,
 245                 .parent_names = (const char *[]){ "sys_pll_dco" },
 246                 .num_parents = 1,
 247                 .flags = CLK_SET_RATE_PARENT,
 248         },
 249 };
 250
 251 static struct clk_fixed_factor meson8b_fclk_div2_div = {
 252         .mult = 1,
 253         .div = 2,
 254         .hw.init = &(struct clk_init_data){
 255                 .name = "fclk_div2_div",
 256                 .ops = &clk_fixed_factor_ops,
 257                 .parent_names = (const char *[]){ "fixed_pll" },
 258                 .num_parents = 1,
 259         },
 260 };
 261
 262 static struct clk_regmap meson8b_fclk_div2 = {
 263         .data = &(struct clk_regmap_gate_data){
 264                 .offset = HHI_MPLL_CNTL6,
 265                 .bit_idx = 27,
 266         },
 267         .hw.init = &(struct clk_init_data){
 268                 .name = "fclk_div2",
 269                 .ops = &clk_regmap_gate_ops,
 270                 .parent_names = (const char *[]){ "fclk_div2_div" },
 271                 .num_parents = 1,
 272                 /*
 273                  * FIXME: Ethernet with a RGMII PHYs is not working if
 274                  * fclk_div2 is disabled. it is currently unclear why this
 275                  * is. keep it enabled until the Ethernet driver knows how
 276                  * to manage this clock.
 277                  */
 278                 .flags = CLK_IS_CRITICAL,
 279         },
 280 };
 281
 282 static struct clk_fixed_factor meson8b_fclk_div3_div = {
 283         .mult = 1,
 284         .div = 3,
 285         .hw.init = &(struct clk_init_data){
 286                 .name = "fclk_div3_div",
 287                 .ops = &clk_fixed_factor_ops,
 288                 .parent_names = (const char *[]){ "fixed_pll" },
 289                 .num_parents = 1,
 290         },
 291 };
 292
 293 static struct clk_regmap meson8b_fclk_div3 = {
 294         .data = &(struct clk_regmap_gate_data){
 295                 .offset = HHI_MPLL_CNTL6,
 296                 .bit_idx = 28,
 297         },
 298         .hw.init = &(struct clk_init_data){
 299                 .name = "fclk_div3",
 300                 .ops = &clk_regmap_gate_ops,
 301                 .parent_names = (const char *[]){ "fclk_div3_div" },
 302                 .num_parents = 1,
 303         },
 304 };
 305
 306 static struct clk_fixed_factor meson8b_fclk_div4_div = {
 307         .mult = 1,
 308         .div = 4,
 309         .hw.init = &(struct clk_init_data){
 310                 .name = "fclk_div4_div",
 311                 .ops = &clk_fixed_factor_ops,
 312                 .parent_names = (const char *[]){ "fixed_pll" },
 313                 .num_parents = 1,
 314         },
 315 };
 316
 317 static struct clk_regmap meson8b_fclk_div4 = {
 318         .data = &(struct clk_regmap_gate_data){
 319                 .offset = HHI_MPLL_CNTL6,
 320                 .bit_idx = 29,
 321         },
 322         .hw.init = &(struct clk_init_data){
 323                 .name = "fclk_div4",
 324                 .ops = &clk_regmap_gate_ops,
 325                 .parent_names = (const char *[]){ "fclk_div4_div" },
 326                 .num_parents = 1,
 327         },
 328 };
 329
 330 static struct clk_fixed_factor meson8b_fclk_div5_div = {
 331         .mult = 1,
 332         .div = 5,
 333         .hw.init = &(struct clk_init_data){
 334                 .name = "fclk_div5_div",
 335                 .ops = &clk_fixed_factor_ops,
 336                 .parent_names = (const char *[]){ "fixed_pll" },
 337                 .num_parents = 1,
 338         },
 339 };
 340
 341 static struct clk_regmap meson8b_fclk_div5 = {
 342         .data = &(struct clk_regmap_gate_data){
 343                 .offset = HHI_MPLL_CNTL6,
 344                 .bit_idx = 30,
 345         },
 346         .hw.init = &(struct clk_init_data){
 347                 .name = "fclk_div5",
 348                 .ops = &clk_regmap_gate_ops,
 349                 .parent_names = (const char *[]){ "fclk_div5_div" },
 350                 .num_parents = 1,
 351         },
 352 };
 353
 354 static struct clk_fixed_factor meson8b_fclk_div7_div = {
 355         .mult = 1,
 356         .div = 7,
 357         .hw.init = &(struct clk_init_data){
 358                 .name = "fclk_div7_div",
 359                 .ops = &clk_fixed_factor_ops,
 360                 .parent_names = (const char *[]){ "fixed_pll" },
 361                 .num_parents = 1,
 362         },
 363 };
 364
 365 static struct clk_regmap meson8b_fclk_div7 = {
 366         .data = &(struct clk_regmap_gate_data){
 367                 .offset = HHI_MPLL_CNTL6,
 368                 .bit_idx = 31,
 369         },
 370         .hw.init = &(struct clk_init_data){
 371                 .name = "fclk_div7",
 372                 .ops = &clk_regmap_gate_ops,
 373                 .parent_names = (const char *[]){ "fclk_div7_div" },
 374                 .num_parents = 1,
 375         },
 376 };
 377
 378 static struct clk_regmap meson8b_mpll_prediv = {
 379         .data = &(struct clk_regmap_div_data){
 380                 .offset = HHI_MPLL_CNTL5,
 381                 .shift = 12,
 382                 .width = 1,
 383         },
 384         .hw.init = &(struct clk_init_data){
 385                 .name = "mpll_prediv",
 386                 .ops = &clk_regmap_divider_ro_ops,
 387                 .parent_names = (const char *[]){ "fixed_pll" },
 388                 .num_parents = 1,
 389         },
 390 };
 391
 392 static struct clk_regmap meson8b_mpll0_div = {
 393         .data = &(struct meson_clk_mpll_data){
 394                 .sdm = {
 395                         .reg_off = HHI_MPLL_CNTL7,
 396                         .shift   = 0,
 397                         .width   = 14,
 398                 },
 399                 .sdm_en = {
 400                         .reg_off = HHI_MPLL_CNTL7,
 401                         .shift   = 15,
 402                         .width   = 1,
 403                 },
 404                 .n2 = {
 405                         .reg_off = HHI_MPLL_CNTL7,
 406                         .shift   = 16,
 407                         .width   = 9,
 408                 },
 409                 .ssen = {
 410                         .reg_off = HHI_MPLL_CNTL,
 411                         .shift   = 25,
 412                         .width   = 1,
 413                 },
 414                 .lock = &meson_clk_lock,
 415         },
 416         .hw.init = &(struct clk_init_data){
 417                 .name = "mpll0_div",
 418                 .ops = &meson_clk_mpll_ops,
 419                 .parent_names = (const char *[]){ "mpll_prediv" },
 420                 .num_parents = 1,
 421         },
 422 };
 423
 424 static struct clk_regmap meson8b_mpll0 = {
 425         .data = &(struct clk_regmap_gate_data){
 426                 .offset = HHI_MPLL_CNTL7,
 427                 .bit_idx = 14,
 428         },
 429         .hw.init = &(struct clk_init_data){
 430                 .name = "mpll0",
 431                 .ops = &clk_regmap_gate_ops,
 432                 .parent_names = (const char *[]){ "mpll0_div" },
 433                 .num_parents = 1,
 434                 .flags = CLK_SET_RATE_PARENT,
 435         },
 436 };
 437
 438 static struct clk_regmap meson8b_mpll1_div = {
 439         .data = &(struct meson_clk_mpll_data){
 440                 .sdm = {
 441                         .reg_off = HHI_MPLL_CNTL8,
 442                         .shift   = 0,
 443                         .width   = 14,
 444                 },
 445                 .sdm_en = {
 446                         .reg_off = HHI_MPLL_CNTL8,
 447                         .shift   = 15,
 448                         .width   = 1,
 449                 },
 450                 .n2 = {
 451                         .reg_off = HHI_MPLL_CNTL8,
 452                         .shift   = 16,
 453                         .width   = 9,
 454                 },
 455                 .lock = &meson_clk_lock,
 456         },
 457         .hw.init = &(struct clk_init_data){
 458                 .name = "mpll1_div",
 459                 .ops = &meson_clk_mpll_ops,
 460                 .parent_names = (const char *[]){ "mpll_prediv" },
 461                 .num_parents = 1,
 462         },
 463 };
 464
 465 static struct clk_regmap meson8b_mpll1 = {
 466         .data = &(struct clk_regmap_gate_data){
 467                 .offset = HHI_MPLL_CNTL8,
 468                 .bit_idx = 14,
 469         },
 470         .hw.init = &(struct clk_init_data){
 471                 .name = "mpll1",
 472                 .ops = &clk_regmap_gate_ops,
 473                 .parent_names = (const char *[]){ "mpll1_div" },
 474                 .num_parents = 1,
 475                 .flags = CLK_SET_RATE_PARENT,
 476         },
 477 };
 478
 479 static struct clk_regmap meson8b_mpll2_div = {
 480         .data = &(struct meson_clk_mpll_data){
 481                 .sdm = {
 482                         .reg_off = HHI_MPLL_CNTL9,
 483                         .shift   = 0,
 484                         .width   = 14,
 485                 },
 486                 .sdm_en = {
 487                         .reg_off = HHI_MPLL_CNTL9,
 488                         .shift   = 15,
 489                         .width   = 1,
 490                 },
 491                 .n2 = {
 492                         .reg_off = HHI_MPLL_CNTL9,
 493                         .shift   = 16,
 494                         .width   = 9,
 495                 },
 496                 .lock = &meson_clk_lock,
 497         },
 498         .hw.init = &(struct clk_init_data){
 499                 .name = "mpll2_div",
 500                 .ops = &meson_clk_mpll_ops,
 501                 .parent_names = (const char *[]){ "mpll_prediv" },
 502                 .num_parents = 1,
 503         },
 504 };
 505
 506 static struct clk_regmap meson8b_mpll2 = {
 507         .data = &(struct clk_regmap_gate_data){
 508                 .offset = HHI_MPLL_CNTL9,
 509                 .bit_idx = 14,
 510         },
 511         .hw.init = &(struct clk_init_data){
 512                 .name = "mpll2",
 513                 .ops = &clk_regmap_gate_ops,
 514                 .parent_names = (const char *[]){ "mpll2_div" },
 515                 .num_parents = 1,
 516                 .flags = CLK_SET_RATE_PARENT,
 517         },
 518 };
 519
 520 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 521 static struct clk_regmap meson8b_mpeg_clk_sel = {
 522         .data = &(struct clk_regmap_mux_data){
 523                 .offset = HHI_MPEG_CLK_CNTL,
 524                 .mask = 0x7,
 525                 .shift = 12,
 526                 .table = mux_table_clk81,
 527         },
 528         .hw.init = &(struct clk_init_data){
 529                 .name = "mpeg_clk_sel",
 530                 .ops = &clk_regmap_mux_ro_ops,
 531                 /*
 532                  * FIXME bits 14:12 selects from 8 possible parents:
 533                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 534                  * fclk_div4, fclk_div3, fclk_div5
 535                  */
 536                 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
 537                         "fclk_div5" },
 538                 .num_parents = 3,
 539         },
 540 };
 541
 542 static struct clk_regmap meson8b_mpeg_clk_div = {
 543         .data = &(struct clk_regmap_div_data){
 544                 .offset = HHI_MPEG_CLK_CNTL,
 545                 .shift = 0,
 546                 .width = 7,
 547         },
 548         .hw.init = &(struct clk_init_data){
 549                 .name = "mpeg_clk_div",
 550                 .ops = &clk_regmap_divider_ro_ops,
 551                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 552                 .num_parents = 1,
 553         },
 554 };
 555
 556 static struct clk_regmap meson8b_clk81 = {
 557         .data = &(struct clk_regmap_gate_data){
 558                 .offset = HHI_MPEG_CLK_CNTL,
 559                 .bit_idx = 7,
 560         },
 561         .hw.init = &(struct clk_init_data){
 562                 .name = "clk81",
 563                 .ops = &clk_regmap_gate_ops,
 564                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 565                 .num_parents = 1,
 566                 .flags = CLK_IS_CRITICAL,
 567         },
 568 };
 569
 570 static struct clk_regmap meson8b_cpu_in_sel = {
 571         .data = &(struct clk_regmap_mux_data){
 572                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 573                 .mask = 0x1,
 574                 .shift = 0,
 575         },
 576         .hw.init = &(struct clk_init_data){
 577                 .name = "cpu_in_sel",
 578                 .ops = &clk_regmap_mux_ops,
 579                 .parent_names = (const char *[]){ "xtal", "sys_pll" },
 580                 .num_parents = 2,
 581                 .flags = (CLK_SET_RATE_PARENT |
 582                           CLK_SET_RATE_NO_REPARENT),
 583         },
 584 };
 585
 586 static struct clk_fixed_factor meson8b_cpu_in_div2 = {
 587         .mult = 1,
 588         .div = 2,
 589         .hw.init = &(struct clk_init_data){
 590                 .name = "cpu_in_div2",
 591                 .ops = &clk_fixed_factor_ops,
 592                 .parent_names = (const char *[]){ "cpu_in_sel" },
 593                 .num_parents = 1,
 594                 .flags = CLK_SET_RATE_PARENT,
 595         },
 596 };
 597
 598 static struct clk_fixed_factor meson8b_cpu_in_div3 = {
 599         .mult = 1,
 600         .div = 3,
 601         .hw.init = &(struct clk_init_data){
 602                 .name = "cpu_in_div3",
 603                 .ops = &clk_fixed_factor_ops,
 604                 .parent_names = (const char *[]){ "cpu_in_sel" },
 605                 .num_parents = 1,
 606                 .flags = CLK_SET_RATE_PARENT,
 607         },
 608 };
 609
 610 static const struct clk_div_table cpu_scale_table[] = {
 611         { .val = 1, .div = 4 },
 612         { .val = 2, .div = 6 },
 613         { .val = 3, .div = 8 },
 614         { .val = 4, .div = 10 },
 615         { .val = 5, .div = 12 },
 616         { .val = 6, .div = 14 },
 617         { .val = 7, .div = 16 },
 618         { .val = 8, .div = 18 },
 619         { /* sentinel */ },
 620 };
 621
 622 static struct clk_regmap meson8b_cpu_scale_div = {
 623         .data = &(struct clk_regmap_div_data){
 624                 .offset =  HHI_SYS_CPU_CLK_CNTL1,
 625                 .shift = 20,
 626                 .width = 10,
 627                 .table = cpu_scale_table,
 628                 .flags = CLK_DIVIDER_ALLOW_ZERO,
 629         },
 630         .hw.init = &(struct clk_init_data){
 631                 .name = "cpu_scale_div",
 632                 .ops = &clk_regmap_divider_ops,
 633                 .parent_names = (const char *[]){ "cpu_in_sel" },
 634                 .num_parents = 1,
 635                 .flags = CLK_SET_RATE_PARENT,
 636         },
 637 };
 638
 639 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
 640 static struct clk_regmap meson8b_cpu_scale_out_sel = {
 641         .data = &(struct clk_regmap_mux_data){
 642                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 643                 .mask = 0x3,
 644                 .shift = 2,
 645                 .table = mux_table_cpu_scale_out_sel,
 646         },
 647         .hw.init = &(struct clk_init_data){
 648                 .name = "cpu_scale_out_sel",
 649                 .ops = &clk_regmap_mux_ops,
 650                 /*
 651                  * NOTE: We are skipping the parent with value 0x2 (which is
 652                  * "cpu_in_div3") because it results in a duty cycle of 33%
 653                  * which makes the system unstable and can result in a lockup
 654                  * of the whole system.
 655                  */
 656                 .parent_names = (const char *[]) { "cpu_in_sel",
 657                                                    "cpu_in_div2",
 658                                                    "cpu_scale_div" },
 659                 .num_parents = 3,
 660                 .flags = CLK_SET_RATE_PARENT,
 661         },
 662 };
 663
 664 static struct clk_regmap meson8b_cpu_clk = {
 665         .data = &(struct clk_regmap_mux_data){
 666                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 667                 .mask = 0x1,
 668                 .shift = 7,
 669         },
 670         .hw.init = &(struct clk_init_data){
 671                 .name = "cpu_clk",
 672                 .ops = &clk_regmap_mux_ops,
 673                 .parent_names = (const char *[]){ "xtal",
 674                                                   "cpu_scale_out_sel" },
 675                 .num_parents = 2,
 676                 .flags = (CLK_SET_RATE_PARENT |
 677                           CLK_SET_RATE_NO_REPARENT |
 678                           CLK_IS_CRITICAL),
 679         },
 680 };
 681
 682 static struct clk_regmap meson8b_nand_clk_sel = {
 683         .data = &(struct clk_regmap_mux_data){
 684                 .offset = HHI_NAND_CLK_CNTL,
 685                 .mask = 0x7,
 686                 .shift = 9,
 687                 .flags = CLK_MUX_ROUND_CLOSEST,
 688         },
 689         .hw.init = &(struct clk_init_data){
 690                 .name = "nand_clk_sel",
 691                 .ops = &clk_regmap_mux_ops,
 692                 /* FIXME all other parents are unknown: */
 693                 .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
 694                         "fclk_div5", "fclk_div7", "xtal" },
 695                 .num_parents = 5,
 696                 .flags = CLK_SET_RATE_PARENT,
 697         },
 698 };
 699
 700 static struct clk_regmap meson8b_nand_clk_div = {
 701         .data = &(struct clk_regmap_div_data){
 702                 .offset =  HHI_NAND_CLK_CNTL,
 703                 .shift = 0,
 704                 .width = 7,
 705                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 706         },
 707         .hw.init = &(struct clk_init_data){
 708                 .name = "nand_clk_div",
 709                 .ops = &clk_regmap_divider_ops,
 710                 .parent_names = (const char *[]){ "nand_clk_sel" },
 711                 .num_parents = 1,
 712                 .flags = CLK_SET_RATE_PARENT,
 713         },
 714 };
 715
 716 static struct clk_regmap meson8b_nand_clk_gate = {
 717         .data = &(struct clk_regmap_gate_data){
 718                 .offset = HHI_NAND_CLK_CNTL,
 719                 .bit_idx = 8,
 720         },
 721         .hw.init = &(struct clk_init_data){
 722                 .name = "nand_clk_gate",
 723                 .ops = &clk_regmap_gate_ops,
 724                 .parent_names = (const char *[]){ "nand_clk_div" },
 725                 .num_parents = 1,
 726                 .flags = CLK_SET_RATE_PARENT,
 727         },
 728 };
 729
 730 static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
 731         .mult = 1,
 732         .div = 2,
 733         .hw.init = &(struct clk_init_data){
 734                 .name = "cpu_clk_div2",
 735                 .ops = &clk_fixed_factor_ops,
 736                 .parent_names = (const char *[]){ "cpu_clk" },
 737                 .num_parents = 1,
 738         },
 739 };
 740
 741 static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
 742         .mult = 1,
 743         .div = 3,
 744         .hw.init = &(struct clk_init_data){
 745                 .name = "cpu_clk_div3",
 746                 .ops = &clk_fixed_factor_ops,
 747                 .parent_names = (const char *[]){ "cpu_clk" },
 748                 .num_parents = 1,
 749         },
 750 };
 751
 752 static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
 753         .mult = 1,
 754         .div = 4,
 755         .hw.init = &(struct clk_init_data){
 756                 .name = "cpu_clk_div4",
 757                 .ops = &clk_fixed_factor_ops,
 758                 .parent_names = (const char *[]){ "cpu_clk" },
 759                 .num_parents = 1,
 760         },
 761 };
 762
 763 static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
 764         .mult = 1,
 765         .div = 5,
 766         .hw.init = &(struct clk_init_data){
 767                 .name = "cpu_clk_div5",
 768                 .ops = &clk_fixed_factor_ops,
 769                 .parent_names = (const char *[]){ "cpu_clk" },
 770                 .num_parents = 1,
 771         },
 772 };
 773
 774 static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
 775         .mult = 1,
 776         .div = 6,
 777         .hw.init = &(struct clk_init_data){
 778                 .name = "cpu_clk_div6",
 779                 .ops = &clk_fixed_factor_ops,
 780                 .parent_names = (const char *[]){ "cpu_clk" },
 781                 .num_parents = 1,
 782         },
 783 };
 784
 785 static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
 786         .mult = 1,
 787         .div = 7,
 788         .hw.init = &(struct clk_init_data){
 789                 .name = "cpu_clk_div7",
 790                 .ops = &clk_fixed_factor_ops,
 791                 .parent_names = (const char *[]){ "cpu_clk" },
 792                 .num_parents = 1,
 793         },
 794 };
 795
 796 static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
 797         .mult = 1,
 798         .div = 8,
 799         .hw.init = &(struct clk_init_data){
 800                 .name = "cpu_clk_div8",
 801                 .ops = &clk_fixed_factor_ops,
 802                 .parent_names = (const char *[]){ "cpu_clk" },
 803                 .num_parents = 1,
 804         },
 805 };
 806
 807 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
 808 static struct clk_regmap meson8b_apb_clk_sel = {
 809         .data = &(struct clk_regmap_mux_data){
 810                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 811                 .mask = 0x7,
 812                 .shift = 3,
 813                 .table = mux_table_apb,
 814         },
 815         .hw.init = &(struct clk_init_data){
 816                 .name = "apb_clk_sel",
 817                 .ops = &clk_regmap_mux_ops,
 818                 .parent_names = (const char *[]){ "cpu_clk_div2",
 819                                                   "cpu_clk_div3",
 820                                                   "cpu_clk_div4",
 821                                                   "cpu_clk_div5",
 822                                                   "cpu_clk_div6",
 823                                                   "cpu_clk_div7",
 824                                                   "cpu_clk_div8", },
 825                 .num_parents = 7,
 826         },
 827 };
 828
 829 static struct clk_regmap meson8b_apb_clk_gate = {
 830         .data = &(struct clk_regmap_gate_data){
 831                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 832                 .bit_idx = 16,
 833                 .flags = CLK_GATE_SET_TO_DISABLE,
 834         },
 835         .hw.init = &(struct clk_init_data){
 836                 .name = "apb_clk_dis",
 837                 .ops = &clk_regmap_gate_ro_ops,
 838                 .parent_names = (const char *[]){ "apb_clk_sel" },
 839                 .num_parents = 1,
 840                 .flags = CLK_SET_RATE_PARENT,
 841         },
 842 };
 843
 844 static struct clk_regmap meson8b_periph_clk_sel = {
 845         .data = &(struct clk_regmap_mux_data){
 846                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 847                 .mask = 0x7,
 848                 .shift = 6,
 849         },
 850         .hw.init = &(struct clk_init_data){
 851                 .name = "periph_clk_sel",
 852                 .ops = &clk_regmap_mux_ops,
 853                 .parent_names = (const char *[]){ "cpu_clk_div2",
 854                                                   "cpu_clk_div3",
 855                                                   "cpu_clk_div4",
 856                                                   "cpu_clk_div5",
 857                                                   "cpu_clk_div6",
 858                                                   "cpu_clk_div7",
 859                                                   "cpu_clk_div8", },
 860                 .num_parents = 7,
 861         },
 862 };
 863
 864 static struct clk_regmap meson8b_periph_clk_gate = {
 865         .data = &(struct clk_regmap_gate_data){
 866                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 867                 .bit_idx = 17,
 868                 .flags = CLK_GATE_SET_TO_DISABLE,
 869         },
 870         .hw.init = &(struct clk_init_data){
 871                 .name = "periph_clk_dis",
 872                 .ops = &clk_regmap_gate_ro_ops,
 873                 .parent_names = (const char *[]){ "periph_clk_sel" },
 874                 .num_parents = 1,
 875                 .flags = CLK_SET_RATE_PARENT,
 876         },
 877 };
 878
 879 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
 880 static struct clk_regmap meson8b_axi_clk_sel = {
 881         .data = &(struct clk_regmap_mux_data){
 882                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 883                 .mask = 0x7,
 884                 .shift = 9,
 885                 .table = mux_table_axi,
 886         },
 887         .hw.init = &(struct clk_init_data){
 888                 .name = "axi_clk_sel",
 889                 .ops = &clk_regmap_mux_ops,
 890                 .parent_names = (const char *[]){ "cpu_clk_div2",
 891                                                   "cpu_clk_div3",
 892                                                   "cpu_clk_div4",
 893                                                   "cpu_clk_div5",
 894                                                   "cpu_clk_div6",
 895                                                   "cpu_clk_div7",
 896                                                   "cpu_clk_div8", },
 897                 .num_parents = 7,
 898         },
 899 };
 900
 901 static struct clk_regmap meson8b_axi_clk_gate = {
 902         .data = &(struct clk_regmap_gate_data){
 903                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 904                 .bit_idx = 18,
 905                 .flags = CLK_GATE_SET_TO_DISABLE,
 906         },
 907         .hw.init = &(struct clk_init_data){
 908                 .name = "axi_clk_dis",
 909                 .ops = &clk_regmap_gate_ro_ops,
 910                 .parent_names = (const char *[]){ "axi_clk_sel" },
 911                 .num_parents = 1,
 912                 .flags = CLK_SET_RATE_PARENT,
 913         },
 914 };
 915
 916 static struct clk_regmap meson8b_l2_dram_clk_sel = {
 917         .data = &(struct clk_regmap_mux_data){
 918                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 919                 .mask = 0x7,
 920                 .shift = 12,
 921         },
 922         .hw.init = &(struct clk_init_data){
 923                 .name = "l2_dram_clk_sel",
 924                 .ops = &clk_regmap_mux_ops,
 925                 .parent_names = (const char *[]){ "cpu_clk_div2",
 926                                                   "cpu_clk_div3",
 927                                                   "cpu_clk_div4",
 928                                                   "cpu_clk_div5",
 929                                                   "cpu_clk_div6",
 930                                                   "cpu_clk_div7",
 931                                                   "cpu_clk_div8", },
 932                 .num_parents = 7,
 933         },
 934 };
 935
 936 static struct clk_regmap meson8b_l2_dram_clk_gate = {
 937         .data = &(struct clk_regmap_gate_data){
 938                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 939                 .bit_idx = 19,
 940                 .flags = CLK_GATE_SET_TO_DISABLE,
 941         },
 942         .hw.init = &(struct clk_init_data){
 943                 .name = "l2_dram_clk_dis",
 944                 .ops = &clk_regmap_gate_ro_ops,
 945                 .parent_names = (const char *[]){ "l2_dram_clk_sel" },
 946                 .num_parents = 1,
 947                 .flags = CLK_SET_RATE_PARENT,
 948         },
 949 };
 950
 951 static struct clk_regmap meson8b_vid_pll_in_sel = {
 952         .data = &(struct clk_regmap_mux_data){
 953                 .offset = HHI_VID_DIVIDER_CNTL,
 954                 .mask = 0x1,
 955                 .shift = 15,
 956         },
 957         .hw.init = &(struct clk_init_data){
 958                 .name = "vid_pll_in_sel",
 959                 .ops = &clk_regmap_mux_ro_ops,
 960                 /*
 961                  * TODO: depending on the SoC there is also a second parent:
 962                  * Meson8: unknown
 963                  * Meson8b: hdmi_pll_dco
 964                  * Meson8m2: vid2_pll
 965                  */
 966                 .parent_names = (const char *[]){ "hdmi_pll_dco" },
 967                 .num_parents = 1,
 968                 .flags = CLK_SET_RATE_PARENT,
 969         },
 970 };
 971
 972 static struct clk_regmap meson8b_vid_pll_in_en = {
 973         .data = &(struct clk_regmap_gate_data){
 974                 .offset = HHI_VID_DIVIDER_CNTL,
 975                 .bit_idx = 16,
 976         },
 977         .hw.init = &(struct clk_init_data){
 978                 .name = "vid_pll_in_en",
 979                 .ops = &clk_regmap_gate_ro_ops,
 980                 .parent_names = (const char *[]){ "vid_pll_in_sel" },
 981                 .num_parents = 1,
 982                 .flags = CLK_SET_RATE_PARENT,
 983         },
 984 };
 985
 986 static struct clk_regmap meson8b_vid_pll_pre_div = {
 987         .data = &(struct clk_regmap_div_data){
 988                 .offset =  HHI_VID_DIVIDER_CNTL,
 989                 .shift = 4,
 990                 .width = 3,
 991         },
 992         .hw.init = &(struct clk_init_data){
 993                 .name = "vid_pll_pre_div",
 994                 .ops = &clk_regmap_divider_ro_ops,
 995                 .parent_names = (const char *[]){ "vid_pll_in_en" },
 996                 .num_parents = 1,
 997                 .flags = CLK_SET_RATE_PARENT,
 998         },
 999 };
1000
1001 static struct clk_regmap meson8b_vid_pll_post_div = {
1002         .data = &(struct clk_regmap_div_data){
1003                 .offset =  HHI_VID_DIVIDER_CNTL,
1004                 .shift = 12,
1005                 .width = 3,
1006         },
1007         .hw.init = &(struct clk_init_data){
1008                 .name = "vid_pll_post_div",
1009                 .ops = &clk_regmap_divider_ro_ops,
1010                 .parent_names = (const char *[]){ "vid_pll_pre_div" },
1011                 .num_parents = 1,
1012                 .flags = CLK_SET_RATE_PARENT,
1013         },
1014 };
1015
1016 static struct clk_regmap meson8b_vid_pll = {
1017         .data = &(struct clk_regmap_mux_data){
1018                 .offset = HHI_VID_DIVIDER_CNTL,
1019                 .mask = 0x3,
1020                 .shift = 8,
1021         },
1022         .hw.init = &(struct clk_init_data){
1023                 .name = "vid_pll",
1024                 .ops = &clk_regmap_mux_ro_ops,
1025                 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
1026                 .parent_names = (const char *[]){ "vid_pll_pre_div",
1027                                                   "vid_pll_post_div" },
1028                 .num_parents = 2,
1029                 .flags = CLK_SET_RATE_PARENT,
1030         },
1031 };
1032
1033 static struct clk_regmap meson8b_vid_pll_final_div = {
1034         .data = &(struct clk_regmap_div_data){
1035                 .offset =  HHI_VID_CLK_DIV,
1036                 .shift = 0,
1037                 .width = 8,
1038         },
1039         .hw.init = &(struct clk_init_data){
1040                 .name = "vid_pll_final_div",
1041                 .ops = &clk_regmap_divider_ro_ops,
1042                 .parent_names = (const char *[]){ "vid_pll" },
1043                 .num_parents = 1,
1044                 .flags = CLK_SET_RATE_PARENT,
1045         },
1046 };
1047
1048 static const char * const meson8b_vclk_mux_parents[] = {
1049         "vid_pll_final_div", "fclk_div4", "fclk_div3", "fclk_div5",
1050         "vid_pll_final_div", "fclk_div7", "mpll1"
1051 };
1052
1053 static struct clk_regmap meson8b_vclk_in_sel = {
1054         .data = &(struct clk_regmap_mux_data){
1055                 .offset = HHI_VID_CLK_CNTL,
1056                 .mask = 0x7,
1057                 .shift = 16,
1058         },
1059         .hw.init = &(struct clk_init_data){
1060                 .name = "vclk_in_sel",
1061                 .ops = &clk_regmap_mux_ro_ops,
1062                 .parent_names = meson8b_vclk_mux_parents,
1063                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents),
1064                 .flags = CLK_SET_RATE_PARENT,
1065         },
1066 };
1067
1068 static struct clk_regmap meson8b_vclk_in_en = {
1069         .data = &(struct clk_regmap_gate_data){
1070                 .offset = HHI_VID_CLK_DIV,
1071                 .bit_idx = 16,
1072         },
1073         .hw.init = &(struct clk_init_data){
1074                 .name = "vclk_in_en",
1075                 .ops = &clk_regmap_gate_ro_ops,
1076                 .parent_names = (const char *[]){ "vclk_in_sel" },
1077                 .num_parents = 1,
1078                 .flags = CLK_SET_RATE_PARENT,
1079         },
1080 };
1081
1082 static struct clk_regmap meson8b_vclk_div1_gate = {
1083         .data = &(struct clk_regmap_gate_data){
1084                 .offset = HHI_VID_CLK_DIV,
1085                 .bit_idx = 0,
1086         },
1087         .hw.init = &(struct clk_init_data){
1088                 .name = "vclk_div1_en",
1089                 .ops = &clk_regmap_gate_ro_ops,
1090                 .parent_names = (const char *[]){ "vclk_in_en" },
1091                 .num_parents = 1,
1092                 .flags = CLK_SET_RATE_PARENT,
1093         },
1094 };
1095
1096 static struct clk_fixed_factor meson8b_vclk_div2_div = {
1097         .mult = 1,
1098         .div = 2,
1099         .hw.init = &(struct clk_init_data){
1100                 .name = "vclk_div2",
1101                 .ops = &clk_fixed_factor_ops,
1102                 .parent_names = (const char *[]){ "vclk_in_en" },
1103                 .num_parents = 1,
1104                 .flags = CLK_SET_RATE_PARENT,
1105         }
1106 };
1107
1108 static struct clk_regmap meson8b_vclk_div2_div_gate = {
1109         .data = &(struct clk_regmap_gate_data){
1110                 .offset = HHI_VID_CLK_DIV,
1111                 .bit_idx = 1,
1112         },
1113         .hw.init = &(struct clk_init_data){
1114                 .name = "vclk_div2_en",
1115                 .ops = &clk_regmap_gate_ro_ops,
1116                 .parent_names = (const char *[]){ "vclk_div2" },
1117                 .num_parents = 1,
1118                 .flags = CLK_SET_RATE_PARENT,
1119         },
1120 };
1121
1122 static struct clk_fixed_factor meson8b_vclk_div4_div = {
1123         .mult = 1,
1124         .div = 4,
1125         .hw.init = &(struct clk_init_data){
1126                 .name = "vclk_div4",
1127                 .ops = &clk_fixed_factor_ops,
1128                 .parent_names = (const char *[]){ "vclk_in_en" },
1129                 .num_parents = 1,
1130                 .flags = CLK_SET_RATE_PARENT,
1131         }
1132 };
1133
1134 static struct clk_regmap meson8b_vclk_div4_div_gate = {
1135         .data = &(struct clk_regmap_gate_data){
1136                 .offset = HHI_VID_CLK_DIV,
1137                 .bit_idx = 2,
1138         },
1139         .hw.init = &(struct clk_init_data){
1140                 .name = "vclk_div4_en",
1141                 .ops = &clk_regmap_gate_ro_ops,
1142                 .parent_names = (const char *[]){ "vclk_div4" },
1143                 .num_parents = 1,
1144                 .flags = CLK_SET_RATE_PARENT,
1145         },
1146 };
1147
1148 static struct clk_fixed_factor meson8b_vclk_div6_div = {
1149         .mult = 1,
1150         .div = 6,
1151         .hw.init = &(struct clk_init_data){
1152                 .name = "vclk_div6",
1153                 .ops = &clk_fixed_factor_ops,
1154                 .parent_names = (const char *[]){ "vclk_in_en" },
1155                 .num_parents = 1,
1156                 .flags = CLK_SET_RATE_PARENT,
1157         }
1158 };
1159
1160 static struct clk_regmap meson8b_vclk_div6_div_gate = {
1161         .data = &(struct clk_regmap_gate_data){
1162                 .offset = HHI_VID_CLK_DIV,
1163                 .bit_idx = 3,
1164         },
1165         .hw.init = &(struct clk_init_data){
1166                 .name = "vclk_div6_en",
1167                 .ops = &clk_regmap_gate_ro_ops,
1168                 .parent_names = (const char *[]){ "vclk_div6" },
1169                 .num_parents = 1,
1170                 .flags = CLK_SET_RATE_PARENT,
1171         },
1172 };
1173
1174 static struct clk_fixed_factor meson8b_vclk_div12_div = {
1175         .mult = 1,
1176         .div = 12,
1177         .hw.init = &(struct clk_init_data){
1178                 .name = "vclk_div12",
1179                 .ops = &clk_fixed_factor_ops,
1180                 .parent_names = (const char *[]){ "vclk_in_en" },
1181                 .num_parents = 1,
1182                 .flags = CLK_SET_RATE_PARENT,
1183         }
1184 };
1185
1186 static struct clk_regmap meson8b_vclk_div12_div_gate = {
1187         .data = &(struct clk_regmap_gate_data){
1188                 .offset = HHI_VID_CLK_DIV,
1189                 .bit_idx = 4,
1190         },
1191         .hw.init = &(struct clk_init_data){
1192                 .name = "vclk_div12_en",
1193                 .ops = &clk_regmap_gate_ro_ops,
1194                 .parent_names = (const char *[]){ "vclk_div12" },
1195                 .num_parents = 1,
1196                 .flags = CLK_SET_RATE_PARENT,
1197         },
1198 };
1199
1200 static struct clk_regmap meson8b_vclk2_in_sel = {
1201         .data = &(struct clk_regmap_mux_data){
1202                 .offset = HHI_VIID_CLK_CNTL,
1203                 .mask = 0x7,
1204                 .shift = 16,
1205         },
1206         .hw.init = &(struct clk_init_data){
1207                 .name = "vclk2_in_sel",
1208                 .ops = &clk_regmap_mux_ro_ops,
1209                 .parent_names = meson8b_vclk_mux_parents,
1210                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents),
1211                 .flags = CLK_SET_RATE_PARENT,
1212         },
1213 };
1214
1215 static struct clk_regmap meson8b_vclk2_clk_in_en = {
1216         .data = &(struct clk_regmap_gate_data){
1217                 .offset = HHI_VIID_CLK_DIV,
1218                 .bit_idx = 16,
1219         },
1220         .hw.init = &(struct clk_init_data){
1221                 .name = "vclk2_in_en",
1222                 .ops = &clk_regmap_gate_ro_ops,
1223                 .parent_names = (const char *[]){ "vclk2_in_sel" },
1224                 .num_parents = 1,
1225                 .flags = CLK_SET_RATE_PARENT,
1226         },
1227 };
1228
1229 static struct clk_regmap meson8b_vclk2_div1_gate = {
1230         .data = &(struct clk_regmap_gate_data){
1231                 .offset = HHI_VIID_CLK_DIV,
1232                 .bit_idx = 0,
1233         },
1234         .hw.init = &(struct clk_init_data){
1235                 .name = "vclk2_div1_en",
1236                 .ops = &clk_regmap_gate_ro_ops,
1237                 .parent_names = (const char *[]){ "vclk2_in_en" },
1238                 .num_parents = 1,
1239                 .flags = CLK_SET_RATE_PARENT,
1240         },
1241 };
1242
1243 static struct clk_fixed_factor meson8b_vclk2_div2_div = {
1244         .mult = 1,
1245         .div = 2,
1246         .hw.init = &(struct clk_init_data){
1247                 .name = "vclk2_div2",
1248                 .ops = &clk_fixed_factor_ops,
1249                 .parent_names = (const char *[]){ "vclk2_in_en" },
1250                 .num_parents = 1,
1251                 .flags = CLK_SET_RATE_PARENT,
1252         }
1253 };
1254
1255 static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1256         .data = &(struct clk_regmap_gate_data){
1257                 .offset = HHI_VIID_CLK_DIV,
1258                 .bit_idx = 1,
1259         },
1260         .hw.init = &(struct clk_init_data){
1261                 .name = "vclk2_div2_en",
1262                 .ops = &clk_regmap_gate_ro_ops,
1263                 .parent_names = (const char *[]){ "vclk2_div2" },
1264                 .num_parents = 1,
1265                 .flags = CLK_SET_RATE_PARENT,
1266         },
1267 };
1268
1269 static struct clk_fixed_factor meson8b_vclk2_div4_div = {
1270         .mult = 1,
1271         .div = 4,
1272         .hw.init = &(struct clk_init_data){
1273                 .name = "vclk2_div4",
1274                 .ops = &clk_fixed_factor_ops,
1275                 .parent_names = (const char *[]){ "vclk2_in_en" },
1276                 .num_parents = 1,
1277                 .flags = CLK_SET_RATE_PARENT,
1278         }
1279 };
1280
1281 static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1282         .data = &(struct clk_regmap_gate_data){
1283                 .offset = HHI_VIID_CLK_DIV,
1284                 .bit_idx = 2,
1285         },
1286         .hw.init = &(struct clk_init_data){
1287                 .name = "vclk2_div4_en",
1288                 .ops = &clk_regmap_gate_ro_ops,
1289                 .parent_names = (const char *[]){ "vclk2_div4" },
1290                 .num_parents = 1,
1291                 .flags = CLK_SET_RATE_PARENT,
1292         },
1293 };
1294
1295 static struct clk_fixed_factor meson8b_vclk2_div6_div = {
1296         .mult = 1,
1297         .div = 6,
1298         .hw.init = &(struct clk_init_data){
1299                 .name = "vclk2_div6",
1300                 .ops = &clk_fixed_factor_ops,
1301                 .parent_names = (const char *[]){ "vclk2_in_en" },
1302                 .num_parents = 1,
1303                 .flags = CLK_SET_RATE_PARENT,
1304         }
1305 };
1306
1307 static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1308         .data = &(struct clk_regmap_gate_data){
1309                 .offset = HHI_VIID_CLK_DIV,
1310                 .bit_idx = 3,
1311         },
1312         .hw.init = &(struct clk_init_data){
1313                 .name = "vclk2_div6_en",
1314                 .ops = &clk_regmap_gate_ro_ops,
1315                 .parent_names = (const char *[]){ "vclk2_div6" },
1316                 .num_parents = 1,
1317                 .flags = CLK_SET_RATE_PARENT,
1318         },
1319 };
1320
1321 static struct clk_fixed_factor meson8b_vclk2_div12_div = {
1322         .mult = 1,
1323         .div = 12,
1324         .hw.init = &(struct clk_init_data){
1325                 .name = "vclk2_div12",
1326                 .ops = &clk_fixed_factor_ops,
1327                 .parent_names = (const char *[]){ "vclk2_in_en" },
1328                 .num_parents = 1,
1329                 .flags = CLK_SET_RATE_PARENT,
1330         }
1331 };
1332
1333 static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1334         .data = &(struct clk_regmap_gate_data){
1335                 .offset = HHI_VIID_CLK_DIV,
1336                 .bit_idx = 4,
1337         },
1338         .hw.init = &(struct clk_init_data){
1339                 .name = "vclk2_div12_en",
1340                 .ops = &clk_regmap_gate_ro_ops,
1341                 .parent_names = (const char *[]){ "vclk2_div12" },
1342                 .num_parents = 1,
1343                 .flags = CLK_SET_RATE_PARENT,
1344         },
1345 };
1346
1347 static const char * const meson8b_vclk_enc_mux_parents[] = {
1348         "vclk_div1_en", "vclk_div2_en", "vclk_div4_en", "vclk_div6_en",
1349         "vclk_div12_en",
1350 };
1351
1352 static struct clk_regmap meson8b_cts_enct_sel = {
1353         .data = &(struct clk_regmap_mux_data){
1354                 .offset = HHI_VID_CLK_DIV,
1355                 .mask = 0xf,
1356                 .shift = 20,
1357         },
1358         .hw.init = &(struct clk_init_data){
1359                 .name = "cts_enct_sel",
1360                 .ops = &clk_regmap_mux_ro_ops,
1361                 .parent_names = meson8b_vclk_enc_mux_parents,
1362                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
1363                 .flags = CLK_SET_RATE_PARENT,
1364         },
1365 };
1366
1367 static struct clk_regmap meson8b_cts_enct = {
1368         .data = &(struct clk_regmap_gate_data){
1369                 .offset = HHI_VID_CLK_CNTL2,
1370                 .bit_idx = 1,
1371         },
1372         .hw.init = &(struct clk_init_data){
1373                 .name = "cts_enct",
1374                 .ops = &clk_regmap_gate_ro_ops,
1375                 .parent_names = (const char *[]){ "cts_enct_sel" },
1376                 .num_parents = 1,
1377                 .flags = CLK_SET_RATE_PARENT,
1378         },
1379 };
1380
1381 static struct clk_regmap meson8b_cts_encp_sel = {
1382         .data = &(struct clk_regmap_mux_data){
1383                 .offset = HHI_VID_CLK_DIV,
1384                 .mask = 0xf,
1385                 .shift = 24,
1386         },
1387         .hw.init = &(struct clk_init_data){
1388                 .name = "cts_encp_sel",
1389                 .ops = &clk_regmap_mux_ro_ops,
1390                 .parent_names = meson8b_vclk_enc_mux_parents,
1391                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
1392                 .flags = CLK_SET_RATE_PARENT,
1393         },
1394 };
1395
1396 static struct clk_regmap meson8b_cts_encp = {
1397         .data = &(struct clk_regmap_gate_data){
1398                 .offset = HHI_VID_CLK_CNTL2,
1399                 .bit_idx = 2,
1400         },
1401         .hw.init = &(struct clk_init_data){
1402                 .name = "cts_encp",
1403                 .ops = &clk_regmap_gate_ro_ops,
1404                 .parent_names = (const char *[]){ "cts_encp_sel" },
1405                 .num_parents = 1,
1406                 .flags = CLK_SET_RATE_PARENT,
1407         },
1408 };
1409
1410 static struct clk_regmap meson8b_cts_enci_sel = {
1411         .data = &(struct clk_regmap_mux_data){
1412                 .offset = HHI_VID_CLK_DIV,
1413                 .mask = 0xf,
1414                 .shift = 28,
1415         },
1416         .hw.init = &(struct clk_init_data){
1417                 .name = "cts_enci_sel",
1418                 .ops = &clk_regmap_mux_ro_ops,
1419                 .parent_names = meson8b_vclk_enc_mux_parents,
1420                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
1421                 .flags = CLK_SET_RATE_PARENT,
1422         },
1423 };
1424
1425 static struct clk_regmap meson8b_cts_enci = {
1426         .data = &(struct clk_regmap_gate_data){
1427                 .offset = HHI_VID_CLK_CNTL2,
1428                 .bit_idx = 0,
1429         },
1430         .hw.init = &(struct clk_init_data){
1431                 .name = "cts_enci",
1432                 .ops = &clk_regmap_gate_ro_ops,
1433                 .parent_names = (const char *[]){ "cts_enci_sel" },
1434                 .num_parents = 1,
1435                 .flags = CLK_SET_RATE_PARENT,
1436         },
1437 };
1438
1439 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
1440         .data = &(struct clk_regmap_mux_data){
1441                 .offset = HHI_HDMI_CLK_CNTL,
1442                 .mask = 0xf,
1443                 .shift = 16,
1444         },
1445         .hw.init = &(struct clk_init_data){
1446                 .name = "hdmi_tx_pixel_sel",
1447                 .ops = &clk_regmap_mux_ro_ops,
1448                 .parent_names = meson8b_vclk_enc_mux_parents,
1449                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
1450                 .flags = CLK_SET_RATE_PARENT,
1451         },
1452 };
1453
1454 static struct clk_regmap meson8b_hdmi_tx_pixel = {
1455         .data = &(struct clk_regmap_gate_data){
1456                 .offset = HHI_VID_CLK_CNTL2,
1457                 .bit_idx = 5,
1458         },
1459         .hw.init = &(struct clk_init_data){
1460                 .name = "hdmi_tx_pixel",
1461                 .ops = &clk_regmap_gate_ro_ops,
1462                 .parent_names = (const char *[]){ "hdmi_tx_pixel_sel" },
1463                 .num_parents = 1,
1464                 .flags = CLK_SET_RATE_PARENT,
1465         },
1466 };
1467
1468 static const char * const meson8b_vclk2_enc_mux_parents[] = {
1469         "vclk2_div1_en", "vclk2_div2_en", "vclk2_div4_en", "vclk2_div6_en",
1470         "vclk2_div12_en",
1471 };
1472
1473 static struct clk_regmap meson8b_cts_encl_sel = {
1474         .data = &(struct clk_regmap_mux_data){
1475                 .offset = HHI_VIID_CLK_DIV,
1476                 .mask = 0xf,
1477                 .shift = 12,
1478         },
1479         .hw.init = &(struct clk_init_data){
1480                 .name = "cts_encl_sel",
1481                 .ops = &clk_regmap_mux_ro_ops,
1482                 .parent_names = meson8b_vclk2_enc_mux_parents,
1483                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents),
1484                 .flags = CLK_SET_RATE_PARENT,
1485         },
1486 };
1487
1488 static struct clk_regmap meson8b_cts_encl = {
1489         .data = &(struct clk_regmap_gate_data){
1490                 .offset = HHI_VID_CLK_CNTL2,
1491                 .bit_idx = 3,
1492         },
1493         .hw.init = &(struct clk_init_data){
1494                 .name = "cts_encl",
1495                 .ops = &clk_regmap_gate_ro_ops,
1496                 .parent_names = (const char *[]){ "cts_encl_sel" },
1497                 .num_parents = 1,
1498                 .flags = CLK_SET_RATE_PARENT,
1499         },
1500 };
1501
1502 static struct clk_regmap meson8b_cts_vdac0_sel = {
1503         .data = &(struct clk_regmap_mux_data){
1504                 .offset = HHI_VIID_CLK_DIV,
1505                 .mask = 0xf,
1506                 .shift = 28,
1507         },
1508         .hw.init = &(struct clk_init_data){
1509                 .name = "cts_vdac0_sel",
1510                 .ops = &clk_regmap_mux_ro_ops,
1511                 .parent_names = meson8b_vclk2_enc_mux_parents,
1512                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents),
1513                 .flags = CLK_SET_RATE_PARENT,
1514         },
1515 };
1516
1517 static struct clk_regmap meson8b_cts_vdac0 = {
1518         .data = &(struct clk_regmap_gate_data){
1519                 .offset = HHI_VID_CLK_CNTL2,
1520                 .bit_idx = 4,
1521         },
1522         .hw.init = &(struct clk_init_data){
1523                 .name = "cts_vdac0",
1524                 .ops = &clk_regmap_gate_ro_ops,
1525                 .parent_names = (const char *[]){ "cts_vdac0_sel" },
1526                 .num_parents = 1,
1527                 .flags = CLK_SET_RATE_PARENT,
1528         },
1529 };
1530
1531 static struct clk_regmap meson8b_hdmi_sys_sel = {
1532         .data = &(struct clk_regmap_mux_data){
1533                 .offset = HHI_HDMI_CLK_CNTL,
1534                 .mask = 0x3,
1535                 .shift = 9,
1536                 .flags = CLK_MUX_ROUND_CLOSEST,
1537         },
1538         .hw.init = &(struct clk_init_data){
1539                 .name = "hdmi_sys_sel",
1540                 .ops = &clk_regmap_mux_ro_ops,
1541                 /* FIXME: all other parents are unknown */
1542                 .parent_names = (const char *[]){ "xtal" },
1543                 .num_parents = 1,
1544                 .flags = CLK_SET_RATE_NO_REPARENT,
1545         },
1546 };
1547
1548 static struct clk_regmap meson8b_hdmi_sys_div = {
1549         .data = &(struct clk_regmap_div_data){
1550                 .offset = HHI_HDMI_CLK_CNTL,
1551                 .shift = 0,
1552                 .width = 7,
1553         },
1554         .hw.init = &(struct clk_init_data){
1555                 .name = "hdmi_sys_div",
1556                 .ops = &clk_regmap_divider_ro_ops,
1557                 .parent_names = (const char *[]){ "hdmi_sys_sel" },
1558                 .num_parents = 1,
1559                 .flags = CLK_SET_RATE_PARENT,
1560         },
1561 };
1562
1563 static struct clk_regmap meson8b_hdmi_sys = {
1564         .data = &(struct clk_regmap_gate_data){
1565                 .offset = HHI_HDMI_CLK_CNTL,
1566                 .bit_idx = 8,
1567         },
1568         .hw.init = &(struct clk_init_data) {
1569                 .name = "hdmi_sys",
1570                 .ops = &clk_regmap_gate_ro_ops,
1571                 .parent_names = (const char *[]){ "hdmi_sys_div" },
1572                 .num_parents = 1,
1573                 .flags = CLK_SET_RATE_PARENT,
1574         },
1575 };
1576
1577 /*
1578  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1579  * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
1580  * has mali_0 and no glitch-free mux.
1581  */
1582 static const char * const meson8b_mali_0_1_parent_names[] = {
1583         "xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3",
1584         "fclk_div5"
1585 };
1586
1587 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1588
1589 static struct clk_regmap meson8b_mali_0_sel = {
1590         .data = &(struct clk_regmap_mux_data){
1591                 .offset = HHI_MALI_CLK_CNTL,
1592                 .mask = 0x7,
1593                 .shift = 9,
1594                 .table = meson8b_mali_0_1_mux_table,
1595         },
1596         .hw.init = &(struct clk_init_data){
1597                 .name = "mali_0_sel",
1598                 .ops = &clk_regmap_mux_ops,
1599                 .parent_names = meson8b_mali_0_1_parent_names,
1600                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
1601                 /*
1602                  * Don't propagate rate changes up because the only changeable
1603                  * parents are mpll1 and mpll2 but we need those for audio and
1604                  * RGMII (Ethernet). We don't want to change the audio or
1605                  * Ethernet clocks when setting the GPU frequency.
1606                  */
1607                 .flags = 0,
1608         },
1609 };
1610
1611 static struct clk_regmap meson8b_mali_0_div = {
1612         .data = &(struct clk_regmap_div_data){
1613                 .offset = HHI_MALI_CLK_CNTL,
1614                 .shift = 0,
1615                 .width = 7,
1616         },
1617         .hw.init = &(struct clk_init_data){
1618                 .name = "mali_0_div",
1619                 .ops = &clk_regmap_divider_ops,
1620                 .parent_names = (const char *[]){ "mali_0_sel" },
1621                 .num_parents = 1,
1622                 .flags = CLK_SET_RATE_PARENT,
1623         },
1624 };
1625
1626 static struct clk_regmap meson8b_mali_0 = {
1627         .data = &(struct clk_regmap_gate_data){
1628                 .offset = HHI_MALI_CLK_CNTL,
1629                 .bit_idx = 8,
1630         },
1631         .hw.init = &(struct clk_init_data){
1632                 .name = "mali_0",
1633                 .ops = &clk_regmap_gate_ops,
1634                 .parent_names = (const char *[]){ "mali_0_div" },
1635                 .num_parents = 1,
1636                 .flags = CLK_SET_RATE_PARENT,
1637         },
1638 };
1639
1640 static struct clk_regmap meson8b_mali_1_sel = {
1641         .data = &(struct clk_regmap_mux_data){
1642                 .offset = HHI_MALI_CLK_CNTL,
1643                 .mask = 0x7,
1644                 .shift = 25,
1645                 .table = meson8b_mali_0_1_mux_table,
1646         },
1647         .hw.init = &(struct clk_init_data){
1648                 .name = "mali_1_sel",
1649                 .ops = &clk_regmap_mux_ops,
1650                 .parent_names = meson8b_mali_0_1_parent_names,
1651                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
1652                 /*
1653                  * Don't propagate rate changes up because the only changeable
1654                  * parents are mpll1 and mpll2 but we need those for audio and
1655                  * RGMII (Ethernet). We don't want to change the audio or
1656                  * Ethernet clocks when setting the GPU frequency.
1657                  */
1658                 .flags = 0,
1659         },
1660 };
1661
1662 static struct clk_regmap meson8b_mali_1_div = {
1663         .data = &(struct clk_regmap_div_data){
1664                 .offset = HHI_MALI_CLK_CNTL,
1665                 .shift = 16,
1666                 .width = 7,
1667         },
1668         .hw.init = &(struct clk_init_data){
1669                 .name = "mali_1_div",
1670                 .ops = &clk_regmap_divider_ops,
1671                 .parent_names = (const char *[]){ "mali_1_sel" },
1672                 .num_parents = 1,
1673                 .flags = CLK_SET_RATE_PARENT,
1674         },
1675 };
1676
1677 static struct clk_regmap meson8b_mali_1 = {
1678         .data = &(struct clk_regmap_gate_data){
1679                 .offset = HHI_MALI_CLK_CNTL,
1680                 .bit_idx = 24,
1681         },
1682         .hw.init = &(struct clk_init_data){
1683                 .name = "mali_1",
1684                 .ops = &clk_regmap_gate_ops,
1685                 .parent_names = (const char *[]){ "mali_1_div" },
1686                 .num_parents = 1,
1687                 .flags = CLK_SET_RATE_PARENT,
1688         },
1689 };
1690
1691 static struct clk_regmap meson8b_mali = {
1692         .data = &(struct clk_regmap_mux_data){
1693                 .offset = HHI_MALI_CLK_CNTL,
1694                 .mask = 1,
1695                 .shift = 31,
1696         },
1697         .hw.init = &(struct clk_init_data){
1698                 .name = "mali",
1699                 .ops = &clk_regmap_mux_ops,
1700                 .parent_names = (const char *[]){ "mali_0", "mali_1" },
1701                 .num_parents = 2,
1702                 .flags = CLK_SET_RATE_PARENT,
1703         },
1704 };
1705
1706 static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
1707         PLL_PARAMS(182, 3),
1708         { /* sentinel */ },
1709 };
1710
1711 static struct clk_regmap meson8m2_gp_pll_dco = {
1712         .data = &(struct meson_clk_pll_data){
1713                 .en = {
1714                         .reg_off = HHI_GP_PLL_CNTL,
1715                         .shift   = 30,
1716                         .width   = 1,
1717                 },
1718                 .m = {
1719                         .reg_off = HHI_GP_PLL_CNTL,
1720                         .shift   = 0,
1721                         .width   = 9,
1722                 },
1723                 .n = {
1724                         .reg_off = HHI_GP_PLL_CNTL,
1725                         .shift   = 9,
1726                         .width   = 5,
1727                 },
1728                 .l = {
1729                         .reg_off = HHI_GP_PLL_CNTL,
1730                         .shift   = 31,
1731                         .width   = 1,
1732                 },
1733                 .rst = {
1734                         .reg_off = HHI_GP_PLL_CNTL,
1735                         .shift   = 29,
1736                         .width   = 1,
1737                 },
1738                 .table = meson8m2_gp_pll_params_table,
1739         },
1740         .hw.init = &(struct clk_init_data){
1741                 .name = "gp_pll_dco",
1742                 .ops = &meson_clk_pll_ops,
1743                 .parent_names = (const char *[]){ "xtal" },
1744                 .num_parents = 1,
1745         },
1746 };
1747
1748 static struct clk_regmap meson8m2_gp_pll = {
1749         .data = &(struct clk_regmap_div_data){
1750                 .offset = HHI_GP_PLL_CNTL,
1751                 .shift = 16,
1752                 .width = 2,
1753                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1754         },
1755         .hw.init = &(struct clk_init_data){
1756                 .name = "gp_pll",
1757                 .ops = &clk_regmap_divider_ops,
1758                 .parent_names = (const char *[]){ "gp_pll_dco" },
1759                 .num_parents = 1,
1760                 .flags = CLK_SET_RATE_PARENT,
1761         },
1762 };
1763
1764 static const char * const meson8b_vpu_0_1_parent_names[] = {
1765         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1766 };
1767
1768 static const char * const mmeson8m2_vpu_0_1_parent_names[] = {
1769         "fclk_div4", "fclk_div3", "fclk_div5", "gp_pll"
1770 };
1771
1772 static struct clk_regmap meson8b_vpu_0_sel = {
1773         .data = &(struct clk_regmap_mux_data){
1774                 .offset = HHI_VPU_CLK_CNTL,
1775                 .mask = 0x3,
1776                 .shift = 9,
1777         },
1778         .hw.init = &(struct clk_init_data){
1779                 .name = "vpu_0_sel",
1780                 .ops = &clk_regmap_mux_ops,
1781                 .parent_names = meson8b_vpu_0_1_parent_names,
1782                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
1783                 .flags = CLK_SET_RATE_PARENT,
1784         },
1785 };
1786
1787 static struct clk_regmap meson8m2_vpu_0_sel = {
1788         .data = &(struct clk_regmap_mux_data){
1789                 .offset = HHI_VPU_CLK_CNTL,
1790                 .mask = 0x3,
1791                 .shift = 9,
1792         },
1793         .hw.init = &(struct clk_init_data){
1794                 .name = "vpu_0_sel",
1795                 .ops = &clk_regmap_mux_ops,
1796                 .parent_names = mmeson8m2_vpu_0_1_parent_names,
1797                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
1798                 .flags = CLK_SET_RATE_PARENT,
1799         },
1800 };
1801
1802 static struct clk_regmap meson8b_vpu_0_div = {
1803         .data = &(struct clk_regmap_div_data){
1804                 .offset = HHI_VPU_CLK_CNTL,
1805                 .shift = 0,
1806                 .width = 7,
1807         },
1808         .hw.init = &(struct clk_init_data){
1809                 .name = "vpu_0_div",
1810                 .ops = &clk_regmap_divider_ops,
1811                 .parent_names = (const char *[]){ "vpu_0_sel" },
1812                 .num_parents = 1,
1813                 .flags = CLK_SET_RATE_PARENT,
1814         },
1815 };
1816
1817 static struct clk_regmap meson8b_vpu_0 = {
1818         .data = &(struct clk_regmap_gate_data){
1819                 .offset = HHI_VPU_CLK_CNTL,
1820                 .bit_idx = 8,
1821         },
1822         .hw.init = &(struct clk_init_data) {
1823                 .name = "vpu_0",
1824                 .ops = &clk_regmap_gate_ops,
1825                 .parent_names = (const char *[]){ "vpu_0_div" },
1826                 .num_parents = 1,
1827                 .flags = CLK_SET_RATE_PARENT,
1828         },
1829 };
1830
1831 static struct clk_regmap meson8b_vpu_1_sel = {
1832         .data = &(struct clk_regmap_mux_data){
1833                 .offset = HHI_VPU_CLK_CNTL,
1834                 .mask = 0x3,
1835                 .shift = 25,
1836         },
1837         .hw.init = &(struct clk_init_data){
1838                 .name = "vpu_1_sel",
1839                 .ops = &clk_regmap_mux_ops,
1840                 .parent_names = meson8b_vpu_0_1_parent_names,
1841                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
1842                 .flags = CLK_SET_RATE_PARENT,
1843         },
1844 };
1845
1846 static struct clk_regmap meson8m2_vpu_1_sel = {
1847         .data = &(struct clk_regmap_mux_data){
1848                 .offset = HHI_VPU_CLK_CNTL,
1849                 .mask = 0x3,
1850                 .shift = 25,
1851         },
1852         .hw.init = &(struct clk_init_data){
1853                 .name = "vpu_1_sel",
1854                 .ops = &clk_regmap_mux_ops,
1855                 .parent_names = mmeson8m2_vpu_0_1_parent_names,
1856                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
1857                 .flags = CLK_SET_RATE_PARENT,
1858         },
1859 };
1860
1861 static struct clk_regmap meson8b_vpu_1_div = {
1862         .data = &(struct clk_regmap_div_data){
1863                 .offset = HHI_VPU_CLK_CNTL,
1864                 .shift = 16,
1865                 .width = 7,
1866         },
1867         .hw.init = &(struct clk_init_data){
1868                 .name = "vpu_1_div",
1869                 .ops = &clk_regmap_divider_ops,
1870                 .parent_names = (const char *[]){ "vpu_1_sel" },
1871                 .num_parents = 1,
1872                 .flags = CLK_SET_RATE_PARENT,
1873         },
1874 };
1875
1876 static struct clk_regmap meson8b_vpu_1 = {
1877         .data = &(struct clk_regmap_gate_data){
1878                 .offset = HHI_VPU_CLK_CNTL,
1879                 .bit_idx = 24,
1880         },
1881         .hw.init = &(struct clk_init_data) {
1882                 .name = "vpu_1",
1883                 .ops = &clk_regmap_gate_ops,
1884                 .parent_names = (const char *[]){ "vpu_1_div" },
1885                 .num_parents = 1,
1886                 .flags = CLK_SET_RATE_PARENT,
1887         },
1888 };
1889
1890 static struct clk_regmap meson8b_vpu = {
1891         .data = &(struct clk_regmap_mux_data){
1892                 .offset = HHI_VPU_CLK_CNTL,
1893                 .mask = 1,
1894                 .shift = 31,
1895         },
1896         .hw.init = &(struct clk_init_data){
1897                 .name = "vpu",
1898                 .ops = &clk_regmap_mux_ops,
1899                 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1900                 .num_parents = 2,
1901                 .flags = CLK_SET_RATE_NO_REPARENT,
1902         },
1903 };
1904
1905 static const char * const meson8b_vdec_parent_names[] = {
1906         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1"
1907 };
1908
1909 static struct clk_regmap meson8b_vdec_1_sel = {
1910         .data = &(struct clk_regmap_mux_data){
1911                 .offset = HHI_VDEC_CLK_CNTL,
1912                 .mask = 0x3,
1913                 .shift = 9,
1914                 .flags = CLK_MUX_ROUND_CLOSEST,
1915         },
1916         .hw.init = &(struct clk_init_data){
1917                 .name = "vdec_1_sel",
1918                 .ops = &clk_regmap_mux_ops,
1919                 .parent_names = meson8b_vdec_parent_names,
1920                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
1921                 .flags = CLK_SET_RATE_PARENT,
1922         },
1923 };
1924
1925 static struct clk_regmap meson8b_vdec_1_1_div = {
1926         .data = &(struct clk_regmap_div_data){
1927                 .offset = HHI_VDEC_CLK_CNTL,
1928                 .shift = 0,
1929                 .width = 7,
1930                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1931         },
1932         .hw.init = &(struct clk_init_data){
1933                 .name = "vdec_1_1_div",
1934                 .ops = &clk_regmap_divider_ops,
1935                 .parent_names = (const char *[]){ "vdec_1_sel" },
1936                 .num_parents = 1,
1937                 .flags = CLK_SET_RATE_PARENT,
1938         },
1939 };
1940
1941 static struct clk_regmap meson8b_vdec_1_1 = {
1942         .data = &(struct clk_regmap_gate_data){
1943                 .offset = HHI_VDEC_CLK_CNTL,
1944                 .bit_idx = 8,
1945         },
1946         .hw.init = &(struct clk_init_data) {
1947                 .name = "vdec_1_1",
1948                 .ops = &clk_regmap_gate_ops,
1949                 .parent_names = (const char *[]){ "vdec_1_1_div" },
1950                 .num_parents = 1,
1951                 .flags = CLK_SET_RATE_PARENT,
1952         },
1953 };
1954
1955 static struct clk_regmap meson8b_vdec_1_2_div = {
1956         .data = &(struct clk_regmap_div_data){
1957                 .offset = HHI_VDEC3_CLK_CNTL,
1958                 .shift = 0,
1959                 .width = 7,
1960                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1961         },
1962         .hw.init = &(struct clk_init_data){
1963                 .name = "vdec_1_2_div",
1964                 .ops = &clk_regmap_divider_ops,
1965                 .parent_names = (const char *[]){ "vdec_1_sel" },
1966                 .num_parents = 1,
1967                 .flags = CLK_SET_RATE_PARENT,
1968         },
1969 };
1970
1971 static struct clk_regmap meson8b_vdec_1_2 = {
1972         .data = &(struct clk_regmap_gate_data){
1973                 .offset = HHI_VDEC3_CLK_CNTL,
1974                 .bit_idx = 8,
1975         },
1976         .hw.init = &(struct clk_init_data) {
1977                 .name = "vdec_1_2",
1978                 .ops = &clk_regmap_gate_ops,
1979                 .parent_names = (const char *[]){ "vdec_1_2_div" },
1980                 .num_parents = 1,
1981                 .flags = CLK_SET_RATE_PARENT,
1982         },
1983 };
1984
1985 static struct clk_regmap meson8b_vdec_1 = {
1986         .data = &(struct clk_regmap_mux_data){
1987                 .offset = HHI_VDEC3_CLK_CNTL,
1988                 .mask = 0x1,
1989                 .shift = 15,
1990                 .flags = CLK_MUX_ROUND_CLOSEST,
1991         },
1992         .hw.init = &(struct clk_init_data){
1993                 .name = "vdec_1",
1994                 .ops = &clk_regmap_mux_ops,
1995                 .parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" },
1996                 .num_parents = 2,
1997                 .flags = CLK_SET_RATE_PARENT,
1998         },
1999 };
2000
2001 static struct clk_regmap meson8b_vdec_hcodec_sel = {
2002         .data = &(struct clk_regmap_mux_data){
2003                 .offset = HHI_VDEC_CLK_CNTL,
2004                 .mask = 0x3,
2005                 .shift = 25,
2006                 .flags = CLK_MUX_ROUND_CLOSEST,
2007         },
2008         .hw.init = &(struct clk_init_data){
2009                 .name = "vdec_hcodec_sel",
2010                 .ops = &clk_regmap_mux_ops,
2011                 .parent_names = meson8b_vdec_parent_names,
2012                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2013                 .flags = CLK_SET_RATE_PARENT,
2014         },
2015 };
2016
2017 static struct clk_regmap meson8b_vdec_hcodec_div = {
2018         .data = &(struct clk_regmap_div_data){
2019                 .offset = HHI_VDEC_CLK_CNTL,
2020                 .shift = 16,
2021                 .width = 7,
2022                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2023         },
2024         .hw.init = &(struct clk_init_data){
2025                 .name = "vdec_hcodec_div",
2026                 .ops = &clk_regmap_divider_ops,
2027                 .parent_names = (const char *[]){ "vdec_hcodec_sel" },
2028                 .num_parents = 1,
2029                 .flags = CLK_SET_RATE_PARENT,
2030         },
2031 };
2032
2033 static struct clk_regmap meson8b_vdec_hcodec = {
2034         .data = &(struct clk_regmap_gate_data){
2035                 .offset = HHI_VDEC_CLK_CNTL,
2036                 .bit_idx = 24,
2037         },
2038         .hw.init = &(struct clk_init_data) {
2039                 .name = "vdec_hcodec",
2040                 .ops = &clk_regmap_gate_ops,
2041                 .parent_names = (const char *[]){ "vdec_hcodec_div" },
2042                 .num_parents = 1,
2043                 .flags = CLK_SET_RATE_PARENT,
2044         },
2045 };
2046
2047 static struct clk_regmap meson8b_vdec_2_sel = {
2048         .data = &(struct clk_regmap_mux_data){
2049                 .offset = HHI_VDEC2_CLK_CNTL,
2050                 .mask = 0x3,
2051                 .shift = 9,
2052                 .flags = CLK_MUX_ROUND_CLOSEST,
2053         },
2054         .hw.init = &(struct clk_init_data){
2055                 .name = "vdec_2_sel",
2056                 .ops = &clk_regmap_mux_ops,
2057                 .parent_names = meson8b_vdec_parent_names,
2058                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2059                 .flags = CLK_SET_RATE_PARENT,
2060         },
2061 };
2062
2063 static struct clk_regmap meson8b_vdec_2_div = {
2064         .data = &(struct clk_regmap_div_data){
2065                 .offset = HHI_VDEC2_CLK_CNTL,
2066                 .shift = 0,
2067                 .width = 7,
2068                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2069         },
2070         .hw.init = &(struct clk_init_data){
2071                 .name = "vdec_2_div",
2072                 .ops = &clk_regmap_divider_ops,
2073                 .parent_names = (const char *[]){ "vdec_2_sel" },
2074                 .num_parents = 1,
2075                 .flags = CLK_SET_RATE_PARENT,
2076         },
2077 };
2078
2079 static struct clk_regmap meson8b_vdec_2 = {
2080         .data = &(struct clk_regmap_gate_data){
2081                 .offset = HHI_VDEC2_CLK_CNTL,
2082                 .bit_idx = 8,
2083         },
2084         .hw.init = &(struct clk_init_data) {
2085                 .name = "vdec_2",
2086                 .ops = &clk_regmap_gate_ops,
2087                 .parent_names = (const char *[]){ "vdec_2_div" },
2088                 .num_parents = 1,
2089                 .flags = CLK_SET_RATE_PARENT,
2090         },
2091 };
2092
2093 static struct clk_regmap meson8b_vdec_hevc_sel = {
2094         .data = &(struct clk_regmap_mux_data){
2095                 .offset = HHI_VDEC2_CLK_CNTL,
2096                 .mask = 0x3,
2097                 .shift = 25,
2098                 .flags = CLK_MUX_ROUND_CLOSEST,
2099         },
2100         .hw.init = &(struct clk_init_data){
2101                 .name = "vdec_hevc_sel",
2102                 .ops = &clk_regmap_mux_ops,
2103                 .parent_names = meson8b_vdec_parent_names,
2104                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2105                 .flags = CLK_SET_RATE_PARENT,
2106         },
2107 };
2108
2109 static struct clk_regmap meson8b_vdec_hevc_div = {
2110         .data = &(struct clk_regmap_div_data){
2111                 .offset = HHI_VDEC2_CLK_CNTL,
2112                 .shift = 16,
2113                 .width = 7,
2114                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2115         },
2116         .hw.init = &(struct clk_init_data){
2117                 .name = "vdec_hevc_div",
2118                 .ops = &clk_regmap_divider_ops,
2119                 .parent_names = (const char *[]){ "vdec_hevc_sel" },
2120                 .num_parents = 1,
2121                 .flags = CLK_SET_RATE_PARENT,
2122         },
2123 };
2124
2125 static struct clk_regmap meson8b_vdec_hevc_en = {
2126         .data = &(struct clk_regmap_gate_data){
2127                 .offset = HHI_VDEC2_CLK_CNTL,
2128                 .bit_idx = 24,
2129         },
2130         .hw.init = &(struct clk_init_data) {
2131                 .name = "vdec_hevc_en",
2132                 .ops = &clk_regmap_gate_ops,
2133                 .parent_names = (const char *[]){ "vdec_hevc_div" },
2134                 .num_parents = 1,
2135                 .flags = CLK_SET_RATE_PARENT,
2136         },
2137 };
2138
2139 static struct clk_regmap meson8b_vdec_hevc = {
2140         .data = &(struct clk_regmap_mux_data){
2141                 .offset = HHI_VDEC2_CLK_CNTL,
2142                 .mask = 0x1,
2143                 .shift = 31,
2144                 .flags = CLK_MUX_ROUND_CLOSEST,
2145         },
2146         .hw.init = &(struct clk_init_data){
2147                 .name = "vdec_hevc",
2148                 .ops = &clk_regmap_mux_ops,
2149                 /* TODO: The second parent is currently unknown */
2150                 .parent_names = (const char *[]){ "vdec_hevc_en" },
2151                 .num_parents = 1,
2152                 .flags = CLK_SET_RATE_PARENT,
2153         },
2154 };
2155
2156 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2157 static const char * const meson8b_cts_amclk_parent_names[] = {
2158         "mpll0", "mpll1", "mpll2"
2159 };
2160
2161 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
2162
2163 static struct clk_regmap meson8b_cts_amclk_sel = {
2164         .data = &(struct clk_regmap_mux_data){
2165                 .offset = HHI_AUD_CLK_CNTL,
2166                 .mask = 0x3,
2167                 .shift = 9,
2168                 .table = meson8b_cts_amclk_mux_table,
2169                 .flags = CLK_MUX_ROUND_CLOSEST,
2170         },
2171         .hw.init = &(struct clk_init_data){
2172                 .name = "cts_amclk_sel",
2173                 .ops = &clk_regmap_mux_ops,
2174                 .parent_names = meson8b_cts_amclk_parent_names,
2175                 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_names),
2176         },
2177 };
2178
2179 static struct clk_regmap meson8b_cts_amclk_div = {
2180         .data = &(struct clk_regmap_div_data) {
2181                 .offset = HHI_AUD_CLK_CNTL,
2182                 .shift = 0,
2183                 .width = 8,
2184                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2185         },
2186         .hw.init = &(struct clk_init_data){
2187                 .name = "cts_amclk_div",
2188                 .ops = &clk_regmap_divider_ops,
2189                 .parent_names = (const char *[]){ "cts_amclk_sel" },
2190                 .num_parents = 1,
2191                 .flags = CLK_SET_RATE_PARENT,
2192         },
2193 };
2194
2195 static struct clk_regmap meson8b_cts_amclk = {
2196         .data = &(struct clk_regmap_gate_data){
2197                 .offset = HHI_AUD_CLK_CNTL,
2198                 .bit_idx = 8,
2199         },
2200         .hw.init = &(struct clk_init_data){
2201                 .name = "cts_amclk",
2202                 .ops = &clk_regmap_gate_ops,
2203                 .parent_names = (const char *[]){ "cts_amclk_div" },
2204                 .num_parents = 1,
2205                 .flags = CLK_SET_RATE_PARENT,
2206         },
2207 };
2208
2209 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2210 static const char * const meson8b_cts_mclk_i958_parent_names[] = {
2211         "mpll0", "mpll1", "mpll2"
2212 };
2213
2214 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
2215
2216 static struct clk_regmap meson8b_cts_mclk_i958_sel = {
2217         .data = &(struct clk_regmap_mux_data){
2218                 .offset = HHI_AUD_CLK_CNTL2,
2219                 .mask = 0x3,
2220                 .shift = 25,
2221                 .table = meson8b_cts_mclk_i958_mux_table,
2222                 .flags = CLK_MUX_ROUND_CLOSEST,
2223         },
2224         .hw.init = &(struct clk_init_data) {
2225                 .name = "cts_mclk_i958_sel",
2226                 .ops = &clk_regmap_mux_ops,
2227                 .parent_names = meson8b_cts_mclk_i958_parent_names,
2228                 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_names),
2229         },
2230 };
2231
2232 static struct clk_regmap meson8b_cts_mclk_i958_div = {
2233         .data = &(struct clk_regmap_div_data){
2234                 .offset = HHI_AUD_CLK_CNTL2,
2235                 .shift = 16,
2236                 .width = 8,
2237                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2238         },
2239         .hw.init = &(struct clk_init_data) {
2240                 .name = "cts_mclk_i958_div",
2241                 .ops = &clk_regmap_divider_ops,
2242                 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
2243                 .num_parents = 1,
2244                 .flags = CLK_SET_RATE_PARENT,
2245         },
2246 };
2247
2248 static struct clk_regmap meson8b_cts_mclk_i958 = {
2249         .data = &(struct clk_regmap_gate_data){
2250                 .offset = HHI_AUD_CLK_CNTL2,
2251                 .bit_idx = 24,
2252         },
2253         .hw.init = &(struct clk_init_data){
2254                 .name = "cts_mclk_i958",
2255                 .ops = &clk_regmap_gate_ops,
2256                 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
2257                 .num_parents = 1,
2258                 .flags = CLK_SET_RATE_PARENT,
2259         },
2260 };
2261
2262 static struct clk_regmap meson8b_cts_i958 = {
2263         .data = &(struct clk_regmap_mux_data){
2264                 .offset = HHI_AUD_CLK_CNTL2,
2265                 .mask = 0x1,
2266                 .shift = 27,
2267                 },
2268         .hw.init = &(struct clk_init_data){
2269                 .name = "cts_i958",
2270                 .ops = &clk_regmap_mux_ops,
2271                 .parent_names = (const char *[]){ "cts_amclk",
2272                                                   "cts_mclk_i958" },
2273                 .num_parents = 2,
2274                 /*
2275                  * The parent is specific to origin of the audio data. Let the
2276                  * consumer choose the appropriate parent.
2277                  */
2278                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2279         },
2280 };
2281
2282 /* Everything Else (EE) domain gates */
2283
2284 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
2285 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
2286 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
2287 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
2288 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
2289 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
2290 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
2291 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
2292 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
2293 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
2294 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
2295 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
2296 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
2297 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
2298 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
2299 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
2300 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
2301 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
2302 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
2303
2304 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
2305 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
2306 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
2307 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
2308 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2309 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2310 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2311 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2312 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2313 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2314 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
2315 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
2316 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
2317 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
2318 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
2319 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
2320 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
2321 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
2322 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
2323 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
2324 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
2325 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
2326 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
2327 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
2328 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
2329
2330 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2331 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2332 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2333 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2334 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2335 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2336 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
2337 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
2338 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
2339 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
2340 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
2341 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2342 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
2343
2344 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
2345 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
2346 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2347 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2348 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
2349 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2350 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
2351 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
2352 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
2353 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
2354 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
2355 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
2356 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2357 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
2358 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
2359 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
2360
2361 /* Always On (AO) domain gates */
2362
2363 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
2364 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
2365 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
2366 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
2367
2368 static struct clk_hw_onecell_data meson8_hw_onecell_data = {
2369         .hws = {
2370                 [CLKID_XTAL] = &meson8b_xtal.hw,
2371                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2372                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2373                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2374                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2375                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2376                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2377                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2378                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2379                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2380                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2381                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2382                 [CLKID_CLK81] = &meson8b_clk81.hw,
2383                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2384                 [CLKID_DOS]                 = &meson8b_dos.hw,
2385                 [CLKID_ISA]                 = &meson8b_isa.hw,
2386                 [CLKID_PL301]               = &meson8b_pl301.hw,
2387                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2388                 [CLKID_SPICC]               = &meson8b_spicc.hw,
2389                 [CLKID_I2C]                 = &meson8b_i2c.hw,
2390                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2391                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2392                 [CLKID_RNG0]                = &meson8b_rng0.hw,
2393                 [CLKID_UART0]               = &meson8b_uart0.hw,
2394                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
2395                 [CLKID_STREAM]              = &meson8b_stream.hw,
2396                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2397                 [CLKID_SDIO]                = &meson8b_sdio.hw,
2398                 [CLKID_ABUF]                = &meson8b_abuf.hw,
2399                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2400                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2401                 [CLKID_SPI]                 = &meson8b_spi.hw,
2402                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2403                 [CLKID_ETH]                 = &meson8b_eth.hw,
2404                 [CLKID_DEMUX]               = &meson8b_demux.hw,
2405                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2406                 [CLKID_IEC958]              = &meson8b_iec958.hw,
2407                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2408                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
2409                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2410                 [CLKID_MIXER]               = &meson8b_mixer.hw,
2411                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2412                 [CLKID_ADC]                 = &meson8b_adc.hw,
2413                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2414                 [CLKID_AIU]                 = &meson8b_aiu.hw,
2415                 [CLKID_UART1]               = &meson8b_uart1.hw,
2416                 [CLKID_G2D]                 = &meson8b_g2d.hw,
2417                 [CLKID_USB0]                = &meson8b_usb0.hw,
2418                 [CLKID_USB1]                = &meson8b_usb1.hw,
2419                 [CLKID_RESET]               = &meson8b_reset.hw,
2420                 [CLKID_NAND]                = &meson8b_nand.hw,
2421                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2422                 [CLKID_USB]                 = &meson8b_usb.hw,
2423                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2424                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2425                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
2426                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2427                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2428                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2429                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2430                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2431                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2432                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2433                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2434                 [CLKID_DVIN]                = &meson8b_dvin.hw,
2435                 [CLKID_UART2]               = &meson8b_uart2.hw,
2436                 [CLKID_SANA]                = &meson8b_sana.hw,
2437                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2438                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2439                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2440                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2441                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2442                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2443                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2444                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2445                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2446                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2447                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2448                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2449                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2450                 [CLKID_RNG1]                = &meson8b_rng1.hw,
2451                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2452                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2453                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2454                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2455                 [CLKID_EDP]                 = &meson8b_edp.hw,
2456                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
2457                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
2458                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
2459                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
2460                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
2461                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
2462                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
2463                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
2464                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
2465                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
2466                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
2467                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
2468                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
2469                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
2470                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
2471                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
2472                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
2473                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
2474                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
2475                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
2476                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
2477                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
2478                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
2479                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
2480                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
2481                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
2482                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
2483                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
2484                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
2485                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
2486                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
2487                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
2488                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
2489                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
2490                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
2491                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
2492                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
2493                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
2494                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
2495                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
2496                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
2497                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
2498                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
2499                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
2500                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
2501                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
2502                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
2503                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
2504                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
2505                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
2506                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
2507                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
2508                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
2509                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
2510                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
2511                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
2512                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
2513                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
2514                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
2515                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
2516                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
2517                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
2518                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
2519                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
2520                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
2521                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
2522                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
2523                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
2524                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
2525                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
2526                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
2527                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
2528                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
2529                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
2530                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
2531                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
2532                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
2533                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
2534                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
2535                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
2536                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
2537                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
2538                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
2539                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
2540                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
2541                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
2542                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
2543                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
2544                 [CLKID_MALI]                = &meson8b_mali_0.hw,
2545                 [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
2546                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
2547                 [CLKID_VPU]                 = &meson8b_vpu_0.hw,
2548                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
2549                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
2550                 [CLKID_VDEC_1]              = &meson8b_vdec_1_1.hw,
2551                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
2552                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
2553                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
2554                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
2555                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
2556                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
2557                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
2558                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
2559                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
2560                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
2561                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
2562                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
2563                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
2564                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
2565                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
2566                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
2567                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
2568                 [CLK_NR_CLKS]               = NULL,
2569         },
2570         .num = CLK_NR_CLKS,
2571 };
2572
2573 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
2574         .hws = {
2575                 [CLKID_XTAL] = &meson8b_xtal.hw,
2576                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2577                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2578                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2579                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2580                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2581                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2582                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2583                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2584                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2585                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2586                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2587                 [CLKID_CLK81] = &meson8b_clk81.hw,
2588                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2589                 [CLKID_DOS]                 = &meson8b_dos.hw,
2590                 [CLKID_ISA]                 = &meson8b_isa.hw,
2591                 [CLKID_PL301]               = &meson8b_pl301.hw,
2592                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2593                 [CLKID_SPICC]               = &meson8b_spicc.hw,
2594                 [CLKID_I2C]                 = &meson8b_i2c.hw,
2595                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2596                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2597                 [CLKID_RNG0]                = &meson8b_rng0.hw,
2598                 [CLKID_UART0]               = &meson8b_uart0.hw,
2599                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
2600                 [CLKID_STREAM]              = &meson8b_stream.hw,
2601                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2602                 [CLKID_SDIO]                = &meson8b_sdio.hw,
2603                 [CLKID_ABUF]                = &meson8b_abuf.hw,
2604                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2605                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2606                 [CLKID_SPI]                 = &meson8b_spi.hw,
2607                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2608                 [CLKID_ETH]                 = &meson8b_eth.hw,
2609                 [CLKID_DEMUX]               = &meson8b_demux.hw,
2610                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2611                 [CLKID_IEC958]              = &meson8b_iec958.hw,
2612                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2613                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
2614                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2615                 [CLKID_MIXER]               = &meson8b_mixer.hw,
2616                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2617                 [CLKID_ADC]                 = &meson8b_adc.hw,
2618                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2619                 [CLKID_AIU]                 = &meson8b_aiu.hw,
2620                 [CLKID_UART1]               = &meson8b_uart1.hw,
2621                 [CLKID_G2D]                 = &meson8b_g2d.hw,
2622                 [CLKID_USB0]                = &meson8b_usb0.hw,
2623                 [CLKID_USB1]                = &meson8b_usb1.hw,
2624                 [CLKID_RESET]               = &meson8b_reset.hw,
2625                 [CLKID_NAND]                = &meson8b_nand.hw,
2626                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2627                 [CLKID_USB]                 = &meson8b_usb.hw,
2628                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2629                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2630                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
2631                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2632                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2633                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2634                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2635                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2636                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2637                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2638                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2639                 [CLKID_DVIN]                = &meson8b_dvin.hw,
2640                 [CLKID_UART2]               = &meson8b_uart2.hw,
2641                 [CLKID_SANA]                = &meson8b_sana.hw,
2642                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2643                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2644                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2645                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2646                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2647                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2648                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2649                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2650                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2651                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2652                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2653                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2654                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2655                 [CLKID_RNG1]                = &meson8b_rng1.hw,
2656                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2657                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2658                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2659                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2660                 [CLKID_EDP]                 = &meson8b_edp.hw,
2661                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
2662                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
2663                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
2664                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
2665                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
2666                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
2667                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
2668                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
2669                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
2670                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
2671                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
2672                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
2673                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
2674                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
2675                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
2676                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
2677                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
2678                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
2679                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
2680                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
2681                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
2682                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
2683                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
2684                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
2685                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
2686                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
2687                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
2688                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
2689                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
2690                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
2691                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
2692                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
2693                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
2694                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
2695                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
2696                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
2697                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
2698                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
2699                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
2700                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
2701                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
2702                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
2703                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
2704                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
2705                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
2706                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
2707                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
2708                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
2709                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
2710                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
2711                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
2712                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
2713                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
2714                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
2715                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
2716                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
2717                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
2718                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
2719                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
2720                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
2721                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
2722                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
2723                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
2724                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
2725                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
2726                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
2727                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
2728                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
2729                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
2730                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
2731                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
2732                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
2733                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
2734                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
2735                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
2736                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
2737                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
2738                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
2739                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
2740                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
2741                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
2742                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
2743                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
2744                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
2745                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
2746                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
2747                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
2748                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
2749                 [CLKID_MALI_0]              = &meson8b_mali_0.hw,
2750                 [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
2751                 [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
2752                 [CLKID_MALI_1]              = &meson8b_mali_1.hw,
2753                 [CLKID_MALI]                = &meson8b_mali.hw,
2754                 [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
2755                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
2756                 [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
2757                 [CLKID_VPU_1_SEL]           = &meson8b_vpu_1_sel.hw,
2758                 [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
2759                 [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
2760                 [CLKID_VPU]                 = &meson8b_vpu.hw,
2761                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
2762                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
2763                 [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
2764                 [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
2765                 [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
2766                 [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
2767                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
2768                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
2769                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
2770                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
2771                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
2772                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
2773                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
2774                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
2775                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
2776                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
2777                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
2778                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
2779                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
2780                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
2781                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
2782                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
2783                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
2784                 [CLK_NR_CLKS]               = NULL,
2785         },
2786         .num = CLK_NR_CLKS,
2787 };
2788
2789 static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
2790         .hws = {
2791                 [CLKID_XTAL] = &meson8b_xtal.hw,
2792                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2793                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2794                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2795                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2796                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2797                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2798                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2799                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2800                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2801                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2802                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2803                 [CLKID_CLK81] = &meson8b_clk81.hw,
2804                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2805                 [CLKID_DOS]                 = &meson8b_dos.hw,
2806                 [CLKID_ISA]                 = &meson8b_isa.hw,
2807                 [CLKID_PL301]               = &meson8b_pl301.hw,
2808                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2809                 [CLKID_SPICC]               = &meson8b_spicc.hw,
2810                 [CLKID_I2C]                 = &meson8b_i2c.hw,
2811                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2812                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2813                 [CLKID_RNG0]                = &meson8b_rng0.hw,
2814                 [CLKID_UART0]               = &meson8b_uart0.hw,
2815                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
2816                 [CLKID_STREAM]              = &meson8b_stream.hw,
2817                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2818                 [CLKID_SDIO]                = &meson8b_sdio.hw,
2819                 [CLKID_ABUF]                = &meson8b_abuf.hw,
2820                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2821                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2822                 [CLKID_SPI]                 = &meson8b_spi.hw,
2823                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2824                 [CLKID_ETH]                 = &meson8b_eth.hw,
2825                 [CLKID_DEMUX]               = &meson8b_demux.hw,
2826                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2827                 [CLKID_IEC958]              = &meson8b_iec958.hw,
2828                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2829                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
2830                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2831                 [CLKID_MIXER]               = &meson8b_mixer.hw,
2832                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2833                 [CLKID_ADC]                 = &meson8b_adc.hw,
2834                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2835                 [CLKID_AIU]                 = &meson8b_aiu.hw,
2836                 [CLKID_UART1]               = &meson8b_uart1.hw,
2837                 [CLKID_G2D]                 = &meson8b_g2d.hw,
2838                 [CLKID_USB0]                = &meson8b_usb0.hw,
2839                 [CLKID_USB1]                = &meson8b_usb1.hw,
2840                 [CLKID_RESET]               = &meson8b_reset.hw,
2841                 [CLKID_NAND]                = &meson8b_nand.hw,
2842                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2843                 [CLKID_USB]                 = &meson8b_usb.hw,
2844                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2845                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2846                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
2847                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2848                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2849                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2850                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2851                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2852                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2853                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2854                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2855                 [CLKID_DVIN]                = &meson8b_dvin.hw,
2856                 [CLKID_UART2]               = &meson8b_uart2.hw,
2857                 [CLKID_SANA]                = &meson8b_sana.hw,
2858                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2859                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2860                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2861                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2862                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2863                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2864                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2865                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2866                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2867                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2868                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2869                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2870                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2871                 [CLKID_RNG1]                = &meson8b_rng1.hw,
2872                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2873                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2874                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2875                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2876                 [CLKID_EDP]                 = &meson8b_edp.hw,
2877                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
2878                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
2879                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
2880                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
2881                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
2882                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
2883                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
2884                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
2885                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
2886                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
2887                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
2888                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
2889                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
2890                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
2891                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
2892                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
2893                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
2894                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
2895                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
2896                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
2897                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
2898                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
2899                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
2900                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
2901                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
2902                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
2903                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
2904                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
2905                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
2906                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
2907                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
2908                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
2909                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
2910                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
2911                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
2912                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
2913                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
2914                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
2915                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
2916                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
2917                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
2918                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
2919                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
2920                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
2921                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
2922                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
2923                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
2924                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
2925                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
2926                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
2927                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
2928                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
2929                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
2930                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
2931                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
2932                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
2933                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
2934                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
2935                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
2936                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
2937                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
2938                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
2939                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
2940                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
2941                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
2942                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
2943                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
2944                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
2945                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
2946                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
2947                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
2948                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
2949                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
2950                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
2951                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
2952                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
2953                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
2954                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
2955                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
2956                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
2957                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
2958                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
2959                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
2960                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
2961                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
2962                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
2963                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
2964                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
2965                 [CLKID_MALI_0]              = &meson8b_mali_0.hw,
2966                 [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
2967                 [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
2968                 [CLKID_MALI_1]              = &meson8b_mali_1.hw,
2969                 [CLKID_MALI]                = &meson8b_mali.hw,
2970                 [CLKID_GP_PLL_DCO]          = &meson8m2_gp_pll_dco.hw,
2971                 [CLKID_GP_PLL]              = &meson8m2_gp_pll.hw,
2972                 [CLKID_VPU_0_SEL]           = &meson8m2_vpu_0_sel.hw,
2973                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
2974                 [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
2975                 [CLKID_VPU_1_SEL]           = &meson8m2_vpu_1_sel.hw,
2976                 [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
2977                 [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
2978                 [CLKID_VPU]                 = &meson8b_vpu.hw,
2979                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
2980                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
2981                 [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
2982                 [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
2983                 [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
2984                 [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
2985                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
2986                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
2987                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
2988                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
2989                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
2990                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
2991                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
2992                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
2993                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
2994                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
2995                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
2996                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
2997                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
2998                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
2999                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3000                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3001                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3002                 [CLK_NR_CLKS]               = NULL,
3003         },
3004         .num = CLK_NR_CLKS,
3005 };
3006
3007 static struct clk_regmap *const meson8b_clk_regmaps[] = {
3008         &meson8b_clk81,
3009         &meson8b_ddr,
3010         &meson8b_dos,
3011         &meson8b_isa,
3012         &meson8b_pl301,
3013         &meson8b_periphs,
3014         &meson8b_spicc,
3015         &meson8b_i2c,
3016         &meson8b_sar_adc,
3017         &meson8b_smart_card,
3018         &meson8b_rng0,
3019         &meson8b_uart0,
3020         &meson8b_sdhc,
3021         &meson8b_stream,
3022         &meson8b_async_fifo,
3023         &meson8b_sdio,
3024         &meson8b_abuf,
3025         &meson8b_hiu_iface,
3026         &meson8b_assist_misc,
3027         &meson8b_spi,
3028         &meson8b_i2s_spdif,
3029         &meson8b_eth,
3030         &meson8b_demux,
3031         &meson8b_aiu_glue,
3032         &meson8b_iec958,
3033         &meson8b_i2s_out,
3034         &meson8b_amclk,
3035         &meson8b_aififo2,
3036         &meson8b_mixer,
3037         &meson8b_mixer_iface,
3038         &meson8b_adc,
3039         &meson8b_blkmv,
3040         &meson8b_aiu,
3041         &meson8b_uart1,
3042         &meson8b_g2d,
3043         &meson8b_usb0,
3044         &meson8b_usb1,
3045         &meson8b_reset,
3046         &meson8b_nand,
3047         &meson8b_dos_parser,
3048         &meson8b_usb,
3049         &meson8b_vdin1,
3050         &meson8b_ahb_arb0,
3051         &meson8b_efuse,
3052         &meson8b_boot_rom,
3053         &meson8b_ahb_data_bus,
3054         &meson8b_ahb_ctrl_bus,
3055         &meson8b_hdmi_intr_sync,
3056         &meson8b_hdmi_pclk,
3057         &meson8b_usb1_ddr_bridge,
3058         &meson8b_usb0_ddr_bridge,
3059         &meson8b_mmc_pclk,
3060         &meson8b_dvin,
3061         &meson8b_uart2,
3062         &meson8b_sana,
3063         &meson8b_vpu_intr,
3064         &meson8b_sec_ahb_ahb3_bridge,
3065         &meson8b_clk81_a9,
3066         &meson8b_vclk2_venci0,
3067         &meson8b_vclk2_venci1,
3068         &meson8b_vclk2_vencp0,
3069         &meson8b_vclk2_vencp1,
3070         &meson8b_gclk_venci_int,
3071         &meson8b_gclk_vencp_int,
3072         &meson8b_dac_clk,
3073         &meson8b_aoclk_gate,
3074         &meson8b_iec958_gate,
3075         &meson8b_enc480p,
3076         &meson8b_rng1,
3077         &meson8b_gclk_vencl_int,
3078         &meson8b_vclk2_venclmcc,
3079         &meson8b_vclk2_vencl,
3080         &meson8b_vclk2_other,
3081         &meson8b_edp,
3082         &meson8b_ao_media_cpu,
3083         &meson8b_ao_ahb_sram,
3084         &meson8b_ao_ahb_bus,
3085         &meson8b_ao_iface,
3086         &meson8b_mpeg_clk_div,
3087         &meson8b_mpeg_clk_sel,
3088         &meson8b_mpll0,
3089         &meson8b_mpll1,
3090         &meson8b_mpll2,
3091         &meson8b_mpll0_div,
3092         &meson8b_mpll1_div,
3093         &meson8b_mpll2_div,
3094         &meson8b_fixed_pll,
3095         &meson8b_sys_pll,
3096         &meson8b_cpu_in_sel,
3097         &meson8b_cpu_scale_div,
3098         &meson8b_cpu_scale_out_sel,
3099         &meson8b_cpu_clk,
3100         &meson8b_mpll_prediv,
3101         &meson8b_fclk_div2,
3102         &meson8b_fclk_div3,
3103         &meson8b_fclk_div4,
3104         &meson8b_fclk_div5,
3105         &meson8b_fclk_div7,
3106         &meson8b_nand_clk_sel,
3107         &meson8b_nand_clk_div,
3108         &meson8b_nand_clk_gate,
3109         &meson8b_fixed_pll_dco,
3110         &meson8b_hdmi_pll_dco,
3111         &meson8b_sys_pll_dco,
3112         &meson8b_apb_clk_sel,
3113         &meson8b_apb_clk_gate,
3114         &meson8b_periph_clk_sel,
3115         &meson8b_periph_clk_gate,
3116         &meson8b_axi_clk_sel,
3117         &meson8b_axi_clk_gate,
3118         &meson8b_l2_dram_clk_sel,
3119         &meson8b_l2_dram_clk_gate,
3120         &meson8b_hdmi_pll_lvds_out,
3121         &meson8b_hdmi_pll_hdmi_out,
3122         &meson8b_vid_pll_in_sel,
3123         &meson8b_vid_pll_in_en,
3124         &meson8b_vid_pll_pre_div,
3125         &meson8b_vid_pll_post_div,
3126         &meson8b_vid_pll,
3127         &meson8b_vid_pll_final_div,
3128         &meson8b_vclk_in_sel,
3129         &meson8b_vclk_in_en,
3130         &meson8b_vclk_div1_gate,
3131         &meson8b_vclk_div2_div_gate,
3132         &meson8b_vclk_div4_div_gate,
3133         &meson8b_vclk_div6_div_gate,
3134         &meson8b_vclk_div12_div_gate,
3135         &meson8b_vclk2_in_sel,
3136         &meson8b_vclk2_clk_in_en,
3137         &meson8b_vclk2_div1_gate,
3138         &meson8b_vclk2_div2_div_gate,
3139         &meson8b_vclk2_div4_div_gate,
3140         &meson8b_vclk2_div6_div_gate,
3141         &meson8b_vclk2_div12_div_gate,
3142         &meson8b_cts_enct_sel,
3143         &meson8b_cts_enct,
3144         &meson8b_cts_encp_sel,
3145         &meson8b_cts_encp,
3146         &meson8b_cts_enci_sel,
3147         &meson8b_cts_enci,
3148         &meson8b_hdmi_tx_pixel_sel,
3149         &meson8b_hdmi_tx_pixel,
3150         &meson8b_cts_encl_sel,
3151         &meson8b_cts_encl,
3152         &meson8b_cts_vdac0_sel,
3153         &meson8b_cts_vdac0,
3154         &meson8b_hdmi_sys_sel,
3155         &meson8b_hdmi_sys_div,
3156         &meson8b_hdmi_sys,
3157         &meson8b_mali_0_sel,
3158         &meson8b_mali_0_div,
3159         &meson8b_mali_0,
3160         &meson8b_mali_1_sel,
3161         &meson8b_mali_1_div,
3162         &meson8b_mali_1,
3163         &meson8b_mali,
3164         &meson8m2_gp_pll_dco,
3165         &meson8m2_gp_pll,
3166         &meson8b_vpu_0_sel,
3167         &meson8m2_vpu_0_sel,
3168         &meson8b_vpu_0_div,
3169         &meson8b_vpu_0,
3170         &meson8b_vpu_1_sel,
3171         &meson8m2_vpu_1_sel,
3172         &meson8b_vpu_1_div,
3173         &meson8b_vpu_1,
3174         &meson8b_vpu,
3175         &meson8b_vdec_1_sel,
3176         &meson8b_vdec_1_1_div,
3177         &meson8b_vdec_1_1,
3178         &meson8b_vdec_1_2_div,
3179         &meson8b_vdec_1_2,
3180         &meson8b_vdec_1,
3181         &meson8b_vdec_hcodec_sel,
3182         &meson8b_vdec_hcodec_div,
3183         &meson8b_vdec_hcodec,
3184         &meson8b_vdec_2_sel,
3185         &meson8b_vdec_2_div,
3186         &meson8b_vdec_2,
3187         &meson8b_vdec_hevc_sel,
3188         &meson8b_vdec_hevc_div,
3189         &meson8b_vdec_hevc_en,
3190         &meson8b_vdec_hevc,
3191         &meson8b_cts_amclk,
3192         &meson8b_cts_amclk_sel,
3193         &meson8b_cts_amclk_div,
3194         &meson8b_cts_mclk_i958_sel,
3195         &meson8b_cts_mclk_i958_div,
3196         &meson8b_cts_mclk_i958,
3197         &meson8b_cts_i958,
3198 };
3199
3200 static const struct meson8b_clk_reset_line {
3201         u32 reg;
3202         u8 bit_idx;
3203 } meson8b_clk_reset_bits[] = {
3204         [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
3205                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
3206         },
3207         [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
3208                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
3209         },
3210         [CLKC_RESET_SCU_SOFT_RESET] = {
3211                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
3212         },
3213         [CLKC_RESET_CPU3_SOFT_RESET] = {
3214                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
3215         },
3216         [CLKC_RESET_CPU2_SOFT_RESET] = {
3217                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
3218         },
3219         [CLKC_RESET_CPU1_SOFT_RESET] = {
3220                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
3221         },
3222         [CLKC_RESET_CPU0_SOFT_RESET] = {
3223                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
3224         },
3225         [CLKC_RESET_A5_GLOBAL_RESET] = {
3226                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
3227         },
3228         [CLKC_RESET_A5_AXI_SOFT_RESET] = {
3229                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
3230         },
3231         [CLKC_RESET_A5_ABP_SOFT_RESET] = {
3232                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
3233         },
3234         [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
3235                 .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
3236         },
3237         [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
3238                 .reg = HHI_VID_CLK_CNTL, .bit_idx = 15
3239         },
3240         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
3241                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
3242         },
3243         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
3244                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
3245         },
3246         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
3247                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
3248         },
3249         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
3250                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
3251         },
3252 };
3253
3254 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
3255                                     unsigned long id, bool assert)
3256 {
3257         struct meson8b_clk_reset *meson8b_clk_reset =
3258                 container_of(rcdev, struct meson8b_clk_reset, reset);
3259         unsigned long flags;
3260         const struct meson8b_clk_reset_line *reset;
3261
3262         if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
3263                 return -EINVAL;
3264
3265         reset = &meson8b_clk_reset_bits[id];
3266
3267         spin_lock_irqsave(&meson_clk_lock, flags);
3268
3269         if (assert)
3270                 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
3271                                    BIT(reset->bit_idx), BIT(reset->bit_idx));
3272         else
3273                 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
3274                                    BIT(reset->bit_idx), 0);
3275
3276         spin_unlock_irqrestore(&meson_clk_lock, flags);
3277
3278         return 0;
3279 }
3280
3281 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
3282                                      unsigned long id)
3283 {
3284         return meson8b_clk_reset_update(rcdev, id, true);
3285 }
3286
3287 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
3288                                        unsigned long id)
3289 {
3290         return meson8b_clk_reset_update(rcdev, id, false);
3291 }
3292
3293 static const struct reset_control_ops meson8b_clk_reset_ops = {
3294         .assert = meson8b_clk_reset_assert,
3295         .deassert = meson8b_clk_reset_deassert,
3296 };
3297
3298 struct meson8b_nb_data {
3299         struct notifier_block nb;
3300         struct clk_hw_onecell_data *onecell_data;
3301 };
3302
3303 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
3304                                        unsigned long event, void *data)
3305 {
3306         struct meson8b_nb_data *nb_data =
3307                 container_of(nb, struct meson8b_nb_data, nb);
3308         struct clk_hw **hws = nb_data->onecell_data->hws;
3309         struct clk_hw *cpu_clk_hw, *parent_clk_hw;
3310         struct clk *cpu_clk, *parent_clk;
3311         int ret;
3312
3313         switch (event) {
3314         case PRE_RATE_CHANGE:
3315                 parent_clk_hw = hws[CLKID_XTAL];
3316                 break;
3317
3318         case POST_RATE_CHANGE:
3319                 parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL];
3320                 break;
3321
3322         default:
3323                 return NOTIFY_DONE;
3324         }
3325
3326         cpu_clk_hw = hws[CLKID_CPUCLK];
3327         cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw));
3328
3329         parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw));
3330
3331         ret = clk_set_parent(cpu_clk, parent_clk);
3332         if (ret)
3333                 return notifier_from_errno(ret);
3334
3335         udelay(100);
3336
3337         return NOTIFY_OK;
3338 }
3339
3340 static struct meson8b_nb_data meson8b_cpu_nb_data = {
3341         .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
3342 };
3343
3344 static const struct regmap_config clkc_regmap_config = {
3345         .reg_bits       = 32,
3346         .val_bits       = 32,
3347         .reg_stride     = 4,
3348 };
3349
3350 static void __init meson8b_clkc_init_common(struct device_node *np,
3351                         struct clk_hw_onecell_data *clk_hw_onecell_data)
3352 {
3353         struct meson8b_clk_reset *rstc;
3354         const char *notifier_clk_name;
3355         struct clk *notifier_clk;
3356         void __iomem *clk_base;
3357         struct regmap *map;
3358         int i, ret;
3359
3360         map = syscon_node_to_regmap(of_get_parent(np));
3361         if (IS_ERR(map)) {
3362                 pr_info("failed to get HHI regmap - Trying obsolete regs\n");
3363
3364                 /* Generic clocks, PLLs and some of the reset-bits */
3365                 clk_base = of_iomap(np, 1);
3366                 if (!clk_base) {
3367                         pr_err("%s: Unable to map clk base\n", __func__);
3368                         return;
3369                 }
3370
3371                 map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
3372                 if (IS_ERR(map))
3373                         return;
3374         }
3375
3376         rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
3377         if (!rstc)
3378                 return;
3379
3380         /* Reset Controller */
3381         rstc->regmap = map;
3382         rstc->reset.ops = &meson8b_clk_reset_ops;
3383         rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
3384         rstc->reset.of_node = np;
3385         ret = reset_controller_register(&rstc->reset);
3386         if (ret) {
3387                 pr_err("%s: Failed to register clkc reset controller: %d\n",
3388                        __func__, ret);
3389                 return;
3390         }
3391
3392         /* Populate regmap for the regmap backed clocks */
3393         for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
3394                 meson8b_clk_regmaps[i]->map = map;
3395
3396         /*
3397          * register all clks
3398          * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
3399          */
3400         for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
3401                 /* array might be sparse */
3402                 if (!clk_hw_onecell_data->hws[i])
3403                         continue;
3404
3405                 ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]);
3406                 if (ret)
3407                         return;
3408         }
3409
3410         meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
3411
3412         /*
3413          * FIXME we shouldn't program the muxes in notifier handlers. The
3414          * tricky programming sequence will be handled by the forthcoming
3415          * coordinated clock rates mechanism once that feature is released.
3416          */
3417         notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
3418         notifier_clk = __clk_lookup(notifier_clk_name);
3419         ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
3420         if (ret) {
3421                 pr_err("%s: failed to register the CPU clock notifier\n",
3422                        __func__);
3423                 return;
3424         }
3425
3426         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
3427                                      clk_hw_onecell_data);
3428         if (ret)
3429                 pr_err("%s: failed to register clock provider\n", __func__);
3430 }
3431
3432 static void __init meson8_clkc_init(struct device_node *np)
3433 {
3434         return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
3435 }
3436
3437 static void __init meson8b_clkc_init(struct device_node *np)
3438 {
3439         return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
3440 }
3441
3442 static void __init meson8m2_clkc_init(struct device_node *np)
3443 {
3444         return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
3445 }
3446
3447 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3448                       meson8_clkc_init);
3449 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3450                       meson8b_clkc_init);
3451 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
3452                       meson8m2_clkc_init);