drivers/clk/meson/axg.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AmLogic Meson-AXG Clock Controller Driver
   4  *
   5  * Copyright (c) 2016 Baylibre SAS.
   6  * Author: Michael Turquette <mturquette@baylibre.com>
   7  *
   8  * Copyright (c) 2017 Amlogic, inc.
   9  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/init.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19
  20 #include "clkc.h"
  21 #include "axg.h"
  22
  23 static DEFINE_SPINLOCK(meson_clk_lock);
  24
  25 static struct clk_regmap axg_fixed_pll = {
  26         .data = &(struct meson_clk_pll_data){
  27                 .m = {
  28                         .reg_off = HHI_MPLL_CNTL,
  29                         .shift   = 0,
  30                         .width   = 9,
  31                 },
  32                 .n = {
  33                         .reg_off = HHI_MPLL_CNTL,
  34                         .shift   = 9,
  35                         .width   = 5,
  36                 },
  37                 .od = {
  38                         .reg_off = HHI_MPLL_CNTL,
  39                         .shift   = 16,
  40                         .width   = 2,
  41                 },
  42                 .frac = {
  43                         .reg_off = HHI_MPLL_CNTL2,
  44                         .shift   = 0,
  45                         .width   = 12,
  46                 },
  47                 .l = {
  48                         .reg_off = HHI_MPLL_CNTL,
  49                         .shift   = 31,
  50                         .width   = 1,
  51                 },
  52                 .rst = {
  53                         .reg_off = HHI_MPLL_CNTL,
  54                         .shift   = 29,
  55                         .width   = 1,
  56                 },
  57         },
  58         .hw.init = &(struct clk_init_data){
  59                 .name = "fixed_pll",
  60                 .ops = &meson_clk_pll_ro_ops,
  61                 .parent_names = (const char *[]){ "xtal" },
  62                 .num_parents = 1,
  63         },
  64 };
  65
  66 static struct clk_regmap axg_sys_pll = {
  67         .data = &(struct meson_clk_pll_data){
  68                 .m = {
  69                         .reg_off = HHI_SYS_PLL_CNTL,
  70                         .shift   = 0,
  71                         .width   = 9,
  72                 },
  73                 .n = {
  74                         .reg_off = HHI_SYS_PLL_CNTL,
  75                         .shift   = 9,
  76                         .width   = 5,
  77                 },
  78                 .od = {
  79                         .reg_off = HHI_SYS_PLL_CNTL,
  80                         .shift   = 16,
  81                         .width   = 2,
  82                 },
  83                 .l = {
  84                         .reg_off = HHI_SYS_PLL_CNTL,
  85                         .shift   = 31,
  86                         .width   = 1,
  87                 },
  88                 .rst = {
  89                         .reg_off = HHI_SYS_PLL_CNTL,
  90                         .shift   = 29,
  91                         .width   = 1,
  92                 },
  93         },
  94         .hw.init = &(struct clk_init_data){
  95                 .name = "sys_pll",
  96                 .ops = &meson_clk_pll_ro_ops,
  97                 .parent_names = (const char *[]){ "xtal" },
  98                 .num_parents = 1,
  99                 .flags = CLK_GET_RATE_NOCACHE,
 100         },
 101 };
 102
 103 static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
 104         PLL_RATE(240000000, 40, 1, 2),
 105         PLL_RATE(246000000, 41, 1, 2),
 106         PLL_RATE(252000000, 42, 1, 2),
 107         PLL_RATE(258000000, 43, 1, 2),
 108         PLL_RATE(264000000, 44, 1, 2),
 109         PLL_RATE(270000000, 45, 1, 2),
 110         PLL_RATE(276000000, 46, 1, 2),
 111         PLL_RATE(282000000, 47, 1, 2),
 112         PLL_RATE(288000000, 48, 1, 2),
 113         PLL_RATE(294000000, 49, 1, 2),
 114         PLL_RATE(300000000, 50, 1, 2),
 115         PLL_RATE(306000000, 51, 1, 2),
 116         PLL_RATE(312000000, 52, 1, 2),
 117         PLL_RATE(318000000, 53, 1, 2),
 118         PLL_RATE(324000000, 54, 1, 2),
 119         PLL_RATE(330000000, 55, 1, 2),
 120         PLL_RATE(336000000, 56, 1, 2),
 121         PLL_RATE(342000000, 57, 1, 2),
 122         PLL_RATE(348000000, 58, 1, 2),
 123         PLL_RATE(354000000, 59, 1, 2),
 124         PLL_RATE(360000000, 60, 1, 2),
 125         PLL_RATE(366000000, 61, 1, 2),
 126         PLL_RATE(372000000, 62, 1, 2),
 127         PLL_RATE(378000000, 63, 1, 2),
 128         PLL_RATE(384000000, 64, 1, 2),
 129         PLL_RATE(390000000, 65, 1, 3),
 130         PLL_RATE(396000000, 66, 1, 3),
 131         PLL_RATE(402000000, 67, 1, 3),
 132         PLL_RATE(408000000, 68, 1, 3),
 133         PLL_RATE(480000000, 40, 1, 1),
 134         PLL_RATE(492000000, 41, 1, 1),
 135         PLL_RATE(504000000, 42, 1, 1),
 136         PLL_RATE(516000000, 43, 1, 1),
 137         PLL_RATE(528000000, 44, 1, 1),
 138         PLL_RATE(540000000, 45, 1, 1),
 139         PLL_RATE(552000000, 46, 1, 1),
 140         PLL_RATE(564000000, 47, 1, 1),
 141         PLL_RATE(576000000, 48, 1, 1),
 142         PLL_RATE(588000000, 49, 1, 1),
 143         PLL_RATE(600000000, 50, 1, 1),
 144         PLL_RATE(612000000, 51, 1, 1),
 145         PLL_RATE(624000000, 52, 1, 1),
 146         PLL_RATE(636000000, 53, 1, 1),
 147         PLL_RATE(648000000, 54, 1, 1),
 148         PLL_RATE(660000000, 55, 1, 1),
 149         PLL_RATE(672000000, 56, 1, 1),
 150         PLL_RATE(684000000, 57, 1, 1),
 151         PLL_RATE(696000000, 58, 1, 1),
 152         PLL_RATE(708000000, 59, 1, 1),
 153         PLL_RATE(720000000, 60, 1, 1),
 154         PLL_RATE(732000000, 61, 1, 1),
 155         PLL_RATE(744000000, 62, 1, 1),
 156         PLL_RATE(756000000, 63, 1, 1),
 157         PLL_RATE(768000000, 64, 1, 1),
 158         PLL_RATE(780000000, 65, 1, 1),
 159         PLL_RATE(792000000, 66, 1, 1),
 160         PLL_RATE(804000000, 67, 1, 1),
 161         PLL_RATE(816000000, 68, 1, 1),
 162         PLL_RATE(960000000, 40, 1, 0),
 163         PLL_RATE(984000000, 41, 1, 0),
 164         PLL_RATE(1008000000, 42, 1, 0),
 165         PLL_RATE(1032000000, 43, 1, 0),
 166         PLL_RATE(1056000000, 44, 1, 0),
 167         PLL_RATE(1080000000, 45, 1, 0),
 168         PLL_RATE(1104000000, 46, 1, 0),
 169         PLL_RATE(1128000000, 47, 1, 0),
 170         PLL_RATE(1152000000, 48, 1, 0),
 171         PLL_RATE(1176000000, 49, 1, 0),
 172         PLL_RATE(1200000000, 50, 1, 0),
 173         PLL_RATE(1224000000, 51, 1, 0),
 174         PLL_RATE(1248000000, 52, 1, 0),
 175         PLL_RATE(1272000000, 53, 1, 0),
 176         PLL_RATE(1296000000, 54, 1, 0),
 177         PLL_RATE(1320000000, 55, 1, 0),
 178         PLL_RATE(1344000000, 56, 1, 0),
 179         PLL_RATE(1368000000, 57, 1, 0),
 180         PLL_RATE(1392000000, 58, 1, 0),
 181         PLL_RATE(1416000000, 59, 1, 0),
 182         PLL_RATE(1440000000, 60, 1, 0),
 183         PLL_RATE(1464000000, 61, 1, 0),
 184         PLL_RATE(1488000000, 62, 1, 0),
 185         PLL_RATE(1512000000, 63, 1, 0),
 186         PLL_RATE(1536000000, 64, 1, 0),
 187         PLL_RATE(1560000000, 65, 1, 0),
 188         PLL_RATE(1584000000, 66, 1, 0),
 189         PLL_RATE(1608000000, 67, 1, 0),
 190         PLL_RATE(1632000000, 68, 1, 0),
 191         { /* sentinel */ },
 192 };
 193
 194 const struct reg_sequence axg_gp0_init_regs[] = {
 195         { .reg = HHI_GP0_PLL_CNTL,      .def = 0x40010250 },
 196         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084a000 },
 197         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 198         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 199         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 200         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 201 };
 202
 203 static struct clk_regmap axg_gp0_pll = {
 204         .data = &(struct meson_clk_pll_data){
 205                 .m = {
 206                         .reg_off = HHI_GP0_PLL_CNTL,
 207                         .shift   = 0,
 208                         .width   = 9,
 209                 },
 210                 .n = {
 211                         .reg_off = HHI_GP0_PLL_CNTL,
 212                         .shift   = 9,
 213                         .width   = 5,
 214                 },
 215                 .od = {
 216                         .reg_off = HHI_GP0_PLL_CNTL,
 217                         .shift   = 16,
 218                         .width   = 2,
 219                 },
 220                 .l = {
 221                         .reg_off = HHI_GP0_PLL_CNTL,
 222                         .shift   = 31,
 223                         .width   = 1,
 224                 },
 225                 .rst = {
 226                         .reg_off = HHI_GP0_PLL_CNTL,
 227                         .shift   = 29,
 228                         .width   = 1,
 229                 },
 230                 .table = axg_gp0_pll_rate_table,
 231                 .init_regs = axg_gp0_init_regs,
 232                 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
 233                 .flags = CLK_MESON_PLL_LOCK_LOOP_RST,
 234         },
 235         .hw.init = &(struct clk_init_data){
 236                 .name = "gp0_pll",
 237                 .ops = &meson_clk_pll_ops,
 238                 .parent_names = (const char *[]){ "xtal" },
 239                 .num_parents = 1,
 240         },
 241 };
 242
 243
 244 static struct clk_fixed_factor axg_fclk_div2 = {
 245         .mult = 1,
 246         .div = 2,
 247         .hw.init = &(struct clk_init_data){
 248                 .name = "fclk_div2",
 249                 .ops = &clk_fixed_factor_ops,
 250                 .parent_names = (const char *[]){ "fixed_pll" },
 251                 .num_parents = 1,
 252         },
 253 };
 254
 255 static struct clk_fixed_factor axg_fclk_div3 = {
 256         .mult = 1,
 257         .div = 3,
 258         .hw.init = &(struct clk_init_data){
 259                 .name = "fclk_div3",
 260                 .ops = &clk_fixed_factor_ops,
 261                 .parent_names = (const char *[]){ "fixed_pll" },
 262                 .num_parents = 1,
 263         },
 264 };
 265
 266 static struct clk_fixed_factor axg_fclk_div4 = {
 267         .mult = 1,
 268         .div = 4,
 269         .hw.init = &(struct clk_init_data){
 270                 .name = "fclk_div4",
 271                 .ops = &clk_fixed_factor_ops,
 272                 .parent_names = (const char *[]){ "fixed_pll" },
 273                 .num_parents = 1,
 274         },
 275 };
 276
 277 static struct clk_fixed_factor axg_fclk_div5 = {
 278         .mult = 1,
 279         .div = 5,
 280         .hw.init = &(struct clk_init_data){
 281                 .name = "fclk_div5",
 282                 .ops = &clk_fixed_factor_ops,
 283                 .parent_names = (const char *[]){ "fixed_pll" },
 284                 .num_parents = 1,
 285         },
 286 };
 287
 288 static struct clk_fixed_factor axg_fclk_div7 = {
 289         .mult = 1,
 290         .div = 7,
 291         .hw.init = &(struct clk_init_data){
 292                 .name = "fclk_div7",
 293                 .ops = &clk_fixed_factor_ops,
 294                 .parent_names = (const char *[]){ "fixed_pll" },
 295                 .num_parents = 1,
 296         },
 297 };
 298
 299 static struct clk_regmap axg_mpll0_div = {
 300         .data = &(struct meson_clk_mpll_data){
 301                 .sdm = {
 302                         .reg_off = HHI_MPLL_CNTL7,
 303                         .shift   = 0,
 304                         .width   = 14,
 305                 },
 306                 .sdm_en = {
 307                         .reg_off = HHI_MPLL_CNTL7,
 308                         .shift   = 15,
 309                         .width   = 1,
 310                 },
 311                 .n2 = {
 312                         .reg_off = HHI_MPLL_CNTL7,
 313                         .shift   = 16,
 314                         .width   = 9,
 315                 },
 316                 .ssen = {
 317                         .reg_off = HHI_MPLL_CNTL,
 318                         .shift   = 25,
 319                         .width   = 1,
 320                 },
 321                 .misc = {
 322                         .reg_off = HHI_PLL_TOP_MISC,
 323                         .shift   = 0,
 324                         .width   = 1,
 325                 },
 326                 .lock = &meson_clk_lock,
 327         },
 328         .hw.init = &(struct clk_init_data){
 329                 .name = "mpll0_div",
 330                 .ops = &meson_clk_mpll_ops,
 331                 .parent_names = (const char *[]){ "fixed_pll" },
 332                 .num_parents = 1,
 333         },
 334 };
 335
 336 static struct clk_regmap axg_mpll0 = {
 337         .data = &(struct clk_regmap_gate_data){
 338                 .offset = HHI_MPLL_CNTL7,
 339                 .bit_idx = 14,
 340         },
 341         .hw.init = &(struct clk_init_data){
 342                 .name = "mpll0",
 343                 .ops = &clk_regmap_gate_ops,
 344                 .parent_names = (const char *[]){ "mpll0_div" },
 345                 .num_parents = 1,
 346                 .flags = CLK_SET_RATE_PARENT,
 347         },
 348 };
 349
 350 static struct clk_regmap axg_mpll1_div = {
 351         .data = &(struct meson_clk_mpll_data){
 352                 .sdm = {
 353                         .reg_off = HHI_MPLL_CNTL8,
 354                         .shift   = 0,
 355                         .width   = 14,
 356                 },
 357                 .sdm_en = {
 358                         .reg_off = HHI_MPLL_CNTL8,
 359                         .shift   = 15,
 360                         .width   = 1,
 361                 },
 362                 .n2 = {
 363                         .reg_off = HHI_MPLL_CNTL8,
 364                         .shift   = 16,
 365                         .width   = 9,
 366                 },
 367                 .misc = {
 368                         .reg_off = HHI_PLL_TOP_MISC,
 369                         .shift   = 1,
 370                         .width   = 1,
 371                 },
 372                 .lock = &meson_clk_lock,
 373         },
 374         .hw.init = &(struct clk_init_data){
 375                 .name = "mpll1_div",
 376                 .ops = &meson_clk_mpll_ops,
 377                 .parent_names = (const char *[]){ "fixed_pll" },
 378                 .num_parents = 1,
 379         },
 380 };
 381
 382 static struct clk_regmap axg_mpll1 = {
 383         .data = &(struct clk_regmap_gate_data){
 384                 .offset = HHI_MPLL_CNTL8,
 385                 .bit_idx = 14,
 386         },
 387         .hw.init = &(struct clk_init_data){
 388                 .name = "mpll1",
 389                 .ops = &clk_regmap_gate_ops,
 390                 .parent_names = (const char *[]){ "mpll1_div" },
 391                 .num_parents = 1,
 392                 .flags = CLK_SET_RATE_PARENT,
 393         },
 394 };
 395
 396 static struct clk_regmap axg_mpll2_div = {
 397         .data = &(struct meson_clk_mpll_data){
 398                 .sdm = {
 399                         .reg_off = HHI_MPLL_CNTL9,
 400                         .shift   = 0,
 401                         .width   = 14,
 402                 },
 403                 .sdm_en = {
 404                         .reg_off = HHI_MPLL_CNTL9,
 405                         .shift   = 15,
 406                         .width   = 1,
 407                 },
 408                 .n2 = {
 409                         .reg_off = HHI_MPLL_CNTL9,
 410                         .shift   = 16,
 411                         .width   = 9,
 412                 },
 413                 .misc = {
 414                         .reg_off = HHI_PLL_TOP_MISC,
 415                         .shift   = 2,
 416                         .width   = 1,
 417                 },
 418                 .lock = &meson_clk_lock,
 419         },
 420         .hw.init = &(struct clk_init_data){
 421                 .name = "mpll2_div",
 422                 .ops = &meson_clk_mpll_ops,
 423                 .parent_names = (const char *[]){ "fixed_pll" },
 424                 .num_parents = 1,
 425         },
 426 };
 427
 428 static struct clk_regmap axg_mpll2 = {
 429         .data = &(struct clk_regmap_gate_data){
 430                 .offset = HHI_MPLL_CNTL9,
 431                 .bit_idx = 14,
 432         },
 433         .hw.init = &(struct clk_init_data){
 434                 .name = "mpll2",
 435                 .ops = &clk_regmap_gate_ops,
 436                 .parent_names = (const char *[]){ "mpll2_div" },
 437                 .num_parents = 1,
 438                 .flags = CLK_SET_RATE_PARENT,
 439         },
 440 };
 441
 442 static struct clk_regmap axg_mpll3_div = {
 443         .data = &(struct meson_clk_mpll_data){
 444                 .sdm = {
 445                         .reg_off = HHI_MPLL3_CNTL0,
 446                         .shift   = 12,
 447                         .width   = 14,
 448                 },
 449                 .sdm_en = {
 450                         .reg_off = HHI_MPLL3_CNTL0,
 451                         .shift   = 11,
 452                         .width   = 1,
 453                 },
 454                 .n2 = {
 455                         .reg_off = HHI_MPLL3_CNTL0,
 456                         .shift   = 2,
 457                         .width   = 9,
 458                 },
 459                 .misc = {
 460                         .reg_off = HHI_PLL_TOP_MISC,
 461                         .shift   = 3,
 462                         .width   = 1,
 463                 },
 464                 .lock = &meson_clk_lock,
 465         },
 466         .hw.init = &(struct clk_init_data){
 467                 .name = "mpll3_div",
 468                 .ops = &meson_clk_mpll_ops,
 469                 .parent_names = (const char *[]){ "fixed_pll" },
 470                 .num_parents = 1,
 471         },
 472 };
 473
 474 static struct clk_regmap axg_mpll3 = {
 475         .data = &(struct clk_regmap_gate_data){
 476                 .offset = HHI_MPLL3_CNTL0,
 477                 .bit_idx = 0,
 478         },
 479         .hw.init = &(struct clk_init_data){
 480                 .name = "mpll3",
 481                 .ops = &clk_regmap_gate_ops,
 482                 .parent_names = (const char *[]){ "mpll3_div" },
 483                 .num_parents = 1,
 484                 .flags = CLK_SET_RATE_PARENT,
 485         },
 486 };
 487
 488 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 489 static const char * const clk81_parent_names[] = {
 490         "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
 491         "fclk_div3", "fclk_div5"
 492 };
 493
 494 static struct clk_regmap axg_mpeg_clk_sel = {
 495         .data = &(struct clk_regmap_mux_data){
 496                 .offset = HHI_MPEG_CLK_CNTL,
 497                 .mask = 0x7,
 498                 .shift = 12,
 499                 .table = mux_table_clk81,
 500         },
 501         .hw.init = &(struct clk_init_data){
 502                 .name = "mpeg_clk_sel",
 503                 .ops = &clk_regmap_mux_ro_ops,
 504                 .parent_names = clk81_parent_names,
 505                 .num_parents = ARRAY_SIZE(clk81_parent_names),
 506         },
 507 };
 508
 509 static struct clk_regmap axg_mpeg_clk_div = {
 510         .data = &(struct clk_regmap_div_data){
 511                 .offset = HHI_MPEG_CLK_CNTL,
 512                 .shift = 0,
 513                 .width = 7,
 514         },
 515         .hw.init = &(struct clk_init_data){
 516                 .name = "mpeg_clk_div",
 517                 .ops = &clk_regmap_divider_ops,
 518                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 519                 .num_parents = 1,
 520                 .flags = CLK_SET_RATE_PARENT,
 521         },
 522 };
 523
 524 static struct clk_regmap axg_clk81 = {
 525         .data = &(struct clk_regmap_gate_data){
 526                 .offset = HHI_MPEG_CLK_CNTL,
 527                 .bit_idx = 7,
 528         },
 529         .hw.init = &(struct clk_init_data){
 530                 .name = "clk81",
 531                 .ops = &clk_regmap_gate_ops,
 532                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 533                 .num_parents = 1,
 534                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
 535         },
 536 };
 537
 538 static const char * const axg_sd_emmc_clk0_parent_names[] = {
 539         "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
 540
 541         /*
 542          * Following these parent clocks, we should also have had mpll2, mpll3
 543          * and gp0_pll but these clocks are too precious to be used here. All
 544          * the necessary rates for MMC and NAND operation can be acheived using
 545          * xtal or fclk_div clocks
 546          */
 547 };
 548
 549 /* SDcard clock */
 550 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
 551         .data = &(struct clk_regmap_mux_data){
 552                 .offset = HHI_SD_EMMC_CLK_CNTL,
 553                 .mask = 0x7,
 554                 .shift = 25,
 555         },
 556         .hw.init = &(struct clk_init_data) {
 557                 .name = "sd_emmc_b_clk0_sel",
 558                 .ops = &clk_regmap_mux_ops,
 559                 .parent_names = axg_sd_emmc_clk0_parent_names,
 560                 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
 561                 .flags = CLK_SET_RATE_PARENT,
 562         },
 563 };
 564
 565 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
 566         .data = &(struct clk_regmap_div_data){
 567                 .offset = HHI_SD_EMMC_CLK_CNTL,
 568                 .shift = 16,
 569                 .width = 7,
 570                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 571         },
 572         .hw.init = &(struct clk_init_data) {
 573                 .name = "sd_emmc_b_clk0_div",
 574                 .ops = &clk_regmap_divider_ops,
 575                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
 576                 .num_parents = 1,
 577                 .flags = CLK_SET_RATE_PARENT,
 578         },
 579 };
 580
 581 static struct clk_regmap axg_sd_emmc_b_clk0 = {
 582         .data = &(struct clk_regmap_gate_data){
 583                 .offset = HHI_SD_EMMC_CLK_CNTL,
 584                 .bit_idx = 23,
 585         },
 586         .hw.init = &(struct clk_init_data){
 587                 .name = "sd_emmc_b_clk0",
 588                 .ops = &clk_regmap_gate_ops,
 589                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
 590                 .num_parents = 1,
 591                 .flags = CLK_SET_RATE_PARENT,
 592         },
 593 };
 594
 595 /* EMMC/NAND clock */
 596 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
 597         .data = &(struct clk_regmap_mux_data){
 598                 .offset = HHI_NAND_CLK_CNTL,
 599                 .mask = 0x7,
 600                 .shift = 9,
 601         },
 602         .hw.init = &(struct clk_init_data) {
 603                 .name = "sd_emmc_c_clk0_sel",
 604                 .ops = &clk_regmap_mux_ops,
 605                 .parent_names = axg_sd_emmc_clk0_parent_names,
 606                 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
 607                 .flags = CLK_SET_RATE_PARENT,
 608         },
 609 };
 610
 611 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
 612         .data = &(struct clk_regmap_div_data){
 613                 .offset = HHI_NAND_CLK_CNTL,
 614                 .shift = 0,
 615                 .width = 7,
 616                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 617         },
 618         .hw.init = &(struct clk_init_data) {
 619                 .name = "sd_emmc_c_clk0_div",
 620                 .ops = &clk_regmap_divider_ops,
 621                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
 622                 .num_parents = 1,
 623                 .flags = CLK_SET_RATE_PARENT,
 624         },
 625 };
 626
 627 static struct clk_regmap axg_sd_emmc_c_clk0 = {
 628         .data = &(struct clk_regmap_gate_data){
 629                 .offset = HHI_NAND_CLK_CNTL,
 630                 .bit_idx = 7,
 631         },
 632         .hw.init = &(struct clk_init_data){
 633                 .name = "sd_emmc_c_clk0",
 634                 .ops = &clk_regmap_gate_ops,
 635                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
 636                 .num_parents = 1,
 637                 .flags = CLK_SET_RATE_PARENT,
 638         },
 639 };
 640
 641 /* Everything Else (EE) domain gates */
 642 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
 643 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
 644 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
 645 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
 646 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
 647 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
 648 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
 649 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
 650 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
 651 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
 652 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
 653 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
 654 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
 655 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
 656 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
 657 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
 658 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
 659 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
 660 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
 661 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
 662
 663 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
 664 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
 665 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
 666 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
 667 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
 668 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
 669 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
 670 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
 671 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
 672 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
 673 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
 674
 675 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
 676 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
 677 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
 678 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
 679 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
 680 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
 681 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
 682 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
 683
 684 /* Always On (AO) domain gates */
 685
 686 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
 687 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
 688 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
 689 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
 690 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
 691
 692 /* Array of all clocks provided by this provider */
 693
 694 static struct clk_hw_onecell_data axg_hw_onecell_data = {
 695         .hws = {
 696                 [CLKID_SYS_PLL]                 = &axg_sys_pll.hw,
 697                 [CLKID_FIXED_PLL]               = &axg_fixed_pll.hw,
 698                 [CLKID_FCLK_DIV2]               = &axg_fclk_div2.hw,
 699                 [CLKID_FCLK_DIV3]               = &axg_fclk_div3.hw,
 700                 [CLKID_FCLK_DIV4]               = &axg_fclk_div4.hw,
 701                 [CLKID_FCLK_DIV5]               = &axg_fclk_div5.hw,
 702                 [CLKID_FCLK_DIV7]               = &axg_fclk_div7.hw,
 703                 [CLKID_GP0_PLL]                 = &axg_gp0_pll.hw,
 704                 [CLKID_MPEG_SEL]                = &axg_mpeg_clk_sel.hw,
 705                 [CLKID_MPEG_DIV]                = &axg_mpeg_clk_div.hw,
 706                 [CLKID_CLK81]                   = &axg_clk81.hw,
 707                 [CLKID_MPLL0]                   = &axg_mpll0.hw,
 708                 [CLKID_MPLL1]                   = &axg_mpll1.hw,
 709                 [CLKID_MPLL2]                   = &axg_mpll2.hw,
 710                 [CLKID_MPLL3]                   = &axg_mpll3.hw,
 711                 [CLKID_DDR]                     = &axg_ddr.hw,
 712                 [CLKID_AUDIO_LOCKER]            = &axg_audio_locker.hw,
 713                 [CLKID_MIPI_DSI_HOST]           = &axg_mipi_dsi_host.hw,
 714                 [CLKID_ISA]                     = &axg_isa.hw,
 715                 [CLKID_PL301]                   = &axg_pl301.hw,
 716                 [CLKID_PERIPHS]                 = &axg_periphs.hw,
 717                 [CLKID_SPICC0]                  = &axg_spicc_0.hw,
 718                 [CLKID_I2C]                     = &axg_i2c.hw,
 719                 [CLKID_RNG0]                    = &axg_rng0.hw,
 720                 [CLKID_UART0]                   = &axg_uart0.hw,
 721                 [CLKID_MIPI_DSI_PHY]            = &axg_mipi_dsi_phy.hw,
 722                 [CLKID_SPICC1]                  = &axg_spicc_1.hw,
 723                 [CLKID_PCIE_A]                  = &axg_pcie_a.hw,
 724                 [CLKID_PCIE_B]                  = &axg_pcie_b.hw,
 725                 [CLKID_HIU_IFACE]               = &axg_hiu_reg.hw,
 726                 [CLKID_ASSIST_MISC]             = &axg_assist_misc.hw,
 727                 [CLKID_SD_EMMC_B]               = &axg_emmc_b.hw,
 728                 [CLKID_SD_EMMC_C]               = &axg_emmc_c.hw,
 729                 [CLKID_DMA]                     = &axg_dma.hw,
 730                 [CLKID_SPI]                     = &axg_spi.hw,
 731                 [CLKID_AUDIO]                   = &axg_audio.hw,
 732                 [CLKID_ETH]                     = &axg_eth_core.hw,
 733                 [CLKID_UART1]                   = &axg_uart1.hw,
 734                 [CLKID_G2D]                     = &axg_g2d.hw,
 735                 [CLKID_USB0]                    = &axg_usb0.hw,
 736                 [CLKID_USB1]                    = &axg_usb1.hw,
 737                 [CLKID_RESET]                   = &axg_reset.hw,
 738                 [CLKID_USB]                     = &axg_usb_general.hw,
 739                 [CLKID_AHB_ARB0]                = &axg_ahb_arb0.hw,
 740                 [CLKID_EFUSE]                   = &axg_efuse.hw,
 741                 [CLKID_BOOT_ROM]                = &axg_boot_rom.hw,
 742                 [CLKID_AHB_DATA_BUS]            = &axg_ahb_data_bus.hw,
 743                 [CLKID_AHB_CTRL_BUS]            = &axg_ahb_ctrl_bus.hw,
 744                 [CLKID_USB1_DDR_BRIDGE]         = &axg_usb1_to_ddr.hw,
 745                 [CLKID_USB0_DDR_BRIDGE]         = &axg_usb0_to_ddr.hw,
 746                 [CLKID_MMC_PCLK]                = &axg_mmc_pclk.hw,
 747                 [CLKID_VPU_INTR]                = &axg_vpu_intr.hw,
 748                 [CLKID_SEC_AHB_AHB3_BRIDGE]     = &axg_sec_ahb_ahb3_bridge.hw,
 749                 [CLKID_GIC]                     = &axg_gic.hw,
 750                 [CLKID_AO_MEDIA_CPU]            = &axg_ao_media_cpu.hw,
 751                 [CLKID_AO_AHB_SRAM]             = &axg_ao_ahb_sram.hw,
 752                 [CLKID_AO_AHB_BUS]              = &axg_ao_ahb_bus.hw,
 753                 [CLKID_AO_IFACE]                = &axg_ao_iface.hw,
 754                 [CLKID_AO_I2C]                  = &axg_ao_i2c.hw,
 755                 [CLKID_SD_EMMC_B_CLK0_SEL]      = &axg_sd_emmc_b_clk0_sel.hw,
 756                 [CLKID_SD_EMMC_B_CLK0_DIV]      = &axg_sd_emmc_b_clk0_div.hw,
 757                 [CLKID_SD_EMMC_B_CLK0]          = &axg_sd_emmc_b_clk0.hw,
 758                 [CLKID_SD_EMMC_C_CLK0_SEL]      = &axg_sd_emmc_c_clk0_sel.hw,
 759                 [CLKID_SD_EMMC_C_CLK0_DIV]      = &axg_sd_emmc_c_clk0_div.hw,
 760                 [CLKID_SD_EMMC_C_CLK0]          = &axg_sd_emmc_c_clk0.hw,
 761                 [CLKID_MPLL0_DIV]               = &axg_mpll0_div.hw,
 762                 [CLKID_MPLL1_DIV]               = &axg_mpll1_div.hw,
 763                 [CLKID_MPLL2_DIV]               = &axg_mpll2_div.hw,
 764                 [CLKID_MPLL3_DIV]               = &axg_mpll3_div.hw,
 765                 [NR_CLKS]                       = NULL,
 766         },
 767         .num = NR_CLKS,
 768 };
 769
 770 /* Convenience table to populate regmap in .probe */
 771 static struct clk_regmap *const axg_clk_regmaps[] = {
 772         &axg_clk81,
 773         &axg_ddr,
 774         &axg_audio_locker,
 775         &axg_mipi_dsi_host,
 776         &axg_isa,
 777         &axg_pl301,
 778         &axg_periphs,
 779         &axg_spicc_0,
 780         &axg_i2c,
 781         &axg_rng0,
 782         &axg_uart0,
 783         &axg_mipi_dsi_phy,
 784         &axg_spicc_1,
 785         &axg_pcie_a,
 786         &axg_pcie_b,
 787         &axg_hiu_reg,
 788         &axg_assist_misc,
 789         &axg_emmc_b,
 790         &axg_emmc_c,
 791         &axg_dma,
 792         &axg_spi,
 793         &axg_audio,
 794         &axg_eth_core,
 795         &axg_uart1,
 796         &axg_g2d,
 797         &axg_usb0,
 798         &axg_usb1,
 799         &axg_reset,
 800         &axg_usb_general,
 801         &axg_ahb_arb0,
 802         &axg_efuse,
 803         &axg_boot_rom,
 804         &axg_ahb_data_bus,
 805         &axg_ahb_ctrl_bus,
 806         &axg_usb1_to_ddr,
 807         &axg_usb0_to_ddr,
 808         &axg_mmc_pclk,
 809         &axg_vpu_intr,
 810         &axg_sec_ahb_ahb3_bridge,
 811         &axg_gic,
 812         &axg_ao_media_cpu,
 813         &axg_ao_ahb_sram,
 814         &axg_ao_ahb_bus,
 815         &axg_ao_iface,
 816         &axg_ao_i2c,
 817         &axg_sd_emmc_b_clk0,
 818         &axg_sd_emmc_c_clk0,
 819         &axg_mpeg_clk_div,
 820         &axg_sd_emmc_b_clk0_div,
 821         &axg_sd_emmc_c_clk0_div,
 822         &axg_mpeg_clk_sel,
 823         &axg_sd_emmc_b_clk0_sel,
 824         &axg_sd_emmc_c_clk0_sel,
 825         &axg_mpll0,
 826         &axg_mpll1,
 827         &axg_mpll2,
 828         &axg_mpll3,
 829         &axg_mpll0_div,
 830         &axg_mpll1_div,
 831         &axg_mpll2_div,
 832         &axg_mpll3_div,
 833         &axg_fixed_pll,
 834         &axg_sys_pll,
 835         &axg_gp0_pll,
 836 };
 837
 838 static const struct of_device_id clkc_match_table[] = {
 839         { .compatible = "amlogic,axg-clkc" },
 840         {}
 841 };
 842
 843 static const struct regmap_config clkc_regmap_config = {
 844         .reg_bits       = 32,
 845         .val_bits       = 32,
 846         .reg_stride     = 4,
 847 };
 848
 849 static int axg_clkc_probe(struct platform_device *pdev)
 850 {
 851         struct device *dev = &pdev->dev;
 852         struct resource *res;
 853         void __iomem *clk_base;
 854         struct regmap *map;
 855         int ret, i;
 856
 857         /*  Generic clocks and PLLs */
 858         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 859         if (!res)
 860                 return -EINVAL;
 861
 862         clk_base = devm_ioremap(dev, res->start, resource_size(res));
 863         if (!clk_base) {
 864                 dev_err(dev, "Unable to map clk base\n");
 865                 return -ENXIO;
 866         }
 867
 868         map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config);
 869         if (IS_ERR(map))
 870                 return PTR_ERR(map);
 871
 872         /* Populate regmap for the regmap backed clocks */
 873         for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
 874                 axg_clk_regmaps[i]->map = map;
 875
 876         for (i = 0; i < axg_hw_onecell_data.num; i++) {
 877                 /* array might be sparse */
 878                 if (!axg_hw_onecell_data.hws[i])
 879                         continue;
 880
 881                 ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]);
 882                 if (ret) {
 883                         dev_err(dev, "Clock registration failed\n");
 884                         return ret;
 885                 }
 886         }
 887
 888         return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
 889                                            &axg_hw_onecell_data);
 890 }
 891
 892 static struct platform_driver axg_driver = {
 893         .probe          = axg_clkc_probe,
 894         .driver         = {
 895                 .name   = "axg-clkc",
 896                 .of_match_table = clkc_match_table,
 897         },
 898 };
 899
 900 builtin_platform_driver(axg_driver);