drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/ioctl.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64 #include <asm/dma.h>
  65 #include <linux/bitops.h>
  66 #include <asm/types.h>
  67 #include <linux/termios.h>
  68 #include <linux/workqueue.h>
  69 #include <linux/hdlc.h>
  70
  71 #ifdef CONFIG_HDLC_MODULE
  72 #define CONFIG_HDLC 1
  73 #endif
  74
  75 #define GET_USER(error,value,addr) error = get_user(value,addr)
  76 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79
  80 #include <asm/uaccess.h>
  81
  82 #include "linux/synclink.h"
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 138
 139 struct  _input_signal_events {
 140         int     ri_up;
 141         int     ri_down;
 142         int     dsr_up;
 143         int     dsr_down;
 144         int     dcd_up;
 145         int     dcd_down;
 146         int     cts_up;
 147         int     cts_down;
 148 };
 149
 150 /*
 151  * Device instance data structure
 152  */
 153 typedef struct _synclinkmp_info {
 154         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 155         int                     magic;
 156         int                     flags;
 157         int                     count;          /* count of opens */
 158         int                     line;
 159         unsigned short          close_delay;
 160         unsigned short          closing_wait;   /* time to wait before closing */
 161
 162         struct mgsl_icount      icount;
 163
 164         struct tty_struct       *tty;
 165         int                     timeout;
 166         int                     x_char;         /* xon/xoff character */
 167         int                     blocked_open;   /* # of blocked opens */
 168         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 169         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 170         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 171         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 172         unsigned char           *tx_buf;
 173         int                     tx_put;
 174         int                     tx_get;
 175         int                     tx_count;
 176
 177         wait_queue_head_t       open_wait;
 178         wait_queue_head_t       close_wait;
 179
 180         wait_queue_head_t       status_event_wait_q;
 181         wait_queue_head_t       event_wait_q;
 182         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 183         struct _synclinkmp_info *next_device;   /* device list link */
 184         struct timer_list       status_timer;   /* input signal status check timer */
 185
 186         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 187         struct work_struct task;                        /* task structure for scheduling bh */
 188
 189         u32 max_frame_size;                     /* as set by device config */
 190
 191         u32 pending_bh;
 192
 193         int bh_running;                         /* Protection from multiple */
 194         int isr_overflow;
 195         int bh_requested;
 196
 197         int dcd_chkcount;                       /* check counts to prevent */
 198         int cts_chkcount;                       /* too many IRQs if a signal */
 199         int dsr_chkcount;                       /* is floating */
 200         int ri_chkcount;
 201
 202         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 203         unsigned long buffer_list_phys;
 204
 205         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 206         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 207         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 208         unsigned int current_rx_buf;
 209
 210         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 211         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 212         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 213         unsigned int last_tx_buf;
 214
 215         unsigned char *tmp_rx_buf;
 216         unsigned int tmp_rx_buf_count;
 217
 218         int rx_enabled;
 219         int rx_overflow;
 220
 221         int tx_enabled;
 222         int tx_active;
 223         u32 idle_mode;
 224
 225         unsigned char ie0_value;
 226         unsigned char ie1_value;
 227         unsigned char ie2_value;
 228         unsigned char ctrlreg_value;
 229         unsigned char old_signals;
 230
 231         char device_name[25];                   /* device instance name */
 232
 233         int port_count;
 234         int adapter_num;
 235         int port_num;
 236
 237         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 238
 239         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 240
 241         unsigned int irq_level;                 /* interrupt level */
 242         unsigned long irq_flags;
 243         int irq_requested;                      /* nonzero if IRQ requested */
 244
 245         MGSL_PARAMS params;                     /* communications parameters */
 246
 247         unsigned char serial_signals;           /* current serial signal states */
 248
 249         int irq_occurred;                       /* for diagnostics use */
 250         unsigned int init_error;                /* Initialization startup error */
 251
 252         u32 last_mem_alloc;
 253         unsigned char* memory_base;             /* shared memory address (PCI only) */
 254         u32 phys_memory_base;
 255         int shared_mem_requested;
 256
 257         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 258         u32 phys_sca_base;
 259         u32 sca_offset;
 260         int sca_base_requested;
 261
 262         unsigned char* lcr_base;                /* local config registers (PCI only) */
 263         u32 phys_lcr_base;
 264         u32 lcr_offset;
 265         int lcr_mem_requested;
 266
 267         unsigned char* statctrl_base;           /* status/control register memory */
 268         u32 phys_statctrl_base;
 269         u32 statctrl_offset;
 270         int sca_statctrl_requested;
 271
 272         u32 misc_ctrl_value;
 273         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 274         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 275         BOOLEAN drop_rts_on_tx_done;
 276
 277         struct  _input_signal_events    input_signal_events;
 278
 279         /* SPPP/Cisco HDLC device parts */
 280         int netcount;
 281         int dosyncppp;
 282         spinlock_t netlock;
 283
 284 #ifdef CONFIG_HDLC
 285         struct net_device *netdev;
 286 #endif
 287
 288 } SLMP_INFO;
 289
 290 #define MGSL_MAGIC 0x5401
 291
 292 /*
 293  * define serial signal status change macros
 294  */
 295 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 296 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 297 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 298 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 299
 300 /* Common Register macros */
 301 #define LPR     0x00
 302 #define PABR0   0x02
 303 #define PABR1   0x03
 304 #define WCRL    0x04
 305 #define WCRM    0x05
 306 #define WCRH    0x06
 307 #define DPCR    0x08
 308 #define DMER    0x09
 309 #define ISR0    0x10
 310 #define ISR1    0x11
 311 #define ISR2    0x12
 312 #define IER0    0x14
 313 #define IER1    0x15
 314 #define IER2    0x16
 315 #define ITCR    0x18
 316 #define INTVR   0x1a
 317 #define IMVR    0x1c
 318
 319 /* MSCI Register macros */
 320 #define TRB     0x20
 321 #define TRBL    0x20
 322 #define TRBH    0x21
 323 #define SR0     0x22
 324 #define SR1     0x23
 325 #define SR2     0x24
 326 #define SR3     0x25
 327 #define FST     0x26
 328 #define IE0     0x28
 329 #define IE1     0x29
 330 #define IE2     0x2a
 331 #define FIE     0x2b
 332 #define CMD     0x2c
 333 #define MD0     0x2e
 334 #define MD1     0x2f
 335 #define MD2     0x30
 336 #define CTL     0x31
 337 #define SA0     0x32
 338 #define SA1     0x33
 339 #define IDL     0x34
 340 #define TMC     0x35
 341 #define RXS     0x36
 342 #define TXS     0x37
 343 #define TRC0    0x38
 344 #define TRC1    0x39
 345 #define RRC     0x3a
 346 #define CST0    0x3c
 347 #define CST1    0x3d
 348
 349 /* Timer Register Macros */
 350 #define TCNT    0x60
 351 #define TCNTL   0x60
 352 #define TCNTH   0x61
 353 #define TCONR   0x62
 354 #define TCONRL  0x62
 355 #define TCONRH  0x63
 356 #define TMCS    0x64
 357 #define TEPR    0x65
 358
 359 /* DMA Controller Register macros */
 360 #define DARL    0x80
 361 #define DARH    0x81
 362 #define DARB    0x82
 363 #define BAR     0x80
 364 #define BARL    0x80
 365 #define BARH    0x81
 366 #define BARB    0x82
 367 #define SAR     0x84
 368 #define SARL    0x84
 369 #define SARH    0x85
 370 #define SARB    0x86
 371 #define CPB     0x86
 372 #define CDA     0x88
 373 #define CDAL    0x88
 374 #define CDAH    0x89
 375 #define EDA     0x8a
 376 #define EDAL    0x8a
 377 #define EDAH    0x8b
 378 #define BFL     0x8c
 379 #define BFLL    0x8c
 380 #define BFLH    0x8d
 381 #define BCR     0x8e
 382 #define BCRL    0x8e
 383 #define BCRH    0x8f
 384 #define DSR     0x90
 385 #define DMR     0x91
 386 #define FCT     0x93
 387 #define DIR     0x94
 388 #define DCMD    0x95
 389
 390 /* combine with timer or DMA register address */
 391 #define TIMER0  0x00
 392 #define TIMER1  0x08
 393 #define TIMER2  0x10
 394 #define TIMER3  0x18
 395 #define RXDMA   0x00
 396 #define TXDMA   0x20
 397
 398 /* SCA Command Codes */
 399 #define NOOP            0x00
 400 #define TXRESET         0x01
 401 #define TXENABLE        0x02
 402 #define TXDISABLE       0x03
 403 #define TXCRCINIT       0x04
 404 #define TXCRCEXCL       0x05
 405 #define TXEOM           0x06
 406 #define TXABORT         0x07
 407 #define MPON            0x08
 408 #define TXBUFCLR        0x09
 409 #define RXRESET         0x11
 410 #define RXENABLE        0x12
 411 #define RXDISABLE       0x13
 412 #define RXCRCINIT       0x14
 413 #define RXREJECT        0x15
 414 #define SEARCHMP        0x16
 415 #define RXCRCEXCL       0x17
 416 #define RXCRCCALC       0x18
 417 #define CHRESET         0x21
 418 #define HUNT            0x31
 419
 420 /* DMA command codes */
 421 #define SWABORT         0x01
 422 #define FEICLEAR        0x02
 423
 424 /* IE0 */
 425 #define TXINTE          BIT7
 426 #define RXINTE          BIT6
 427 #define TXRDYE          BIT1
 428 #define RXRDYE          BIT0
 429
 430 /* IE1 & SR1 */
 431 #define UDRN    BIT7
 432 #define IDLE    BIT6
 433 #define SYNCD   BIT4
 434 #define FLGD    BIT4
 435 #define CCTS    BIT3
 436 #define CDCD    BIT2
 437 #define BRKD    BIT1
 438 #define ABTD    BIT1
 439 #define GAPD    BIT1
 440 #define BRKE    BIT0
 441 #define IDLD    BIT0
 442
 443 /* IE2 & SR2 */
 444 #define EOM     BIT7
 445 #define PMP     BIT6
 446 #define SHRT    BIT6
 447 #define PE      BIT5
 448 #define ABT     BIT5
 449 #define FRME    BIT4
 450 #define RBIT    BIT4
 451 #define OVRN    BIT3
 452 #define CRCE    BIT2
 453
 454
 455 /*
 456  * Global linked list of SyncLink devices
 457  */
 458 static SLMP_INFO *synclinkmp_device_list = NULL;
 459 static int synclinkmp_adapter_count = -1;
 460 static int synclinkmp_device_count = 0;
 461
 462 /*
 463  * Set this param to non-zero to load eax with the
 464  * .text section address and breakpoint on module load.
 465  * This is useful for use with gdb and add-symbol-file command.
 466  */
 467 static int break_on_load=0;
 468
 469 /*
 470  * Driver major number, defaults to zero to get auto
 471  * assigned major number. May be forced as module parameter.
 472  */
 473 static int ttymajor=0;
 474
 475 /*
 476  * Array of user specified options for ISA adapters.
 477  */
 478 static int debug_level = 0;
 479 static int maxframe[MAX_DEVICES] = {0,};
 480 static int dosyncppp[MAX_DEVICES] = {0,};
 481
 482 module_param(break_on_load, bool, 0);
 483 module_param(ttymajor, int, 0);
 484 module_param(debug_level, int, 0);
 485 module_param_array(maxframe, int, NULL, 0);
 486 module_param_array(dosyncppp, int, NULL, 0);
 487
 488 static char *driver_name = "SyncLink MultiPort driver";
 489 static char *driver_version = "$Revision: 4.38 $";
 490
 491 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 492 static void synclinkmp_remove_one(struct pci_dev *dev);
 493
 494 static struct pci_device_id synclinkmp_pci_tbl[] = {
 495         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 496         { 0, }, /* terminate list */
 497 };
 498 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 499
 500 MODULE_LICENSE("GPL");
 501
 502 static struct pci_driver synclinkmp_pci_driver = {
 503         .name           = "synclinkmp",
 504         .id_table       = synclinkmp_pci_tbl,
 505         .probe          = synclinkmp_init_one,
 506         .remove         = __devexit_p(synclinkmp_remove_one),
 507 };
 508
 509
 510 static struct tty_driver *serial_driver;
 511
 512 /* number of characters left in xmit buffer before we ask for more */
 513 #define WAKEUP_CHARS 256
 514
 515
 516 /* tty callbacks */
 517
 518 static int  open(struct tty_struct *tty, struct file * filp);
 519 static void close(struct tty_struct *tty, struct file * filp);
 520 static void hangup(struct tty_struct *tty);
 521 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 522
 523 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 524 static void put_char(struct tty_struct *tty, unsigned char ch);
 525 static void send_xchar(struct tty_struct *tty, char ch);
 526 static void wait_until_sent(struct tty_struct *tty, int timeout);
 527 static int  write_room(struct tty_struct *tty);
 528 static void flush_chars(struct tty_struct *tty);
 529 static void flush_buffer(struct tty_struct *tty);
 530 static void tx_hold(struct tty_struct *tty);
 531 static void tx_release(struct tty_struct *tty);
 532
 533 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 534 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 535 static int  chars_in_buffer(struct tty_struct *tty);
 536 static void throttle(struct tty_struct * tty);
 537 static void unthrottle(struct tty_struct * tty);
 538 static void set_break(struct tty_struct *tty, int break_state);
 539
 540 #ifdef CONFIG_HDLC
 541 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 542 static void hdlcdev_tx_done(SLMP_INFO *info);
 543 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 544 static int  hdlcdev_init(SLMP_INFO *info);
 545 static void hdlcdev_exit(SLMP_INFO *info);
 546 #endif
 547
 548 /* ioctl handlers */
 549
 550 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 551 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 552 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 553 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 554 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 555 static int  tx_enable(SLMP_INFO *info, int enable);
 556 static int  tx_abort(SLMP_INFO *info);
 557 static int  rx_enable(SLMP_INFO *info, int enable);
 558 static int  modem_input_wait(SLMP_INFO *info,int arg);
 559 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 560 static int  tiocmget(struct tty_struct *tty, struct file *file);
 561 static int  tiocmset(struct tty_struct *tty, struct file *file,
 562                      unsigned int set, unsigned int clear);
 563 static void set_break(struct tty_struct *tty, int break_state);
 564
 565 static void add_device(SLMP_INFO *info);
 566 static void device_init(int adapter_num, struct pci_dev *pdev);
 567 static int  claim_resources(SLMP_INFO *info);
 568 static void release_resources(SLMP_INFO *info);
 569
 570 static int  startup(SLMP_INFO *info);
 571 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 572 static void shutdown(SLMP_INFO *info);
 573 static void program_hw(SLMP_INFO *info);
 574 static void change_params(SLMP_INFO *info);
 575
 576 static int  init_adapter(SLMP_INFO *info);
 577 static int  register_test(SLMP_INFO *info);
 578 static int  irq_test(SLMP_INFO *info);
 579 static int  loopback_test(SLMP_INFO *info);
 580 static int  adapter_test(SLMP_INFO *info);
 581 static int  memory_test(SLMP_INFO *info);
 582
 583 static void reset_adapter(SLMP_INFO *info);
 584 static void reset_port(SLMP_INFO *info);
 585 static void async_mode(SLMP_INFO *info);
 586 static void hdlc_mode(SLMP_INFO *info);
 587
 588 static void rx_stop(SLMP_INFO *info);
 589 static void rx_start(SLMP_INFO *info);
 590 static void rx_reset_buffers(SLMP_INFO *info);
 591 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 592 static int  rx_get_frame(SLMP_INFO *info);
 593
 594 static void tx_start(SLMP_INFO *info);
 595 static void tx_stop(SLMP_INFO *info);
 596 static void tx_load_fifo(SLMP_INFO *info);
 597 static void tx_set_idle(SLMP_INFO *info);
 598 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 599
 600 static void get_signals(SLMP_INFO *info);
 601 static void set_signals(SLMP_INFO *info);
 602 static void enable_loopback(SLMP_INFO *info, int enable);
 603 static void set_rate(SLMP_INFO *info, u32 data_rate);
 604
 605 static int  bh_action(SLMP_INFO *info);
 606 static void bh_handler(void* Context);
 607 static void bh_receive(SLMP_INFO *info);
 608 static void bh_transmit(SLMP_INFO *info);
 609 static void bh_status(SLMP_INFO *info);
 610 static void isr_timer(SLMP_INFO *info);
 611 static void isr_rxint(SLMP_INFO *info);
 612 static void isr_rxrdy(SLMP_INFO *info);
 613 static void isr_txint(SLMP_INFO *info);
 614 static void isr_txrdy(SLMP_INFO *info);
 615 static void isr_rxdmaok(SLMP_INFO *info);
 616 static void isr_rxdmaerror(SLMP_INFO *info);
 617 static void isr_txdmaok(SLMP_INFO *info);
 618 static void isr_txdmaerror(SLMP_INFO *info);
 619 static void isr_io_pin(SLMP_INFO *info, u16 status);
 620
 621 static int  alloc_dma_bufs(SLMP_INFO *info);
 622 static void free_dma_bufs(SLMP_INFO *info);
 623 static int  alloc_buf_list(SLMP_INFO *info);
 624 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 625 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 626 static void free_tmp_rx_buf(SLMP_INFO *info);
 627
 628 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 629 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 630 static void tx_timeout(unsigned long context);
 631 static void status_timeout(unsigned long context);
 632
 633 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 634 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 635 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 636 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 637 static unsigned char read_status_reg(SLMP_INFO * info);
 638 static void write_control_reg(SLMP_INFO * info);
 639
 640
 641 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 642 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 643 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 644
 645 static u32 misc_ctrl_value = 0x007e4040;
 646 static u32 lcr1_brdr_value = 0x00800028;
 647
 648 static u32 read_ahead_count = 8;
 649
 650 /* DPCR, DMA Priority Control
 651  *
 652  * 07..05  Not used, must be 0
 653  * 04      BRC, bus release condition: 0=all transfers complete
 654  *              1=release after 1 xfer on all channels
 655  * 03      CCC, channel change condition: 0=every cycle
 656  *              1=after each channel completes all xfers
 657  * 02..00  PR<2..0>, priority 100=round robin
 658  *
 659  * 00000100 = 0x00
 660  */
 661 static unsigned char dma_priority = 0x04;
 662
 663 // Number of bytes that can be written to shared RAM
 664 // in a single write operation
 665 static u32 sca_pci_load_interval = 64;
 666
 667 /*
 668  * 1st function defined in .text section. Calling this function in
 669  * init_module() followed by a breakpoint allows a remote debugger
 670  * (gdb) to get the .text address for the add-symbol-file command.
 671  * This allows remote debugging of dynamically loadable modules.
 672  */
 673 static void* synclinkmp_get_text_ptr(void);
 674 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 675
 676 static inline int sanity_check(SLMP_INFO *info,
 677                                char *name, const char *routine)
 678 {
 679 #ifdef SANITY_CHECK
 680         static const char *badmagic =
 681                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 682         static const char *badinfo =
 683                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 684
 685         if (!info) {
 686                 printk(badinfo, name, routine);
 687                 return 1;
 688         }
 689         if (info->magic != MGSL_MAGIC) {
 690                 printk(badmagic, name, routine);
 691                 return 1;
 692         }
 693 #else
 694         if (!info)
 695                 return 1;
 696 #endif
 697         return 0;
 698 }
 699
 700 /**
 701  * line discipline callback wrappers
 702  *
 703  * The wrappers maintain line discipline references
 704  * while calling into the line discipline.
 705  *
 706  * ldisc_receive_buf  - pass receive data to line discipline
 707  */
 708
 709 static void ldisc_receive_buf(struct tty_struct *tty,
 710                               const __u8 *data, char *flags, int count)
 711 {
 712         struct tty_ldisc *ld;
 713         if (!tty)
 714                 return;
 715         ld = tty_ldisc_ref(tty);
 716         if (ld) {
 717                 if (ld->receive_buf)
 718                         ld->receive_buf(tty, data, flags, count);
 719                 tty_ldisc_deref(ld);
 720         }
 721 }
 722
 723 /* tty callbacks */
 724
 725 /* Called when a port is opened.  Init and enable port.
 726  */
 727 static int open(struct tty_struct *tty, struct file *filp)
 728 {
 729         SLMP_INFO *info;
 730         int retval, line;
 731         unsigned long flags;
 732
 733         line = tty->index;
 734         if ((line < 0) || (line >= synclinkmp_device_count)) {
 735                 printk("%s(%d): open with invalid line #%d.\n",
 736                         __FILE__,__LINE__,line);
 737                 return -ENODEV;
 738         }
 739
 740         info = synclinkmp_device_list;
 741         while(info && info->line != line)
 742                 info = info->next_device;
 743         if (sanity_check(info, tty->name, "open"))
 744                 return -ENODEV;
 745         if ( info->init_error ) {
 746                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 747                         __FILE__,__LINE__,info->device_name,info->init_error);
 748                 return -ENODEV;
 749         }
 750
 751         tty->driver_data = info;
 752         info->tty = tty;
 753
 754         if (debug_level >= DEBUG_LEVEL_INFO)
 755                 printk("%s(%d):%s open(), old ref count = %d\n",
 756                          __FILE__,__LINE__,tty->driver->name, info->count);
 757
 758         /* If port is closing, signal caller to try again */
 759         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 760                 if (info->flags & ASYNC_CLOSING)
 761                         interruptible_sleep_on(&info->close_wait);
 762                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 763                         -EAGAIN : -ERESTARTSYS);
 764                 goto cleanup;
 765         }
 766
 767         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 768
 769         spin_lock_irqsave(&info->netlock, flags);
 770         if (info->netcount) {
 771                 retval = -EBUSY;
 772                 spin_unlock_irqrestore(&info->netlock, flags);
 773                 goto cleanup;
 774         }
 775         info->count++;
 776         spin_unlock_irqrestore(&info->netlock, flags);
 777
 778         if (info->count == 1) {
 779                 /* 1st open on this device, init hardware */
 780                 retval = startup(info);
 781                 if (retval < 0)
 782                         goto cleanup;
 783         }
 784
 785         retval = block_til_ready(tty, filp, info);
 786         if (retval) {
 787                 if (debug_level >= DEBUG_LEVEL_INFO)
 788                         printk("%s(%d):%s block_til_ready() returned %d\n",
 789                                  __FILE__,__LINE__, info->device_name, retval);
 790                 goto cleanup;
 791         }
 792
 793         if (debug_level >= DEBUG_LEVEL_INFO)
 794                 printk("%s(%d):%s open() success\n",
 795                          __FILE__,__LINE__, info->device_name);
 796         retval = 0;
 797
 798 cleanup:
 799         if (retval) {
 800                 if (tty->count == 1)
 801                         info->tty = NULL; /* tty layer will release tty struct */
 802                 if(info->count)
 803                         info->count--;
 804         }
 805
 806         return retval;
 807 }
 808
 809 /* Called when port is closed. Wait for remaining data to be
 810  * sent. Disable port and free resources.
 811  */
 812 static void close(struct tty_struct *tty, struct file *filp)
 813 {
 814         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 815
 816         if (sanity_check(info, tty->name, "close"))
 817                 return;
 818
 819         if (debug_level >= DEBUG_LEVEL_INFO)
 820                 printk("%s(%d):%s close() entry, count=%d\n",
 821                          __FILE__,__LINE__, info->device_name, info->count);
 822
 823         if (!info->count)
 824                 return;
 825
 826         if (tty_hung_up_p(filp))
 827                 goto cleanup;
 828
 829         if ((tty->count == 1) && (info->count != 1)) {
 830                 /*
 831                  * tty->count is 1 and the tty structure will be freed.
 832                  * info->count should be one in this case.
 833                  * if it's not, correct it so that the port is shutdown.
 834                  */
 835                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 836                        "info->count is %d\n",
 837                          __FILE__,__LINE__, info->device_name, info->count);
 838                 info->count = 1;
 839         }
 840
 841         info->count--;
 842
 843         /* if at least one open remaining, leave hardware active */
 844         if (info->count)
 845                 goto cleanup;
 846
 847         info->flags |= ASYNC_CLOSING;
 848
 849         /* set tty->closing to notify line discipline to
 850          * only process XON/XOFF characters. Only the N_TTY
 851          * discipline appears to use this (ppp does not).
 852          */
 853         tty->closing = 1;
 854
 855         /* wait for transmit data to clear all layers */
 856
 857         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 858                 if (debug_level >= DEBUG_LEVEL_INFO)
 859                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 860                                  __FILE__,__LINE__, info->device_name );
 861                 tty_wait_until_sent(tty, info->closing_wait);
 862         }
 863
 864         if (info->flags & ASYNC_INITIALIZED)
 865                 wait_until_sent(tty, info->timeout);
 866
 867         if (tty->driver->flush_buffer)
 868                 tty->driver->flush_buffer(tty);
 869
 870         tty_ldisc_flush(tty);
 871
 872         shutdown(info);
 873
 874         tty->closing = 0;
 875         info->tty = NULL;
 876
 877         if (info->blocked_open) {
 878                 if (info->close_delay) {
 879                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 880                 }
 881                 wake_up_interruptible(&info->open_wait);
 882         }
 883
 884         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 885
 886         wake_up_interruptible(&info->close_wait);
 887
 888 cleanup:
 889         if (debug_level >= DEBUG_LEVEL_INFO)
 890                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 891                         tty->driver->name, info->count);
 892 }
 893
 894 /* Called by tty_hangup() when a hangup is signaled.
 895  * This is the same as closing all open descriptors for the port.
 896  */
 897 static void hangup(struct tty_struct *tty)
 898 {
 899         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 900
 901         if (debug_level >= DEBUG_LEVEL_INFO)
 902                 printk("%s(%d):%s hangup()\n",
 903                          __FILE__,__LINE__, info->device_name );
 904
 905         if (sanity_check(info, tty->name, "hangup"))
 906                 return;
 907
 908         flush_buffer(tty);
 909         shutdown(info);
 910
 911         info->count = 0;
 912         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 913         info->tty = NULL;
 914
 915         wake_up_interruptible(&info->open_wait);
 916 }
 917
 918 /* Set new termios settings
 919  */
 920 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 921 {
 922         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 923         unsigned long flags;
 924
 925         if (debug_level >= DEBUG_LEVEL_INFO)
 926                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 927                         tty->driver->name );
 928
 929         /* just return if nothing has changed */
 930         if ((tty->termios->c_cflag == old_termios->c_cflag)
 931             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 932                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 933           return;
 934
 935         change_params(info);
 936
 937         /* Handle transition to B0 status */
 938         if (old_termios->c_cflag & CBAUD &&
 939             !(tty->termios->c_cflag & CBAUD)) {
 940                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 941                 spin_lock_irqsave(&info->lock,flags);
 942                 set_signals(info);
 943                 spin_unlock_irqrestore(&info->lock,flags);
 944         }
 945
 946         /* Handle transition away from B0 status */
 947         if (!(old_termios->c_cflag & CBAUD) &&
 948             tty->termios->c_cflag & CBAUD) {
 949                 info->serial_signals |= SerialSignal_DTR;
 950                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 951                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 952                         info->serial_signals |= SerialSignal_RTS;
 953                 }
 954                 spin_lock_irqsave(&info->lock,flags);
 955                 set_signals(info);
 956                 spin_unlock_irqrestore(&info->lock,flags);
 957         }
 958
 959         /* Handle turning off CRTSCTS */
 960         if (old_termios->c_cflag & CRTSCTS &&
 961             !(tty->termios->c_cflag & CRTSCTS)) {
 962                 tty->hw_stopped = 0;
 963                 tx_release(tty);
 964         }
 965 }
 966
 967 /* Send a block of data
 968  *
 969  * Arguments:
 970  *
 971  *      tty             pointer to tty information structure
 972  *      buf             pointer to buffer containing send data
 973  *      count           size of send data in bytes
 974  *
 975  * Return Value:        number of characters written
 976  */
 977 static int write(struct tty_struct *tty,
 978                  const unsigned char *buf, int count)
 979 {
 980         int     c, ret = 0;
 981         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 982         unsigned long flags;
 983
 984         if (debug_level >= DEBUG_LEVEL_INFO)
 985                 printk("%s(%d):%s write() count=%d\n",
 986                        __FILE__,__LINE__,info->device_name,count);
 987
 988         if (sanity_check(info, tty->name, "write"))
 989                 goto cleanup;
 990
 991         if (!tty || !info->tx_buf)
 992                 goto cleanup;
 993
 994         if (info->params.mode == MGSL_MODE_HDLC) {
 995                 if (count > info->max_frame_size) {
 996                         ret = -EIO;
 997                         goto cleanup;
 998                 }
 999                 if (info->tx_active)
1000                         goto cleanup;
1001                 if (info->tx_count) {
1002                         /* send accumulated data from send_char() calls */
1003                         /* as frame and wait before accepting more data. */
1004                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1005                         goto start;
1006                 }
1007                 ret = info->tx_count = count;
1008                 tx_load_dma_buffer(info, buf, count);
1009                 goto start;
1010         }
1011
1012         for (;;) {
1013                 c = min_t(int, count,
1014                         min(info->max_frame_size - info->tx_count - 1,
1015                             info->max_frame_size - info->tx_put));
1016                 if (c <= 0)
1017                         break;
1018
1019                 memcpy(info->tx_buf + info->tx_put, buf, c);
1020
1021                 spin_lock_irqsave(&info->lock,flags);
1022                 info->tx_put += c;
1023                 if (info->tx_put >= info->max_frame_size)
1024                         info->tx_put -= info->max_frame_size;
1025                 info->tx_count += c;
1026                 spin_unlock_irqrestore(&info->lock,flags);
1027
1028                 buf += c;
1029                 count -= c;
1030                 ret += c;
1031         }
1032
1033         if (info->params.mode == MGSL_MODE_HDLC) {
1034                 if (count) {
1035                         ret = info->tx_count = 0;
1036                         goto cleanup;
1037                 }
1038                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1039         }
1040 start:
1041         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1042                 spin_lock_irqsave(&info->lock,flags);
1043                 if (!info->tx_active)
1044                         tx_start(info);
1045                 spin_unlock_irqrestore(&info->lock,flags);
1046         }
1047
1048 cleanup:
1049         if (debug_level >= DEBUG_LEVEL_INFO)
1050                 printk( "%s(%d):%s write() returning=%d\n",
1051                         __FILE__,__LINE__,info->device_name,ret);
1052         return ret;
1053 }
1054
1055 /* Add a character to the transmit buffer.
1056  */
1057 static void put_char(struct tty_struct *tty, unsigned char ch)
1058 {
1059         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1060         unsigned long flags;
1061
1062         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1063                 printk( "%s(%d):%s put_char(%d)\n",
1064                         __FILE__,__LINE__,info->device_name,ch);
1065         }
1066
1067         if (sanity_check(info, tty->name, "put_char"))
1068                 return;
1069
1070         if (!tty || !info->tx_buf)
1071                 return;
1072
1073         spin_lock_irqsave(&info->lock,flags);
1074
1075         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1076              !info->tx_active ) {
1077
1078                 if (info->tx_count < info->max_frame_size - 1) {
1079                         info->tx_buf[info->tx_put++] = ch;
1080                         if (info->tx_put >= info->max_frame_size)
1081                                 info->tx_put -= info->max_frame_size;
1082                         info->tx_count++;
1083                 }
1084         }
1085
1086         spin_unlock_irqrestore(&info->lock,flags);
1087 }
1088
1089 /* Send a high-priority XON/XOFF character
1090  */
1091 static void send_xchar(struct tty_struct *tty, char ch)
1092 {
1093         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1094         unsigned long flags;
1095
1096         if (debug_level >= DEBUG_LEVEL_INFO)
1097                 printk("%s(%d):%s send_xchar(%d)\n",
1098                          __FILE__,__LINE__, info->device_name, ch );
1099
1100         if (sanity_check(info, tty->name, "send_xchar"))
1101                 return;
1102
1103         info->x_char = ch;
1104         if (ch) {
1105                 /* Make sure transmit interrupts are on */
1106                 spin_lock_irqsave(&info->lock,flags);
1107                 if (!info->tx_enabled)
1108                         tx_start(info);
1109                 spin_unlock_irqrestore(&info->lock,flags);
1110         }
1111 }
1112
1113 /* Wait until the transmitter is empty.
1114  */
1115 static void wait_until_sent(struct tty_struct *tty, int timeout)
1116 {
1117         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1118         unsigned long orig_jiffies, char_time;
1119
1120         if (!info )
1121                 return;
1122
1123         if (debug_level >= DEBUG_LEVEL_INFO)
1124                 printk("%s(%d):%s wait_until_sent() entry\n",
1125                          __FILE__,__LINE__, info->device_name );
1126
1127         if (sanity_check(info, tty->name, "wait_until_sent"))
1128                 return;
1129
1130         if (!(info->flags & ASYNC_INITIALIZED))
1131                 goto exit;
1132
1133         orig_jiffies = jiffies;
1134
1135         /* Set check interval to 1/5 of estimated time to
1136          * send a character, and make it at least 1. The check
1137          * interval should also be less than the timeout.
1138          * Note: use tight timings here to satisfy the NIST-PCTS.
1139          */
1140
1141         if ( info->params.data_rate ) {
1142                 char_time = info->timeout/(32 * 5);
1143                 if (!char_time)
1144                         char_time++;
1145         } else
1146                 char_time = 1;
1147
1148         if (timeout)
1149                 char_time = min_t(unsigned long, char_time, timeout);
1150
1151         if ( info->params.mode == MGSL_MODE_HDLC ) {
1152                 while (info->tx_active) {
1153                         msleep_interruptible(jiffies_to_msecs(char_time));
1154                         if (signal_pending(current))
1155                                 break;
1156                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1157                                 break;
1158                 }
1159         } else {
1160                 //TODO: determine if there is something similar to USC16C32
1161                 //      TXSTATUS_ALL_SENT status
1162                 while ( info->tx_active && info->tx_enabled) {
1163                         msleep_interruptible(jiffies_to_msecs(char_time));
1164                         if (signal_pending(current))
1165                                 break;
1166                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1167                                 break;
1168                 }
1169         }
1170
1171 exit:
1172         if (debug_level >= DEBUG_LEVEL_INFO)
1173                 printk("%s(%d):%s wait_until_sent() exit\n",
1174                          __FILE__,__LINE__, info->device_name );
1175 }
1176
1177 /* Return the count of free bytes in transmit buffer
1178  */
1179 static int write_room(struct tty_struct *tty)
1180 {
1181         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1182         int ret;
1183
1184         if (sanity_check(info, tty->name, "write_room"))
1185                 return 0;
1186
1187         if (info->params.mode == MGSL_MODE_HDLC) {
1188                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1189         } else {
1190                 ret = info->max_frame_size - info->tx_count - 1;
1191                 if (ret < 0)
1192                         ret = 0;
1193         }
1194
1195         if (debug_level >= DEBUG_LEVEL_INFO)
1196                 printk("%s(%d):%s write_room()=%d\n",
1197                        __FILE__, __LINE__, info->device_name, ret);
1198
1199         return ret;
1200 }
1201
1202 /* enable transmitter and send remaining buffered characters
1203  */
1204 static void flush_chars(struct tty_struct *tty)
1205 {
1206         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1207         unsigned long flags;
1208
1209         if ( debug_level >= DEBUG_LEVEL_INFO )
1210                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1211                         __FILE__,__LINE__,info->device_name,info->tx_count);
1212
1213         if (sanity_check(info, tty->name, "flush_chars"))
1214                 return;
1215
1216         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1217             !info->tx_buf)
1218                 return;
1219
1220         if ( debug_level >= DEBUG_LEVEL_INFO )
1221                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1222                         __FILE__,__LINE__,info->device_name );
1223
1224         spin_lock_irqsave(&info->lock,flags);
1225
1226         if (!info->tx_active) {
1227                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1228                         info->tx_count ) {
1229                         /* operating in synchronous (frame oriented) mode */
1230                         /* copy data from circular tx_buf to */
1231                         /* transmit DMA buffer. */
1232                         tx_load_dma_buffer(info,
1233                                  info->tx_buf,info->tx_count);
1234                 }
1235                 tx_start(info);
1236         }
1237
1238         spin_unlock_irqrestore(&info->lock,flags);
1239 }
1240
1241 /* Discard all data in the send buffer
1242  */
1243 static void flush_buffer(struct tty_struct *tty)
1244 {
1245         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1246         unsigned long flags;
1247
1248         if (debug_level >= DEBUG_LEVEL_INFO)
1249                 printk("%s(%d):%s flush_buffer() entry\n",
1250                          __FILE__,__LINE__, info->device_name );
1251
1252         if (sanity_check(info, tty->name, "flush_buffer"))
1253                 return;
1254
1255         spin_lock_irqsave(&info->lock,flags);
1256         info->tx_count = info->tx_put = info->tx_get = 0;
1257         del_timer(&info->tx_timer);
1258         spin_unlock_irqrestore(&info->lock,flags);
1259
1260         wake_up_interruptible(&tty->write_wait);
1261         tty_wakeup(tty);
1262 }
1263
1264 /* throttle (stop) transmitter
1265  */
1266 static void tx_hold(struct tty_struct *tty)
1267 {
1268         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1269         unsigned long flags;
1270
1271         if (sanity_check(info, tty->name, "tx_hold"))
1272                 return;
1273
1274         if ( debug_level >= DEBUG_LEVEL_INFO )
1275                 printk("%s(%d):%s tx_hold()\n",
1276                         __FILE__,__LINE__,info->device_name);
1277
1278         spin_lock_irqsave(&info->lock,flags);
1279         if (info->tx_enabled)
1280                 tx_stop(info);
1281         spin_unlock_irqrestore(&info->lock,flags);
1282 }
1283
1284 /* release (start) transmitter
1285  */
1286 static void tx_release(struct tty_struct *tty)
1287 {
1288         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1289         unsigned long flags;
1290
1291         if (sanity_check(info, tty->name, "tx_release"))
1292                 return;
1293
1294         if ( debug_level >= DEBUG_LEVEL_INFO )
1295                 printk("%s(%d):%s tx_release()\n",
1296                         __FILE__,__LINE__,info->device_name);
1297
1298         spin_lock_irqsave(&info->lock,flags);
1299         if (!info->tx_enabled)
1300                 tx_start(info);
1301         spin_unlock_irqrestore(&info->lock,flags);
1302 }
1303
1304 /* Service an IOCTL request
1305  *
1306  * Arguments:
1307  *
1308  *      tty     pointer to tty instance data
1309  *      file    pointer to associated file object for device
1310  *      cmd     IOCTL command code
1311  *      arg     command argument/context
1312  *
1313  * Return Value:        0 if success, otherwise error code
1314  */
1315 static int ioctl(struct tty_struct *tty, struct file *file,
1316                  unsigned int cmd, unsigned long arg)
1317 {
1318         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1319         int error;
1320         struct mgsl_icount cnow;        /* kernel counter temps */
1321         struct serial_icounter_struct __user *p_cuser;  /* user space */
1322         unsigned long flags;
1323         void __user *argp = (void __user *)arg;
1324
1325         if (debug_level >= DEBUG_LEVEL_INFO)
1326                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1327                         info->device_name, cmd );
1328
1329         if (sanity_check(info, tty->name, "ioctl"))
1330                 return -ENODEV;
1331
1332         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1333             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1334                 if (tty->flags & (1 << TTY_IO_ERROR))
1335                     return -EIO;
1336         }
1337
1338         switch (cmd) {
1339         case MGSL_IOCGPARAMS:
1340                 return get_params(info, argp);
1341         case MGSL_IOCSPARAMS:
1342                 return set_params(info, argp);
1343         case MGSL_IOCGTXIDLE:
1344                 return get_txidle(info, argp);
1345         case MGSL_IOCSTXIDLE:
1346                 return set_txidle(info, (int)arg);
1347         case MGSL_IOCTXENABLE:
1348                 return tx_enable(info, (int)arg);
1349         case MGSL_IOCRXENABLE:
1350                 return rx_enable(info, (int)arg);
1351         case MGSL_IOCTXABORT:
1352                 return tx_abort(info);
1353         case MGSL_IOCGSTATS:
1354                 return get_stats(info, argp);
1355         case MGSL_IOCWAITEVENT:
1356                 return wait_mgsl_event(info, argp);
1357         case MGSL_IOCLOOPTXDONE:
1358                 return 0; // TODO: Not supported, need to document
1359                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1360                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1361                  */
1362         case TIOCMIWAIT:
1363                 return modem_input_wait(info,(int)arg);
1364
1365                 /*
1366                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1367                  * Return: write counters to the user passed counter struct
1368                  * NB: both 1->0 and 0->1 transitions are counted except for
1369                  *     RI where only 0->1 is counted.
1370                  */
1371         case TIOCGICOUNT:
1372                 spin_lock_irqsave(&info->lock,flags);
1373                 cnow = info->icount;
1374                 spin_unlock_irqrestore(&info->lock,flags);
1375                 p_cuser = argp;
1376                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1377                 if (error) return error;
1378                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1379                 if (error) return error;
1380                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1381                 if (error) return error;
1382                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1383                 if (error) return error;
1384                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1385                 if (error) return error;
1386                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1387                 if (error) return error;
1388                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1389                 if (error) return error;
1390                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1391                 if (error) return error;
1392                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1393                 if (error) return error;
1394                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1395                 if (error) return error;
1396                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1397                 if (error) return error;
1398                 return 0;
1399         default:
1400                 return -ENOIOCTLCMD;
1401         }
1402         return 0;
1403 }
1404
1405 /*
1406  * /proc fs routines....
1407  */
1408
1409 static inline int line_info(char *buf, SLMP_INFO *info)
1410 {
1411         char    stat_buf[30];
1412         int     ret;
1413         unsigned long flags;
1414
1415         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1416                        "\tIRQ=%d MaxFrameSize=%u\n",
1417                 info->device_name,
1418                 info->phys_sca_base,
1419                 info->phys_memory_base,
1420                 info->phys_statctrl_base,
1421                 info->phys_lcr_base,
1422                 info->irq_level,
1423                 info->max_frame_size );
1424
1425         /* output current serial signal states */
1426         spin_lock_irqsave(&info->lock,flags);
1427         get_signals(info);
1428         spin_unlock_irqrestore(&info->lock,flags);
1429
1430         stat_buf[0] = 0;
1431         stat_buf[1] = 0;
1432         if (info->serial_signals & SerialSignal_RTS)
1433                 strcat(stat_buf, "|RTS");
1434         if (info->serial_signals & SerialSignal_CTS)
1435                 strcat(stat_buf, "|CTS");
1436         if (info->serial_signals & SerialSignal_DTR)
1437                 strcat(stat_buf, "|DTR");
1438         if (info->serial_signals & SerialSignal_DSR)
1439                 strcat(stat_buf, "|DSR");
1440         if (info->serial_signals & SerialSignal_DCD)
1441                 strcat(stat_buf, "|CD");
1442         if (info->serial_signals & SerialSignal_RI)
1443                 strcat(stat_buf, "|RI");
1444
1445         if (info->params.mode == MGSL_MODE_HDLC) {
1446                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1447                               info->icount.txok, info->icount.rxok);
1448                 if (info->icount.txunder)
1449                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1450                 if (info->icount.txabort)
1451                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1452                 if (info->icount.rxshort)
1453                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1454                 if (info->icount.rxlong)
1455                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1456                 if (info->icount.rxover)
1457                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1458                 if (info->icount.rxcrc)
1459                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1460         } else {
1461                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1462                               info->icount.tx, info->icount.rx);
1463                 if (info->icount.frame)
1464                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1465                 if (info->icount.parity)
1466                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1467                 if (info->icount.brk)
1468                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1469                 if (info->icount.overrun)
1470                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1471         }
1472
1473         /* Append serial signal status to end */
1474         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1475
1476         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1477          info->tx_active,info->bh_requested,info->bh_running,
1478          info->pending_bh);
1479
1480         return ret;
1481 }
1482
1483 /* Called to print information about devices
1484  */
1485 int read_proc(char *page, char **start, off_t off, int count,
1486               int *eof, void *data)
1487 {
1488         int len = 0, l;
1489         off_t   begin = 0;
1490         SLMP_INFO *info;
1491
1492         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1493
1494         info = synclinkmp_device_list;
1495         while( info ) {
1496                 l = line_info(page + len, info);
1497                 len += l;
1498                 if (len+begin > off+count)
1499                         goto done;
1500                 if (len+begin < off) {
1501                         begin += len;
1502                         len = 0;
1503                 }
1504                 info = info->next_device;
1505         }
1506
1507         *eof = 1;
1508 done:
1509         if (off >= len+begin)
1510                 return 0;
1511         *start = page + (off-begin);
1512         return ((count < begin+len-off) ? count : begin+len-off);
1513 }
1514
1515 /* Return the count of bytes in transmit buffer
1516  */
1517 static int chars_in_buffer(struct tty_struct *tty)
1518 {
1519         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1520
1521         if (sanity_check(info, tty->name, "chars_in_buffer"))
1522                 return 0;
1523
1524         if (debug_level >= DEBUG_LEVEL_INFO)
1525                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1526                        __FILE__, __LINE__, info->device_name, info->tx_count);
1527
1528         return info->tx_count;
1529 }
1530
1531 /* Signal remote device to throttle send data (our receive data)
1532  */
1533 static void throttle(struct tty_struct * tty)
1534 {
1535         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1536         unsigned long flags;
1537
1538         if (debug_level >= DEBUG_LEVEL_INFO)
1539                 printk("%s(%d):%s throttle() entry\n",
1540                          __FILE__,__LINE__, info->device_name );
1541
1542         if (sanity_check(info, tty->name, "throttle"))
1543                 return;
1544
1545         if (I_IXOFF(tty))
1546                 send_xchar(tty, STOP_CHAR(tty));
1547
1548         if (tty->termios->c_cflag & CRTSCTS) {
1549                 spin_lock_irqsave(&info->lock,flags);
1550                 info->serial_signals &= ~SerialSignal_RTS;
1551                 set_signals(info);
1552                 spin_unlock_irqrestore(&info->lock,flags);
1553         }
1554 }
1555
1556 /* Signal remote device to stop throttling send data (our receive data)
1557  */
1558 static void unthrottle(struct tty_struct * tty)
1559 {
1560         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1561         unsigned long flags;
1562
1563         if (debug_level >= DEBUG_LEVEL_INFO)
1564                 printk("%s(%d):%s unthrottle() entry\n",
1565                          __FILE__,__LINE__, info->device_name );
1566
1567         if (sanity_check(info, tty->name, "unthrottle"))
1568                 return;
1569
1570         if (I_IXOFF(tty)) {
1571                 if (info->x_char)
1572                         info->x_char = 0;
1573                 else
1574                         send_xchar(tty, START_CHAR(tty));
1575         }
1576
1577         if (tty->termios->c_cflag & CRTSCTS) {
1578                 spin_lock_irqsave(&info->lock,flags);
1579                 info->serial_signals |= SerialSignal_RTS;
1580                 set_signals(info);
1581                 spin_unlock_irqrestore(&info->lock,flags);
1582         }
1583 }
1584
1585 /* set or clear transmit break condition
1586  * break_state  -1=set break condition, 0=clear
1587  */
1588 static void set_break(struct tty_struct *tty, int break_state)
1589 {
1590         unsigned char RegValue;
1591         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1592         unsigned long flags;
1593
1594         if (debug_level >= DEBUG_LEVEL_INFO)
1595                 printk("%s(%d):%s set_break(%d)\n",
1596                          __FILE__,__LINE__, info->device_name, break_state);
1597
1598         if (sanity_check(info, tty->name, "set_break"))
1599                 return;
1600
1601         spin_lock_irqsave(&info->lock,flags);
1602         RegValue = read_reg(info, CTL);
1603         if (break_state == -1)
1604                 RegValue |= BIT3;
1605         else
1606                 RegValue &= ~BIT3;
1607         write_reg(info, CTL, RegValue);
1608         spin_unlock_irqrestore(&info->lock,flags);
1609 }
1610
1611 #ifdef CONFIG_HDLC
1612
1613 /**
1614  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1615  * set encoding and frame check sequence (FCS) options
1616  *
1617  * dev       pointer to network device structure
1618  * encoding  serial encoding setting
1619  * parity    FCS setting
1620  *
1621  * returns 0 if success, otherwise error code
1622  */
1623 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1624                           unsigned short parity)
1625 {
1626         SLMP_INFO *info = dev_to_port(dev);
1627         unsigned char  new_encoding;
1628         unsigned short new_crctype;
1629
1630         /* return error if TTY interface open */
1631         if (info->count)
1632                 return -EBUSY;
1633
1634         switch (encoding)
1635         {
1636         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1637         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1638         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1639         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1640         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1641         default: return -EINVAL;
1642         }
1643
1644         switch (parity)
1645         {
1646         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1647         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1648         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1649         default: return -EINVAL;
1650         }
1651
1652         info->params.encoding = new_encoding;
1653         info->params.crc_type = new_crctype;;
1654
1655         /* if network interface up, reprogram hardware */
1656         if (info->netcount)
1657                 program_hw(info);
1658
1659         return 0;
1660 }
1661
1662 /**
1663  * called by generic HDLC layer to send frame
1664  *
1665  * skb  socket buffer containing HDLC frame
1666  * dev  pointer to network device structure
1667  *
1668  * returns 0 if success, otherwise error code
1669  */
1670 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1671 {
1672         SLMP_INFO *info = dev_to_port(dev);
1673         struct net_device_stats *stats = hdlc_stats(dev);
1674         unsigned long flags;
1675
1676         if (debug_level >= DEBUG_LEVEL_INFO)
1677                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1678
1679         /* stop sending until this frame completes */
1680         netif_stop_queue(dev);
1681
1682         /* copy data to device buffers */
1683         info->tx_count = skb->len;
1684         tx_load_dma_buffer(info, skb->data, skb->len);
1685
1686         /* update network statistics */
1687         stats->tx_packets++;
1688         stats->tx_bytes += skb->len;
1689
1690         /* done with socket buffer, so free it */
1691         dev_kfree_skb(skb);
1692
1693         /* save start time for transmit timeout detection */
1694         dev->trans_start = jiffies;
1695
1696         /* start hardware transmitter if necessary */
1697         spin_lock_irqsave(&info->lock,flags);
1698         if (!info->tx_active)
1699                 tx_start(info);
1700         spin_unlock_irqrestore(&info->lock,flags);
1701
1702         return 0;
1703 }
1704
1705 /**
1706  * called by network layer when interface enabled
1707  * claim resources and initialize hardware
1708  *
1709  * dev  pointer to network device structure
1710  *
1711  * returns 0 if success, otherwise error code
1712  */
1713 static int hdlcdev_open(struct net_device *dev)
1714 {
1715         SLMP_INFO *info = dev_to_port(dev);
1716         int rc;
1717         unsigned long flags;
1718
1719         if (debug_level >= DEBUG_LEVEL_INFO)
1720                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1721
1722         /* generic HDLC layer open processing */
1723         if ((rc = hdlc_open(dev)))
1724                 return rc;
1725
1726         /* arbitrate between network and tty opens */
1727         spin_lock_irqsave(&info->netlock, flags);
1728         if (info->count != 0 || info->netcount != 0) {
1729                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1730                 spin_unlock_irqrestore(&info->netlock, flags);
1731                 return -EBUSY;
1732         }
1733         info->netcount=1;
1734         spin_unlock_irqrestore(&info->netlock, flags);
1735
1736         /* claim resources and init adapter */
1737         if ((rc = startup(info)) != 0) {
1738                 spin_lock_irqsave(&info->netlock, flags);
1739                 info->netcount=0;
1740                 spin_unlock_irqrestore(&info->netlock, flags);
1741                 return rc;
1742         }
1743
1744         /* assert DTR and RTS, apply hardware settings */
1745         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1746         program_hw(info);
1747
1748         /* enable network layer transmit */
1749         dev->trans_start = jiffies;
1750         netif_start_queue(dev);
1751
1752         /* inform generic HDLC layer of current DCD status */
1753         spin_lock_irqsave(&info->lock, flags);
1754         get_signals(info);
1755         spin_unlock_irqrestore(&info->lock, flags);
1756         hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
1757
1758         return 0;
1759 }
1760
1761 /**
1762  * called by network layer when interface is disabled
1763  * shutdown hardware and release resources
1764  *
1765  * dev  pointer to network device structure
1766  *
1767  * returns 0 if success, otherwise error code
1768  */
1769 static int hdlcdev_close(struct net_device *dev)
1770 {
1771         SLMP_INFO *info = dev_to_port(dev);
1772         unsigned long flags;
1773
1774         if (debug_level >= DEBUG_LEVEL_INFO)
1775                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1776
1777         netif_stop_queue(dev);
1778
1779         /* shutdown adapter and release resources */
1780         shutdown(info);
1781
1782         hdlc_close(dev);
1783
1784         spin_lock_irqsave(&info->netlock, flags);
1785         info->netcount=0;
1786         spin_unlock_irqrestore(&info->netlock, flags);
1787
1788         return 0;
1789 }
1790
1791 /**
1792  * called by network layer to process IOCTL call to network device
1793  *
1794  * dev  pointer to network device structure
1795  * ifr  pointer to network interface request structure
1796  * cmd  IOCTL command code
1797  *
1798  * returns 0 if success, otherwise error code
1799  */
1800 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1801 {
1802         const size_t size = sizeof(sync_serial_settings);
1803         sync_serial_settings new_line;
1804         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1805         SLMP_INFO *info = dev_to_port(dev);
1806         unsigned int flags;
1807
1808         if (debug_level >= DEBUG_LEVEL_INFO)
1809                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1810
1811         /* return error if TTY interface open */
1812         if (info->count)
1813                 return -EBUSY;
1814
1815         if (cmd != SIOCWANDEV)
1816                 return hdlc_ioctl(dev, ifr, cmd);
1817
1818         switch(ifr->ifr_settings.type) {
1819         case IF_GET_IFACE: /* return current sync_serial_settings */
1820
1821                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1822                 if (ifr->ifr_settings.size < size) {
1823                         ifr->ifr_settings.size = size; /* data size wanted */
1824                         return -ENOBUFS;
1825                 }
1826
1827                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1828                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1829                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1830                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1831
1832                 switch (flags){
1833                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1834                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1835                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1836                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1837                 default: new_line.clock_type = CLOCK_DEFAULT;
1838                 }
1839
1840                 new_line.clock_rate = info->params.clock_speed;
1841                 new_line.loopback   = info->params.loopback ? 1:0;
1842
1843                 if (copy_to_user(line, &new_line, size))
1844                         return -EFAULT;
1845                 return 0;
1846
1847         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1848
1849                 if(!capable(CAP_NET_ADMIN))
1850                         return -EPERM;
1851                 if (copy_from_user(&new_line, line, size))
1852                         return -EFAULT;
1853
1854                 switch (new_line.clock_type)
1855                 {
1856                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1857                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1858                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1859                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1860                 case CLOCK_DEFAULT:  flags = info->params.flags &
1861                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1862                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1863                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1864                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1865                 default: return -EINVAL;
1866                 }
1867
1868                 if (new_line.loopback != 0 && new_line.loopback != 1)
1869                         return -EINVAL;
1870
1871                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1872                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1873                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1874                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1875                 info->params.flags |= flags;
1876
1877                 info->params.loopback = new_line.loopback;
1878
1879                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1880                         info->params.clock_speed = new_line.clock_rate;
1881                 else
1882                         info->params.clock_speed = 0;
1883
1884                 /* if network interface up, reprogram hardware */
1885                 if (info->netcount)
1886                         program_hw(info);
1887                 return 0;
1888
1889         default:
1890                 return hdlc_ioctl(dev, ifr, cmd);
1891         }
1892 }
1893
1894 /**
1895  * called by network layer when transmit timeout is detected
1896  *
1897  * dev  pointer to network device structure
1898  */
1899 static void hdlcdev_tx_timeout(struct net_device *dev)
1900 {
1901         SLMP_INFO *info = dev_to_port(dev);
1902         struct net_device_stats *stats = hdlc_stats(dev);
1903         unsigned long flags;
1904
1905         if (debug_level >= DEBUG_LEVEL_INFO)
1906                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1907
1908         stats->tx_errors++;
1909         stats->tx_aborted_errors++;
1910
1911         spin_lock_irqsave(&info->lock,flags);
1912         tx_stop(info);
1913         spin_unlock_irqrestore(&info->lock,flags);
1914
1915         netif_wake_queue(dev);
1916 }
1917
1918 /**
1919  * called by device driver when transmit completes
1920  * reenable network layer transmit if stopped
1921  *
1922  * info  pointer to device instance information
1923  */
1924 static void hdlcdev_tx_done(SLMP_INFO *info)
1925 {
1926         if (netif_queue_stopped(info->netdev))
1927                 netif_wake_queue(info->netdev);
1928 }
1929
1930 /**
1931  * called by device driver when frame received
1932  * pass frame to network layer
1933  *
1934  * info  pointer to device instance information
1935  * buf   pointer to buffer contianing frame data
1936  * size  count of data bytes in buf
1937  */
1938 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1939 {
1940         struct sk_buff *skb = dev_alloc_skb(size);
1941         struct net_device *dev = info->netdev;
1942         struct net_device_stats *stats = hdlc_stats(dev);
1943
1944         if (debug_level >= DEBUG_LEVEL_INFO)
1945                 printk("hdlcdev_rx(%s)\n",dev->name);
1946
1947         if (skb == NULL) {
1948                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1949                 stats->rx_dropped++;
1950                 return;
1951         }
1952
1953         memcpy(skb_put(skb, size),buf,size);
1954
1955         skb->protocol = hdlc_type_trans(skb, info->netdev);
1956
1957         stats->rx_packets++;
1958         stats->rx_bytes += size;
1959
1960         netif_rx(skb);
1961
1962         info->netdev->last_rx = jiffies;
1963 }
1964
1965 /**
1966  * called by device driver when adding device instance
1967  * do generic HDLC initialization
1968  *
1969  * info  pointer to device instance information
1970  *
1971  * returns 0 if success, otherwise error code
1972  */
1973 static int hdlcdev_init(SLMP_INFO *info)
1974 {
1975         int rc;
1976         struct net_device *dev;
1977         hdlc_device *hdlc;
1978
1979         /* allocate and initialize network and HDLC layer objects */
1980
1981         if (!(dev = alloc_hdlcdev(info))) {
1982                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1983                 return -ENOMEM;
1984         }
1985
1986         /* for network layer reporting purposes only */
1987         dev->mem_start = info->phys_sca_base;
1988         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1989         dev->irq       = info->irq_level;
1990
1991         /* network layer callbacks and settings */
1992         dev->do_ioctl       = hdlcdev_ioctl;
1993         dev->open           = hdlcdev_open;
1994         dev->stop           = hdlcdev_close;
1995         dev->tx_timeout     = hdlcdev_tx_timeout;
1996         dev->watchdog_timeo = 10*HZ;
1997         dev->tx_queue_len   = 50;
1998
1999         /* generic HDLC layer callbacks and settings */
2000         hdlc         = dev_to_hdlc(dev);
2001         hdlc->attach = hdlcdev_attach;
2002         hdlc->xmit   = hdlcdev_xmit;
2003
2004         /* register objects with HDLC layer */
2005         if ((rc = register_hdlc_device(dev))) {
2006                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2007                 free_netdev(dev);
2008                 return rc;
2009         }
2010
2011         info->netdev = dev;
2012         return 0;
2013 }
2014
2015 /**
2016  * called by device driver when removing device instance
2017  * do generic HDLC cleanup
2018  *
2019  * info  pointer to device instance information
2020  */
2021 static void hdlcdev_exit(SLMP_INFO *info)
2022 {
2023         unregister_hdlc_device(info->netdev);
2024         free_netdev(info->netdev);
2025         info->netdev = NULL;
2026 }
2027
2028 #endif /* CONFIG_HDLC */
2029
2030
2031 /* Return next bottom half action to perform.
2032  * Return Value:        BH action code or 0 if nothing to do.
2033  */
2034 int bh_action(SLMP_INFO *info)
2035 {
2036         unsigned long flags;
2037         int rc = 0;
2038
2039         spin_lock_irqsave(&info->lock,flags);
2040
2041         if (info->pending_bh & BH_RECEIVE) {
2042                 info->pending_bh &= ~BH_RECEIVE;
2043                 rc = BH_RECEIVE;
2044         } else if (info->pending_bh & BH_TRANSMIT) {
2045                 info->pending_bh &= ~BH_TRANSMIT;
2046                 rc = BH_TRANSMIT;
2047         } else if (info->pending_bh & BH_STATUS) {
2048                 info->pending_bh &= ~BH_STATUS;
2049                 rc = BH_STATUS;
2050         }
2051
2052         if (!rc) {
2053                 /* Mark BH routine as complete */
2054                 info->bh_running   = 0;
2055                 info->bh_requested = 0;
2056         }
2057
2058         spin_unlock_irqrestore(&info->lock,flags);
2059
2060         return rc;
2061 }
2062
2063 /* Perform bottom half processing of work items queued by ISR.
2064  */
2065 void bh_handler(void* Context)
2066 {
2067         SLMP_INFO *info = (SLMP_INFO*)Context;
2068         int action;
2069
2070         if (!info)
2071                 return;
2072
2073         if ( debug_level >= DEBUG_LEVEL_BH )
2074                 printk( "%s(%d):%s bh_handler() entry\n",
2075                         __FILE__,__LINE__,info->device_name);
2076
2077         info->bh_running = 1;
2078
2079         while((action = bh_action(info)) != 0) {
2080
2081                 /* Process work item */
2082                 if ( debug_level >= DEBUG_LEVEL_BH )
2083                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2084                                 __FILE__,__LINE__,info->device_name, action);
2085
2086                 switch (action) {
2087
2088                 case BH_RECEIVE:
2089                         bh_receive(info);
2090                         break;
2091                 case BH_TRANSMIT:
2092                         bh_transmit(info);
2093                         break;
2094                 case BH_STATUS:
2095                         bh_status(info);
2096                         break;
2097                 default:
2098                         /* unknown work item ID */
2099                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2100                                 __FILE__,__LINE__,info->device_name,action);
2101                         break;
2102                 }
2103         }
2104
2105         if ( debug_level >= DEBUG_LEVEL_BH )
2106                 printk( "%s(%d):%s bh_handler() exit\n",
2107                         __FILE__,__LINE__,info->device_name);
2108 }
2109
2110 void bh_receive(SLMP_INFO *info)
2111 {
2112         if ( debug_level >= DEBUG_LEVEL_BH )
2113                 printk( "%s(%d):%s bh_receive()\n",
2114                         __FILE__,__LINE__,info->device_name);
2115
2116         while( rx_get_frame(info) );
2117 }
2118
2119 void bh_transmit(SLMP_INFO *info)
2120 {
2121         struct tty_struct *tty = info->tty;
2122
2123         if ( debug_level >= DEBUG_LEVEL_BH )
2124                 printk( "%s(%d):%s bh_transmit() entry\n",
2125                         __FILE__,__LINE__,info->device_name);
2126
2127         if (tty) {
2128                 tty_wakeup(tty);
2129                 wake_up_interruptible(&tty->write_wait);
2130         }
2131 }
2132
2133 void bh_status(SLMP_INFO *info)
2134 {
2135         if ( debug_level >= DEBUG_LEVEL_BH )
2136                 printk( "%s(%d):%s bh_status() entry\n",
2137                         __FILE__,__LINE__,info->device_name);
2138
2139         info->ri_chkcount = 0;
2140         info->dsr_chkcount = 0;
2141         info->dcd_chkcount = 0;
2142         info->cts_chkcount = 0;
2143 }
2144
2145 void isr_timer(SLMP_INFO * info)
2146 {
2147         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2148
2149         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2150         write_reg(info, IER2, 0);
2151
2152         /* TMCS, Timer Control/Status Register
2153          *
2154          * 07      CMF, Compare match flag (read only) 1=match
2155          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2156          * 05      Reserved, must be 0
2157          * 04      TME, Timer Enable
2158          * 03..00  Reserved, must be 0
2159          *
2160          * 0000 0000
2161          */
2162         write_reg(info, (unsigned char)(timer + TMCS), 0);
2163
2164         info->irq_occurred = TRUE;
2165
2166         if ( debug_level >= DEBUG_LEVEL_ISR )
2167                 printk("%s(%d):%s isr_timer()\n",
2168                         __FILE__,__LINE__,info->device_name);
2169 }
2170
2171 void isr_rxint(SLMP_INFO * info)
2172 {
2173         struct tty_struct *tty = info->tty;
2174         struct  mgsl_icount *icount = &info->icount;
2175         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2176         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2177
2178         /* clear status bits */
2179         if (status)
2180                 write_reg(info, SR1, status);
2181
2182         if (status2)
2183                 write_reg(info, SR2, status2);
2184
2185         if ( debug_level >= DEBUG_LEVEL_ISR )
2186                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2187                         __FILE__,__LINE__,info->device_name,status,status2);
2188
2189         if (info->params.mode == MGSL_MODE_ASYNC) {
2190                 if (status & BRKD) {
2191                         icount->brk++;
2192
2193                         /* process break detection if tty control
2194                          * is not set to ignore it
2195                          */
2196                         if ( tty ) {
2197                                 if (!(status & info->ignore_status_mask1)) {
2198                                         if (info->read_status_mask1 & BRKD) {
2199                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2200                                                 if (info->flags & ASYNC_SAK)
2201                                                         do_SAK(tty);
2202                                         }
2203                                 }
2204                         }
2205                 }
2206         }
2207         else {
2208                 if (status & (FLGD|IDLD)) {
2209                         if (status & FLGD)
2210                                 info->icount.exithunt++;
2211                         else if (status & IDLD)
2212                                 info->icount.rxidle++;
2213                         wake_up_interruptible(&info->event_wait_q);
2214                 }
2215         }
2216
2217         if (status & CDCD) {
2218                 /* simulate a common modem status change interrupt
2219                  * for our handler
2220                  */
2221                 get_signals( info );
2222                 isr_io_pin(info,
2223                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2224         }
2225 }
2226
2227 /*
2228  * handle async rx data interrupts
2229  */
2230 void isr_rxrdy(SLMP_INFO * info)
2231 {
2232         u16 status;
2233         unsigned char DataByte;
2234         struct tty_struct *tty = info->tty;
2235         struct  mgsl_icount *icount = &info->icount;
2236
2237         if ( debug_level >= DEBUG_LEVEL_ISR )
2238                 printk("%s(%d):%s isr_rxrdy\n",
2239                         __FILE__,__LINE__,info->device_name);
2240
2241         while((status = read_reg(info,CST0)) & BIT0)
2242         {
2243                 DataByte = read_reg(info,TRB);
2244
2245                 if ( tty ) {
2246                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2247                                 continue;
2248
2249                         *tty->flip.char_buf_ptr = DataByte;
2250                         *tty->flip.flag_buf_ptr = 0;
2251                 }
2252
2253                 icount->rx++;
2254
2255                 if ( status & (PE + FRME + OVRN) ) {
2256                         printk("%s(%d):%s rxerr=%04X\n",
2257                                 __FILE__,__LINE__,info->device_name,status);
2258
2259                         /* update error statistics */
2260                         if (status & PE)
2261                                 icount->parity++;
2262                         else if (status & FRME)
2263                                 icount->frame++;
2264                         else if (status & OVRN)
2265                                 icount->overrun++;
2266
2267                         /* discard char if tty control flags say so */
2268                         if (status & info->ignore_status_mask2)
2269                                 continue;
2270
2271                         status &= info->read_status_mask2;
2272
2273                         if ( tty ) {
2274                                 if (status & PE)
2275                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2276                                 else if (status & FRME)
2277                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2278                                 if (status & OVRN) {
2279                                         /* Overrun is special, since it's
2280                                          * reported immediately, and doesn't
2281                                          * affect the current character
2282                                          */
2283                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2284                                                 tty->flip.count++;
2285                                                 tty->flip.flag_buf_ptr++;
2286                                                 tty->flip.char_buf_ptr++;
2287                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2288                                         }
2289                                 }
2290                         }
2291                 }       /* end of if (error) */
2292
2293                 if ( tty ) {
2294                         tty->flip.flag_buf_ptr++;
2295                         tty->flip.char_buf_ptr++;
2296                         tty->flip.count++;
2297                 }
2298         }
2299
2300         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2301                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2302                         __FILE__,__LINE__,info->device_name,
2303                         tty ? tty->flip.count : 0);
2304                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2305                         __FILE__,__LINE__,info->device_name,
2306                         icount->rx,icount->brk,icount->parity,
2307                         icount->frame,icount->overrun);
2308         }
2309
2310         if ( tty && tty->flip.count )
2311                 tty_flip_buffer_push(tty);
2312 }
2313
2314 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2315 {
2316         if ( debug_level >= DEBUG_LEVEL_ISR )
2317                 printk("%s(%d):%s isr_txeom status=%02x\n",
2318                         __FILE__,__LINE__,info->device_name,status);
2319
2320         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2321         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2322         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2323
2324         if (status & UDRN) {
2325                 write_reg(info, CMD, TXRESET);
2326                 write_reg(info, CMD, TXENABLE);
2327         } else
2328                 write_reg(info, CMD, TXBUFCLR);
2329
2330         /* disable and clear tx interrupts */
2331         info->ie0_value &= ~TXRDYE;
2332         info->ie1_value &= ~(IDLE + UDRN);
2333         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2334         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2335
2336         if ( info->tx_active ) {
2337                 if (info->params.mode != MGSL_MODE_ASYNC) {
2338                         if (status & UDRN)
2339                                 info->icount.txunder++;
2340                         else if (status & IDLE)
2341                                 info->icount.txok++;
2342                 }
2343
2344                 info->tx_active = 0;
2345                 info->tx_count = info->tx_put = info->tx_get = 0;
2346
2347                 del_timer(&info->tx_timer);
2348
2349                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2350                         info->serial_signals &= ~SerialSignal_RTS;
2351                         info->drop_rts_on_tx_done = 0;
2352                         set_signals(info);
2353                 }
2354
2355 #ifdef CONFIG_HDLC
2356                 if (info->netcount)
2357                         hdlcdev_tx_done(info);
2358                 else
2359 #endif
2360                 {
2361                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2362                                 tx_stop(info);
2363                                 return;
2364                         }
2365                         info->pending_bh |= BH_TRANSMIT;
2366                 }
2367         }
2368 }
2369
2370
2371 /*
2372  * handle tx status interrupts
2373  */
2374 void isr_txint(SLMP_INFO * info)
2375 {
2376         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2377
2378         /* clear status bits */
2379         write_reg(info, SR1, status);
2380
2381         if ( debug_level >= DEBUG_LEVEL_ISR )
2382                 printk("%s(%d):%s isr_txint status=%02x\n",
2383                         __FILE__,__LINE__,info->device_name,status);
2384
2385         if (status & (UDRN + IDLE))
2386                 isr_txeom(info, status);
2387
2388         if (status & CCTS) {
2389                 /* simulate a common modem status change interrupt
2390                  * for our handler
2391                  */
2392                 get_signals( info );
2393                 isr_io_pin(info,
2394                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2395
2396         }
2397 }
2398
2399 /*
2400  * handle async tx data interrupts
2401  */
2402 void isr_txrdy(SLMP_INFO * info)
2403 {
2404         if ( debug_level >= DEBUG_LEVEL_ISR )
2405                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2406                         __FILE__,__LINE__,info->device_name,info->tx_count);
2407
2408         if (info->params.mode != MGSL_MODE_ASYNC) {
2409                 /* disable TXRDY IRQ, enable IDLE IRQ */
2410                 info->ie0_value &= ~TXRDYE;
2411                 info->ie1_value |= IDLE;
2412                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2413                 return;
2414         }
2415
2416         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2417                 tx_stop(info);
2418                 return;
2419         }
2420
2421         if ( info->tx_count )
2422                 tx_load_fifo( info );
2423         else {
2424                 info->tx_active = 0;
2425                 info->ie0_value &= ~TXRDYE;
2426                 write_reg(info, IE0, info->ie0_value);
2427         }
2428
2429         if (info->tx_count < WAKEUP_CHARS)
2430                 info->pending_bh |= BH_TRANSMIT;
2431 }
2432
2433 void isr_rxdmaok(SLMP_INFO * info)
2434 {
2435         /* BIT7 = EOT (end of transfer)
2436          * BIT6 = EOM (end of message/frame)
2437          */
2438         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2439
2440         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2441         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2442
2443         if ( debug_level >= DEBUG_LEVEL_ISR )
2444                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2445                         __FILE__,__LINE__,info->device_name,status);
2446
2447         info->pending_bh |= BH_RECEIVE;
2448 }
2449
2450 void isr_rxdmaerror(SLMP_INFO * info)
2451 {
2452         /* BIT5 = BOF (buffer overflow)
2453          * BIT4 = COF (counter overflow)
2454          */
2455         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2456
2457         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2458         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2459
2460         if ( debug_level >= DEBUG_LEVEL_ISR )
2461                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2462                         __FILE__,__LINE__,info->device_name,status);
2463
2464         info->rx_overflow = TRUE;
2465         info->pending_bh |= BH_RECEIVE;
2466 }
2467
2468 void isr_txdmaok(SLMP_INFO * info)
2469 {
2470         unsigned char status_reg1 = read_reg(info, SR1);
2471
2472         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2473         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2474         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2475
2476         if ( debug_level >= DEBUG_LEVEL_ISR )
2477                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2478                         __FILE__,__LINE__,info->device_name,status_reg1);
2479
2480         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2481         write_reg16(info, TRC0, 0);
2482         info->ie0_value |= TXRDYE;
2483         write_reg(info, IE0, info->ie0_value);
2484 }
2485
2486 void isr_txdmaerror(SLMP_INFO * info)
2487 {
2488         /* BIT5 = BOF (buffer overflow)
2489          * BIT4 = COF (counter overflow)
2490          */
2491         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2492
2493         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2494         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2495
2496         if ( debug_level >= DEBUG_LEVEL_ISR )
2497                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2498                         __FILE__,__LINE__,info->device_name,status);
2499 }
2500
2501 /* handle input serial signal changes
2502  */
2503 void isr_io_pin( SLMP_INFO *info, u16 status )
2504 {
2505         struct  mgsl_icount *icount;
2506
2507         if ( debug_level >= DEBUG_LEVEL_ISR )
2508                 printk("%s(%d):isr_io_pin status=%04X\n",
2509                         __FILE__,__LINE__,status);
2510
2511         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2512                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2513                 icount = &info->icount;
2514                 /* update input line counters */
2515                 if (status & MISCSTATUS_RI_LATCHED) {
2516                         icount->rng++;
2517                         if ( status & SerialSignal_RI )
2518                                 info->input_signal_events.ri_up++;
2519                         else
2520                                 info->input_signal_events.ri_down++;
2521                 }
2522                 if (status & MISCSTATUS_DSR_LATCHED) {
2523                         icount->dsr++;
2524                         if ( status & SerialSignal_DSR )
2525                                 info->input_signal_events.dsr_up++;
2526                         else
2527                                 info->input_signal_events.dsr_down++;
2528                 }
2529                 if (status & MISCSTATUS_DCD_LATCHED) {
2530                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2531                                 info->ie1_value &= ~CDCD;
2532                                 write_reg(info, IE1, info->ie1_value);
2533                         }
2534                         icount->dcd++;
2535                         if (status & SerialSignal_DCD) {
2536                                 info->input_signal_events.dcd_up++;
2537                         } else
2538                                 info->input_signal_events.dcd_down++;
2539 #ifdef CONFIG_HDLC
2540                         if (info->netcount)
2541                                 hdlc_set_carrier(status & SerialSignal_DCD, info->netdev);
2542 #endif
2543                 }
2544                 if (status & MISCSTATUS_CTS_LATCHED)
2545                 {
2546                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2547                                 info->ie1_value &= ~CCTS;
2548                                 write_reg(info, IE1, info->ie1_value);
2549                         }
2550                         icount->cts++;
2551                         if ( status & SerialSignal_CTS )
2552                                 info->input_signal_events.cts_up++;
2553                         else
2554                                 info->input_signal_events.cts_down++;
2555                 }
2556                 wake_up_interruptible(&info->status_event_wait_q);
2557                 wake_up_interruptible(&info->event_wait_q);
2558
2559                 if ( (info->flags & ASYNC_CHECK_CD) &&
2560                      (status & MISCSTATUS_DCD_LATCHED) ) {
2561                         if ( debug_level >= DEBUG_LEVEL_ISR )
2562                                 printk("%s CD now %s...", info->device_name,
2563                                        (status & SerialSignal_DCD) ? "on" : "off");
2564                         if (status & SerialSignal_DCD)
2565                                 wake_up_interruptible(&info->open_wait);
2566                         else {
2567                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2568                                         printk("doing serial hangup...");
2569                                 if (info->tty)
2570                                         tty_hangup(info->tty);
2571                         }
2572                 }
2573
2574                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2575                      (status & MISCSTATUS_CTS_LATCHED) ) {
2576                         if ( info->tty ) {
2577                                 if (info->tty->hw_stopped) {
2578                                         if (status & SerialSignal_CTS) {
2579                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2580                                                         printk("CTS tx start...");
2581                                                 info->tty->hw_stopped = 0;
2582                                                 tx_start(info);
2583                                                 info->pending_bh |= BH_TRANSMIT;
2584                                                 return;
2585                                         }
2586                                 } else {
2587                                         if (!(status & SerialSignal_CTS)) {
2588                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2589                                                         printk("CTS tx stop...");
2590                                                 info->tty->hw_stopped = 1;
2591                                                 tx_stop(info);
2592                                         }
2593                                 }
2594                         }
2595                 }
2596         }
2597
2598         info->pending_bh |= BH_STATUS;
2599 }
2600
2601 /* Interrupt service routine entry point.
2602  *
2603  * Arguments:
2604  *      irq             interrupt number that caused interrupt
2605  *      dev_id          device ID supplied during interrupt registration
2606  *      regs            interrupted processor context
2607  */
2608 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2609                                         struct pt_regs *regs)
2610 {
2611         SLMP_INFO * info;
2612         unsigned char status, status0, status1=0;
2613         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2614         unsigned char timerstatus0, timerstatus1=0;
2615         unsigned char shift;
2616         unsigned int i;
2617         unsigned short tmp;
2618
2619         if ( debug_level >= DEBUG_LEVEL_ISR )
2620                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2621                         __FILE__,__LINE__,irq);
2622
2623         info = (SLMP_INFO *)dev_id;
2624         if (!info)
2625                 return IRQ_NONE;
2626
2627         spin_lock(&info->lock);
2628
2629         for(;;) {
2630
2631                 /* get status for SCA0 (ports 0-1) */
2632                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2633                 status0 = (unsigned char)tmp;
2634                 dmastatus0 = (unsigned char)(tmp>>8);
2635                 timerstatus0 = read_reg(info, ISR2);
2636
2637                 if ( debug_level >= DEBUG_LEVEL_ISR )
2638                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2639                                 __FILE__,__LINE__,info->device_name,
2640                                 status0,dmastatus0,timerstatus0);
2641
2642                 if (info->port_count == 4) {
2643                         /* get status for SCA1 (ports 2-3) */
2644                         tmp = read_reg16(info->port_array[2], ISR0);
2645                         status1 = (unsigned char)tmp;
2646                         dmastatus1 = (unsigned char)(tmp>>8);
2647                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2648
2649                         if ( debug_level >= DEBUG_LEVEL_ISR )
2650                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2651                                         __FILE__,__LINE__,info->device_name,
2652                                         status1,dmastatus1,timerstatus1);
2653                 }
2654
2655                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2656                          !status1 && !dmastatus1 && !timerstatus1)
2657                         break;
2658
2659                 for(i=0; i < info->port_count ; i++) {
2660                         if (info->port_array[i] == NULL)
2661                                 continue;
2662                         if (i < 2) {
2663                                 status = status0;
2664                                 dmastatus = dmastatus0;
2665                         } else {
2666                                 status = status1;
2667                                 dmastatus = dmastatus1;
2668                         }
2669
2670                         shift = i & 1 ? 4 :0;
2671
2672                         if (status & BIT0 << shift)
2673                                 isr_rxrdy(info->port_array[i]);
2674                         if (status & BIT1 << shift)
2675                                 isr_txrdy(info->port_array[i]);
2676                         if (status & BIT2 << shift)
2677                                 isr_rxint(info->port_array[i]);
2678                         if (status & BIT3 << shift)
2679                                 isr_txint(info->port_array[i]);
2680
2681                         if (dmastatus & BIT0 << shift)
2682                                 isr_rxdmaerror(info->port_array[i]);
2683                         if (dmastatus & BIT1 << shift)
2684                                 isr_rxdmaok(info->port_array[i]);
2685                         if (dmastatus & BIT2 << shift)
2686                                 isr_txdmaerror(info->port_array[i]);
2687                         if (dmastatus & BIT3 << shift)
2688                                 isr_txdmaok(info->port_array[i]);
2689                 }
2690
2691                 if (timerstatus0 & (BIT5 | BIT4))
2692                         isr_timer(info->port_array[0]);
2693                 if (timerstatus0 & (BIT7 | BIT6))
2694                         isr_timer(info->port_array[1]);
2695                 if (timerstatus1 & (BIT5 | BIT4))
2696                         isr_timer(info->port_array[2]);
2697                 if (timerstatus1 & (BIT7 | BIT6))
2698                         isr_timer(info->port_array[3]);
2699         }
2700
2701         for(i=0; i < info->port_count ; i++) {
2702                 SLMP_INFO * port = info->port_array[i];
2703
2704                 /* Request bottom half processing if there's something
2705                  * for it to do and the bh is not already running.
2706                  *
2707                  * Note: startup adapter diags require interrupts.
2708                  * do not request bottom half processing if the
2709                  * device is not open in a normal mode.
2710                  */
2711                 if ( port && (port->count || port->netcount) &&
2712                      port->pending_bh && !port->bh_running &&
2713                      !port->bh_requested ) {
2714                         if ( debug_level >= DEBUG_LEVEL_ISR )
2715                                 printk("%s(%d):%s queueing bh task.\n",
2716                                         __FILE__,__LINE__,port->device_name);
2717                         schedule_work(&port->task);
2718                         port->bh_requested = 1;
2719                 }
2720         }
2721
2722         spin_unlock(&info->lock);
2723
2724         if ( debug_level >= DEBUG_LEVEL_ISR )
2725                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2726                         __FILE__,__LINE__,irq);
2727         return IRQ_HANDLED;
2728 }
2729
2730 /* Initialize and start device.
2731  */
2732 static int startup(SLMP_INFO * info)
2733 {
2734         if ( debug_level >= DEBUG_LEVEL_INFO )
2735                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2736
2737         if (info->flags & ASYNC_INITIALIZED)
2738                 return 0;
2739
2740         if (!info->tx_buf) {
2741                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2742                 if (!info->tx_buf) {
2743                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2744                                 __FILE__,__LINE__,info->device_name);
2745                         return -ENOMEM;
2746                 }
2747         }
2748
2749         info->pending_bh = 0;
2750
2751         memset(&info->icount, 0, sizeof(info->icount));
2752
2753         /* program hardware for current parameters */
2754         reset_port(info);
2755
2756         change_params(info);
2757
2758         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2759         add_timer(&info->status_timer);
2760
2761         if (info->tty)
2762                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2763
2764         info->flags |= ASYNC_INITIALIZED;
2765
2766         return 0;
2767 }
2768
2769 /* Called by close() and hangup() to shutdown hardware
2770  */
2771 static void shutdown(SLMP_INFO * info)
2772 {
2773         unsigned long flags;
2774
2775         if (!(info->flags & ASYNC_INITIALIZED))
2776                 return;
2777
2778         if (debug_level >= DEBUG_LEVEL_INFO)
2779                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2780                          __FILE__,__LINE__, info->device_name );
2781
2782         /* clear status wait queue because status changes */
2783         /* can't happen after shutting down the hardware */
2784         wake_up_interruptible(&info->status_event_wait_q);
2785         wake_up_interruptible(&info->event_wait_q);
2786
2787         del_timer(&info->tx_timer);
2788         del_timer(&info->status_timer);
2789
2790         if (info->tx_buf) {
2791                 kfree(info->tx_buf);
2792                 info->tx_buf = NULL;
2793         }
2794
2795         spin_lock_irqsave(&info->lock,flags);
2796
2797         reset_port(info);
2798
2799         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2800                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2801                 set_signals(info);
2802         }
2803
2804         spin_unlock_irqrestore(&info->lock,flags);
2805
2806         if (info->tty)
2807                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2808
2809         info->flags &= ~ASYNC_INITIALIZED;
2810 }
2811
2812 static void program_hw(SLMP_INFO *info)
2813 {
2814         unsigned long flags;
2815
2816         spin_lock_irqsave(&info->lock,flags);
2817
2818         rx_stop(info);
2819         tx_stop(info);
2820
2821         info->tx_count = info->tx_put = info->tx_get = 0;
2822
2823         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2824                 hdlc_mode(info);
2825         else
2826                 async_mode(info);
2827
2828         set_signals(info);
2829
2830         info->dcd_chkcount = 0;
2831         info->cts_chkcount = 0;
2832         info->ri_chkcount = 0;
2833         info->dsr_chkcount = 0;
2834
2835         info->ie1_value |= (CDCD|CCTS);
2836         write_reg(info, IE1, info->ie1_value);
2837
2838         get_signals(info);
2839
2840         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2841                 rx_start(info);
2842
2843         spin_unlock_irqrestore(&info->lock,flags);
2844 }
2845
2846 /* Reconfigure adapter based on new parameters
2847  */
2848 static void change_params(SLMP_INFO *info)
2849 {
2850         unsigned cflag;
2851         int bits_per_char;
2852
2853         if (!info->tty || !info->tty->termios)
2854                 return;
2855
2856         if (debug_level >= DEBUG_LEVEL_INFO)
2857                 printk("%s(%d):%s change_params()\n",
2858                          __FILE__,__LINE__, info->device_name );
2859
2860         cflag = info->tty->termios->c_cflag;
2861
2862         /* if B0 rate (hangup) specified then negate DTR and RTS */
2863         /* otherwise assert DTR and RTS */
2864         if (cflag & CBAUD)
2865                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2866         else
2867                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2868
2869         /* byte size and parity */
2870
2871         switch (cflag & CSIZE) {
2872               case CS5: info->params.data_bits = 5; break;
2873               case CS6: info->params.data_bits = 6; break;
2874               case CS7: info->params.data_bits = 7; break;
2875               case CS8: info->params.data_bits = 8; break;
2876               /* Never happens, but GCC is too dumb to figure it out */
2877               default:  info->params.data_bits = 7; break;
2878               }
2879
2880         if (cflag & CSTOPB)
2881                 info->params.stop_bits = 2;
2882         else
2883                 info->params.stop_bits = 1;
2884
2885         info->params.parity = ASYNC_PARITY_NONE;
2886         if (cflag & PARENB) {
2887                 if (cflag & PARODD)
2888                         info->params.parity = ASYNC_PARITY_ODD;
2889                 else
2890                         info->params.parity = ASYNC_PARITY_EVEN;
2891 #ifdef CMSPAR
2892                 if (cflag & CMSPAR)
2893                         info->params.parity = ASYNC_PARITY_SPACE;
2894 #endif
2895         }
2896
2897         /* calculate number of jiffies to transmit a full
2898          * FIFO (32 bytes) at specified data rate
2899          */
2900         bits_per_char = info->params.data_bits +
2901                         info->params.stop_bits + 1;
2902
2903         /* if port data rate is set to 460800 or less then
2904          * allow tty settings to override, otherwise keep the
2905          * current data rate.
2906          */
2907         if (info->params.data_rate <= 460800) {
2908                 info->params.data_rate = tty_get_baud_rate(info->tty);
2909         }
2910
2911         if ( info->params.data_rate ) {
2912                 info->timeout = (32*HZ*bits_per_char) /
2913                                 info->params.data_rate;
2914         }
2915         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2916
2917         if (cflag & CRTSCTS)
2918                 info->flags |= ASYNC_CTS_FLOW;
2919         else
2920                 info->flags &= ~ASYNC_CTS_FLOW;
2921
2922         if (cflag & CLOCAL)
2923                 info->flags &= ~ASYNC_CHECK_CD;
2924         else
2925                 info->flags |= ASYNC_CHECK_CD;
2926
2927         /* process tty input control flags */
2928
2929         info->read_status_mask2 = OVRN;
2930         if (I_INPCK(info->tty))
2931                 info->read_status_mask2 |= PE | FRME;
2932         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2933                 info->read_status_mask1 |= BRKD;
2934         if (I_IGNPAR(info->tty))
2935                 info->ignore_status_mask2 |= PE | FRME;
2936         if (I_IGNBRK(info->tty)) {
2937                 info->ignore_status_mask1 |= BRKD;
2938                 /* If ignoring parity and break indicators, ignore
2939                  * overruns too.  (For real raw support).
2940                  */
2941                 if (I_IGNPAR(info->tty))
2942                         info->ignore_status_mask2 |= OVRN;
2943         }
2944
2945         program_hw(info);
2946 }
2947
2948 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2949 {
2950         int err;
2951
2952         if (debug_level >= DEBUG_LEVEL_INFO)
2953                 printk("%s(%d):%s get_params()\n",
2954                          __FILE__,__LINE__, info->device_name);
2955
2956         if (!user_icount) {
2957                 memset(&info->icount, 0, sizeof(info->icount));
2958         } else {
2959                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2960                 if (err)
2961                         return -EFAULT;
2962         }
2963
2964         return 0;
2965 }
2966
2967 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2968 {
2969         int err;
2970         if (debug_level >= DEBUG_LEVEL_INFO)
2971                 printk("%s(%d):%s get_params()\n",
2972                          __FILE__,__LINE__, info->device_name);
2973
2974         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2975         if (err) {
2976                 if ( debug_level >= DEBUG_LEVEL_INFO )
2977                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2978                                 __FILE__,__LINE__,info->device_name);
2979                 return -EFAULT;
2980         }
2981
2982         return 0;
2983 }
2984
2985 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2986 {
2987         unsigned long flags;
2988         MGSL_PARAMS tmp_params;
2989         int err;
2990
2991         if (debug_level >= DEBUG_LEVEL_INFO)
2992                 printk("%s(%d):%s set_params\n",
2993                         __FILE__,__LINE__,info->device_name );
2994         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2995         if (err) {
2996                 if ( debug_level >= DEBUG_LEVEL_INFO )
2997                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2998                                 __FILE__,__LINE__,info->device_name);
2999                 return -EFAULT;
3000         }
3001
3002         spin_lock_irqsave(&info->lock,flags);
3003         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3004         spin_unlock_irqrestore(&info->lock,flags);
3005
3006         change_params(info);
3007
3008         return 0;
3009 }
3010
3011 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3012 {
3013         int err;
3014
3015         if (debug_level >= DEBUG_LEVEL_INFO)
3016                 printk("%s(%d):%s get_txidle()=%d\n",
3017                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3018
3019         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3020         if (err) {
3021                 if ( debug_level >= DEBUG_LEVEL_INFO )
3022                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3023                                 __FILE__,__LINE__,info->device_name);
3024                 return -EFAULT;
3025         }
3026
3027         return 0;
3028 }
3029
3030 static int set_txidle(SLMP_INFO * info, int idle_mode)
3031 {
3032         unsigned long flags;
3033
3034         if (debug_level >= DEBUG_LEVEL_INFO)
3035                 printk("%s(%d):%s set_txidle(%d)\n",
3036                         __FILE__,__LINE__,info->device_name, idle_mode );
3037
3038         spin_lock_irqsave(&info->lock,flags);
3039         info->idle_mode = idle_mode;
3040         tx_set_idle( info );
3041         spin_unlock_irqrestore(&info->lock,flags);
3042         return 0;
3043 }
3044
3045 static int tx_enable(SLMP_INFO * info, int enable)
3046 {
3047         unsigned long flags;
3048
3049         if (debug_level >= DEBUG_LEVEL_INFO)
3050                 printk("%s(%d):%s tx_enable(%d)\n",
3051                         __FILE__,__LINE__,info->device_name, enable);
3052
3053         spin_lock_irqsave(&info->lock,flags);
3054         if ( enable ) {
3055                 if ( !info->tx_enabled ) {
3056                         tx_start(info);
3057                 }
3058         } else {
3059                 if ( info->tx_enabled )
3060                         tx_stop(info);
3061         }
3062         spin_unlock_irqrestore(&info->lock,flags);
3063         return 0;
3064 }
3065
3066 /* abort send HDLC frame
3067  */
3068 static int tx_abort(SLMP_INFO * info)
3069 {
3070         unsigned long flags;
3071
3072         if (debug_level >= DEBUG_LEVEL_INFO)
3073                 printk("%s(%d):%s tx_abort()\n",
3074                         __FILE__,__LINE__,info->device_name);
3075
3076         spin_lock_irqsave(&info->lock,flags);
3077         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3078                 info->ie1_value &= ~UDRN;
3079                 info->ie1_value |= IDLE;
3080                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3081                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3082
3083                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3084                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3085
3086                 write_reg(info, CMD, TXABORT);
3087         }
3088         spin_unlock_irqrestore(&info->lock,flags);
3089         return 0;
3090 }
3091
3092 static int rx_enable(SLMP_INFO * info, int enable)
3093 {
3094         unsigned long flags;
3095
3096         if (debug_level >= DEBUG_LEVEL_INFO)
3097                 printk("%s(%d):%s rx_enable(%d)\n",
3098                         __FILE__,__LINE__,info->device_name,enable);
3099
3100         spin_lock_irqsave(&info->lock,flags);
3101         if ( enable ) {
3102                 if ( !info->rx_enabled )
3103                         rx_start(info);
3104         } else {
3105                 if ( info->rx_enabled )
3106                         rx_stop(info);
3107         }
3108         spin_unlock_irqrestore(&info->lock,flags);
3109         return 0;
3110 }
3111
3112 /* wait for specified event to occur
3113  */
3114 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3115 {
3116         unsigned long flags;
3117         int s;
3118         int rc=0;
3119         struct mgsl_icount cprev, cnow;
3120         int events;
3121         int mask;
3122         struct  _input_signal_events oldsigs, newsigs;
3123         DECLARE_WAITQUEUE(wait, current);
3124
3125         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3126         if (rc) {
3127                 return  -EFAULT;
3128         }
3129
3130         if (debug_level >= DEBUG_LEVEL_INFO)
3131                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3132                         __FILE__,__LINE__,info->device_name,mask);
3133
3134         spin_lock_irqsave(&info->lock,flags);
3135
3136         /* return immediately if state matches requested events */
3137         get_signals(info);
3138         s = info->serial_signals;
3139
3140         events = mask &
3141                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3142                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3143                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3144                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3145         if (events) {
3146                 spin_unlock_irqrestore(&info->lock,flags);
3147                 goto exit;
3148         }
3149
3150         /* save current irq counts */
3151         cprev = info->icount;
3152         oldsigs = info->input_signal_events;
3153
3154         /* enable hunt and idle irqs if needed */
3155         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3156                 unsigned char oldval = info->ie1_value;
3157                 unsigned char newval = oldval +
3158                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3159                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3160                 if ( oldval != newval ) {
3161                         info->ie1_value = newval;
3162                         write_reg(info, IE1, info->ie1_value);
3163                 }
3164         }
3165
3166         set_current_state(TASK_INTERRUPTIBLE);
3167         add_wait_queue(&info->event_wait_q, &wait);
3168
3169         spin_unlock_irqrestore(&info->lock,flags);
3170
3171         for(;;) {
3172                 schedule();
3173                 if (signal_pending(current)) {
3174                         rc = -ERESTARTSYS;
3175                         break;
3176                 }
3177
3178                 /* get current irq counts */
3179                 spin_lock_irqsave(&info->lock,flags);
3180                 cnow = info->icount;
3181                 newsigs = info->input_signal_events;
3182                 set_current_state(TASK_INTERRUPTIBLE);
3183                 spin_unlock_irqrestore(&info->lock,flags);
3184
3185                 /* if no change, wait aborted for some reason */
3186                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3187                     newsigs.dsr_down == oldsigs.dsr_down &&
3188                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3189                     newsigs.dcd_down == oldsigs.dcd_down &&
3190                     newsigs.cts_up   == oldsigs.cts_up   &&
3191                     newsigs.cts_down == oldsigs.cts_down &&
3192                     newsigs.ri_up    == oldsigs.ri_up    &&
3193                     newsigs.ri_down  == oldsigs.ri_down  &&
3194                     cnow.exithunt    == cprev.exithunt   &&
3195                     cnow.rxidle      == cprev.rxidle) {
3196                         rc = -EIO;
3197                         break;
3198                 }
3199
3200                 events = mask &
3201                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3202                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3203                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3204                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3205                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3206                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3207                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3208                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3209                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3210                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3211                 if (events)
3212                         break;
3213
3214                 cprev = cnow;
3215                 oldsigs = newsigs;
3216         }
3217
3218         remove_wait_queue(&info->event_wait_q, &wait);
3219         set_current_state(TASK_RUNNING);
3220
3221
3222         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3223                 spin_lock_irqsave(&info->lock,flags);
3224                 if (!waitqueue_active(&info->event_wait_q)) {
3225                         /* disable enable exit hunt mode/idle rcvd IRQs */
3226                         info->ie1_value &= ~(FLGD|IDLD);
3227                         write_reg(info, IE1, info->ie1_value);
3228                 }
3229                 spin_unlock_irqrestore(&info->lock,flags);
3230         }
3231 exit:
3232         if ( rc == 0 )
3233                 PUT_USER(rc, events, mask_ptr);
3234
3235         return rc;
3236 }
3237
3238 static int modem_input_wait(SLMP_INFO *info,int arg)
3239 {
3240         unsigned long flags;
3241         int rc;
3242         struct mgsl_icount cprev, cnow;
3243         DECLARE_WAITQUEUE(wait, current);
3244
3245         /* save current irq counts */
3246         spin_lock_irqsave(&info->lock,flags);
3247         cprev = info->icount;
3248         add_wait_queue(&info->status_event_wait_q, &wait);
3249         set_current_state(TASK_INTERRUPTIBLE);
3250         spin_unlock_irqrestore(&info->lock,flags);
3251
3252         for(;;) {
3253                 schedule();
3254                 if (signal_pending(current)) {
3255                         rc = -ERESTARTSYS;
3256                         break;
3257                 }
3258
3259                 /* get new irq counts */
3260                 spin_lock_irqsave(&info->lock,flags);
3261                 cnow = info->icount;
3262                 set_current_state(TASK_INTERRUPTIBLE);
3263                 spin_unlock_irqrestore(&info->lock,flags);
3264
3265                 /* if no change, wait aborted for some reason */
3266                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3267                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3268                         rc = -EIO;
3269                         break;
3270                 }
3271
3272                 /* check for change in caller specified modem input */
3273                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3274                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3275                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3276                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3277                         rc = 0;
3278                         break;
3279                 }
3280
3281                 cprev = cnow;
3282         }
3283         remove_wait_queue(&info->status_event_wait_q, &wait);
3284         set_current_state(TASK_RUNNING);
3285         return rc;
3286 }
3287
3288 /* return the state of the serial control and status signals
3289  */
3290 static int tiocmget(struct tty_struct *tty, struct file *file)
3291 {
3292         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3293         unsigned int result;
3294         unsigned long flags;
3295
3296         spin_lock_irqsave(&info->lock,flags);
3297         get_signals(info);
3298         spin_unlock_irqrestore(&info->lock,flags);
3299
3300         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3301                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3302                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3303                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3304                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3305                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3306
3307         if (debug_level >= DEBUG_LEVEL_INFO)
3308                 printk("%s(%d):%s tiocmget() value=%08X\n",
3309                          __FILE__,__LINE__, info->device_name, result );
3310         return result;
3311 }
3312
3313 /* set modem control signals (DTR/RTS)
3314  */
3315 static int tiocmset(struct tty_struct *tty, struct file *file,
3316                     unsigned int set, unsigned int clear)
3317 {
3318         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3319         unsigned long flags;
3320
3321         if (debug_level >= DEBUG_LEVEL_INFO)
3322                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3323                         __FILE__,__LINE__,info->device_name, set, clear);
3324
3325         if (set & TIOCM_RTS)
3326                 info->serial_signals |= SerialSignal_RTS;
3327         if (set & TIOCM_DTR)
3328                 info->serial_signals |= SerialSignal_DTR;
3329         if (clear & TIOCM_RTS)
3330                 info->serial_signals &= ~SerialSignal_RTS;
3331         if (clear & TIOCM_DTR)
3332                 info->serial_signals &= ~SerialSignal_DTR;
3333
3334         spin_lock_irqsave(&info->lock,flags);
3335         set_signals(info);
3336         spin_unlock_irqrestore(&info->lock,flags);
3337
3338         return 0;
3339 }
3340
3341
3342
3343 /* Block the current process until the specified port is ready to open.
3344  */
3345 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3346                            SLMP_INFO *info)
3347 {
3348         DECLARE_WAITQUEUE(wait, current);
3349         int             retval;
3350         int             do_clocal = 0, extra_count = 0;
3351         unsigned long   flags;
3352
3353         if (debug_level >= DEBUG_LEVEL_INFO)
3354                 printk("%s(%d):%s block_til_ready()\n",
3355                          __FILE__,__LINE__, tty->driver->name );
3356
3357         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3358                 /* nonblock mode is set or port is not enabled */
3359                 /* just verify that callout device is not active */
3360                 info->flags |= ASYNC_NORMAL_ACTIVE;
3361                 return 0;
3362         }
3363
3364         if (tty->termios->c_cflag & CLOCAL)
3365                 do_clocal = 1;
3366
3367         /* Wait for carrier detect and the line to become
3368          * free (i.e., not in use by the callout).  While we are in
3369          * this loop, info->count is dropped by one, so that
3370          * close() knows when to free things.  We restore it upon
3371          * exit, either normal or abnormal.
3372          */
3373
3374         retval = 0;
3375         add_wait_queue(&info->open_wait, &wait);
3376
3377         if (debug_level >= DEBUG_LEVEL_INFO)
3378                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3379                          __FILE__,__LINE__, tty->driver->name, info->count );
3380
3381         spin_lock_irqsave(&info->lock, flags);
3382         if (!tty_hung_up_p(filp)) {
3383                 extra_count = 1;
3384                 info->count--;
3385         }
3386         spin_unlock_irqrestore(&info->lock, flags);
3387         info->blocked_open++;
3388
3389         while (1) {
3390                 if ((tty->termios->c_cflag & CBAUD)) {
3391                         spin_lock_irqsave(&info->lock,flags);
3392                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3393                         set_signals(info);
3394                         spin_unlock_irqrestore(&info->lock,flags);
3395                 }
3396
3397                 set_current_state(TASK_INTERRUPTIBLE);
3398
3399                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3400                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3401                                         -EAGAIN : -ERESTARTSYS;
3402                         break;
3403                 }
3404
3405                 spin_lock_irqsave(&info->lock,flags);
3406                 get_signals(info);
3407                 spin_unlock_irqrestore(&info->lock,flags);
3408
3409                 if (!(info->flags & ASYNC_CLOSING) &&
3410                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3411                         break;
3412                 }
3413
3414                 if (signal_pending(current)) {
3415                         retval = -ERESTARTSYS;
3416                         break;
3417                 }
3418
3419                 if (debug_level >= DEBUG_LEVEL_INFO)
3420                         printk("%s(%d):%s block_til_ready() count=%d\n",
3421                                  __FILE__,__LINE__, tty->driver->name, info->count );
3422
3423                 schedule();
3424         }
3425
3426         set_current_state(TASK_RUNNING);
3427         remove_wait_queue(&info->open_wait, &wait);
3428
3429         if (extra_count)
3430                 info->count++;
3431         info->blocked_open--;
3432
3433         if (debug_level >= DEBUG_LEVEL_INFO)
3434                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3435                          __FILE__,__LINE__, tty->driver->name, info->count );
3436
3437         if (!retval)
3438                 info->flags |= ASYNC_NORMAL_ACTIVE;
3439
3440         return retval;
3441 }
3442
3443 int alloc_dma_bufs(SLMP_INFO *info)
3444 {
3445         unsigned short BuffersPerFrame;
3446         unsigned short BufferCount;
3447
3448         // Force allocation to start at 64K boundary for each port.
3449         // This is necessary because *all* buffer descriptors for a port
3450         // *must* be in the same 64K block. All descriptors on a port
3451         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3452         // into the CBP register.
3453         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3454
3455         /* Calculate the number of DMA buffers necessary to hold the */
3456         /* largest allowable frame size. Note: If the max frame size is */
3457         /* not an even multiple of the DMA buffer size then we need to */
3458         /* round the buffer count per frame up one. */
3459
3460         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3461         if ( info->max_frame_size % SCABUFSIZE )
3462                 BuffersPerFrame++;
3463
3464         /* calculate total number of data buffers (SCABUFSIZE) possible
3465          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3466          * for the descriptor list (BUFFERLISTSIZE).
3467          */
3468         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3469
3470         /* limit number of buffers to maximum amount of descriptors */
3471         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3472                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3473
3474         /* use enough buffers to transmit one max size frame */
3475         info->tx_buf_count = BuffersPerFrame + 1;
3476
3477         /* never use more than half the available buffers for transmit */
3478         if (info->tx_buf_count > (BufferCount/2))
3479                 info->tx_buf_count = BufferCount/2;
3480
3481         if (info->tx_buf_count > SCAMAXDESC)
3482                 info->tx_buf_count = SCAMAXDESC;
3483
3484         /* use remaining buffers for receive */
3485         info->rx_buf_count = BufferCount - info->tx_buf_count;
3486
3487         if (info->rx_buf_count > SCAMAXDESC)
3488                 info->rx_buf_count = SCAMAXDESC;
3489
3490         if ( debug_level >= DEBUG_LEVEL_INFO )
3491                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3492                         __FILE__,__LINE__, info->device_name,
3493                         info->tx_buf_count,info->rx_buf_count);
3494
3495         if ( alloc_buf_list( info ) < 0 ||
3496                 alloc_frame_bufs(info,
3497                                         info->rx_buf_list,
3498                                         info->rx_buf_list_ex,
3499                                         info->rx_buf_count) < 0 ||
3500                 alloc_frame_bufs(info,
3501                                         info->tx_buf_list,
3502                                         info->tx_buf_list_ex,
3503                                         info->tx_buf_count) < 0 ||
3504                 alloc_tmp_rx_buf(info) < 0 ) {
3505                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3506                         __FILE__,__LINE__, info->device_name);
3507                 return -ENOMEM;
3508         }
3509
3510         rx_reset_buffers( info );
3511
3512         return 0;
3513 }
3514
3515 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3516  */
3517 int alloc_buf_list(SLMP_INFO *info)
3518 {
3519         unsigned int i;
3520
3521         /* build list in adapter shared memory */
3522         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3523         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3524         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3525
3526         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3527
3528         /* Save virtual address pointers to the receive and */
3529         /* transmit buffer lists. (Receive 1st). These pointers will */
3530         /* be used by the processor to access the lists. */
3531         info->rx_buf_list = (SCADESC *)info->buffer_list;
3532
3533         info->tx_buf_list = (SCADESC *)info->buffer_list;
3534         info->tx_buf_list += info->rx_buf_count;
3535
3536         /* Build links for circular buffer entry lists (tx and rx)
3537          *
3538          * Note: links are physical addresses read by the SCA device
3539          * to determine the next buffer entry to use.
3540          */
3541
3542         for ( i = 0; i < info->rx_buf_count; i++ ) {
3543                 /* calculate and store physical address of this buffer entry */
3544                 info->rx_buf_list_ex[i].phys_entry =
3545                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3546
3547                 /* calculate and store physical address of */
3548                 /* next entry in cirular list of entries */
3549                 info->rx_buf_list[i].next = info->buffer_list_phys;
3550                 if ( i < info->rx_buf_count - 1 )
3551                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3552
3553                 info->rx_buf_list[i].length = SCABUFSIZE;
3554         }
3555
3556         for ( i = 0; i < info->tx_buf_count; i++ ) {
3557                 /* calculate and store physical address of this buffer entry */
3558                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3559                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3560
3561                 /* calculate and store physical address of */
3562                 /* next entry in cirular list of entries */
3563
3564                 info->tx_buf_list[i].next = info->buffer_list_phys +
3565                         info->rx_buf_count * sizeof(SCADESC);
3566
3567                 if ( i < info->tx_buf_count - 1 )
3568                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3569         }
3570
3571         return 0;
3572 }
3573
3574 /* Allocate the frame DMA buffers used by the specified buffer list.
3575  */
3576 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3577 {
3578         int i;
3579         unsigned long phys_addr;
3580
3581         for ( i = 0; i < count; i++ ) {
3582                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3583                 phys_addr = info->port_array[0]->last_mem_alloc;
3584                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3585
3586                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3587                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3588         }
3589
3590         return 0;
3591 }
3592
3593 void free_dma_bufs(SLMP_INFO *info)
3594 {
3595         info->buffer_list = NULL;
3596         info->rx_buf_list = NULL;
3597         info->tx_buf_list = NULL;
3598 }
3599
3600 /* allocate buffer large enough to hold max_frame_size.
3601  * This buffer is used to pass an assembled frame to the line discipline.
3602  */
3603 int alloc_tmp_rx_buf(SLMP_INFO *info)
3604 {
3605         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3606         if (info->tmp_rx_buf == NULL)
3607                 return -ENOMEM;
3608         return 0;
3609 }
3610
3611 void free_tmp_rx_buf(SLMP_INFO *info)
3612 {
3613         if (info->tmp_rx_buf)
3614                 kfree(info->tmp_rx_buf);
3615         info->tmp_rx_buf = NULL;
3616 }
3617
3618 int claim_resources(SLMP_INFO *info)
3619 {
3620         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3621                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3622                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3623                 info->init_error = DiagStatus_AddressConflict;
3624                 goto errout;
3625         }
3626         else
3627                 info->shared_mem_requested = 1;
3628
3629         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3630                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3631                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3632                 info->init_error = DiagStatus_AddressConflict;
3633                 goto errout;
3634         }
3635         else
3636                 info->lcr_mem_requested = 1;
3637
3638         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3639                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3640                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3641                 info->init_error = DiagStatus_AddressConflict;
3642                 goto errout;
3643         }
3644         else
3645                 info->sca_base_requested = 1;
3646
3647         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3648                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3649                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3650                 info->init_error = DiagStatus_AddressConflict;
3651                 goto errout;
3652         }
3653         else
3654                 info->sca_statctrl_requested = 1;
3655
3656         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3657         if (!info->memory_base) {
3658                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3659                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3660                 info->init_error = DiagStatus_CantAssignPciResources;
3661                 goto errout;
3662         }
3663
3664         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3665         if (!info->lcr_base) {
3666                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3667                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3668                 info->init_error = DiagStatus_CantAssignPciResources;
3669                 goto errout;
3670         }
3671         info->lcr_base += info->lcr_offset;
3672
3673         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3674         if (!info->sca_base) {
3675                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3676                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3677                 info->init_error = DiagStatus_CantAssignPciResources;
3678                 goto errout;
3679         }
3680         info->sca_base += info->sca_offset;
3681
3682         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3683         if (!info->statctrl_base) {
3684                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3685                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3686                 info->init_error = DiagStatus_CantAssignPciResources;
3687                 goto errout;
3688         }
3689         info->statctrl_base += info->statctrl_offset;
3690
3691         if ( !memory_test(info) ) {
3692                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3693                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3694                 info->init_error = DiagStatus_MemoryError;
3695                 goto errout;
3696         }
3697
3698         return 0;
3699
3700 errout:
3701         release_resources( info );
3702         return -ENODEV;
3703 }
3704
3705 void release_resources(SLMP_INFO *info)
3706 {
3707         if ( debug_level >= DEBUG_LEVEL_INFO )
3708                 printk( "%s(%d):%s release_resources() entry\n",
3709                         __FILE__,__LINE__,info->device_name );
3710
3711         if ( info->irq_requested ) {
3712                 free_irq(info->irq_level, info);
3713                 info->irq_requested = 0;
3714         }
3715
3716         if ( info->shared_mem_requested ) {
3717                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3718                 info->shared_mem_requested = 0;
3719         }
3720         if ( info->lcr_mem_requested ) {
3721                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3722                 info->lcr_mem_requested = 0;
3723         }
3724         if ( info->sca_base_requested ) {
3725                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3726                 info->sca_base_requested = 0;
3727         }
3728         if ( info->sca_statctrl_requested ) {
3729                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3730                 info->sca_statctrl_requested = 0;
3731         }
3732
3733         if (info->memory_base){
3734                 iounmap(info->memory_base);
3735                 info->memory_base = NULL;
3736         }
3737
3738         if (info->sca_base) {
3739                 iounmap(info->sca_base - info->sca_offset);
3740                 info->sca_base=NULL;
3741         }
3742
3743         if (info->statctrl_base) {
3744                 iounmap(info->statctrl_base - info->statctrl_offset);
3745                 info->statctrl_base=NULL;
3746         }
3747
3748         if (info->lcr_base){
3749                 iounmap(info->lcr_base - info->lcr_offset);
3750                 info->lcr_base = NULL;
3751         }
3752
3753         if ( debug_level >= DEBUG_LEVEL_INFO )
3754                 printk( "%s(%d):%s release_resources() exit\n",
3755                         __FILE__,__LINE__,info->device_name );
3756 }
3757
3758 /* Add the specified device instance data structure to the
3759  * global linked list of devices and increment the device count.
3760  */
3761 void add_device(SLMP_INFO *info)
3762 {
3763         info->next_device = NULL;
3764         info->line = synclinkmp_device_count;
3765         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3766
3767         if (info->line < MAX_DEVICES) {
3768                 if (maxframe[info->line])
3769                         info->max_frame_size = maxframe[info->line];
3770                 info->dosyncppp = dosyncppp[info->line];
3771         }
3772
3773         synclinkmp_device_count++;
3774
3775         if ( !synclinkmp_device_list )
3776                 synclinkmp_device_list = info;
3777         else {
3778                 SLMP_INFO *current_dev = synclinkmp_device_list;
3779                 while( current_dev->next_device )
3780                         current_dev = current_dev->next_device;
3781                 current_dev->next_device = info;
3782         }
3783
3784         if ( info->max_frame_size < 4096 )
3785                 info->max_frame_size = 4096;
3786         else if ( info->max_frame_size > 65535 )
3787                 info->max_frame_size = 65535;
3788
3789         printk( "SyncLink MultiPort %s: "
3790                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3791                 info->device_name,
3792                 info->phys_sca_base,
3793                 info->phys_memory_base,
3794                 info->phys_statctrl_base,
3795                 info->phys_lcr_base,
3796                 info->irq_level,
3797                 info->max_frame_size );
3798
3799 #ifdef CONFIG_HDLC
3800         hdlcdev_init(info);
3801 #endif
3802 }
3803
3804 /* Allocate and initialize a device instance structure
3805  *
3806  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3807  */
3808 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3809 {
3810         SLMP_INFO *info;
3811
3812         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3813                  GFP_KERNEL);
3814
3815         if (!info) {
3816                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3817                         __FILE__,__LINE__, adapter_num, port_num);
3818         } else {
3819                 memset(info, 0, sizeof(SLMP_INFO));
3820                 info->magic = MGSL_MAGIC;
3821                 INIT_WORK(&info->task, bh_handler, info);
3822                 info->max_frame_size = 4096;
3823                 info->close_delay = 5*HZ/10;
3824                 info->closing_wait = 30*HZ;
3825                 init_waitqueue_head(&info->open_wait);
3826                 init_waitqueue_head(&info->close_wait);
3827                 init_waitqueue_head(&info->status_event_wait_q);
3828                 init_waitqueue_head(&info->event_wait_q);
3829                 spin_lock_init(&info->netlock);
3830                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3831                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3832                 info->adapter_num = adapter_num;
3833                 info->port_num = port_num;
3834
3835                 /* Copy configuration info to device instance data */
3836                 info->irq_level = pdev->irq;
3837                 info->phys_lcr_base = pci_resource_start(pdev,0);
3838                 info->phys_sca_base = pci_resource_start(pdev,2);
3839                 info->phys_memory_base = pci_resource_start(pdev,3);
3840                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3841
3842                 /* Because veremap only works on page boundaries we must map
3843                  * a larger area than is actually implemented for the LCR
3844                  * memory range. We map a full page starting at the page boundary.
3845                  */
3846                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3847                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3848
3849                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3850                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3851
3852                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3853                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3854
3855                 info->bus_type = MGSL_BUS_TYPE_PCI;
3856                 info->irq_flags = SA_SHIRQ;
3857
3858                 init_timer(&info->tx_timer);
3859                 info->tx_timer.data = (unsigned long)info;
3860                 info->tx_timer.function = tx_timeout;
3861
3862                 init_timer(&info->status_timer);
3863                 info->status_timer.data = (unsigned long)info;
3864                 info->status_timer.function = status_timeout;
3865
3866                 /* Store the PCI9050 misc control register value because a flaw
3867                  * in the PCI9050 prevents LCR registers from being read if
3868                  * BIOS assigns an LCR base address with bit 7 set.
3869                  *
3870                  * Only the misc control register is accessed for which only
3871                  * write access is needed, so set an initial value and change
3872                  * bits to the device instance data as we write the value
3873                  * to the actual misc control register.
3874                  */
3875                 info->misc_ctrl_value = 0x087e4546;
3876
3877                 /* initial port state is unknown - if startup errors
3878                  * occur, init_error will be set to indicate the
3879                  * problem. Once the port is fully initialized,
3880                  * this value will be set to 0 to indicate the
3881                  * port is available.
3882                  */
3883                 info->init_error = -1;
3884         }
3885
3886         return info;
3887 }
3888
3889 void device_init(int adapter_num, struct pci_dev *pdev)
3890 {
3891         SLMP_INFO *port_array[SCA_MAX_PORTS];
3892         int port;
3893
3894         /* allocate device instances for up to SCA_MAX_PORTS devices */
3895         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3896                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3897                 if( port_array[port] == NULL ) {
3898                         for ( --port; port >= 0; --port )
3899                                 kfree(port_array[port]);
3900                         return;
3901                 }
3902         }
3903
3904         /* give copy of port_array to all ports and add to device list  */
3905         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3906                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3907                 add_device( port_array[port] );
3908                 spin_lock_init(&port_array[port]->lock);
3909         }
3910
3911         /* Allocate and claim adapter resources */
3912         if ( !claim_resources(port_array[0]) ) {
3913
3914                 alloc_dma_bufs(port_array[0]);
3915
3916                 /* copy resource information from first port to others */
3917                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3918                         port_array[port]->lock  = port_array[0]->lock;
3919                         port_array[port]->irq_level     = port_array[0]->irq_level;
3920                         port_array[port]->memory_base   = port_array[0]->memory_base;
3921                         port_array[port]->sca_base      = port_array[0]->sca_base;
3922                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3923                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3924                         alloc_dma_bufs(port_array[port]);
3925                 }
3926
3927                 if ( request_irq(port_array[0]->irq_level,
3928                                         synclinkmp_interrupt,
3929                                         port_array[0]->irq_flags,
3930                                         port_array[0]->device_name,
3931                                         port_array[0]) < 0 ) {
3932                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3933                                 __FILE__,__LINE__,
3934                                 port_array[0]->device_name,
3935                                 port_array[0]->irq_level );
3936                 }
3937                 else {
3938                         port_array[0]->irq_requested = 1;
3939                         adapter_test(port_array[0]);
3940                 }
3941         }
3942 }
3943
3944 static struct tty_operations ops = {
3945         .open = open,
3946         .close = close,
3947         .write = write,
3948         .put_char = put_char,
3949         .flush_chars = flush_chars,
3950         .write_room = write_room,
3951         .chars_in_buffer = chars_in_buffer,
3952         .flush_buffer = flush_buffer,
3953         .ioctl = ioctl,
3954         .throttle = throttle,
3955         .unthrottle = unthrottle,
3956         .send_xchar = send_xchar,
3957         .break_ctl = set_break,
3958         .wait_until_sent = wait_until_sent,
3959         .read_proc = read_proc,
3960         .set_termios = set_termios,
3961         .stop = tx_hold,
3962         .start = tx_release,
3963         .hangup = hangup,
3964         .tiocmget = tiocmget,
3965         .tiocmset = tiocmset,
3966 };
3967
3968 static void synclinkmp_cleanup(void)
3969 {
3970         int rc;
3971         SLMP_INFO *info;
3972         SLMP_INFO *tmp;
3973
3974         printk("Unloading %s %s\n", driver_name, driver_version);
3975
3976         if (serial_driver) {
3977                 if ((rc = tty_unregister_driver(serial_driver)))
3978                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3979                                __FILE__,__LINE__,rc);
3980                 put_tty_driver(serial_driver);
3981         }
3982
3983         /* reset devices */
3984         info = synclinkmp_device_list;
3985         while(info) {
3986                 reset_port(info);
3987                 info = info->next_device;
3988         }
3989
3990         /* release devices */
3991         info = synclinkmp_device_list;
3992         while(info) {
3993 #ifdef CONFIG_HDLC
3994                 hdlcdev_exit(info);
3995 #endif
3996                 free_dma_bufs(info);
3997                 free_tmp_rx_buf(info);
3998                 if ( info->port_num == 0 ) {
3999                         if (info->sca_base)
4000                                 write_reg(info, LPR, 1); /* set low power mode */
4001                         release_resources(info);
4002                 }
4003                 tmp = info;
4004                 info = info->next_device;
4005                 kfree(tmp);
4006         }
4007
4008         pci_unregister_driver(&synclinkmp_pci_driver);
4009 }
4010
4011 /* Driver initialization entry point.
4012  */
4013
4014 static int __init synclinkmp_init(void)
4015 {
4016         int rc;
4017
4018         if (break_on_load) {
4019                 synclinkmp_get_text_ptr();
4020                 BREAKPOINT();
4021         }
4022
4023         printk("%s %s\n", driver_name, driver_version);
4024
4025         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4026                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4027                 return rc;
4028         }
4029
4030         serial_driver = alloc_tty_driver(128);
4031         if (!serial_driver) {
4032                 rc = -ENOMEM;
4033                 goto error;
4034         }
4035
4036         /* Initialize the tty_driver structure */
4037
4038         serial_driver->owner = THIS_MODULE;
4039         serial_driver->driver_name = "synclinkmp";
4040         serial_driver->name = "ttySLM";
4041         serial_driver->major = ttymajor;
4042         serial_driver->minor_start = 64;
4043         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4044         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4045         serial_driver->init_termios = tty_std_termios;
4046         serial_driver->init_termios.c_cflag =
4047                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4048         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4049         tty_set_operations(serial_driver, &ops);
4050         if ((rc = tty_register_driver(serial_driver)) < 0) {
4051                 printk("%s(%d):Couldn't register serial driver\n",
4052                         __FILE__,__LINE__);
4053                 put_tty_driver(serial_driver);
4054                 serial_driver = NULL;
4055                 goto error;
4056         }
4057
4058         printk("%s %s, tty major#%d\n",
4059                 driver_name, driver_version,
4060                 serial_driver->major);
4061
4062         return 0;
4063
4064 error:
4065         synclinkmp_cleanup();
4066         return rc;
4067 }
4068
4069 static void __exit synclinkmp_exit(void)
4070 {
4071         synclinkmp_cleanup();
4072 }
4073
4074 module_init(synclinkmp_init);
4075 module_exit(synclinkmp_exit);
4076
4077 /* Set the port for internal loopback mode.
4078  * The TxCLK and RxCLK signals are generated from the BRG and
4079  * the TxD is looped back to the RxD internally.
4080  */
4081 void enable_loopback(SLMP_INFO *info, int enable)
4082 {
4083         if (enable) {
4084                 /* MD2 (Mode Register 2)
4085                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4086                  */
4087                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4088
4089                 /* degate external TxC clock source */
4090                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4091                 write_control_reg(info);
4092
4093                 /* RXS/TXS (Rx/Tx clock source)
4094                  * 07      Reserved, must be 0
4095                  * 06..04  Clock Source, 100=BRG
4096                  * 03..00  Clock Divisor, 0000=1
4097                  */
4098                 write_reg(info, RXS, 0x40);
4099                 write_reg(info, TXS, 0x40);
4100
4101         } else {
4102                 /* MD2 (Mode Register 2)
4103                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4104                  */
4105                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4106
4107                 /* RXS/TXS (Rx/Tx clock source)
4108                  * 07      Reserved, must be 0
4109                  * 06..04  Clock Source, 000=RxC/TxC Pin
4110                  * 03..00  Clock Divisor, 0000=1
4111                  */
4112                 write_reg(info, RXS, 0x00);
4113                 write_reg(info, TXS, 0x00);
4114         }
4115
4116         /* set LinkSpeed if available, otherwise default to 2Mbps */
4117         if (info->params.clock_speed)
4118                 set_rate(info, info->params.clock_speed);
4119         else
4120                 set_rate(info, 3686400);
4121 }
4122
4123 /* Set the baud rate register to the desired speed
4124  *
4125  *      data_rate       data rate of clock in bits per second
4126  *                      A data rate of 0 disables the AUX clock.
4127  */
4128 void set_rate( SLMP_INFO *info, u32 data_rate )
4129 {
4130         u32 TMCValue;
4131         unsigned char BRValue;
4132         u32 Divisor=0;
4133
4134         /* fBRG = fCLK/(TMC * 2^BR)
4135          */
4136         if (data_rate != 0) {
4137                 Divisor = 14745600/data_rate;
4138                 if (!Divisor)
4139                         Divisor = 1;
4140
4141                 TMCValue = Divisor;
4142
4143                 BRValue = 0;
4144                 if (TMCValue != 1 && TMCValue != 2) {
4145                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4146                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4147                          * 50/50 duty cycle.
4148                          */
4149                         BRValue = 1;
4150                         TMCValue >>= 1;
4151                 }
4152
4153                 /* while TMCValue is too big for TMC register, divide
4154                  * by 2 and increment BR exponent.
4155                  */
4156                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4157                         TMCValue >>= 1;
4158
4159                 write_reg(info, TXS,
4160                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4161                 write_reg(info, RXS,
4162                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4163                 write_reg(info, TMC, (unsigned char)TMCValue);
4164         }
4165         else {
4166                 write_reg(info, TXS,0);
4167                 write_reg(info, RXS,0);
4168                 write_reg(info, TMC, 0);
4169         }
4170 }
4171
4172 /* Disable receiver
4173  */
4174 void rx_stop(SLMP_INFO *info)
4175 {
4176         if (debug_level >= DEBUG_LEVEL_ISR)
4177                 printk("%s(%d):%s rx_stop()\n",
4178                          __FILE__,__LINE__, info->device_name );
4179
4180         write_reg(info, CMD, RXRESET);
4181
4182         info->ie0_value &= ~RXRDYE;
4183         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4184
4185         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4186         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4187         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4188
4189         info->rx_enabled = 0;
4190         info->rx_overflow = 0;
4191 }
4192
4193 /* enable the receiver
4194  */
4195 void rx_start(SLMP_INFO *info)
4196 {
4197         int i;
4198
4199         if (debug_level >= DEBUG_LEVEL_ISR)
4200                 printk("%s(%d):%s rx_start()\n",
4201                          __FILE__,__LINE__, info->device_name );
4202
4203         write_reg(info, CMD, RXRESET);
4204
4205         if ( info->params.mode == MGSL_MODE_HDLC ) {
4206                 /* HDLC, disabe IRQ on rxdata */
4207                 info->ie0_value &= ~RXRDYE;
4208                 write_reg(info, IE0, info->ie0_value);
4209
4210                 /* Reset all Rx DMA buffers and program rx dma */
4211                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4212                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4213
4214                 for (i = 0; i < info->rx_buf_count; i++) {
4215                         info->rx_buf_list[i].status = 0xff;
4216
4217                         // throttle to 4 shared memory writes at a time to prevent
4218                         // hogging local bus (keep latency time for DMA requests low).
4219                         if (!(i % 4))
4220                                 read_status_reg(info);
4221                 }
4222                 info->current_rx_buf = 0;
4223
4224                 /* set current/1st descriptor address */
4225                 write_reg16(info, RXDMA + CDA,
4226                         info->rx_buf_list_ex[0].phys_entry);
4227
4228                 /* set new last rx descriptor address */
4229                 write_reg16(info, RXDMA + EDA,
4230                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4231
4232                 /* set buffer length (shared by all rx dma data buffers) */
4233                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4234
4235                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4236                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4237         } else {
4238                 /* async, enable IRQ on rxdata */
4239                 info->ie0_value |= RXRDYE;
4240                 write_reg(info, IE0, info->ie0_value);
4241         }
4242
4243         write_reg(info, CMD, RXENABLE);
4244
4245         info->rx_overflow = FALSE;
4246         info->rx_enabled = 1;
4247 }
4248
4249 /* Enable the transmitter and send a transmit frame if
4250  * one is loaded in the DMA buffers.
4251  */
4252 void tx_start(SLMP_INFO *info)
4253 {
4254         if (debug_level >= DEBUG_LEVEL_ISR)
4255                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4256                          __FILE__,__LINE__, info->device_name,info->tx_count );
4257
4258         if (!info->tx_enabled ) {
4259                 write_reg(info, CMD, TXRESET);
4260                 write_reg(info, CMD, TXENABLE);
4261                 info->tx_enabled = TRUE;
4262         }
4263
4264         if ( info->tx_count ) {
4265
4266                 /* If auto RTS enabled and RTS is inactive, then assert */
4267                 /* RTS and set a flag indicating that the driver should */
4268                 /* negate RTS when the transmission completes. */
4269
4270                 info->drop_rts_on_tx_done = 0;
4271
4272                 if (info->params.mode != MGSL_MODE_ASYNC) {
4273
4274                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4275                                 get_signals( info );
4276                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4277                                         info->serial_signals |= SerialSignal_RTS;
4278                                         set_signals( info );
4279                                         info->drop_rts_on_tx_done = 1;
4280                                 }
4281                         }
4282
4283                         write_reg16(info, TRC0,
4284                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4285
4286                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4287                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4288
4289                         /* set TX CDA (current descriptor address) */
4290                         write_reg16(info, TXDMA + CDA,
4291                                 info->tx_buf_list_ex[0].phys_entry);
4292
4293                         /* set TX EDA (last descriptor address) */
4294                         write_reg16(info, TXDMA + EDA,
4295                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4296
4297                         /* enable underrun IRQ */
4298                         info->ie1_value &= ~IDLE;
4299                         info->ie1_value |= UDRN;
4300                         write_reg(info, IE1, info->ie1_value);
4301                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4302
4303                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4304                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4305
4306                         info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4307                         add_timer(&info->tx_timer);
4308                 }
4309                 else {
4310                         tx_load_fifo(info);
4311                         /* async, enable IRQ on txdata */
4312                         info->ie0_value |= TXRDYE;
4313                         write_reg(info, IE0, info->ie0_value);
4314                 }
4315
4316                 info->tx_active = 1;
4317         }
4318 }
4319
4320 /* stop the transmitter and DMA
4321  */
4322 void tx_stop( SLMP_INFO *info )
4323 {
4324         if (debug_level >= DEBUG_LEVEL_ISR)
4325                 printk("%s(%d):%s tx_stop()\n",
4326                          __FILE__,__LINE__, info->device_name );
4327
4328         del_timer(&info->tx_timer);
4329
4330         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4331         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4332
4333         write_reg(info, CMD, TXRESET);
4334
4335         info->ie1_value &= ~(UDRN + IDLE);
4336         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4337         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4338
4339         info->ie0_value &= ~TXRDYE;
4340         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4341
4342         info->tx_enabled = 0;
4343         info->tx_active  = 0;
4344 }
4345
4346 /* Fill the transmit FIFO until the FIFO is full or
4347  * there is no more data to load.
4348  */
4349 void tx_load_fifo(SLMP_INFO *info)
4350 {
4351         u8 TwoBytes[2];
4352
4353         /* do nothing is now tx data available and no XON/XOFF pending */
4354
4355         if ( !info->tx_count && !info->x_char )
4356                 return;
4357
4358         /* load the Transmit FIFO until FIFOs full or all data sent */
4359
4360         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4361
4362                 /* there is more space in the transmit FIFO and */
4363                 /* there is more data in transmit buffer */
4364
4365                 if ( (info->tx_count > 1) && !info->x_char ) {
4366                         /* write 16-bits */
4367                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4368                         if (info->tx_get >= info->max_frame_size)
4369                                 info->tx_get -= info->max_frame_size;
4370                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4371                         if (info->tx_get >= info->max_frame_size)
4372                                 info->tx_get -= info->max_frame_size;
4373
4374                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4375
4376                         info->tx_count -= 2;
4377                         info->icount.tx += 2;
4378                 } else {
4379                         /* only 1 byte left to transmit or 1 FIFO slot left */
4380
4381                         if (info->x_char) {
4382                                 /* transmit pending high priority char */
4383                                 write_reg(info, TRB, info->x_char);
4384                                 info->x_char = 0;
4385                         } else {
4386                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4387                                 if (info->tx_get >= info->max_frame_size)
4388                                         info->tx_get -= info->max_frame_size;
4389                                 info->tx_count--;
4390                         }
4391                         info->icount.tx++;
4392                 }
4393         }
4394 }
4395
4396 /* Reset a port to a known state
4397  */
4398 void reset_port(SLMP_INFO *info)
4399 {
4400         if (info->sca_base) {
4401
4402                 tx_stop(info);
4403                 rx_stop(info);
4404
4405                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4406                 set_signals(info);
4407
4408                 /* disable all port interrupts */
4409                 info->ie0_value = 0;
4410                 info->ie1_value = 0;
4411                 info->ie2_value = 0;
4412                 write_reg(info, IE0, info->ie0_value);
4413                 write_reg(info, IE1, info->ie1_value);
4414                 write_reg(info, IE2, info->ie2_value);
4415
4416                 write_reg(info, CMD, CHRESET);
4417         }
4418 }
4419
4420 /* Reset all the ports to a known state.
4421  */
4422 void reset_adapter(SLMP_INFO *info)
4423 {
4424         int i;
4425
4426         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4427                 if (info->port_array[i])
4428                         reset_port(info->port_array[i]);
4429         }
4430 }
4431
4432 /* Program port for asynchronous communications.
4433  */
4434 void async_mode(SLMP_INFO *info)
4435 {
4436
4437         unsigned char RegValue;
4438
4439         tx_stop(info);
4440         rx_stop(info);
4441
4442         /* MD0, Mode Register 0
4443          *
4444          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4445          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4446          * 03      Reserved, must be 0
4447          * 02      CRCCC, CRC Calculation, 0=disabled
4448          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4449          *
4450          * 0000 0000
4451          */
4452         RegValue = 0x00;
4453         if (info->params.stop_bits != 1)
4454                 RegValue |= BIT1;
4455         write_reg(info, MD0, RegValue);
4456
4457         /* MD1, Mode Register 1
4458          *
4459          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4460          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4461          * 03..02  RXCHR<1..0>, rx char size
4462          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4463          *
4464          * 0100 0000
4465          */
4466         RegValue = 0x40;
4467         switch (info->params.data_bits) {
4468         case 7: RegValue |= BIT4 + BIT2; break;
4469         case 6: RegValue |= BIT5 + BIT3; break;
4470         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4471         }
4472         if (info->params.parity != ASYNC_PARITY_NONE) {
4473                 RegValue |= BIT1;
4474                 if (info->params.parity == ASYNC_PARITY_ODD)
4475                         RegValue |= BIT0;
4476         }
4477         write_reg(info, MD1, RegValue);
4478
4479         /* MD2, Mode Register 2
4480          *
4481          * 07..02  Reserved, must be 0
4482          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4483          *
4484          * 0000 0000
4485          */
4486         RegValue = 0x00;
4487         if (info->params.loopback)
4488                 RegValue |= (BIT1 + BIT0);
4489         write_reg(info, MD2, RegValue);
4490
4491         /* RXS, Receive clock source
4492          *
4493          * 07      Reserved, must be 0
4494          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4495          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4496          */
4497         RegValue=BIT6;
4498         write_reg(info, RXS, RegValue);
4499
4500         /* TXS, Transmit clock source
4501          *
4502          * 07      Reserved, must be 0
4503          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4504          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4505          */
4506         RegValue=BIT6;
4507         write_reg(info, TXS, RegValue);
4508
4509         /* Control Register
4510          *
4511          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4512          */
4513         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4514         write_control_reg(info);
4515
4516         tx_set_idle(info);
4517
4518         /* RRC Receive Ready Control 0
4519          *
4520          * 07..05  Reserved, must be 0
4521          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4522          */
4523         write_reg(info, RRC, 0x00);
4524
4525         /* TRC0 Transmit Ready Control 0
4526          *
4527          * 07..05  Reserved, must be 0
4528          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4529          */
4530         write_reg(info, TRC0, 0x10);
4531
4532         /* TRC1 Transmit Ready Control 1
4533          *
4534          * 07..05  Reserved, must be 0
4535          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4536          */
4537         write_reg(info, TRC1, 0x1e);
4538
4539         /* CTL, MSCI control register
4540          *
4541          * 07..06  Reserved, set to 0
4542          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4543          * 04      IDLC, idle control, 0=mark 1=idle register
4544          * 03      BRK, break, 0=off 1 =on (async)
4545          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4546          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4547          * 00      RTS, RTS output control, 0=active 1=inactive
4548          *
4549          * 0001 0001
4550          */
4551         RegValue = 0x10;
4552         if (!(info->serial_signals & SerialSignal_RTS))
4553                 RegValue |= 0x01;
4554         write_reg(info, CTL, RegValue);
4555
4556         /* enable status interrupts */
4557         info->ie0_value |= TXINTE + RXINTE;
4558         write_reg(info, IE0, info->ie0_value);
4559
4560         /* enable break detect interrupt */
4561         info->ie1_value = BRKD;
4562         write_reg(info, IE1, info->ie1_value);
4563
4564         /* enable rx overrun interrupt */
4565         info->ie2_value = OVRN;
4566         write_reg(info, IE2, info->ie2_value);
4567
4568         set_rate( info, info->params.data_rate * 16 );
4569 }
4570
4571 /* Program the SCA for HDLC communications.
4572  */
4573 void hdlc_mode(SLMP_INFO *info)
4574 {
4575         unsigned char RegValue;
4576         u32 DpllDivisor;
4577
4578         // Can't use DPLL because SCA outputs recovered clock on RxC when
4579         // DPLL mode selected. This causes output contention with RxC receiver.
4580         // Use of DPLL would require external hardware to disable RxC receiver
4581         // when DPLL mode selected.
4582         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4583
4584         /* disable DMA interrupts */
4585         write_reg(info, TXDMA + DIR, 0);
4586         write_reg(info, RXDMA + DIR, 0);
4587
4588         /* MD0, Mode Register 0
4589          *
4590          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4591          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4592          * 03      Reserved, must be 0
4593          * 02      CRCCC, CRC Calculation, 1=enabled
4594          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4595          * 00      CRC0, CRC initial value, 1 = all 1s
4596          *
4597          * 1000 0001
4598          */
4599         RegValue = 0x81;
4600         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4601                 RegValue |= BIT4;
4602         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4603                 RegValue |= BIT4;
4604         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4605                 RegValue |= BIT2 + BIT1;
4606         write_reg(info, MD0, RegValue);
4607
4608         /* MD1, Mode Register 1
4609          *
4610          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4611          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4612          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4613          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4614          *
4615          * 0000 0000
4616          */
4617         RegValue = 0x00;
4618         write_reg(info, MD1, RegValue);
4619
4620         /* MD2, Mode Register 2
4621          *
4622          * 07      NRZFM, 0=NRZ, 1=FM
4623          * 06..05  CODE<1..0> Encoding, 00=NRZ
4624          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4625          * 02      Reserved, must be 0
4626          * 01..00  CNCT<1..0> Channel connection, 0=normal
4627          *
4628          * 0000 0000
4629          */
4630         RegValue = 0x00;
4631         switch(info->params.encoding) {
4632         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4633         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4634         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4635         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4636 #if 0
4637         case HDLC_ENCODING_NRZB:                                        /* not supported */
4638         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4639         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4640 #endif
4641         }
4642         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4643                 DpllDivisor = 16;
4644                 RegValue |= BIT3;
4645         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4646                 DpllDivisor = 8;
4647         } else {
4648                 DpllDivisor = 32;
4649                 RegValue |= BIT4;
4650         }
4651         write_reg(info, MD2, RegValue);
4652
4653
4654         /* RXS, Receive clock source
4655          *
4656          * 07      Reserved, must be 0
4657          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4658          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4659          */
4660         RegValue=0;
4661         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4662                 RegValue |= BIT6;
4663         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4664                 RegValue |= BIT6 + BIT5;
4665         write_reg(info, RXS, RegValue);
4666
4667         /* TXS, Transmit clock source
4668          *
4669          * 07      Reserved, must be 0
4670          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4671          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4672          */
4673         RegValue=0;
4674         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4675                 RegValue |= BIT6;
4676         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4677                 RegValue |= BIT6 + BIT5;
4678         write_reg(info, TXS, RegValue);
4679
4680         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4681                 set_rate(info, info->params.clock_speed * DpllDivisor);
4682         else
4683                 set_rate(info, info->params.clock_speed);
4684
4685         /* GPDATA (General Purpose I/O Data Register)
4686          *
4687          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4688          */
4689         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4690                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4691         else
4692                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4693         write_control_reg(info);
4694
4695         /* RRC Receive Ready Control 0
4696          *
4697          * 07..05  Reserved, must be 0
4698          * 04..00  RRC<4..0> Rx FIFO trigger active
4699          */
4700         write_reg(info, RRC, rx_active_fifo_level);
4701
4702         /* TRC0 Transmit Ready Control 0
4703          *
4704          * 07..05  Reserved, must be 0
4705          * 04..00  TRC<4..0> Tx FIFO trigger active
4706          */
4707         write_reg(info, TRC0, tx_active_fifo_level);
4708
4709         /* TRC1 Transmit Ready Control 1
4710          *
4711          * 07..05  Reserved, must be 0
4712          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4713          */
4714         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4715
4716         /* DMR, DMA Mode Register
4717          *
4718          * 07..05  Reserved, must be 0
4719          * 04      TMOD, Transfer Mode: 1=chained-block
4720          * 03      Reserved, must be 0
4721          * 02      NF, Number of Frames: 1=multi-frame
4722          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4723          * 00      Reserved, must be 0
4724          *
4725          * 0001 0100
4726          */
4727         write_reg(info, TXDMA + DMR, 0x14);
4728         write_reg(info, RXDMA + DMR, 0x14);
4729
4730         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4731         write_reg(info, RXDMA + CPB,
4732                 (unsigned char)(info->buffer_list_phys >> 16));
4733
4734         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4735         write_reg(info, TXDMA + CPB,
4736                 (unsigned char)(info->buffer_list_phys >> 16));
4737
4738         /* enable status interrupts. other code enables/disables
4739          * the individual sources for these two interrupt classes.
4740          */
4741         info->ie0_value |= TXINTE + RXINTE;
4742         write_reg(info, IE0, info->ie0_value);
4743
4744         /* CTL, MSCI control register
4745          *
4746          * 07..06  Reserved, set to 0
4747          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4748          * 04      IDLC, idle control, 0=mark 1=idle register
4749          * 03      BRK, break, 0=off 1 =on (async)
4750          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4751          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4752          * 00      RTS, RTS output control, 0=active 1=inactive
4753          *
4754          * 0001 0001
4755          */
4756         RegValue = 0x10;
4757         if (!(info->serial_signals & SerialSignal_RTS))
4758                 RegValue |= 0x01;
4759         write_reg(info, CTL, RegValue);
4760
4761         /* preamble not supported ! */
4762
4763         tx_set_idle(info);
4764         tx_stop(info);
4765         rx_stop(info);
4766
4767         set_rate(info, info->params.clock_speed);
4768
4769         if (info->params.loopback)
4770                 enable_loopback(info,1);
4771 }
4772
4773 /* Set the transmit HDLC idle mode
4774  */
4775 void tx_set_idle(SLMP_INFO *info)
4776 {
4777         unsigned char RegValue = 0xff;
4778
4779         /* Map API idle mode to SCA register bits */
4780         switch(info->idle_mode) {
4781         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4782         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4783         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4784         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4785         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4786         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4787         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4788         }
4789
4790         write_reg(info, IDL, RegValue);
4791 }
4792
4793 /* Query the adapter for the state of the V24 status (input) signals.
4794  */
4795 void get_signals(SLMP_INFO *info)
4796 {
4797         u16 status = read_reg(info, SR3);
4798         u16 gpstatus = read_status_reg(info);
4799         u16 testbit;
4800
4801         /* clear all serial signals except DTR and RTS */
4802         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4803
4804         /* set serial signal bits to reflect MISR */
4805
4806         if (!(status & BIT3))
4807                 info->serial_signals |= SerialSignal_CTS;
4808
4809         if ( !(status & BIT2))
4810                 info->serial_signals |= SerialSignal_DCD;
4811
4812         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4813         if (!(gpstatus & testbit))
4814                 info->serial_signals |= SerialSignal_RI;
4815
4816         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4817         if (!(gpstatus & testbit))
4818                 info->serial_signals |= SerialSignal_DSR;
4819 }
4820
4821 /* Set the state of DTR and RTS based on contents of
4822  * serial_signals member of device context.
4823  */
4824 void set_signals(SLMP_INFO *info)
4825 {
4826         unsigned char RegValue;
4827         u16 EnableBit;
4828
4829         RegValue = read_reg(info, CTL);
4830         if (info->serial_signals & SerialSignal_RTS)
4831                 RegValue &= ~BIT0;
4832         else
4833                 RegValue |= BIT0;
4834         write_reg(info, CTL, RegValue);
4835
4836         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4837         EnableBit = BIT1 << (info->port_num*2);
4838         if (info->serial_signals & SerialSignal_DTR)
4839                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4840         else
4841                 info->port_array[0]->ctrlreg_value |= EnableBit;
4842         write_control_reg(info);
4843 }
4844
4845 /*******************/
4846 /* DMA Buffer Code */
4847 /*******************/
4848
4849 /* Set the count for all receive buffers to SCABUFSIZE
4850  * and set the current buffer to the first buffer. This effectively
4851  * makes all buffers free and discards any data in buffers.
4852  */
4853 void rx_reset_buffers(SLMP_INFO *info)
4854 {
4855         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4856 }
4857
4858 /* Free the buffers used by a received frame
4859  *
4860  * info   pointer to device instance data
4861  * first  index of 1st receive buffer of frame
4862  * last   index of last receive buffer of frame
4863  */
4864 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4865 {
4866         int done = 0;
4867
4868         while(!done) {
4869                 /* reset current buffer for reuse */
4870                 info->rx_buf_list[first].status = 0xff;
4871
4872                 if (first == last) {
4873                         done = 1;
4874                         /* set new last rx descriptor address */
4875                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4876                 }
4877
4878                 first++;
4879                 if (first == info->rx_buf_count)
4880                         first = 0;
4881         }
4882
4883         /* set current buffer to next buffer after last buffer of frame */
4884         info->current_rx_buf = first;
4885 }
4886
4887 /* Return a received frame from the receive DMA buffers.
4888  * Only frames received without errors are returned.
4889  *
4890  * Return Value:        1 if frame returned, otherwise 0
4891  */
4892 int rx_get_frame(SLMP_INFO *info)
4893 {
4894         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4895         unsigned short status;
4896         unsigned int framesize = 0;
4897         int ReturnCode = 0;
4898         unsigned long flags;
4899         struct tty_struct *tty = info->tty;
4900         unsigned char addr_field = 0xff;
4901         SCADESC *desc;
4902         SCADESC_EX *desc_ex;
4903
4904 CheckAgain:
4905         /* assume no frame returned, set zero length */
4906         framesize = 0;
4907         addr_field = 0xff;
4908
4909         /*
4910          * current_rx_buf points to the 1st buffer of the next available
4911          * receive frame. To find the last buffer of the frame look for
4912          * a non-zero status field in the buffer entries. (The status
4913          * field is set by the 16C32 after completing a receive frame.
4914          */
4915         StartIndex = EndIndex = info->current_rx_buf;
4916
4917         for ( ;; ) {
4918                 desc = &info->rx_buf_list[EndIndex];
4919                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4920
4921                 if (desc->status == 0xff)
4922                         goto Cleanup;   /* current desc still in use, no frames available */
4923
4924                 if (framesize == 0 && info->params.addr_filter != 0xff)
4925                         addr_field = desc_ex->virt_addr[0];
4926
4927                 framesize += desc->length;
4928
4929                 /* Status != 0 means last buffer of frame */
4930                 if (desc->status)
4931                         break;
4932
4933                 EndIndex++;
4934                 if (EndIndex == info->rx_buf_count)
4935                         EndIndex = 0;
4936
4937                 if (EndIndex == info->current_rx_buf) {
4938                         /* all buffers have been 'used' but none mark      */
4939                         /* the end of a frame. Reset buffers and receiver. */
4940                         if ( info->rx_enabled ){
4941                                 spin_lock_irqsave(&info->lock,flags);
4942                                 rx_start(info);
4943                                 spin_unlock_irqrestore(&info->lock,flags);
4944                         }
4945                         goto Cleanup;
4946                 }
4947
4948         }
4949
4950         /* check status of receive frame */
4951
4952         /* frame status is byte stored after frame data
4953          *
4954          * 7 EOM (end of msg), 1 = last buffer of frame
4955          * 6 Short Frame, 1 = short frame
4956          * 5 Abort, 1 = frame aborted
4957          * 4 Residue, 1 = last byte is partial
4958          * 3 Overrun, 1 = overrun occurred during frame reception
4959          * 2 CRC,     1 = CRC error detected
4960          *
4961          */
4962         status = desc->status;
4963
4964         /* ignore CRC bit if not using CRC (bit is undefined) */
4965         /* Note:CRC is not save to data buffer */
4966         if (info->params.crc_type == HDLC_CRC_NONE)
4967                 status &= ~BIT2;
4968
4969         if (framesize == 0 ||
4970                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4971                 /* discard 0 byte frames, this seems to occur sometime
4972                  * when remote is idling flags.
4973                  */
4974                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4975                 goto CheckAgain;
4976         }
4977
4978         if (framesize < 2)
4979                 status |= BIT6;
4980
4981         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4982                 /* received frame has errors,
4983                  * update counts and mark frame size as 0
4984                  */
4985                 if (status & BIT6)
4986                         info->icount.rxshort++;
4987                 else if (status & BIT5)
4988                         info->icount.rxabort++;
4989                 else if (status & BIT3)
4990                         info->icount.rxover++;
4991                 else
4992                         info->icount.rxcrc++;
4993
4994                 framesize = 0;
4995 #ifdef CONFIG_HDLC
4996                 {
4997                         struct net_device_stats *stats = hdlc_stats(info->netdev);
4998                         stats->rx_errors++;
4999                         stats->rx_frame_errors++;
5000                 }
5001 #endif
5002         }
5003
5004         if ( debug_level >= DEBUG_LEVEL_BH )
5005                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5006                         __FILE__,__LINE__,info->device_name,status,framesize);
5007
5008         if ( debug_level >= DEBUG_LEVEL_DATA )
5009                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5010                         min_t(int, framesize,SCABUFSIZE),0);
5011
5012         if (framesize) {
5013                 if (framesize > info->max_frame_size)
5014                         info->icount.rxlong++;
5015                 else {
5016                         /* copy dma buffer(s) to contiguous intermediate buffer */
5017                         int copy_count = framesize;
5018                         int index = StartIndex;
5019                         unsigned char *ptmp = info->tmp_rx_buf;
5020                         info->tmp_rx_buf_count = framesize;
5021
5022                         info->icount.rxok++;
5023
5024                         while(copy_count) {
5025                                 int partial_count = min(copy_count,SCABUFSIZE);
5026                                 memcpy( ptmp,
5027                                         info->rx_buf_list_ex[index].virt_addr,
5028                                         partial_count );
5029                                 ptmp += partial_count;
5030                                 copy_count -= partial_count;
5031
5032                                 if ( ++index == info->rx_buf_count )
5033                                         index = 0;
5034                         }
5035
5036 #ifdef CONFIG_HDLC
5037                         if (info->netcount)
5038                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5039                         else
5040 #endif
5041                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5042                                                   info->flag_buf, framesize);
5043                 }
5044         }
5045         /* Free the buffers used by this frame. */
5046         rx_free_frame_buffers( info, StartIndex, EndIndex );
5047
5048         ReturnCode = 1;
5049
5050 Cleanup:
5051         if ( info->rx_enabled && info->rx_overflow ) {
5052                 /* Receiver is enabled, but needs to restarted due to
5053                  * rx buffer overflow. If buffers are empty, restart receiver.
5054                  */
5055                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5056                         spin_lock_irqsave(&info->lock,flags);
5057                         rx_start(info);
5058                         spin_unlock_irqrestore(&info->lock,flags);
5059                 }
5060         }
5061
5062         return ReturnCode;
5063 }
5064
5065 /* load the transmit DMA buffer with data
5066  */
5067 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5068 {
5069         unsigned short copy_count;
5070         unsigned int i = 0;
5071         SCADESC *desc;
5072         SCADESC_EX *desc_ex;
5073
5074         if ( debug_level >= DEBUG_LEVEL_DATA )
5075                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5076
5077         /* Copy source buffer to one or more DMA buffers, starting with
5078          * the first transmit dma buffer.
5079          */
5080         for(i=0;;)
5081         {
5082                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5083
5084                 desc = &info->tx_buf_list[i];
5085                 desc_ex = &info->tx_buf_list_ex[i];
5086
5087                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5088
5089                 desc->length = copy_count;
5090                 desc->status = 0;
5091
5092                 buf += copy_count;
5093                 count -= copy_count;
5094
5095                 if (!count)
5096                         break;
5097
5098                 i++;
5099                 if (i >= info->tx_buf_count)
5100                         i = 0;
5101         }
5102
5103         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5104         info->last_tx_buf = ++i;
5105 }
5106
5107 int register_test(SLMP_INFO *info)
5108 {
5109         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5110         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
5111         unsigned int i;
5112         int rc = TRUE;
5113         unsigned long flags;
5114
5115         spin_lock_irqsave(&info->lock,flags);
5116         reset_port(info);
5117
5118         /* assume failure */
5119         info->init_error = DiagStatus_AddressFailure;
5120
5121         /* Write bit patterns to various registers but do it out of */
5122         /* sync, then read back and verify values. */
5123
5124         for (i = 0 ; i < count ; i++) {
5125                 write_reg(info, TMC, testval[i]);
5126                 write_reg(info, IDL, testval[(i+1)%count]);
5127                 write_reg(info, SA0, testval[(i+2)%count]);
5128                 write_reg(info, SA1, testval[(i+3)%count]);
5129
5130                 if ( (read_reg(info, TMC) != testval[i]) ||
5131                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5132                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5133                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5134                 {
5135                         rc = FALSE;
5136                         break;
5137                 }
5138         }
5139
5140         reset_port(info);
5141         spin_unlock_irqrestore(&info->lock,flags);
5142
5143         return rc;
5144 }
5145
5146 int irq_test(SLMP_INFO *info)
5147 {
5148         unsigned long timeout;
5149         unsigned long flags;
5150
5151         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5152
5153         spin_lock_irqsave(&info->lock,flags);
5154         reset_port(info);
5155
5156         /* assume failure */
5157         info->init_error = DiagStatus_IrqFailure;
5158         info->irq_occurred = FALSE;
5159
5160         /* setup timer0 on SCA0 to interrupt */
5161
5162         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5163         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5164
5165         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5166         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5167
5168
5169         /* TMCS, Timer Control/Status Register
5170          *
5171          * 07      CMF, Compare match flag (read only) 1=match
5172          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5173          * 05      Reserved, must be 0
5174          * 04      TME, Timer Enable
5175          * 03..00  Reserved, must be 0
5176          *
5177          * 0101 0000
5178          */
5179         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5180
5181         spin_unlock_irqrestore(&info->lock,flags);
5182
5183         timeout=100;
5184         while( timeout-- && !info->irq_occurred ) {
5185                 msleep_interruptible(10);
5186         }
5187
5188         spin_lock_irqsave(&info->lock,flags);
5189         reset_port(info);
5190         spin_unlock_irqrestore(&info->lock,flags);
5191
5192         return info->irq_occurred;
5193 }
5194
5195 /* initialize individual SCA device (2 ports)
5196  */
5197 static int sca_init(SLMP_INFO *info)
5198 {
5199         /* set wait controller to single mem partition (low), no wait states */
5200         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5201         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5202         write_reg(info, WCRL, 0);       /* wait controller low range */
5203         write_reg(info, WCRM, 0);       /* wait controller mid range */
5204         write_reg(info, WCRH, 0);       /* wait controller high range */
5205
5206         /* DPCR, DMA Priority Control
5207          *
5208          * 07..05  Not used, must be 0
5209          * 04      BRC, bus release condition: 0=all transfers complete
5210          * 03      CCC, channel change condition: 0=every cycle
5211          * 02..00  PR<2..0>, priority 100=round robin
5212          *
5213          * 00000100 = 0x04
5214          */
5215         write_reg(info, DPCR, dma_priority);
5216
5217         /* DMA Master Enable, BIT7: 1=enable all channels */
5218         write_reg(info, DMER, 0x80);
5219
5220         /* enable all interrupt classes */
5221         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5222         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5223         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5224
5225         /* ITCR, interrupt control register
5226          * 07      IPC, interrupt priority, 0=MSCI->DMA
5227          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5228          * 04      VOS, Vector Output, 0=unmodified vector
5229          * 03..00  Reserved, must be 0
5230          */
5231         write_reg(info, ITCR, 0);
5232
5233         return TRUE;
5234 }
5235
5236 /* initialize adapter hardware
5237  */
5238 int init_adapter(SLMP_INFO *info)
5239 {
5240         int i;
5241
5242         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5243         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5244         u32 readval;
5245
5246         info->misc_ctrl_value |= BIT30;
5247         *MiscCtrl = info->misc_ctrl_value;
5248
5249         /*
5250          * Force at least 170ns delay before clearing
5251          * reset bit. Each read from LCR takes at least
5252          * 30ns so 10 times for 300ns to be safe.
5253          */
5254         for(i=0;i<10;i++)
5255                 readval = *MiscCtrl;
5256
5257         info->misc_ctrl_value &= ~BIT30;
5258         *MiscCtrl = info->misc_ctrl_value;
5259
5260         /* init control reg (all DTRs off, all clksel=input) */
5261         info->ctrlreg_value = 0xaa;
5262         write_control_reg(info);
5263
5264         {
5265                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5266                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5267
5268                 switch(read_ahead_count)
5269                 {
5270                 case 16:
5271                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5272                         break;
5273                 case 8:
5274                         lcr1_brdr_value |= BIT5 + BIT4;
5275                         break;
5276                 case 4:
5277                         lcr1_brdr_value |= BIT5 + BIT3;
5278                         break;
5279                 case 0:
5280                         lcr1_brdr_value |= BIT5;
5281                         break;
5282                 }
5283
5284                 *LCR1BRDR = lcr1_brdr_value;
5285                 *MiscCtrl = misc_ctrl_value;
5286         }
5287
5288         sca_init(info->port_array[0]);
5289         sca_init(info->port_array[2]);
5290
5291         return TRUE;
5292 }
5293
5294 /* Loopback an HDLC frame to test the hardware
5295  * interrupt and DMA functions.
5296  */
5297 int loopback_test(SLMP_INFO *info)
5298 {
5299 #define TESTFRAMESIZE 20
5300
5301         unsigned long timeout;
5302         u16 count = TESTFRAMESIZE;
5303         unsigned char buf[TESTFRAMESIZE];
5304         int rc = FALSE;
5305         unsigned long flags;
5306
5307         struct tty_struct *oldtty = info->tty;
5308         u32 speed = info->params.clock_speed;
5309
5310         info->params.clock_speed = 3686400;
5311         info->tty = NULL;
5312
5313         /* assume failure */
5314         info->init_error = DiagStatus_DmaFailure;
5315
5316         /* build and send transmit frame */
5317         for (count = 0; count < TESTFRAMESIZE;++count)
5318                 buf[count] = (unsigned char)count;
5319
5320         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5321
5322         /* program hardware for HDLC and enabled receiver */
5323         spin_lock_irqsave(&info->lock,flags);
5324         hdlc_mode(info);
5325         enable_loopback(info,1);
5326         rx_start(info);
5327         info->tx_count = count;
5328         tx_load_dma_buffer(info,buf,count);
5329         tx_start(info);
5330         spin_unlock_irqrestore(&info->lock,flags);
5331
5332         /* wait for receive complete */
5333         /* Set a timeout for waiting for interrupt. */
5334         for ( timeout = 100; timeout; --timeout ) {
5335                 msleep_interruptible(10);
5336
5337                 if (rx_get_frame(info)) {
5338                         rc = TRUE;
5339                         break;
5340                 }
5341         }
5342
5343         /* verify received frame length and contents */
5344         if (rc == TRUE &&
5345                 ( info->tmp_rx_buf_count != count ||
5346                   memcmp(buf, info->tmp_rx_buf,count))) {
5347                 rc = FALSE;
5348         }
5349
5350         spin_lock_irqsave(&info->lock,flags);
5351         reset_adapter(info);
5352         spin_unlock_irqrestore(&info->lock,flags);
5353
5354         info->params.clock_speed = speed;
5355         info->tty = oldtty;
5356
5357         return rc;
5358 }
5359
5360 /* Perform diagnostics on hardware
5361  */
5362 int adapter_test( SLMP_INFO *info )
5363 {
5364         unsigned long flags;
5365         if ( debug_level >= DEBUG_LEVEL_INFO )
5366                 printk( "%s(%d):Testing device %s\n",
5367                         __FILE__,__LINE__,info->device_name );
5368
5369         spin_lock_irqsave(&info->lock,flags);
5370         init_adapter(info);
5371         spin_unlock_irqrestore(&info->lock,flags);
5372
5373         info->port_array[0]->port_count = 0;
5374
5375         if ( register_test(info->port_array[0]) &&
5376                 register_test(info->port_array[1])) {
5377
5378                 info->port_array[0]->port_count = 2;
5379
5380                 if ( register_test(info->port_array[2]) &&
5381                         register_test(info->port_array[3]) )
5382                         info->port_array[0]->port_count += 2;
5383         }
5384         else {
5385                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5386                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5387                 return -ENODEV;
5388         }
5389
5390         if ( !irq_test(info->port_array[0]) ||
5391                 !irq_test(info->port_array[1]) ||
5392                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5393                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5394                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5395                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5396                 return -ENODEV;
5397         }
5398
5399         if (!loopback_test(info->port_array[0]) ||
5400                 !loopback_test(info->port_array[1]) ||
5401                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5402                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5403                 printk( "%s(%d):DMA test failure for device %s\n",
5404                         __FILE__,__LINE__,info->device_name);
5405                 return -ENODEV;
5406         }
5407
5408         if ( debug_level >= DEBUG_LEVEL_INFO )
5409                 printk( "%s(%d):device %s passed diagnostics\n",
5410                         __FILE__,__LINE__,info->device_name );
5411
5412         info->port_array[0]->init_error = 0;
5413         info->port_array[1]->init_error = 0;
5414         if ( info->port_count > 2 ) {
5415                 info->port_array[2]->init_error = 0;
5416                 info->port_array[3]->init_error = 0;
5417         }
5418
5419         return 0;
5420 }
5421
5422 /* Test the shared memory on a PCI adapter.
5423  */
5424 int memory_test(SLMP_INFO *info)
5425 {
5426         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5427                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5428         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5429         unsigned long i;
5430         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5431         unsigned long * addr = (unsigned long *)info->memory_base;
5432
5433         /* Test data lines with test pattern at one location. */
5434
5435         for ( i = 0 ; i < count ; i++ ) {
5436                 *addr = testval[i];
5437                 if ( *addr != testval[i] )
5438                         return FALSE;
5439         }
5440
5441         /* Test address lines with incrementing pattern over */
5442         /* entire address range. */
5443
5444         for ( i = 0 ; i < limit ; i++ ) {
5445                 *addr = i * 4;
5446                 addr++;
5447         }
5448
5449         addr = (unsigned long *)info->memory_base;
5450
5451         for ( i = 0 ; i < limit ; i++ ) {
5452                 if ( *addr != i * 4 )
5453                         return FALSE;
5454                 addr++;
5455         }
5456
5457         memset( info->memory_base, 0, SCA_MEM_SIZE );
5458         return TRUE;
5459 }
5460
5461 /* Load data into PCI adapter shared memory.
5462  *
5463  * The PCI9050 releases control of the local bus
5464  * after completing the current read or write operation.
5465  *
5466  * While the PCI9050 write FIFO not empty, the
5467  * PCI9050 treats all of the writes as a single transaction
5468  * and does not release the bus. This causes DMA latency problems
5469  * at high speeds when copying large data blocks to the shared memory.
5470  *
5471  * This function breaks a write into multiple transations by
5472  * interleaving a read which flushes the write FIFO and 'completes'
5473  * the write transation. This allows any pending DMA request to gain control
5474  * of the local bus in a timely fasion.
5475  */
5476 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5477 {
5478         /* A load interval of 16 allows for 4 32-bit writes at */
5479         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5480
5481         unsigned short interval = count / sca_pci_load_interval;
5482         unsigned short i;
5483
5484         for ( i = 0 ; i < interval ; i++ )
5485         {
5486                 memcpy(dest, src, sca_pci_load_interval);
5487                 read_status_reg(info);
5488                 dest += sca_pci_load_interval;
5489                 src += sca_pci_load_interval;
5490         }
5491
5492         memcpy(dest, src, count % sca_pci_load_interval);
5493 }
5494
5495 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5496 {
5497         int i;
5498         int linecount;
5499         if (xmit)
5500                 printk("%s tx data:\n",info->device_name);
5501         else
5502                 printk("%s rx data:\n",info->device_name);
5503
5504         while(count) {
5505                 if (count > 16)
5506                         linecount = 16;
5507                 else
5508                         linecount = count;
5509
5510                 for(i=0;i<linecount;i++)
5511                         printk("%02X ",(unsigned char)data[i]);
5512                 for(;i<17;i++)
5513                         printk("   ");
5514                 for(i=0;i<linecount;i++) {
5515                         if (data[i]>=040 && data[i]<=0176)
5516                                 printk("%c",data[i]);
5517                         else
5518                                 printk(".");
5519                 }
5520                 printk("\n");
5521
5522                 data  += linecount;
5523                 count -= linecount;
5524         }
5525 }       /* end of trace_block() */
5526
5527 /* called when HDLC frame times out
5528  * update stats and do tx completion processing
5529  */
5530 void tx_timeout(unsigned long context)
5531 {
5532         SLMP_INFO *info = (SLMP_INFO*)context;
5533         unsigned long flags;
5534
5535         if ( debug_level >= DEBUG_LEVEL_INFO )
5536                 printk( "%s(%d):%s tx_timeout()\n",
5537                         __FILE__,__LINE__,info->device_name);
5538         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5539                 info->icount.txtimeout++;
5540         }
5541         spin_lock_irqsave(&info->lock,flags);
5542         info->tx_active = 0;
5543         info->tx_count = info->tx_put = info->tx_get = 0;
5544
5545         spin_unlock_irqrestore(&info->lock,flags);
5546
5547 #ifdef CONFIG_HDLC
5548         if (info->netcount)
5549                 hdlcdev_tx_done(info);
5550         else
5551 #endif
5552                 bh_transmit(info);
5553 }
5554
5555 /* called to periodically check the DSR/RI modem signal input status
5556  */
5557 void status_timeout(unsigned long context)
5558 {
5559         u16 status = 0;
5560         SLMP_INFO *info = (SLMP_INFO*)context;
5561         unsigned long flags;
5562         unsigned char delta;
5563
5564
5565         spin_lock_irqsave(&info->lock,flags);
5566         get_signals(info);
5567         spin_unlock_irqrestore(&info->lock,flags);
5568
5569         /* check for DSR/RI state change */
5570
5571         delta = info->old_signals ^ info->serial_signals;
5572         info->old_signals = info->serial_signals;
5573
5574         if (delta & SerialSignal_DSR)
5575                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5576
5577         if (delta & SerialSignal_RI)
5578                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5579
5580         if (delta & SerialSignal_DCD)
5581                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5582
5583         if (delta & SerialSignal_CTS)
5584                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5585
5586         if (status)
5587                 isr_io_pin(info,status);
5588
5589         info->status_timer.data = (unsigned long)info;
5590         info->status_timer.function = status_timeout;
5591         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5592         add_timer(&info->status_timer);
5593 }
5594
5595
5596 /* Register Access Routines -
5597  * All registers are memory mapped
5598  */
5599 #define CALC_REGADDR() \
5600         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5601         if (info->port_num > 1) \
5602                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5603         if ( info->port_num & 1) { \
5604                 if (Addr > 0x7f) \
5605                         RegAddr += 0x40;        /* DMA access */ \
5606                 else if (Addr > 0x1f && Addr < 0x60) \
5607                         RegAddr += 0x20;        /* MSCI access */ \
5608         }
5609
5610
5611 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5612 {
5613         CALC_REGADDR();
5614         return *RegAddr;
5615 }
5616 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5617 {
5618         CALC_REGADDR();
5619         *RegAddr = Value;
5620 }
5621
5622 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5623 {
5624         CALC_REGADDR();
5625         return *((u16 *)RegAddr);
5626 }
5627
5628 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5629 {
5630         CALC_REGADDR();
5631         *((u16 *)RegAddr) = Value;
5632 }
5633
5634 unsigned char read_status_reg(SLMP_INFO * info)
5635 {
5636         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5637         return *RegAddr;
5638 }
5639
5640 void write_control_reg(SLMP_INFO * info)
5641 {
5642         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5643         *RegAddr = info->port_array[0]->ctrlreg_value;
5644 }
5645
5646
5647 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5648                                           const struct pci_device_id *ent)
5649 {
5650         if (pci_enable_device(dev)) {
5651                 printk("error enabling pci device %p\n", dev);
5652                 return -EIO;
5653         }
5654         device_init( ++synclinkmp_adapter_count, dev );
5655         return 0;
5656 }
5657
5658 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5659 {
5660 }