drivers/char/drm/via_dma.c

   1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
   7  * All Rights Reserved.
   8  *
   9  * Copyright 2004 The Unichrome project.
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a
  13  * copy of this software and associated documentation files (the "Software"),
  14  * to deal in the Software without restriction, including without limitation
  15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  16  * and/or sell copies of the Software, and to permit persons to whom the
  17  * Software is furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice (including the
  20  * next paragraph) shall be included in all copies or substantial portions
  21  * of the Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  30  *
  31  * Authors:
  32  *    Tungsten Graphics,
  33  *    Erdi Chen,
  34  *    Thomas Hellstrom.
  35  */
  36
  37 #include "drmP.h"
  38 #include "drm.h"
  39 #include "via_drm.h"
  40 #include "via_drv.h"
  41 #include "via_3d_reg.h"
  42
  43 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
  44 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
  45
  46 /* defines for VIA 3D registers */
  47 #define VIA_REG_STATUS          0x400
  48 #define VIA_REG_TRANSET         0x43C
  49 #define VIA_REG_TRANSPACE       0x440
  50
  51 /* VIA_REG_STATUS(0x400): Engine Status */
  52 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
  53 #define VIA_2D_ENG_BUSY         0x00000001      /* 2D Engine is busy */
  54 #define VIA_3D_ENG_BUSY         0x00000002      /* 3D Engine is busy */
  55 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
  56
  57 #define SetReg2DAGP(nReg, nData) {                              \
  58         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
  59         *((uint32_t *)(vb) + 1) = (nData);                      \
  60         vb = ((uint32_t *)vb) + 2;                              \
  61         dev_priv->dma_low +=8;                                  \
  62 }
  63
  64 #define via_flush_write_combine() DRM_MEMORYBARRIER()
  65
  66 #define VIA_OUT_RING_QW(w1,w2)                  \
  67         *vb++ = (w1);                           \
  68         *vb++ = (w2);                           \
  69         dev_priv->dma_low += 8;
  70
  71 static void via_cmdbuf_start(drm_via_private_t * dev_priv);
  72 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
  73 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
  74 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
  75 static int via_wait_idle(drm_via_private_t * dev_priv);
  76 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords);
  77
  78 /*
  79  * Free space in command buffer.
  80  */
  81
  82 static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv)
  83 {
  84         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  85         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
  86
  87         return ((hw_addr <= dev_priv->dma_low) ?
  88                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
  89                 (hw_addr - dev_priv->dma_low));
  90 }
  91
  92 /*
  93  * How much does the command regulator lag behind?
  94  */
  95
  96 static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv)
  97 {
  98         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  99         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
 100
 101         return ((hw_addr <= dev_priv->dma_low) ?
 102                 (dev_priv->dma_low - hw_addr) :
 103                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
 104 }
 105
 106 /*
 107  * Check that the given size fits in the buffer, otherwise wait.
 108  */
 109
 110 static inline int
 111 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
 112 {
 113         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 114         uint32_t cur_addr, hw_addr, next_addr;
 115         volatile uint32_t *hw_addr_ptr;
 116         uint32_t count;
 117         hw_addr_ptr = dev_priv->hw_addr_ptr;
 118         cur_addr = dev_priv->dma_low;
 119         next_addr = cur_addr + size + 512 * 1024;
 120         count = 1000000;
 121         do {
 122                 hw_addr = *hw_addr_ptr - agp_base;
 123                 if (count-- == 0) {
 124                         DRM_ERROR
 125                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
 126                              hw_addr, cur_addr, next_addr);
 127                         return -1;
 128                 }
 129         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
 130         return 0;
 131 }
 132
 133 /*
 134  * Checks whether buffer head has reach the end. Rewind the ring buffer
 135  * when necessary.
 136  *
 137  * Returns virtual pointer to ring buffer.
 138  */
 139
 140 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
 141                                       unsigned int size)
 142 {
 143         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
 144             dev_priv->dma_high) {
 145                 via_cmdbuf_rewind(dev_priv);
 146         }
 147         if (via_cmdbuf_wait(dev_priv, size) != 0) {
 148                 return NULL;
 149         }
 150
 151         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 152 }
 153
 154 int via_dma_cleanup(drm_device_t * dev)
 155 {
 156         if (dev->dev_private) {
 157                 drm_via_private_t *dev_priv =
 158                     (drm_via_private_t *) dev->dev_private;
 159
 160                 if (dev_priv->ring.virtual_start) {
 161                         via_cmdbuf_reset(dev_priv);
 162
 163                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 164                         dev_priv->ring.virtual_start = NULL;
 165                 }
 166
 167         }
 168
 169         return 0;
 170 }
 171
 172 static int via_initialize(drm_device_t * dev,
 173                           drm_via_private_t * dev_priv,
 174                           drm_via_dma_init_t * init)
 175 {
 176         if (!dev_priv || !dev_priv->mmio) {
 177                 DRM_ERROR("via_dma_init called before via_map_init\n");
 178                 return DRM_ERR(EFAULT);
 179         }
 180
 181         if (dev_priv->ring.virtual_start != NULL) {
 182                 DRM_ERROR("%s called again without calling cleanup\n",
 183                           __FUNCTION__);
 184                 return DRM_ERR(EFAULT);
 185         }
 186
 187         if (!dev->agp || !dev->agp->base) {
 188                 DRM_ERROR("%s called with no agp memory available\n",
 189                           __FUNCTION__);
 190                 return DRM_ERR(EFAULT);
 191         }
 192
 193         dev_priv->ring.map.offset = dev->agp->base + init->offset;
 194         dev_priv->ring.map.size = init->size;
 195         dev_priv->ring.map.type = 0;
 196         dev_priv->ring.map.flags = 0;
 197         dev_priv->ring.map.mtrr = 0;
 198
 199         drm_core_ioremap(&dev_priv->ring.map, dev);
 200
 201         if (dev_priv->ring.map.handle == NULL) {
 202                 via_dma_cleanup(dev);
 203                 DRM_ERROR("can not ioremap virtual address for"
 204                           " ring buffer\n");
 205                 return DRM_ERR(ENOMEM);
 206         }
 207
 208         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 209
 210         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
 211         dev_priv->dma_low = 0;
 212         dev_priv->dma_high = init->size;
 213         dev_priv->dma_wrap = init->size;
 214         dev_priv->dma_offset = init->offset;
 215         dev_priv->last_pause_ptr = NULL;
 216         dev_priv->hw_addr_ptr = dev_priv->mmio->handle + init->reg_pause_addr;
 217
 218         via_cmdbuf_start(dev_priv);
 219
 220         return 0;
 221 }
 222
 223 int via_dma_init(DRM_IOCTL_ARGS)
 224 {
 225         DRM_DEVICE;
 226         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 227         drm_via_dma_init_t init;
 228         int retcode = 0;
 229
 230         DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data,
 231                                  sizeof(init));
 232
 233         switch (init.func) {
 234         case VIA_INIT_DMA:
 235                 if (!capable(CAP_SYS_ADMIN))
 236                         retcode = DRM_ERR(EPERM);
 237                 else
 238                         retcode = via_initialize(dev, dev_priv, &init);
 239                 break;
 240         case VIA_CLEANUP_DMA:
 241                 if (!capable(CAP_SYS_ADMIN))
 242                         retcode = DRM_ERR(EPERM);
 243                 else
 244                         retcode = via_dma_cleanup(dev);
 245                 break;
 246         case VIA_DMA_INITIALIZED:
 247                 retcode = (dev_priv->ring.virtual_start != NULL) ?
 248                     0 : DRM_ERR(EFAULT);
 249                 break;
 250         default:
 251                 retcode = DRM_ERR(EINVAL);
 252                 break;
 253         }
 254
 255         return retcode;
 256 }
 257
 258 static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
 259 {
 260         drm_via_private_t *dev_priv;
 261         uint32_t *vb;
 262         int ret;
 263
 264         dev_priv = (drm_via_private_t *) dev->dev_private;
 265
 266         if (dev_priv->ring.virtual_start == NULL) {
 267                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
 268                           __FUNCTION__);
 269                 return DRM_ERR(EFAULT);
 270         }
 271
 272         if (cmd->size > VIA_PCI_BUF_SIZE) {
 273                 return DRM_ERR(ENOMEM);
 274         }
 275
 276         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 277                 return DRM_ERR(EFAULT);
 278
 279         /*
 280          * Running this function on AGP memory is dead slow. Therefore
 281          * we run it on a temporary cacheable system memory buffer and
 282          * copy it to AGP memory when ready.
 283          */
 284
 285         if ((ret =
 286              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
 287                                        cmd->size, dev, 1))) {
 288                 return ret;
 289         }
 290
 291         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
 292         if (vb == NULL) {
 293                 return DRM_ERR(EAGAIN);
 294         }
 295
 296         memcpy(vb, dev_priv->pci_buf, cmd->size);
 297
 298         dev_priv->dma_low += cmd->size;
 299
 300         /*
 301          * Small submissions somehow stalls the CPU. (AGP cache effects?)
 302          * pad to greater size.
 303          */
 304
 305         if (cmd->size < 0x100)
 306                 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
 307         via_cmdbuf_pause(dev_priv);
 308
 309         return 0;
 310 }
 311
 312 int via_driver_dma_quiescent(drm_device_t * dev)
 313 {
 314         drm_via_private_t *dev_priv = dev->dev_private;
 315
 316         if (!via_wait_idle(dev_priv)) {
 317                 return DRM_ERR(EBUSY);
 318         }
 319         return 0;
 320 }
 321
 322 int via_flush_ioctl(DRM_IOCTL_ARGS)
 323 {
 324         DRM_DEVICE;
 325
 326         LOCK_TEST_WITH_RETURN(dev, filp);
 327
 328         return via_driver_dma_quiescent(dev);
 329 }
 330
 331 int via_cmdbuffer(DRM_IOCTL_ARGS)
 332 {
 333         DRM_DEVICE;
 334         drm_via_cmdbuffer_t cmdbuf;
 335         int ret;
 336
 337         LOCK_TEST_WITH_RETURN(dev, filp);
 338
 339         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 340                                  sizeof(cmdbuf));
 341
 342         DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
 343
 344         ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
 345         if (ret) {
 346                 return ret;
 347         }
 348
 349         return 0;
 350 }
 351
 352 extern int
 353 via_parse_command_stream(drm_device_t * dev, const uint32_t * buf,
 354                          unsigned int size);
 355 static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
 356                                       drm_via_cmdbuffer_t * cmd)
 357 {
 358         drm_via_private_t *dev_priv = dev->dev_private;
 359         int ret;
 360
 361         if (cmd->size > VIA_PCI_BUF_SIZE) {
 362                 return DRM_ERR(ENOMEM);
 363         }
 364         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 365                 return DRM_ERR(EFAULT);
 366
 367         if ((ret =
 368              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
 369                                        cmd->size, dev, 0))) {
 370                 return ret;
 371         }
 372
 373         ret =
 374             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
 375                                      cmd->size);
 376         return ret;
 377 }
 378
 379 int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
 380 {
 381         DRM_DEVICE;
 382         drm_via_cmdbuffer_t cmdbuf;
 383         int ret;
 384
 385         LOCK_TEST_WITH_RETURN(dev, filp);
 386
 387         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 388                                  sizeof(cmdbuf));
 389
 390         DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
 391                   cmdbuf.size);
 392
 393         ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
 394         if (ret) {
 395                 return ret;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
 402                                          uint32_t * vb, int qw_count)
 403 {
 404         for (; qw_count > 0; --qw_count) {
 405                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
 406         }
 407         return vb;
 408 }
 409
 410 /*
 411  * This function is used internally by ring buffer mangement code.
 412  *
 413  * Returns virtual pointer to ring buffer.
 414  */
 415 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
 416 {
 417         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 418 }
 419
 420 /*
 421  * Hooks a segment of data into the tail of the ring-buffer by
 422  * modifying the pause address stored in the buffer itself. If
 423  * the regulator has already paused, restart it.
 424  */
 425 static int via_hook_segment(drm_via_private_t * dev_priv,
 426                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
 427                             int no_pci_fire)
 428 {
 429         int paused, count;
 430         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
 431
 432         via_flush_write_combine();
 433         while (!*(via_get_dma(dev_priv) - 1)) ;
 434         *dev_priv->last_pause_ptr = pause_addr_lo;
 435         via_flush_write_combine();
 436
 437         /*
 438          * The below statement is inserted to really force the flush.
 439          * Not sure it is needed.
 440          */
 441
 442         while (!*dev_priv->last_pause_ptr) ;
 443         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
 444         while (!*dev_priv->last_pause_ptr) ;
 445
 446         paused = 0;
 447         count = 20;
 448
 449         while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--) ;
 450         if ((count <= 8) && (count >= 0)) {
 451                 uint32_t rgtr, ptr;
 452                 rgtr = *(dev_priv->hw_addr_ptr);
 453                 ptr = ((char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
 454                     dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 -
 455                     CMDBUF_ALIGNMENT_SIZE;
 456                 if (rgtr <= ptr) {
 457                         DRM_ERROR
 458                             ("Command regulator\npaused at count %d, address %x, "
 459                              "while current pause address is %x.\n"
 460                              "Please mail this message to "
 461                              "<unichrome-devel@lists.sourceforge.net>\n", count,
 462                              rgtr, ptr);
 463                 }
 464         }
 465
 466         if (paused && !no_pci_fire) {
 467                 uint32_t rgtr, ptr;
 468                 uint32_t ptr_low;
 469
 470                 count = 1000000;
 471                 while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY)
 472                        && count--) ;
 473
 474                 rgtr = *(dev_priv->hw_addr_ptr);
 475                 ptr = ((char *)paused_at - dev_priv->dma_ptr) +
 476                     dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 477
 478                 ptr_low = (ptr > 3 * CMDBUF_ALIGNMENT_SIZE) ?
 479                     ptr - 3 * CMDBUF_ALIGNMENT_SIZE : 0;
 480                 if (rgtr <= ptr && rgtr >= ptr_low) {
 481                         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 482                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 483                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 484                 }
 485         }
 486         return paused;
 487 }
 488
 489 static int via_wait_idle(drm_via_private_t * dev_priv)
 490 {
 491         int count = 10000000;
 492         while (count-- && (VIA_READ(VIA_REG_STATUS) &
 493                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
 494                             VIA_3D_ENG_BUSY))) ;
 495         return count;
 496 }
 497
 498 static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
 499                                uint32_t addr, uint32_t * cmd_addr_hi,
 500                                uint32_t * cmd_addr_lo, int skip_wait)
 501 {
 502         uint32_t agp_base;
 503         uint32_t cmd_addr, addr_lo, addr_hi;
 504         uint32_t *vb;
 505         uint32_t qw_pad_count;
 506
 507         if (!skip_wait)
 508                 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
 509
 510         vb = via_get_dma(dev_priv);
 511         VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
 512                         (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
 513         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 514         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
 515             ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 516
 517         cmd_addr = (addr) ? addr :
 518             agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
 519         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
 520                    (cmd_addr & HC_HAGPBpL_MASK));
 521         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
 522
 523         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 524         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
 525         return vb;
 526 }
 527
 528 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 529 {
 530         uint32_t pause_addr_lo, pause_addr_hi;
 531         uint32_t start_addr, start_addr_lo;
 532         uint32_t end_addr, end_addr_lo;
 533         uint32_t command;
 534         uint32_t agp_base;
 535
 536         dev_priv->dma_low = 0;
 537
 538         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 539         start_addr = agp_base;
 540         end_addr = agp_base + dev_priv->dma_high;
 541
 542         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
 543         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 544         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
 545                    ((end_addr & 0xff000000) >> 16));
 546
 547         dev_priv->last_pause_ptr =
 548             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
 549                           &pause_addr_hi, &pause_addr_lo, 1) - 1;
 550
 551         via_flush_write_combine();
 552         while (!*dev_priv->last_pause_ptr) ;
 553
 554         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 555         VIA_WRITE(VIA_REG_TRANSPACE, command);
 556         VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
 557         VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
 558
 559         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 560         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 561
 562         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
 563 }
 564
 565 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords)
 566 {
 567         uint32_t *vb;
 568
 569         via_cmdbuf_wait(dev_priv, qwords + 2);
 570         vb = via_get_dma(dev_priv);
 571         VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
 572         via_align_buffer(dev_priv, vb, qwords);
 573 }
 574
 575 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
 576 {
 577         uint32_t *vb = via_get_dma(dev_priv);
 578         SetReg2DAGP(0x0C, (0 | (0 << 16)));
 579         SetReg2DAGP(0x10, 0 | (0 << 16));
 580         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
 581 }
 582
 583 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 584 {
 585         uint32_t agp_base;
 586         uint32_t pause_addr_lo, pause_addr_hi;
 587         uint32_t jump_addr_lo, jump_addr_hi;
 588         volatile uint32_t *last_pause_ptr;
 589         uint32_t dma_low_save1, dma_low_save2;
 590
 591         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 592         via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
 593                       &jump_addr_lo, 0);
 594
 595         dev_priv->dma_wrap = dev_priv->dma_low;
 596
 597         /*
 598          * Wrap command buffer to the beginning.
 599          */
 600
 601         dev_priv->dma_low = 0;
 602         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
 603                 DRM_ERROR("via_cmdbuf_jump failed\n");
 604         }
 605
 606         via_dummy_bitblt(dev_priv);
 607         via_dummy_bitblt(dev_priv);
 608
 609         last_pause_ptr =
 610             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 611                           &pause_addr_lo, 0) - 1;
 612         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 613                       &pause_addr_lo, 0);
 614
 615         *last_pause_ptr = pause_addr_lo;
 616         dma_low_save1 = dev_priv->dma_low;
 617
 618         /*
 619          * Now, set a trap that will pause the regulator if it tries to rerun the old
 620          * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
 621          * and reissues the jump command over PCI, while the regulator has already taken the jump
 622          * and actually paused at the current buffer end).
 623          * There appears to be no other way to detect this condition, since the hw_addr_pointer
 624          * does not seem to get updated immediately when a jump occurs.
 625          */
 626
 627         last_pause_ptr =
 628             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 629                           &pause_addr_lo, 0) - 1;
 630         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 631                       &pause_addr_lo, 0);
 632         *last_pause_ptr = pause_addr_lo;
 633
 634         dma_low_save2 = dev_priv->dma_low;
 635         dev_priv->dma_low = dma_low_save1;
 636         via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);
 637         dev_priv->dma_low = dma_low_save2;
 638         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
 639 }
 640
 641 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
 642 {
 643         via_cmdbuf_jump(dev_priv);
 644 }
 645
 646 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
 647 {
 648         uint32_t pause_addr_lo, pause_addr_hi;
 649
 650         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
 651         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
 652 }
 653
 654 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
 655 {
 656         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
 657 }
 658
 659 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
 660 {
 661         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
 662         via_wait_idle(dev_priv);
 663 }
 664
 665 /*
 666  * User interface to the space and lag functions.
 667  */
 668
 669 int via_cmdbuf_size(DRM_IOCTL_ARGS)
 670 {
 671         DRM_DEVICE;
 672         drm_via_cmdbuf_size_t d_siz;
 673         int ret = 0;
 674         uint32_t tmp_size, count;
 675         drm_via_private_t *dev_priv;
 676
 677         DRM_DEBUG("via cmdbuf_size\n");
 678         LOCK_TEST_WITH_RETURN(dev, filp);
 679
 680         dev_priv = (drm_via_private_t *) dev->dev_private;
 681
 682         if (dev_priv->ring.virtual_start == NULL) {
 683                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
 684                           __FUNCTION__);
 685                 return DRM_ERR(EFAULT);
 686         }
 687
 688         DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data,
 689                                  sizeof(d_siz));
 690
 691         count = 1000000;
 692         tmp_size = d_siz.size;
 693         switch (d_siz.func) {
 694         case VIA_CMDBUF_SPACE:
 695                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size)
 696                        && count--) {
 697                         if (!d_siz.wait) {
 698                                 break;
 699                         }
 700                 }
 701                 if (!count) {
 702                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
 703                         ret = DRM_ERR(EAGAIN);
 704                 }
 705                 break;
 706         case VIA_CMDBUF_LAG:
 707                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size)
 708                        && count--) {
 709                         if (!d_siz.wait) {
 710                                 break;
 711                         }
 712                 }
 713                 if (!count) {
 714                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
 715                         ret = DRM_ERR(EAGAIN);
 716                 }
 717                 break;
 718         default:
 719                 ret = DRM_ERR(EFAULT);
 720         }
 721         d_siz.size = tmp_size;
 722
 723         DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz,
 724                                sizeof(d_siz));
 725         return ret;
 726 }