drivers/base/regmap/regmap-irq.c

   1 /*
   2  * regmap based irq_chip
   3  *
   4  * Copyright 2011 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/export.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20 #include <linux/slab.h>
  21
  22 #include "internal.h"
  23
  24 struct regmap_irq_chip_data {
  25         struct mutex lock;
  26         struct irq_chip irq_chip;
  27
  28         struct regmap *map;
  29         const struct regmap_irq_chip *chip;
  30
  31         int irq_base;
  32         struct irq_domain *domain;
  33
  34         int irq;
  35         int wake_count;
  36
  37         void *status_reg_buf;
  38         unsigned int *main_status_buf;
  39         unsigned int *status_buf;
  40         unsigned int *mask_buf;
  41         unsigned int *mask_buf_def;
  42         unsigned int *wake_buf;
  43         unsigned int *type_buf;
  44         unsigned int *type_buf_def;
  45
  46         unsigned int irq_reg_stride;
  47         unsigned int type_reg_stride;
  48
  49         bool clear_status:1;
  50 };
  51
  52 static inline const
  53 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
  54                                      int irq)
  55 {
  56         return &data->chip->irqs[irq];
  57 }
  58
  59 static void regmap_irq_lock(struct irq_data *data)
  60 {
  61         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  62
  63         mutex_lock(&d->lock);
  64 }
  65
  66 static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
  67                                   unsigned int reg, unsigned int mask,
  68                                   unsigned int val)
  69 {
  70         if (d->chip->mask_writeonly)
  71                 return regmap_write_bits(d->map, reg, mask, val);
  72         else
  73                 return regmap_update_bits(d->map, reg, mask, val);
  74 }
  75
  76 static void regmap_irq_sync_unlock(struct irq_data *data)
  77 {
  78         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  79         struct regmap *map = d->map;
  80         int i, ret;
  81         u32 reg;
  82         u32 unmask_offset;
  83         u32 val;
  84
  85         if (d->chip->runtime_pm) {
  86                 ret = pm_runtime_get_sync(map->dev);
  87                 if (ret < 0)
  88                         dev_err(map->dev, "IRQ sync failed to resume: %d\n",
  89                                 ret);
  90         }
  91
  92         if (d->clear_status) {
  93                 for (i = 0; i < d->chip->num_regs; i++) {
  94                         reg = d->chip->status_base +
  95                                 (i * map->reg_stride * d->irq_reg_stride);
  96
  97                         ret = regmap_read(map, reg, &val);
  98                         if (ret)
  99                                 dev_err(d->map->dev,
 100                                         "Failed to clear the interrupt status bits\n");
 101                 }
 102
 103                 d->clear_status = false;
 104         }
 105
 106         /*
 107          * If there's been a change in the mask write it back to the
 108          * hardware.  We rely on the use of the regmap core cache to
 109          * suppress pointless writes.
 110          */
 111         for (i = 0; i < d->chip->num_regs; i++) {
 112                 if (!d->chip->mask_base)
 113                         continue;
 114
 115                 reg = d->chip->mask_base +
 116                         (i * map->reg_stride * d->irq_reg_stride);
 117                 if (d->chip->mask_invert) {
 118                         ret = regmap_irq_update_bits(d, reg,
 119                                          d->mask_buf_def[i], ~d->mask_buf[i]);
 120                 } else if (d->chip->unmask_base) {
 121                         /* set mask with mask_base register */
 122                         ret = regmap_irq_update_bits(d, reg,
 123                                         d->mask_buf_def[i], ~d->mask_buf[i]);
 124                         if (ret < 0)
 125                                 dev_err(d->map->dev,
 126                                         "Failed to sync unmasks in %x\n",
 127                                         reg);
 128                         unmask_offset = d->chip->unmask_base -
 129                                                         d->chip->mask_base;
 130                         /* clear mask with unmask_base register */
 131                         ret = regmap_irq_update_bits(d,
 132                                         reg + unmask_offset,
 133                                         d->mask_buf_def[i],
 134                                         d->mask_buf[i]);
 135                 } else {
 136                         ret = regmap_irq_update_bits(d, reg,
 137                                          d->mask_buf_def[i], d->mask_buf[i]);
 138                 }
 139                 if (ret != 0)
 140                         dev_err(d->map->dev, "Failed to sync masks in %x\n",
 141                                 reg);
 142
 143                 reg = d->chip->wake_base +
 144                         (i * map->reg_stride * d->irq_reg_stride);
 145                 if (d->wake_buf) {
 146                         if (d->chip->wake_invert)
 147                                 ret = regmap_irq_update_bits(d, reg,
 148                                                          d->mask_buf_def[i],
 149                                                          ~d->wake_buf[i]);
 150                         else
 151                                 ret = regmap_irq_update_bits(d, reg,
 152                                                          d->mask_buf_def[i],
 153                                                          d->wake_buf[i]);
 154                         if (ret != 0)
 155                                 dev_err(d->map->dev,
 156                                         "Failed to sync wakes in %x: %d\n",
 157                                         reg, ret);
 158                 }
 159
 160                 if (!d->chip->init_ack_masked)
 161                         continue;
 162                 /*
 163                  * Ack all the masked interrupts unconditionally,
 164                  * OR if there is masked interrupt which hasn't been Acked,
 165                  * it'll be ignored in irq handler, then may introduce irq storm
 166                  */
 167                 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
 168                         reg = d->chip->ack_base +
 169                                 (i * map->reg_stride * d->irq_reg_stride);
 170                         /* some chips ack by write 0 */
 171                         if (d->chip->ack_invert)
 172                                 ret = regmap_write(map, reg, ~d->mask_buf[i]);
 173                         else
 174                                 ret = regmap_write(map, reg, d->mask_buf[i]);
 175                         if (ret != 0)
 176                                 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
 177                                         reg, ret);
 178                 }
 179         }
 180
 181         /* Don't update the type bits if we're using mask bits for irq type. */
 182         if (!d->chip->type_in_mask) {
 183                 for (i = 0; i < d->chip->num_type_reg; i++) {
 184                         if (!d->type_buf_def[i])
 185                                 continue;
 186                         reg = d->chip->type_base +
 187                                 (i * map->reg_stride * d->type_reg_stride);
 188                         if (d->chip->type_invert)
 189                                 ret = regmap_irq_update_bits(d, reg,
 190                                         d->type_buf_def[i], ~d->type_buf[i]);
 191                         else
 192                                 ret = regmap_irq_update_bits(d, reg,
 193                                         d->type_buf_def[i], d->type_buf[i]);
 194                         if (ret != 0)
 195                                 dev_err(d->map->dev, "Failed to sync type in %x\n",
 196                                         reg);
 197                 }
 198         }
 199
 200         if (d->chip->runtime_pm)
 201                 pm_runtime_put(map->dev);
 202
 203         /* If we've changed our wakeup count propagate it to the parent */
 204         if (d->wake_count < 0)
 205                 for (i = d->wake_count; i < 0; i++)
 206                         irq_set_irq_wake(d->irq, 0);
 207         else if (d->wake_count > 0)
 208                 for (i = 0; i < d->wake_count; i++)
 209                         irq_set_irq_wake(d->irq, 1);
 210
 211         d->wake_count = 0;
 212
 213         mutex_unlock(&d->lock);
 214 }
 215
 216 static void regmap_irq_enable(struct irq_data *data)
 217 {
 218         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 219         struct regmap *map = d->map;
 220         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 221         unsigned int mask, type;
 222
 223         type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
 224
 225         /*
 226          * The type_in_mask flag means that the underlying hardware uses
 227          * separate mask bits for rising and falling edge interrupts, but
 228          * we want to make them into a single virtual interrupt with
 229          * configurable edge.
 230          *
 231          * If the interrupt we're enabling defines the falling or rising
 232          * masks then instead of using the regular mask bits for this
 233          * interrupt, use the value previously written to the type buffer
 234          * at the corresponding offset in regmap_irq_set_type().
 235          */
 236         if (d->chip->type_in_mask && type)
 237                 mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
 238         else
 239                 mask = irq_data->mask;
 240
 241         if (d->chip->clear_on_unmask)
 242                 d->clear_status = true;
 243
 244         d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
 245 }
 246
 247 static void regmap_irq_disable(struct irq_data *data)
 248 {
 249         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 250         struct regmap *map = d->map;
 251         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 252
 253         d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
 254 }
 255
 256 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 257 {
 258         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 259         struct regmap *map = d->map;
 260         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 261         int reg;
 262         const struct regmap_irq_type *t = &irq_data->type;
 263
 264         if ((t->types_supported & type) != type)
 265                 return 0;
 266
 267         reg = t->type_reg_offset / map->reg_stride;
 268
 269         if (t->type_reg_mask)
 270                 d->type_buf[reg] &= ~t->type_reg_mask;
 271         else
 272                 d->type_buf[reg] &= ~(t->type_falling_val |
 273                                       t->type_rising_val |
 274                                       t->type_level_low_val |
 275                                       t->type_level_high_val);
 276         switch (type) {
 277         case IRQ_TYPE_EDGE_FALLING:
 278                 d->type_buf[reg] |= t->type_falling_val;
 279                 break;
 280
 281         case IRQ_TYPE_EDGE_RISING:
 282                 d->type_buf[reg] |= t->type_rising_val;
 283                 break;
 284
 285         case IRQ_TYPE_EDGE_BOTH:
 286                 d->type_buf[reg] |= (t->type_falling_val |
 287                                         t->type_rising_val);
 288                 break;
 289
 290         case IRQ_TYPE_LEVEL_HIGH:
 291                 d->type_buf[reg] |= t->type_level_high_val;
 292                 break;
 293
 294         case IRQ_TYPE_LEVEL_LOW:
 295                 d->type_buf[reg] |= t->type_level_low_val;
 296                 break;
 297         default:
 298                 return -EINVAL;
 299         }
 300         return 0;
 301 }
 302
 303 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
 304 {
 305         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 306         struct regmap *map = d->map;
 307         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 308
 309         if (on) {
 310                 if (d->wake_buf)
 311                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 312                                 &= ~irq_data->mask;
 313                 d->wake_count++;
 314         } else {
 315                 if (d->wake_buf)
 316                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 317                                 |= irq_data->mask;
 318                 d->wake_count--;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static const struct irq_chip regmap_irq_chip = {
 325         .irq_bus_lock           = regmap_irq_lock,
 326         .irq_bus_sync_unlock    = regmap_irq_sync_unlock,
 327         .irq_disable            = regmap_irq_disable,
 328         .irq_enable             = regmap_irq_enable,
 329         .irq_set_type           = regmap_irq_set_type,
 330         .irq_set_wake           = regmap_irq_set_wake,
 331 };
 332
 333 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 334                                            unsigned int b)
 335 {
 336         const struct regmap_irq_chip *chip = data->chip;
 337         struct regmap *map = data->map;
 338         struct regmap_irq_sub_irq_map *subreg;
 339         int i, ret = 0;
 340
 341         if (!chip->sub_reg_offsets) {
 342                 /* Assume linear mapping */
 343                 ret = regmap_read(map, chip->status_base +
 344                                   (b * map->reg_stride * data->irq_reg_stride),
 345                                    &data->status_buf[b]);
 346         } else {
 347                 subreg = &chip->sub_reg_offsets[b];
 348                 for (i = 0; i < subreg->num_regs; i++) {
 349                         unsigned int offset = subreg->offset[i];
 350
 351                         ret = regmap_read(map, chip->status_base + offset,
 352                                           &data->status_buf[offset]);
 353                         if (ret)
 354                                 break;
 355                 }
 356         }
 357         return ret;
 358 }
 359
 360 static irqreturn_t regmap_irq_thread(int irq, void *d)
 361 {
 362         struct regmap_irq_chip_data *data = d;
 363         const struct regmap_irq_chip *chip = data->chip;
 364         struct regmap *map = data->map;
 365         int ret, i;
 366         bool handled = false;
 367         u32 reg;
 368
 369         if (chip->handle_pre_irq)
 370                 chip->handle_pre_irq(chip->irq_drv_data);
 371
 372         if (chip->runtime_pm) {
 373                 ret = pm_runtime_get_sync(map->dev);
 374                 if (ret < 0) {
 375                         dev_err(map->dev, "IRQ thread failed to resume: %d\n",
 376                                 ret);
 377                         pm_runtime_put(map->dev);
 378                         goto exit;
 379                 }
 380         }
 381
 382         /*
 383          * Read only registers with active IRQs if the chip has 'main status
 384          * register'. Else read in the statuses, using a single bulk read if
 385          * possible in order to reduce the I/O overheads.
 386          */
 387
 388         if (chip->num_main_regs) {
 389                 unsigned int max_main_bits;
 390                 unsigned long size;
 391
 392                 size = chip->num_regs * sizeof(unsigned int);
 393
 394                 max_main_bits = (chip->num_main_status_bits) ?
 395                                  chip->num_main_status_bits : chip->num_regs;
 396                 /* Clear the status buf as we don't read all status regs */
 397                 memset(data->status_buf, 0, size);
 398
 399                 /* We could support bulk read for main status registers
 400                  * but I don't expect to see devices with really many main
 401                  * status registers so let's only support single reads for the
 402                  * sake of simplicity. and add bulk reads only if needed
 403                  */
 404                 for (i = 0; i < chip->num_main_regs; i++) {
 405                         ret = regmap_read(map, chip->main_status +
 406                                   (i * map->reg_stride
 407                                    * data->irq_reg_stride),
 408                                   &data->main_status_buf[i]);
 409                         if (ret) {
 410                                 dev_err(map->dev,
 411                                         "Failed to read IRQ status %d\n",
 412                                         ret);
 413                                 goto exit;
 414                         }
 415                 }
 416
 417                 /* Read sub registers with active IRQs */
 418                 for (i = 0; i < chip->num_main_regs; i++) {
 419                         unsigned int b;
 420                         const unsigned long mreg = data->main_status_buf[i];
 421
 422                         for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
 423                                 if (i * map->format.val_bytes * 8 + b >
 424                                     max_main_bits)
 425                                         break;
 426                                 ret = read_sub_irq_data(data, b);
 427
 428                                 if (ret != 0) {
 429                                         dev_err(map->dev,
 430                                                 "Failed to read IRQ status %d\n",
 431                                                 ret);
 432                                         if (chip->runtime_pm)
 433                                                 pm_runtime_put(map->dev);
 434                                         goto exit;
 435                                 }
 436                         }
 437
 438                 }
 439         } else if (!map->use_single_read && map->reg_stride == 1 &&
 440                    data->irq_reg_stride == 1) {
 441
 442                 u8 *buf8 = data->status_reg_buf;
 443                 u16 *buf16 = data->status_reg_buf;
 444                 u32 *buf32 = data->status_reg_buf;
 445
 446                 BUG_ON(!data->status_reg_buf);
 447
 448                 ret = regmap_bulk_read(map, chip->status_base,
 449                                        data->status_reg_buf,
 450                                        chip->num_regs);
 451                 if (ret != 0) {
 452                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 453                                 ret);
 454                         goto exit;
 455                 }
 456
 457                 for (i = 0; i < data->chip->num_regs; i++) {
 458                         switch (map->format.val_bytes) {
 459                         case 1:
 460                                 data->status_buf[i] = buf8[i];
 461                                 break;
 462                         case 2:
 463                                 data->status_buf[i] = buf16[i];
 464                                 break;
 465                         case 4:
 466                                 data->status_buf[i] = buf32[i];
 467                                 break;
 468                         default:
 469                                 BUG();
 470                                 goto exit;
 471                         }
 472                 }
 473
 474         } else {
 475                 for (i = 0; i < data->chip->num_regs; i++) {
 476                         ret = regmap_read(map, chip->status_base +
 477                                           (i * map->reg_stride
 478                                            * data->irq_reg_stride),
 479                                           &data->status_buf[i]);
 480
 481                         if (ret != 0) {
 482                                 dev_err(map->dev,
 483                                         "Failed to read IRQ status: %d\n",
 484                                         ret);
 485                                 if (chip->runtime_pm)
 486                                         pm_runtime_put(map->dev);
 487                                 goto exit;
 488                         }
 489                 }
 490         }
 491
 492         /*
 493          * Ignore masked IRQs and ack if we need to; we ack early so
 494          * there is no race between handling and acknowleding the
 495          * interrupt.  We assume that typically few of the interrupts
 496          * will fire simultaneously so don't worry about overhead from
 497          * doing a write per register.
 498          */
 499         for (i = 0; i < data->chip->num_regs; i++) {
 500                 data->status_buf[i] &= ~data->mask_buf[i];
 501
 502                 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 503                         reg = chip->ack_base +
 504                                 (i * map->reg_stride * data->irq_reg_stride);
 505                         ret = regmap_write(map, reg, data->status_buf[i]);
 506                         if (ret != 0)
 507                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 508                                         reg, ret);
 509                 }
 510         }
 511
 512         for (i = 0; i < chip->num_irqs; i++) {
 513                 if (data->status_buf[chip->irqs[i].reg_offset /
 514                                      map->reg_stride] & chip->irqs[i].mask) {
 515                         handle_nested_irq(irq_find_mapping(data->domain, i));
 516                         handled = true;
 517                 }
 518         }
 519
 520         if (chip->runtime_pm)
 521                 pm_runtime_put(map->dev);
 522
 523 exit:
 524         if (chip->handle_post_irq)
 525                 chip->handle_post_irq(chip->irq_drv_data);
 526
 527         if (handled)
 528                 return IRQ_HANDLED;
 529         else
 530                 return IRQ_NONE;
 531 }
 532
 533 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
 534                           irq_hw_number_t hw)
 535 {
 536         struct regmap_irq_chip_data *data = h->host_data;
 537
 538         irq_set_chip_data(virq, data);
 539         irq_set_chip(virq, &data->irq_chip);
 540         irq_set_nested_thread(virq, 1);
 541         irq_set_parent(virq, data->irq);
 542         irq_set_noprobe(virq);
 543
 544         return 0;
 545 }
 546
 547 static const struct irq_domain_ops regmap_domain_ops = {
 548         .map    = regmap_irq_map,
 549         .xlate  = irq_domain_xlate_onetwocell,
 550 };
 551
 552 /**
 553  * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
 554  *
 555  * @map: The regmap for the device.
 556  * @irq: The IRQ the device uses to signal interrupts.
 557  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 558  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 559  * @chip: Configuration for the interrupt controller.
 560  * @data: Runtime data structure for the controller, allocated on success.
 561  *
 562  * Returns 0 on success or an errno on failure.
 563  *
 564  * In order for this to be efficient the chip really should use a
 565  * register cache.  The chip driver is responsible for restoring the
 566  * register values used by the IRQ controller over suspend and resume.
 567  */
 568 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 569                         int irq_base, const struct regmap_irq_chip *chip,
 570                         struct regmap_irq_chip_data **data)
 571 {
 572         struct regmap_irq_chip_data *d;
 573         int i;
 574         int ret = -ENOMEM;
 575         int num_type_reg;
 576         u32 reg;
 577         u32 unmask_offset;
 578
 579         if (chip->num_regs <= 0)
 580                 return -EINVAL;
 581
 582         if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
 583                 return -EINVAL;
 584
 585         for (i = 0; i < chip->num_irqs; i++) {
 586                 if (chip->irqs[i].reg_offset % map->reg_stride)
 587                         return -EINVAL;
 588                 if (chip->irqs[i].reg_offset / map->reg_stride >=
 589                     chip->num_regs)
 590                         return -EINVAL;
 591         }
 592
 593         if (irq_base) {
 594                 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
 595                 if (irq_base < 0) {
 596                         dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
 597                                  irq_base);
 598                         return irq_base;
 599                 }
 600         }
 601
 602         d = kzalloc(sizeof(*d), GFP_KERNEL);
 603         if (!d)
 604                 return -ENOMEM;
 605
 606         if (chip->num_main_regs) {
 607                 d->main_status_buf = kcalloc(chip->num_main_regs,
 608                                              sizeof(unsigned int),
 609                                              GFP_KERNEL);
 610
 611                 if (!d->main_status_buf)
 612                         goto err_alloc;
 613         }
 614
 615         d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 616                                 GFP_KERNEL);
 617         if (!d->status_buf)
 618                 goto err_alloc;
 619
 620         d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 621                               GFP_KERNEL);
 622         if (!d->mask_buf)
 623                 goto err_alloc;
 624
 625         d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
 626                                   GFP_KERNEL);
 627         if (!d->mask_buf_def)
 628                 goto err_alloc;
 629
 630         if (chip->wake_base) {
 631                 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 632                                       GFP_KERNEL);
 633                 if (!d->wake_buf)
 634                         goto err_alloc;
 635         }
 636
 637         num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
 638         if (num_type_reg) {
 639                 d->type_buf_def = kcalloc(num_type_reg,
 640                                           sizeof(unsigned int), GFP_KERNEL);
 641                 if (!d->type_buf_def)
 642                         goto err_alloc;
 643
 644                 d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
 645                                       GFP_KERNEL);
 646                 if (!d->type_buf)
 647                         goto err_alloc;
 648         }
 649
 650         d->irq_chip = regmap_irq_chip;
 651         d->irq_chip.name = chip->name;
 652         d->irq = irq;
 653         d->map = map;
 654         d->chip = chip;
 655         d->irq_base = irq_base;
 656
 657         if (chip->irq_reg_stride)
 658                 d->irq_reg_stride = chip->irq_reg_stride;
 659         else
 660                 d->irq_reg_stride = 1;
 661
 662         if (chip->type_reg_stride)
 663                 d->type_reg_stride = chip->type_reg_stride;
 664         else
 665                 d->type_reg_stride = 1;
 666
 667         if (!map->use_single_read && map->reg_stride == 1 &&
 668             d->irq_reg_stride == 1) {
 669                 d->status_reg_buf = kmalloc_array(chip->num_regs,
 670                                                   map->format.val_bytes,
 671                                                   GFP_KERNEL);
 672                 if (!d->status_reg_buf)
 673                         goto err_alloc;
 674         }
 675
 676         mutex_init(&d->lock);
 677
 678         for (i = 0; i < chip->num_irqs; i++)
 679                 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
 680                         |= chip->irqs[i].mask;
 681
 682         /* Mask all the interrupts by default */
 683         for (i = 0; i < chip->num_regs; i++) {
 684                 d->mask_buf[i] = d->mask_buf_def[i];
 685                 if (!chip->mask_base)
 686                         continue;
 687
 688                 reg = chip->mask_base +
 689                         (i * map->reg_stride * d->irq_reg_stride);
 690                 if (chip->mask_invert)
 691                         ret = regmap_irq_update_bits(d, reg,
 692                                          d->mask_buf[i], ~d->mask_buf[i]);
 693                 else if (d->chip->unmask_base) {
 694                         unmask_offset = d->chip->unmask_base -
 695                                         d->chip->mask_base;
 696                         ret = regmap_irq_update_bits(d,
 697                                         reg + unmask_offset,
 698                                         d->mask_buf[i],
 699                                         d->mask_buf[i]);
 700                 } else
 701                         ret = regmap_irq_update_bits(d, reg,
 702                                          d->mask_buf[i], d->mask_buf[i]);
 703                 if (ret != 0) {
 704                         dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 705                                 reg, ret);
 706                         goto err_alloc;
 707                 }
 708
 709                 if (!chip->init_ack_masked)
 710                         continue;
 711
 712                 /* Ack masked but set interrupts */
 713                 reg = chip->status_base +
 714                         (i * map->reg_stride * d->irq_reg_stride);
 715                 ret = regmap_read(map, reg, &d->status_buf[i]);
 716                 if (ret != 0) {
 717                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 718                                 ret);
 719                         goto err_alloc;
 720                 }
 721
 722                 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 723                         reg = chip->ack_base +
 724                                 (i * map->reg_stride * d->irq_reg_stride);
 725                         if (chip->ack_invert)
 726                                 ret = regmap_write(map, reg,
 727                                         ~(d->status_buf[i] & d->mask_buf[i]));
 728                         else
 729                                 ret = regmap_write(map, reg,
 730                                         d->status_buf[i] & d->mask_buf[i]);
 731                         if (ret != 0) {
 732                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 733                                         reg, ret);
 734                                 goto err_alloc;
 735                         }
 736                 }
 737         }
 738
 739         /* Wake is disabled by default */
 740         if (d->wake_buf) {
 741                 for (i = 0; i < chip->num_regs; i++) {
 742                         d->wake_buf[i] = d->mask_buf_def[i];
 743                         reg = chip->wake_base +
 744                                 (i * map->reg_stride * d->irq_reg_stride);
 745
 746                         if (chip->wake_invert)
 747                                 ret = regmap_irq_update_bits(d, reg,
 748                                                          d->mask_buf_def[i],
 749                                                          0);
 750                         else
 751                                 ret = regmap_irq_update_bits(d, reg,
 752                                                          d->mask_buf_def[i],
 753                                                          d->wake_buf[i]);
 754                         if (ret != 0) {
 755                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 756                                         reg, ret);
 757                                 goto err_alloc;
 758                         }
 759                 }
 760         }
 761
 762         if (chip->num_type_reg && !chip->type_in_mask) {
 763                 for (i = 0; i < chip->num_type_reg; ++i) {
 764                         if (!d->type_buf_def[i])
 765                                 continue;
 766
 767                         reg = chip->type_base +
 768                                 (i * map->reg_stride * d->type_reg_stride);
 769
 770                         ret = regmap_read(map, reg, &d->type_buf_def[i]);
 771
 772                         if (d->chip->type_invert)
 773                                 d->type_buf_def[i] = ~d->type_buf_def[i];
 774
 775                         if (ret) {
 776                                 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
 777                                         reg, ret);
 778                                 goto err_alloc;
 779                         }
 780                 }
 781         }
 782
 783         if (irq_base)
 784                 d->domain = irq_domain_add_legacy(map->dev->of_node,
 785                                                   chip->num_irqs, irq_base, 0,
 786                                                   &regmap_domain_ops, d);
 787         else
 788                 d->domain = irq_domain_add_linear(map->dev->of_node,
 789                                                   chip->num_irqs,
 790                                                   &regmap_domain_ops, d);
 791         if (!d->domain) {
 792                 dev_err(map->dev, "Failed to create IRQ domain\n");
 793                 ret = -ENOMEM;
 794                 goto err_alloc;
 795         }
 796
 797         ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
 798                                    irq_flags | IRQF_ONESHOT,
 799                                    chip->name, d);
 800         if (ret != 0) {
 801                 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
 802                         irq, chip->name, ret);
 803                 goto err_domain;
 804         }
 805
 806         *data = d;
 807
 808         return 0;
 809
 810 err_domain:
 811         /* Should really dispose of the domain but... */
 812 err_alloc:
 813         kfree(d->type_buf);
 814         kfree(d->type_buf_def);
 815         kfree(d->wake_buf);
 816         kfree(d->mask_buf_def);
 817         kfree(d->mask_buf);
 818         kfree(d->status_buf);
 819         kfree(d->status_reg_buf);
 820         kfree(d);
 821         return ret;
 822 }
 823 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 824
 825 /**
 826  * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
 827  *
 828  * @irq: Primary IRQ for the device
 829  * @d: &regmap_irq_chip_data allocated by regmap_add_irq_chip()
 830  *
 831  * This function also disposes of all mapped IRQs on the chip.
 832  */
 833 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 834 {
 835         unsigned int virq;
 836         int hwirq;
 837
 838         if (!d)
 839                 return;
 840
 841         free_irq(irq, d);
 842
 843         /* Dispose all virtual irq from irq domain before removing it */
 844         for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
 845                 /* Ignore hwirq if holes in the IRQ list */
 846                 if (!d->chip->irqs[hwirq].mask)
 847                         continue;
 848
 849                 /*
 850                  * Find the virtual irq of hwirq on chip and if it is
 851                  * there then dispose it
 852                  */
 853                 virq = irq_find_mapping(d->domain, hwirq);
 854                 if (virq)
 855                         irq_dispose_mapping(virq);
 856         }
 857
 858         irq_domain_remove(d->domain);
 859         kfree(d->type_buf);
 860         kfree(d->type_buf_def);
 861         kfree(d->wake_buf);
 862         kfree(d->mask_buf_def);
 863         kfree(d->mask_buf);
 864         kfree(d->status_reg_buf);
 865         kfree(d->status_buf);
 866         kfree(d);
 867 }
 868 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
 869
 870 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
 871 {
 872         struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
 873
 874         regmap_del_irq_chip(d->irq, d);
 875 }
 876
 877 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
 878
 879 {
 880         struct regmap_irq_chip_data **r = res;
 881
 882         if (!r || !*r) {
 883                 WARN_ON(!r || !*r);
 884                 return 0;
 885         }
 886         return *r == data;
 887 }
 888
 889 /**
 890  * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
 891  *
 892  * @dev: The device pointer on which irq_chip belongs to.
 893  * @map: The regmap for the device.
 894  * @irq: The IRQ the device uses to signal interrupts
 895  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 896  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 897  * @chip: Configuration for the interrupt controller.
 898  * @data: Runtime data structure for the controller, allocated on success
 899  *
 900  * Returns 0 on success or an errno on failure.
 901  *
 902  * The &regmap_irq_chip_data will be automatically released when the device is
 903  * unbound.
 904  */
 905 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
 906                              int irq_flags, int irq_base,
 907                              const struct regmap_irq_chip *chip,
 908                              struct regmap_irq_chip_data **data)
 909 {
 910         struct regmap_irq_chip_data **ptr, *d;
 911         int ret;
 912
 913         ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
 914                            GFP_KERNEL);
 915         if (!ptr)
 916                 return -ENOMEM;
 917
 918         ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
 919                                   chip, &d);
 920         if (ret < 0) {
 921                 devres_free(ptr);
 922                 return ret;
 923         }
 924
 925         *ptr = d;
 926         devres_add(dev, ptr);
 927         *data = d;
 928         return 0;
 929 }
 930 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
 931
 932 /**
 933  * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
 934  *
 935  * @dev: Device for which which resource was allocated.
 936  * @irq: Primary IRQ for the device.
 937  * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
 938  *
 939  * A resource managed version of regmap_del_irq_chip().
 940  */
 941 void devm_regmap_del_irq_chip(struct device *dev, int irq,
 942                               struct regmap_irq_chip_data *data)
 943 {
 944         int rc;
 945
 946         WARN_ON(irq != data->irq);
 947         rc = devres_release(dev, devm_regmap_irq_chip_release,
 948                             devm_regmap_irq_chip_match, data);
 949
 950         if (rc != 0)
 951                 WARN_ON(rc);
 952 }
 953 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
 954
 955 /**
 956  * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
 957  *
 958  * @data: regmap irq controller to operate on.
 959  *
 960  * Useful for drivers to request their own IRQs.
 961  */
 962 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
 963 {
 964         WARN_ON(!data->irq_base);
 965         return data->irq_base;
 966 }
 967 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
 968
 969 /**
 970  * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
 971  *
 972  * @data: regmap irq controller to operate on.
 973  * @irq: index of the interrupt requested in the chip IRQs.
 974  *
 975  * Useful for drivers to request their own IRQs.
 976  */
 977 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
 978 {
 979         /* Handle holes in the IRQ list */
 980         if (!data->chip->irqs[irq].mask)
 981                 return -EINVAL;
 982
 983         return irq_create_mapping(data->domain, irq);
 984 }
 985 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
 986
 987 /**
 988  * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
 989  *
 990  * @data: regmap_irq controller to operate on.
 991  *
 992  * Useful for drivers to request their own IRQs and for integration
 993  * with subsystems.  For ease of integration NULL is accepted as a
 994  * domain, allowing devices to just call this even if no domain is
 995  * allocated.
 996  */
 997 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
 998 {
 999         if (data)
1000                 return data->domain;
1001         else
1002                 return NULL;
1003 }
1004 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);