2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 * Chris Zankel <chris@zankel.net>
12 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
17 #include <linux/errno.h>
18 #include <linux/init.h>
20 #include <linux/proc_fs.h>
21 #include <linux/screen_info.h>
22 #include <linux/bootmem.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/clk-provider.h>
26 #include <linux/cpu.h>
28 #include <linux/of_fdt.h>
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
35 # include <linux/timex.h>
39 # include <linux/seq_file.h>
42 #include <asm/bootparam.h>
43 #include <asm/mmu_context.h>
44 #include <asm/pgtable.h>
45 #include <asm/processor.h>
46 #include <asm/timex.h>
47 #include <asm/platform.h>
49 #include <asm/setup.h>
50 #include <asm/param.h>
51 #include <asm/traps.h>
53 #include <asm/sysmem.h>
55 #include <platform/hardware.h>
57 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
58 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
61 #ifdef CONFIG_BLK_DEV_FD
62 extern struct fd_ops no_fd_ops;
63 struct fd_ops *fd_ops;
66 extern struct rtc_ops no_rtc_ops;
67 struct rtc_ops *rtc_ops;
69 #ifdef CONFIG_BLK_DEV_INITRD
70 extern unsigned long initrd_start;
71 extern unsigned long initrd_end;
72 int initrd_is_mapped = 0;
73 extern int initrd_below_start_ok;
77 void *dtb_start = __dtb_start;
80 unsigned char aux_device_present;
81 extern unsigned long loops_per_jiffy;
83 /* Command line specified as configuration option. */
85 static char __initdata command_line[COMMAND_LINE_SIZE];
87 #ifdef CONFIG_CMDLINE_BOOL
88 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
92 * Boot parameter parsing.
94 * The Xtensa port uses a list of variable-sized tags to pass data to
95 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
96 * to be recognised. The list is terminated with a zero-sized
100 typedef struct tagtable {
102 int (*parse)(const bp_tag_t*);
105 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
106 __attribute__((used, section(".taglist"))) = { tag, fn }
108 /* parse current tag */
110 static int __init parse_tag_mem(const bp_tag_t *tag)
112 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
114 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
117 return add_sysmem_bank(mi->start, mi->end);
120 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
122 #ifdef CONFIG_BLK_DEV_INITRD
124 static int __init parse_tag_initrd(const bp_tag_t* tag)
126 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
128 initrd_start = (unsigned long)__va(mi->start);
129 initrd_end = (unsigned long)__va(mi->end);
134 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
138 static int __init parse_tag_fdt(const bp_tag_t *tag)
140 dtb_start = __va(tag->data[0]);
144 __tagtable(BP_TAG_FDT, parse_tag_fdt);
146 #endif /* CONFIG_OF */
148 #endif /* CONFIG_BLK_DEV_INITRD */
150 static int __init parse_tag_cmdline(const bp_tag_t* tag)
152 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
156 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
158 static int __init parse_bootparam(const bp_tag_t* tag)
160 extern tagtable_t __tagtable_begin, __tagtable_end;
163 /* Boot parameters must start with a BP_TAG_FIRST tag. */
165 if (tag->id != BP_TAG_FIRST) {
166 printk(KERN_WARNING "Invalid boot parameters!\n");
170 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
172 /* Parse all tags. */
174 while (tag != NULL && tag->id != BP_TAG_LAST) {
175 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
176 if (tag->id == t->tag) {
181 if (t == &__tagtable_end)
182 printk(KERN_WARNING "Ignoring tag "
183 "0x%08x\n", tag->id);
184 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
191 bool __initdata dt_memory_scan = false;
193 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
194 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
195 EXPORT_SYMBOL(xtensa_kio_paddr);
197 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
198 int depth, void *data)
200 const __be32 *ranges;
206 if (!of_flat_dt_is_compatible(node, "simple-bus"))
209 ranges = of_get_flat_dt_prop(node, "ranges", &len);
215 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
216 /* round down to nearest 256MB boundary */
217 xtensa_kio_paddr &= 0xf0000000;
222 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
223 int depth, void *data)
229 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
235 add_sysmem_bank(base, base + size);
238 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
240 return __alloc_bootmem(size, align, 0);
243 void __init early_init_devtree(void *params)
245 if (sysmem.nr_banks == 0)
246 dt_memory_scan = true;
248 early_init_dt_scan(params);
249 of_scan_flat_dt(xtensa_dt_io_area, NULL);
251 if (!command_line[0])
252 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
255 static int __init xtensa_device_probe(void)
261 device_initcall(xtensa_device_probe);
263 #endif /* CONFIG_OF */
266 * Initialize architecture. (Early stage)
269 void __init init_arch(bp_tag_t *bp_start)
271 /* Parse boot parameters */
274 parse_bootparam(bp_start);
277 early_init_devtree(dtb_start);
280 if (sysmem.nr_banks == 0) {
281 add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
282 PLATFORM_DEFAULT_MEM_START +
283 PLATFORM_DEFAULT_MEM_SIZE);
286 #ifdef CONFIG_CMDLINE_BOOL
287 if (!command_line[0])
288 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
291 /* Early hook for platforms */
293 platform_init(bp_start);
295 /* Initialize MMU. */
301 * Initialize system. Setup memory and reserve regions.
306 extern char _WindowVectors_text_start;
307 extern char _WindowVectors_text_end;
308 extern char _DebugInterruptVector_literal_start;
309 extern char _DebugInterruptVector_text_end;
310 extern char _KernelExceptionVector_literal_start;
311 extern char _KernelExceptionVector_text_end;
312 extern char _UserExceptionVector_literal_start;
313 extern char _UserExceptionVector_text_end;
314 extern char _DoubleExceptionVector_literal_start;
315 extern char _DoubleExceptionVector_text_end;
316 #if XCHAL_EXCM_LEVEL >= 2
317 extern char _Level2InterruptVector_text_start;
318 extern char _Level2InterruptVector_text_end;
320 #if XCHAL_EXCM_LEVEL >= 3
321 extern char _Level3InterruptVector_text_start;
322 extern char _Level3InterruptVector_text_end;
324 #if XCHAL_EXCM_LEVEL >= 4
325 extern char _Level4InterruptVector_text_start;
326 extern char _Level4InterruptVector_text_end;
328 #if XCHAL_EXCM_LEVEL >= 5
329 extern char _Level5InterruptVector_text_start;
330 extern char _Level5InterruptVector_text_end;
332 #if XCHAL_EXCM_LEVEL >= 6
333 extern char _Level6InterruptVector_text_start;
334 extern char _Level6InterruptVector_text_end;
337 extern char _SecondaryResetVector_text_start;
338 extern char _SecondaryResetVector_text_end;
342 #ifdef CONFIG_S32C1I_SELFTEST
343 #if XCHAL_HAVE_S32C1I
345 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
348 * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
350 * If *v == cmp, set *v = set. Return previous *v.
352 static inline int probed_compare_swap(int *v, int cmp, int set)
356 __asm__ __volatile__(
359 " wsr %2, scompare1\n"
360 "1: s32c1i %0, %3, 0\n"
361 : "=a" (set), "=&a" (tmp)
362 : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
368 /* Handle probed exception */
370 static void __init do_probed_exception(struct pt_regs *regs,
371 unsigned long exccause)
373 if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
374 regs->pc += 3; /* skip the s32c1i instruction */
377 do_unhandled(regs, exccause);
381 /* Simple test of S32C1I (soc bringup assist) */
383 static int __init check_s32c1i(void)
385 int n, cause1, cause2;
386 void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
389 handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
390 do_probed_exception);
391 handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
392 do_probed_exception);
393 handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
394 do_probed_exception);
396 /* First try an S32C1I that does not store: */
399 n = probed_compare_swap(&rcw_word, 0, 2);
402 /* took exception? */
404 /* unclean exception? */
405 if (n != 2 || rcw_word != 1)
406 panic("S32C1I exception error");
407 } else if (rcw_word != 1 || n != 1) {
408 panic("S32C1I compare error");
411 /* Then an S32C1I that stores: */
413 rcw_word = 0x1234567;
414 n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
418 /* unclean exception? */
419 if (n != 0xabcde || rcw_word != 0x1234567)
420 panic("S32C1I exception error (b)");
421 } else if (rcw_word != 0xabcde || n != 0x1234567) {
422 panic("S32C1I store error");
425 /* Verify consistency of exceptions: */
426 if (cause1 || cause2) {
427 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
428 /* If emulation of S32C1I upon bus error gets implemented,
429 we can get rid of this panic for single core (not SMP) */
430 panic("S32C1I exceptions not currently supported");
432 if (cause1 != cause2)
433 panic("inconsistent S32C1I exceptions");
435 trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
436 trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
437 trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
441 #else /* XCHAL_HAVE_S32C1I */
443 /* This condition should not occur with a commercially deployed processor.
444 Display reminder for early engr test or demo chips / FPGA bitstreams */
445 static int __init check_s32c1i(void)
447 pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
451 #endif /* XCHAL_HAVE_S32C1I */
452 early_initcall(check_s32c1i);
453 #endif /* CONFIG_S32C1I_SELFTEST */
456 void __init setup_arch(char **cmdline_p)
458 strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
459 *cmdline_p = command_line;
461 /* Reserve some memory regions */
463 #ifdef CONFIG_BLK_DEV_INITRD
464 if (initrd_start < initrd_end) {
465 initrd_is_mapped = mem_reserve(__pa(initrd_start),
466 __pa(initrd_end), 0) == 0;
467 initrd_below_start_ok = 1;
473 mem_reserve(__pa(&_stext),__pa(&_end), 1);
475 mem_reserve(__pa(&_WindowVectors_text_start),
476 __pa(&_WindowVectors_text_end), 0);
478 mem_reserve(__pa(&_DebugInterruptVector_literal_start),
479 __pa(&_DebugInterruptVector_text_end), 0);
481 mem_reserve(__pa(&_KernelExceptionVector_literal_start),
482 __pa(&_KernelExceptionVector_text_end), 0);
484 mem_reserve(__pa(&_UserExceptionVector_literal_start),
485 __pa(&_UserExceptionVector_text_end), 0);
487 mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
488 __pa(&_DoubleExceptionVector_text_end), 0);
490 #if XCHAL_EXCM_LEVEL >= 2
491 mem_reserve(__pa(&_Level2InterruptVector_text_start),
492 __pa(&_Level2InterruptVector_text_end), 0);
494 #if XCHAL_EXCM_LEVEL >= 3
495 mem_reserve(__pa(&_Level3InterruptVector_text_start),
496 __pa(&_Level3InterruptVector_text_end), 0);
498 #if XCHAL_EXCM_LEVEL >= 4
499 mem_reserve(__pa(&_Level4InterruptVector_text_start),
500 __pa(&_Level4InterruptVector_text_end), 0);
502 #if XCHAL_EXCM_LEVEL >= 5
503 mem_reserve(__pa(&_Level5InterruptVector_text_start),
504 __pa(&_Level5InterruptVector_text_end), 0);
506 #if XCHAL_EXCM_LEVEL >= 6
507 mem_reserve(__pa(&_Level6InterruptVector_text_start),
508 __pa(&_Level6InterruptVector_text_end), 0);
512 mem_reserve(__pa(&_SecondaryResetVector_text_start),
513 __pa(&_SecondaryResetVector_text_end), 0);
518 unflatten_and_copy_device_tree();
520 platform_setup(cmdline_p);
530 # if defined(CONFIG_VGA_CONSOLE)
531 conswitchp = &vga_con;
532 # elif defined(CONFIG_DUMMY_CONSOLE)
533 conswitchp = &dummy_con;
538 platform_pcibios_init();
542 static DEFINE_PER_CPU(struct cpu, cpu_data);
544 static int __init topology_init(void)
548 for_each_possible_cpu(i) {
549 struct cpu *cpu = &per_cpu(cpu_data, i);
550 cpu->hotpluggable = !!i;
551 register_cpu(cpu, i);
556 subsys_initcall(topology_init);
558 void machine_restart(char * cmd)
563 void machine_halt(void)
569 void machine_power_off(void)
571 platform_power_off();
574 #ifdef CONFIG_PROC_FS
577 * Display some core information through /proc/cpuinfo.
581 c_show(struct seq_file *f, void *slot)
583 /* high-level stuff */
584 seq_printf(f, "CPU count\t: %u\n"
585 "CPU list\t: %*pbl\n"
586 "vendor_id\t: Tensilica\n"
587 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
588 "core ID\t\t: " XCHAL_CORE_ID "\n"
591 "cpu MHz\t\t: %lu.%02lu\n"
592 "bogomips\t: %lu.%02lu\n",
594 cpumask_pr_args(cpu_online_mask),
595 XCHAL_BUILD_UNIQUE_ID,
596 XCHAL_HAVE_BE ? "big" : "little",
598 (ccount_freq/10000) % 100,
599 loops_per_jiffy/(500000/HZ),
600 (loops_per_jiffy/(5000/HZ)) % 100);
602 seq_printf(f,"flags\t\t: "
612 #if XCHAL_HAVE_DENSITY
615 #if XCHAL_HAVE_BOOLEANS
624 #if XCHAL_HAVE_MINMAX
630 #if XCHAL_HAVE_CLAMPS
642 #if XCHAL_HAVE_MUL32_HIGH
648 #if XCHAL_HAVE_S32C1I
654 seq_printf(f,"physical aregs\t: %d\n"
665 seq_printf(f,"num ints\t: %d\n"
669 "debug level\t: %d\n",
670 XCHAL_NUM_INTERRUPTS,
671 XCHAL_NUM_EXTINTERRUPTS,
677 seq_printf(f,"icache line size: %d\n"
678 "icache ways\t: %d\n"
679 "icache size\t: %d\n"
681 #if XCHAL_ICACHE_LINE_LOCKABLE
685 "dcache line size: %d\n"
686 "dcache ways\t: %d\n"
687 "dcache size\t: %d\n"
689 #if XCHAL_DCACHE_IS_WRITEBACK
692 #if XCHAL_DCACHE_LINE_LOCKABLE
696 XCHAL_ICACHE_LINESIZE,
699 XCHAL_DCACHE_LINESIZE,
707 * We show only CPU #0 info.
710 c_start(struct seq_file *f, loff_t *pos)
712 return (*pos == 0) ? (void *)1 : NULL;
716 c_next(struct seq_file *f, void *v, loff_t *pos)
722 c_stop(struct seq_file *f, void *v)
726 const struct seq_operations cpuinfo_op =
734 #endif /* CONFIG_PROC_FS */