arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/proto.h>
  43 #include <asm/mach_apic.h>
  44 #include <asm/acpi.h>
  45 #include <asm/dma.h>
  46 #include <asm/nmi.h>
  47 #include <asm/msidef.h>
  48 #include <asm/hypertransport.h>
  49
  50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
  51
  52 #define __apicdebuginit  __init
  53
  54 int sis_apic_bug; /* not actually supported, dummy for compile */
  55
  56 static int no_timer_check;
  57
  58 static int disable_timer_pin_1 __initdata;
  59
  60 int timer_over_8254 __initdata = 1;
  61
  62 /* Where if anywhere is the i8259 connect in external int mode */
  63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  64
  65 static DEFINE_SPINLOCK(ioapic_lock);
  66 DEFINE_SPINLOCK(vector_lock);
  67
  68 /*
  69  * # of IRQ routing registers
  70  */
  71 int nr_ioapic_registers[MAX_IO_APICS];
  72
  73 /*
  74  * Rough estimation of how many shared IRQs there are, can
  75  * be changed anytime.
  76  */
  77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  79
  80 /*
  81  * This is performance-critical, we want to do it O(1)
  82  *
  83  * the indexing order of this array favors 1:1 mappings
  84  * between pins and IRQs.
  85  */
  86
  87 static struct irq_pin_list {
  88         short apic, pin, next;
  89 } irq_2_pin[PIN_MAP_SIZE];
  90
  91 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  92                                                                         \
  93 {                                                                       \
  94         int pin;                                                        \
  95         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  96                                                                         \
  97         BUG_ON(irq >= NR_IRQS);                                         \
  98         for (;;) {                                                      \
  99                 unsigned int reg;                                       \
 100                 pin = entry->pin;                                       \
 101                 if (pin == -1)                                          \
 102                         break;                                          \
 103                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 104                 reg ACTION;                                             \
 105                 io_apic_modify(entry->apic, reg);                       \
 106                 if (!entry->next)                                       \
 107                         break;                                          \
 108                 entry = irq_2_pin + entry->next;                        \
 109         }                                                               \
 110         FINAL;                                                          \
 111 }
 112
 113 union entry_union {
 114         struct { u32 w1, w2; };
 115         struct IO_APIC_route_entry entry;
 116 };
 117
 118 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 119 {
 120         union entry_union eu;
 121         unsigned long flags;
 122         spin_lock_irqsave(&ioapic_lock, flags);
 123         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 124         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 125         spin_unlock_irqrestore(&ioapic_lock, flags);
 126         return eu.entry;
 127 }
 128
 129 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 130 {
 131         unsigned long flags;
 132         union entry_union eu;
 133         eu.entry = e;
 134         spin_lock_irqsave(&ioapic_lock, flags);
 135         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 136         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 137         spin_unlock_irqrestore(&ioapic_lock, flags);
 138 }
 139
 140 #ifdef CONFIG_SMP
 141 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 142 {
 143         int apic, pin;
 144         struct irq_pin_list *entry = irq_2_pin + irq;
 145
 146         BUG_ON(irq >= NR_IRQS);
 147         for (;;) {
 148                 unsigned int reg;
 149                 apic = entry->apic;
 150                 pin = entry->pin;
 151                 if (pin == -1)
 152                         break;
 153                 io_apic_write(apic, 0x11 + pin*2, dest);
 154                 reg = io_apic_read(apic, 0x10 + pin*2);
 155                 reg &= ~0x000000ff;
 156                 reg |= vector;
 157                 io_apic_modify(apic, reg);
 158                 if (!entry->next)
 159                         break;
 160                 entry = irq_2_pin + entry->next;
 161         }
 162 }
 163
 164 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 165 {
 166         unsigned long flags;
 167         unsigned int dest;
 168         cpumask_t tmp;
 169         int vector;
 170
 171         cpus_and(tmp, mask, cpu_online_map);
 172         if (cpus_empty(tmp))
 173                 tmp = TARGET_CPUS;
 174
 175         cpus_and(mask, tmp, CPU_MASK_ALL);
 176
 177         vector = assign_irq_vector(irq, mask, &tmp);
 178         if (vector < 0)
 179                 return;
 180
 181         dest = cpu_mask_to_apicid(tmp);
 182
 183         /*
 184          * Only the high 8 bits are valid.
 185          */
 186         dest = SET_APIC_LOGICAL_ID(dest);
 187
 188         spin_lock_irqsave(&ioapic_lock, flags);
 189         __target_IO_APIC_irq(irq, dest, vector);
 190         set_native_irq_info(irq, mask);
 191         spin_unlock_irqrestore(&ioapic_lock, flags);
 192 }
 193 #endif
 194
 195 /*
 196  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 197  * shared ISA-space IRQs, so we have to support them. We are super
 198  * fast in the common case, and fast for shared ISA-space IRQs.
 199  */
 200 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 201 {
 202         static int first_free_entry = NR_IRQS;
 203         struct irq_pin_list *entry = irq_2_pin + irq;
 204
 205         BUG_ON(irq >= NR_IRQS);
 206         while (entry->next)
 207                 entry = irq_2_pin + entry->next;
 208
 209         if (entry->pin != -1) {
 210                 entry->next = first_free_entry;
 211                 entry = irq_2_pin + entry->next;
 212                 if (++first_free_entry >= PIN_MAP_SIZE)
 213                         panic("io_apic.c: ran out of irq_2_pin entries!");
 214         }
 215         entry->apic = apic;
 216         entry->pin = pin;
 217 }
 218
 219
 220 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 221                                                                         \
 222         static void name##_IO_APIC_irq (unsigned int irq)               \
 223         __DO_ACTION(R, ACTION, FINAL)
 224
 225 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 226                                                 /* mask = 1 */
 227 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 228                                                 /* mask = 0 */
 229
 230 static void mask_IO_APIC_irq (unsigned int irq)
 231 {
 232         unsigned long flags;
 233
 234         spin_lock_irqsave(&ioapic_lock, flags);
 235         __mask_IO_APIC_irq(irq);
 236         spin_unlock_irqrestore(&ioapic_lock, flags);
 237 }
 238
 239 static void unmask_IO_APIC_irq (unsigned int irq)
 240 {
 241         unsigned long flags;
 242
 243         spin_lock_irqsave(&ioapic_lock, flags);
 244         __unmask_IO_APIC_irq(irq);
 245         spin_unlock_irqrestore(&ioapic_lock, flags);
 246 }
 247
 248 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 249 {
 250         struct IO_APIC_route_entry entry;
 251
 252         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 253         entry = ioapic_read_entry(apic, pin);
 254         if (entry.delivery_mode == dest_SMI)
 255                 return;
 256         /*
 257          * Disable it in the IO-APIC irq-routing table:
 258          */
 259         memset(&entry, 0, sizeof(entry));
 260         entry.mask = 1;
 261         ioapic_write_entry(apic, pin, entry);
 262 }
 263
 264 static void clear_IO_APIC (void)
 265 {
 266         int apic, pin;
 267
 268         for (apic = 0; apic < nr_ioapics; apic++)
 269                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 270                         clear_IO_APIC_pin(apic, pin);
 271 }
 272
 273 int skip_ioapic_setup;
 274 int ioapic_force;
 275
 276 /* dummy parsing: see setup.c */
 277
 278 static int __init disable_ioapic_setup(char *str)
 279 {
 280         skip_ioapic_setup = 1;
 281         return 0;
 282 }
 283 early_param("noapic", disable_ioapic_setup);
 284
 285 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 286 static int __init disable_timer_pin_setup(char *arg)
 287 {
 288         disable_timer_pin_1 = 1;
 289         return 1;
 290 }
 291 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 292
 293 static int __init setup_disable_8254_timer(char *s)
 294 {
 295         timer_over_8254 = -1;
 296         return 1;
 297 }
 298 static int __init setup_enable_8254_timer(char *s)
 299 {
 300         timer_over_8254 = 2;
 301         return 1;
 302 }
 303
 304 __setup("disable_8254_timer", setup_disable_8254_timer);
 305 __setup("enable_8254_timer", setup_enable_8254_timer);
 306
 307
 308 /*
 309  * Find the IRQ entry number of a certain pin.
 310  */
 311 static int find_irq_entry(int apic, int pin, int type)
 312 {
 313         int i;
 314
 315         for (i = 0; i < mp_irq_entries; i++)
 316                 if (mp_irqs[i].mpc_irqtype == type &&
 317                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 318                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 319                     mp_irqs[i].mpc_dstirq == pin)
 320                         return i;
 321
 322         return -1;
 323 }
 324
 325 /*
 326  * Find the pin to which IRQ[irq] (ISA) is connected
 327  */
 328 static int __init find_isa_irq_pin(int irq, int type)
 329 {
 330         int i;
 331
 332         for (i = 0; i < mp_irq_entries; i++) {
 333                 int lbus = mp_irqs[i].mpc_srcbus;
 334
 335                 if (test_bit(lbus, mp_bus_not_pci) &&
 336                     (mp_irqs[i].mpc_irqtype == type) &&
 337                     (mp_irqs[i].mpc_srcbusirq == irq))
 338
 339                         return mp_irqs[i].mpc_dstirq;
 340         }
 341         return -1;
 342 }
 343
 344 static int __init find_isa_irq_apic(int irq, int type)
 345 {
 346         int i;
 347
 348         for (i = 0; i < mp_irq_entries; i++) {
 349                 int lbus = mp_irqs[i].mpc_srcbus;
 350
 351                 if (test_bit(lbus, mp_bus_not_pci) &&
 352                     (mp_irqs[i].mpc_irqtype == type) &&
 353                     (mp_irqs[i].mpc_srcbusirq == irq))
 354                         break;
 355         }
 356         if (i < mp_irq_entries) {
 357                 int apic;
 358                 for(apic = 0; apic < nr_ioapics; apic++) {
 359                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 360                                 return apic;
 361                 }
 362         }
 363
 364         return -1;
 365 }
 366
 367 /*
 368  * Find a specific PCI IRQ entry.
 369  * Not an __init, possibly needed by modules
 370  */
 371 static int pin_2_irq(int idx, int apic, int pin);
 372
 373 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 374 {
 375         int apic, i, best_guess = -1;
 376
 377         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 378                 bus, slot, pin);
 379         if (mp_bus_id_to_pci_bus[bus] == -1) {
 380                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 381                 return -1;
 382         }
 383         for (i = 0; i < mp_irq_entries; i++) {
 384                 int lbus = mp_irqs[i].mpc_srcbus;
 385
 386                 for (apic = 0; apic < nr_ioapics; apic++)
 387                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 388                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 389                                 break;
 390
 391                 if (!test_bit(lbus, mp_bus_not_pci) &&
 392                     !mp_irqs[i].mpc_irqtype &&
 393                     (bus == lbus) &&
 394                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 395                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 396
 397                         if (!(apic || IO_APIC_IRQ(irq)))
 398                                 continue;
 399
 400                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 401                                 return irq;
 402                         /*
 403                          * Use the first all-but-pin matching entry as a
 404                          * best-guess fuzzy result for broken mptables.
 405                          */
 406                         if (best_guess < 0)
 407                                 best_guess = irq;
 408                 }
 409         }
 410         BUG_ON(best_guess >= NR_IRQS);
 411         return best_guess;
 412 }
 413
 414 /* ISA interrupts are always polarity zero edge triggered,
 415  * when listed as conforming in the MP table. */
 416
 417 #define default_ISA_trigger(idx)        (0)
 418 #define default_ISA_polarity(idx)       (0)
 419
 420 /* PCI interrupts are always polarity one level triggered,
 421  * when listed as conforming in the MP table. */
 422
 423 #define default_PCI_trigger(idx)        (1)
 424 #define default_PCI_polarity(idx)       (1)
 425
 426 static int __init MPBIOS_polarity(int idx)
 427 {
 428         int bus = mp_irqs[idx].mpc_srcbus;
 429         int polarity;
 430
 431         /*
 432          * Determine IRQ line polarity (high active or low active):
 433          */
 434         switch (mp_irqs[idx].mpc_irqflag & 3)
 435         {
 436                 case 0: /* conforms, ie. bus-type dependent polarity */
 437                         if (test_bit(bus, mp_bus_not_pci))
 438                                 polarity = default_ISA_polarity(idx);
 439                         else
 440                                 polarity = default_PCI_polarity(idx);
 441                         break;
 442                 case 1: /* high active */
 443                 {
 444                         polarity = 0;
 445                         break;
 446                 }
 447                 case 2: /* reserved */
 448                 {
 449                         printk(KERN_WARNING "broken BIOS!!\n");
 450                         polarity = 1;
 451                         break;
 452                 }
 453                 case 3: /* low active */
 454                 {
 455                         polarity = 1;
 456                         break;
 457                 }
 458                 default: /* invalid */
 459                 {
 460                         printk(KERN_WARNING "broken BIOS!!\n");
 461                         polarity = 1;
 462                         break;
 463                 }
 464         }
 465         return polarity;
 466 }
 467
 468 static int MPBIOS_trigger(int idx)
 469 {
 470         int bus = mp_irqs[idx].mpc_srcbus;
 471         int trigger;
 472
 473         /*
 474          * Determine IRQ trigger mode (edge or level sensitive):
 475          */
 476         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 477         {
 478                 case 0: /* conforms, ie. bus-type dependent */
 479                         if (test_bit(bus, mp_bus_not_pci))
 480                                 trigger = default_ISA_trigger(idx);
 481                         else
 482                                 trigger = default_PCI_trigger(idx);
 483                         break;
 484                 case 1: /* edge */
 485                 {
 486                         trigger = 0;
 487                         break;
 488                 }
 489                 case 2: /* reserved */
 490                 {
 491                         printk(KERN_WARNING "broken BIOS!!\n");
 492                         trigger = 1;
 493                         break;
 494                 }
 495                 case 3: /* level */
 496                 {
 497                         trigger = 1;
 498                         break;
 499                 }
 500                 default: /* invalid */
 501                 {
 502                         printk(KERN_WARNING "broken BIOS!!\n");
 503                         trigger = 0;
 504                         break;
 505                 }
 506         }
 507         return trigger;
 508 }
 509
 510 static inline int irq_polarity(int idx)
 511 {
 512         return MPBIOS_polarity(idx);
 513 }
 514
 515 static inline int irq_trigger(int idx)
 516 {
 517         return MPBIOS_trigger(idx);
 518 }
 519
 520 static int pin_2_irq(int idx, int apic, int pin)
 521 {
 522         int irq, i;
 523         int bus = mp_irqs[idx].mpc_srcbus;
 524
 525         /*
 526          * Debugging check, we are in big trouble if this message pops up!
 527          */
 528         if (mp_irqs[idx].mpc_dstirq != pin)
 529                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 530
 531         if (test_bit(bus, mp_bus_not_pci)) {
 532                 irq = mp_irqs[idx].mpc_srcbusirq;
 533         } else {
 534                 /*
 535                  * PCI IRQs are mapped in order
 536                  */
 537                 i = irq = 0;
 538                 while (i < apic)
 539                         irq += nr_ioapic_registers[i++];
 540                 irq += pin;
 541         }
 542         BUG_ON(irq >= NR_IRQS);
 543         return irq;
 544 }
 545
 546 static inline int IO_APIC_irq_trigger(int irq)
 547 {
 548         int apic, idx, pin;
 549
 550         for (apic = 0; apic < nr_ioapics; apic++) {
 551                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 552                         idx = find_irq_entry(apic,pin,mp_INT);
 553                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 554                                 return irq_trigger(idx);
 555                 }
 556         }
 557         /*
 558          * nonexistent IRQs are edge default
 559          */
 560         return 0;
 561 }
 562
 563 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 564 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
 565         [0] = FIRST_EXTERNAL_VECTOR + 0,
 566         [1] = FIRST_EXTERNAL_VECTOR + 1,
 567         [2] = FIRST_EXTERNAL_VECTOR + 2,
 568         [3] = FIRST_EXTERNAL_VECTOR + 3,
 569         [4] = FIRST_EXTERNAL_VECTOR + 4,
 570         [5] = FIRST_EXTERNAL_VECTOR + 5,
 571         [6] = FIRST_EXTERNAL_VECTOR + 6,
 572         [7] = FIRST_EXTERNAL_VECTOR + 7,
 573         [8] = FIRST_EXTERNAL_VECTOR + 8,
 574         [9] = FIRST_EXTERNAL_VECTOR + 9,
 575         [10] = FIRST_EXTERNAL_VECTOR + 10,
 576         [11] = FIRST_EXTERNAL_VECTOR + 11,
 577         [12] = FIRST_EXTERNAL_VECTOR + 12,
 578         [13] = FIRST_EXTERNAL_VECTOR + 13,
 579         [14] = FIRST_EXTERNAL_VECTOR + 14,
 580         [15] = FIRST_EXTERNAL_VECTOR + 15,
 581 };
 582
 583 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
 584         [0] = CPU_MASK_ALL,
 585         [1] = CPU_MASK_ALL,
 586         [2] = CPU_MASK_ALL,
 587         [3] = CPU_MASK_ALL,
 588         [4] = CPU_MASK_ALL,
 589         [5] = CPU_MASK_ALL,
 590         [6] = CPU_MASK_ALL,
 591         [7] = CPU_MASK_ALL,
 592         [8] = CPU_MASK_ALL,
 593         [9] = CPU_MASK_ALL,
 594         [10] = CPU_MASK_ALL,
 595         [11] = CPU_MASK_ALL,
 596         [12] = CPU_MASK_ALL,
 597         [13] = CPU_MASK_ALL,
 598         [14] = CPU_MASK_ALL,
 599         [15] = CPU_MASK_ALL,
 600 };
 601
 602 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 603 {
 604         /*
 605          * NOTE! The local APIC isn't very good at handling
 606          * multiple interrupts at the same interrupt level.
 607          * As the interrupt level is determined by taking the
 608          * vector number and shifting that right by 4, we
 609          * want to spread these out a bit so that they don't
 610          * all fall in the same interrupt level.
 611          *
 612          * Also, we've got to be careful not to trash gate
 613          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 614          */
 615         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 616         int old_vector = -1;
 617         int cpu;
 618
 619         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
 620
 621         /* Only try and allocate irqs on cpus that are present */
 622         cpus_and(mask, mask, cpu_online_map);
 623
 624         if (irq_vector[irq] > 0)
 625                 old_vector = irq_vector[irq];
 626         if (old_vector > 0) {
 627                 cpus_and(*result, irq_domain[irq], mask);
 628                 if (!cpus_empty(*result))
 629                         return old_vector;
 630         }
 631
 632         for_each_cpu_mask(cpu, mask) {
 633                 cpumask_t domain, new_mask;
 634                 int new_cpu;
 635                 int vector, offset;
 636
 637                 domain = vector_allocation_domain(cpu);
 638                 cpus_and(new_mask, domain, cpu_online_map);
 639
 640                 vector = current_vector;
 641                 offset = current_offset;
 642 next:
 643                 vector += 8;
 644                 if (vector >= FIRST_SYSTEM_VECTOR) {
 645                         /* If we run out of vectors on large boxen, must share them. */
 646                         offset = (offset + 1) % 8;
 647                         vector = FIRST_DEVICE_VECTOR + offset;
 648                 }
 649                 if (unlikely(current_vector == vector))
 650                         continue;
 651                 if (vector == IA32_SYSCALL_VECTOR)
 652                         goto next;
 653                 for_each_cpu_mask(new_cpu, new_mask)
 654                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 655                                 goto next;
 656                 /* Found one! */
 657                 current_vector = vector;
 658                 current_offset = offset;
 659                 if (old_vector >= 0) {
 660                         cpumask_t old_mask;
 661                         int old_cpu;
 662                         cpus_and(old_mask, irq_domain[irq], cpu_online_map);
 663                         for_each_cpu_mask(old_cpu, old_mask)
 664                                 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
 665                 }
 666                 for_each_cpu_mask(new_cpu, new_mask)
 667                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 668                 irq_vector[irq] = vector;
 669                 irq_domain[irq] = domain;
 670                 cpus_and(*result, domain, mask);
 671                 return vector;
 672         }
 673         return -ENOSPC;
 674 }
 675
 676 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 677 {
 678         int vector;
 679         unsigned long flags;
 680
 681         spin_lock_irqsave(&vector_lock, flags);
 682         vector = __assign_irq_vector(irq, mask, result);
 683         spin_unlock_irqrestore(&vector_lock, flags);
 684         return vector;
 685 }
 686
 687 void __setup_vector_irq(int cpu)
 688 {
 689         /* Initialize vector_irq on a new cpu */
 690         /* This function must be called with vector_lock held */
 691         unsigned long flags;
 692         int irq, vector;
 693
 694
 695         /* Mark the inuse vectors */
 696         for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
 697                 if (!cpu_isset(cpu, irq_domain[irq]))
 698                         continue;
 699                 vector = irq_vector[irq];
 700                 per_cpu(vector_irq, cpu)[vector] = irq;
 701         }
 702         /* Mark the free vectors */
 703         for (vector = 0; vector < NR_VECTORS; ++vector) {
 704                 irq = per_cpu(vector_irq, cpu)[vector];
 705                 if (irq < 0)
 706                         continue;
 707                 if (!cpu_isset(cpu, irq_domain[irq]))
 708                         per_cpu(vector_irq, cpu)[vector] = -1;
 709         }
 710 }
 711
 712
 713 extern void (*interrupt[NR_IRQS])(void);
 714
 715 static struct irq_chip ioapic_chip;
 716
 717 #define IOAPIC_AUTO     -1
 718 #define IOAPIC_EDGE     0
 719 #define IOAPIC_LEVEL    1
 720
 721 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 722 {
 723         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 724                         trigger == IOAPIC_LEVEL)
 725                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 726                                               handle_fasteoi_irq, "fasteoi");
 727         else
 728                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 729                                               handle_edge_irq, "edge");
 730 }
 731
 732 static void __init setup_IO_APIC_irqs(void)
 733 {
 734         struct IO_APIC_route_entry entry;
 735         int apic, pin, idx, irq, first_notcon = 1, vector;
 736         unsigned long flags;
 737
 738         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 739
 740         for (apic = 0; apic < nr_ioapics; apic++) {
 741         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 742
 743                 /*
 744                  * add it to the IO-APIC irq-routing table:
 745                  */
 746                 memset(&entry,0,sizeof(entry));
 747
 748                 entry.delivery_mode = INT_DELIVERY_MODE;
 749                 entry.dest_mode = INT_DEST_MODE;
 750                 entry.mask = 0;                         /* enable IRQ */
 751                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 752
 753                 idx = find_irq_entry(apic,pin,mp_INT);
 754                 if (idx == -1) {
 755                         if (first_notcon) {
 756                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 757                                 first_notcon = 0;
 758                         } else
 759                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 760                         continue;
 761                 }
 762
 763                 entry.trigger = irq_trigger(idx);
 764                 entry.polarity = irq_polarity(idx);
 765
 766                 if (irq_trigger(idx)) {
 767                         entry.trigger = 1;
 768                         entry.mask = 1;
 769                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 770                 }
 771
 772                 irq = pin_2_irq(idx, apic, pin);
 773                 add_pin_to_irq(irq, apic, pin);
 774
 775                 if (!apic && !IO_APIC_IRQ(irq))
 776                         continue;
 777
 778                 if (IO_APIC_IRQ(irq)) {
 779                         cpumask_t mask;
 780                         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
 781                         if (vector < 0)
 782                                 continue;
 783
 784                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
 785                         entry.vector = vector;
 786
 787                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 788                         if (!apic && (irq < 16))
 789                                 disable_8259A_irq(irq);
 790                 }
 791                 ioapic_write_entry(apic, pin, entry);
 792
 793                 spin_lock_irqsave(&ioapic_lock, flags);
 794                 set_native_irq_info(irq, TARGET_CPUS);
 795                 spin_unlock_irqrestore(&ioapic_lock, flags);
 796         }
 797         }
 798
 799         if (!first_notcon)
 800                 apic_printk(APIC_VERBOSE," not connected.\n");
 801 }
 802
 803 /*
 804  * Set up the 8259A-master output pin as broadcast to all
 805  * CPUs.
 806  */
 807 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 808 {
 809         struct IO_APIC_route_entry entry;
 810         unsigned long flags;
 811
 812         memset(&entry,0,sizeof(entry));
 813
 814         disable_8259A_irq(0);
 815
 816         /* mask LVT0 */
 817         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 818
 819         /*
 820          * We use logical delivery to get the timer IRQ
 821          * to the first CPU.
 822          */
 823         entry.dest_mode = INT_DEST_MODE;
 824         entry.mask = 0;                                 /* unmask IRQ now */
 825         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 826         entry.delivery_mode = INT_DELIVERY_MODE;
 827         entry.polarity = 0;
 828         entry.trigger = 0;
 829         entry.vector = vector;
 830
 831         /*
 832          * The timer IRQ doesn't have to know that behind the
 833          * scene we have a 8259A-master in AEOI mode ...
 834          */
 835         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 836
 837         /*
 838          * Add it to the IO-APIC irq-routing table:
 839          */
 840         spin_lock_irqsave(&ioapic_lock, flags);
 841         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 842         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 843         spin_unlock_irqrestore(&ioapic_lock, flags);
 844
 845         enable_8259A_irq(0);
 846 }
 847
 848 void __init UNEXPECTED_IO_APIC(void)
 849 {
 850 }
 851
 852 void __apicdebuginit print_IO_APIC(void)
 853 {
 854         int apic, i;
 855         union IO_APIC_reg_00 reg_00;
 856         union IO_APIC_reg_01 reg_01;
 857         union IO_APIC_reg_02 reg_02;
 858         unsigned long flags;
 859
 860         if (apic_verbosity == APIC_QUIET)
 861                 return;
 862
 863         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 864         for (i = 0; i < nr_ioapics; i++)
 865                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 866                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 867
 868         /*
 869          * We are a bit conservative about what we expect.  We have to
 870          * know about every hardware change ASAP.
 871          */
 872         printk(KERN_INFO "testing the IO APIC.......................\n");
 873
 874         for (apic = 0; apic < nr_ioapics; apic++) {
 875
 876         spin_lock_irqsave(&ioapic_lock, flags);
 877         reg_00.raw = io_apic_read(apic, 0);
 878         reg_01.raw = io_apic_read(apic, 1);
 879         if (reg_01.bits.version >= 0x10)
 880                 reg_02.raw = io_apic_read(apic, 2);
 881         spin_unlock_irqrestore(&ioapic_lock, flags);
 882
 883         printk("\n");
 884         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 885         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 886         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 887         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 888                 UNEXPECTED_IO_APIC();
 889
 890         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 891         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 892         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 893                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 894                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 895                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 896                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 897                 (reg_01.bits.entries != 0x2E) &&
 898                 (reg_01.bits.entries != 0x3F) &&
 899                 (reg_01.bits.entries != 0x03)
 900         )
 901                 UNEXPECTED_IO_APIC();
 902
 903         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 904         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 905         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 906                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 907                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 908                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 909                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 910                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 911         )
 912                 UNEXPECTED_IO_APIC();
 913         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 914                 UNEXPECTED_IO_APIC();
 915
 916         if (reg_01.bits.version >= 0x10) {
 917                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 918                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 919                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 920                         UNEXPECTED_IO_APIC();
 921         }
 922
 923         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 924
 925         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 926                           " Stat Dest Deli Vect:   \n");
 927
 928         for (i = 0; i <= reg_01.bits.entries; i++) {
 929                 struct IO_APIC_route_entry entry;
 930
 931                 entry = ioapic_read_entry(apic, i);
 932
 933                 printk(KERN_DEBUG " %02x %03X %02X  ",
 934                         i,
 935                         entry.dest.logical.logical_dest,
 936                         entry.dest.physical.physical_dest
 937                 );
 938
 939                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 940                         entry.mask,
 941                         entry.trigger,
 942                         entry.irr,
 943                         entry.polarity,
 944                         entry.delivery_status,
 945                         entry.dest_mode,
 946                         entry.delivery_mode,
 947                         entry.vector
 948                 );
 949         }
 950         }
 951         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 952         for (i = 0; i < NR_IRQS; i++) {
 953                 struct irq_pin_list *entry = irq_2_pin + i;
 954                 if (entry->pin < 0)
 955                         continue;
 956                 printk(KERN_DEBUG "IRQ%d ", i);
 957                 for (;;) {
 958                         printk("-> %d:%d", entry->apic, entry->pin);
 959                         if (!entry->next)
 960                                 break;
 961                         entry = irq_2_pin + entry->next;
 962                 }
 963                 printk("\n");
 964         }
 965
 966         printk(KERN_INFO ".................................... done.\n");
 967
 968         return;
 969 }
 970
 971 #if 0
 972
 973 static __apicdebuginit void print_APIC_bitfield (int base)
 974 {
 975         unsigned int v;
 976         int i, j;
 977
 978         if (apic_verbosity == APIC_QUIET)
 979                 return;
 980
 981         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 982         for (i = 0; i < 8; i++) {
 983                 v = apic_read(base + i*0x10);
 984                 for (j = 0; j < 32; j++) {
 985                         if (v & (1<<j))
 986                                 printk("1");
 987                         else
 988                                 printk("0");
 989                 }
 990                 printk("\n");
 991         }
 992 }
 993
 994 void __apicdebuginit print_local_APIC(void * dummy)
 995 {
 996         unsigned int v, ver, maxlvt;
 997
 998         if (apic_verbosity == APIC_QUIET)
 999                 return;
1000
1001         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1002                 smp_processor_id(), hard_smp_processor_id());
1003         v = apic_read(APIC_ID);
1004         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1005         v = apic_read(APIC_LVR);
1006         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1007         ver = GET_APIC_VERSION(v);
1008         maxlvt = get_maxlvt();
1009
1010         v = apic_read(APIC_TASKPRI);
1011         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1012
1013         v = apic_read(APIC_ARBPRI);
1014         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1015                 v & APIC_ARBPRI_MASK);
1016         v = apic_read(APIC_PROCPRI);
1017         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1018
1019         v = apic_read(APIC_EOI);
1020         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1021         v = apic_read(APIC_RRR);
1022         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1023         v = apic_read(APIC_LDR);
1024         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1025         v = apic_read(APIC_DFR);
1026         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1027         v = apic_read(APIC_SPIV);
1028         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1029
1030         printk(KERN_DEBUG "... APIC ISR field:\n");
1031         print_APIC_bitfield(APIC_ISR);
1032         printk(KERN_DEBUG "... APIC TMR field:\n");
1033         print_APIC_bitfield(APIC_TMR);
1034         printk(KERN_DEBUG "... APIC IRR field:\n");
1035         print_APIC_bitfield(APIC_IRR);
1036
1037         v = apic_read(APIC_ESR);
1038         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1039
1040         v = apic_read(APIC_ICR);
1041         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1042         v = apic_read(APIC_ICR2);
1043         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1044
1045         v = apic_read(APIC_LVTT);
1046         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1047
1048         if (maxlvt > 3) {                       /* PC is LVT#4. */
1049                 v = apic_read(APIC_LVTPC);
1050                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1051         }
1052         v = apic_read(APIC_LVT0);
1053         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1054         v = apic_read(APIC_LVT1);
1055         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1056
1057         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1058                 v = apic_read(APIC_LVTERR);
1059                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1060         }
1061
1062         v = apic_read(APIC_TMICT);
1063         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1064         v = apic_read(APIC_TMCCT);
1065         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1066         v = apic_read(APIC_TDCR);
1067         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1068         printk("\n");
1069 }
1070
1071 void print_all_local_APICs (void)
1072 {
1073         on_each_cpu(print_local_APIC, NULL, 1, 1);
1074 }
1075
1076 void __apicdebuginit print_PIC(void)
1077 {
1078         unsigned int v;
1079         unsigned long flags;
1080
1081         if (apic_verbosity == APIC_QUIET)
1082                 return;
1083
1084         printk(KERN_DEBUG "\nprinting PIC contents\n");
1085
1086         spin_lock_irqsave(&i8259A_lock, flags);
1087
1088         v = inb(0xa1) << 8 | inb(0x21);
1089         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1090
1091         v = inb(0xa0) << 8 | inb(0x20);
1092         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1093
1094         outb(0x0b,0xa0);
1095         outb(0x0b,0x20);
1096         v = inb(0xa0) << 8 | inb(0x20);
1097         outb(0x0a,0xa0);
1098         outb(0x0a,0x20);
1099
1100         spin_unlock_irqrestore(&i8259A_lock, flags);
1101
1102         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1103
1104         v = inb(0x4d1) << 8 | inb(0x4d0);
1105         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1106 }
1107
1108 #endif  /*  0  */
1109
1110 static void __init enable_IO_APIC(void)
1111 {
1112         union IO_APIC_reg_01 reg_01;
1113         int i8259_apic, i8259_pin;
1114         int i, apic;
1115         unsigned long flags;
1116
1117         for (i = 0; i < PIN_MAP_SIZE; i++) {
1118                 irq_2_pin[i].pin = -1;
1119                 irq_2_pin[i].next = 0;
1120         }
1121
1122         /*
1123          * The number of IO-APIC IRQ registers (== #pins):
1124          */
1125         for (apic = 0; apic < nr_ioapics; apic++) {
1126                 spin_lock_irqsave(&ioapic_lock, flags);
1127                 reg_01.raw = io_apic_read(apic, 1);
1128                 spin_unlock_irqrestore(&ioapic_lock, flags);
1129                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1130         }
1131         for(apic = 0; apic < nr_ioapics; apic++) {
1132                 int pin;
1133                 /* See if any of the pins is in ExtINT mode */
1134                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1135                         struct IO_APIC_route_entry entry;
1136                         entry = ioapic_read_entry(apic, pin);
1137
1138                         /* If the interrupt line is enabled and in ExtInt mode
1139                          * I have found the pin where the i8259 is connected.
1140                          */
1141                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1142                                 ioapic_i8259.apic = apic;
1143                                 ioapic_i8259.pin  = pin;
1144                                 goto found_i8259;
1145                         }
1146                 }
1147         }
1148  found_i8259:
1149         /* Look to see what if the MP table has reported the ExtINT */
1150         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1151         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1152         /* Trust the MP table if nothing is setup in the hardware */
1153         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1154                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1155                 ioapic_i8259.pin  = i8259_pin;
1156                 ioapic_i8259.apic = i8259_apic;
1157         }
1158         /* Complain if the MP table and the hardware disagree */
1159         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1160                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1161         {
1162                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1163         }
1164
1165         /*
1166          * Do not trust the IO-APIC being empty at bootup
1167          */
1168         clear_IO_APIC();
1169 }
1170
1171 /*
1172  * Not an __init, needed by the reboot code
1173  */
1174 void disable_IO_APIC(void)
1175 {
1176         /*
1177          * Clear the IO-APIC before rebooting:
1178          */
1179         clear_IO_APIC();
1180
1181         /*
1182          * If the i8259 is routed through an IOAPIC
1183          * Put that IOAPIC in virtual wire mode
1184          * so legacy interrupts can be delivered.
1185          */
1186         if (ioapic_i8259.pin != -1) {
1187                 struct IO_APIC_route_entry entry;
1188
1189                 memset(&entry, 0, sizeof(entry));
1190                 entry.mask            = 0; /* Enabled */
1191                 entry.trigger         = 0; /* Edge */
1192                 entry.irr             = 0;
1193                 entry.polarity        = 0; /* High */
1194                 entry.delivery_status = 0;
1195                 entry.dest_mode       = 0; /* Physical */
1196                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1197                 entry.vector          = 0;
1198                 entry.dest.physical.physical_dest =
1199                                         GET_APIC_ID(apic_read(APIC_ID));
1200
1201                 /*
1202                  * Add it to the IO-APIC irq-routing table:
1203                  */
1204                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1205         }
1206
1207         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1208 }
1209
1210 /*
1211  * There is a nasty bug in some older SMP boards, their mptable lies
1212  * about the timer IRQ. We do the following to work around the situation:
1213  *
1214  *      - timer IRQ defaults to IO-APIC IRQ
1215  *      - if this function detects that timer IRQs are defunct, then we fall
1216  *        back to ISA timer IRQs
1217  */
1218 static int __init timer_irq_works(void)
1219 {
1220         unsigned long t1 = jiffies;
1221
1222         local_irq_enable();
1223         /* Let ten ticks pass... */
1224         mdelay((10 * 1000) / HZ);
1225
1226         /*
1227          * Expect a few ticks at least, to be sure some possible
1228          * glue logic does not lock up after one or two first
1229          * ticks in a non-ExtINT mode.  Also the local APIC
1230          * might have cached one ExtINT interrupt.  Finally, at
1231          * least one tick may be lost due to delays.
1232          */
1233
1234         /* jiffies wrap? */
1235         if (jiffies - t1 > 4)
1236                 return 1;
1237         return 0;
1238 }
1239
1240 /*
1241  * In the SMP+IOAPIC case it might happen that there are an unspecified
1242  * number of pending IRQ events unhandled. These cases are very rare,
1243  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1244  * better to do it this way as thus we do not have to be aware of
1245  * 'pending' interrupts in the IRQ path, except at this point.
1246  */
1247 /*
1248  * Edge triggered needs to resend any interrupt
1249  * that was delayed but this is now handled in the device
1250  * independent code.
1251  */
1252
1253 /*
1254  * Starting up a edge-triggered IO-APIC interrupt is
1255  * nasty - we need to make sure that we get the edge.
1256  * If it is already asserted for some reason, we need
1257  * return 1 to indicate that is was pending.
1258  *
1259  * This is not complete - we should be able to fake
1260  * an edge even if it isn't on the 8259A...
1261  */
1262
1263 static unsigned int startup_ioapic_irq(unsigned int irq)
1264 {
1265         int was_pending = 0;
1266         unsigned long flags;
1267
1268         spin_lock_irqsave(&ioapic_lock, flags);
1269         if (irq < 16) {
1270                 disable_8259A_irq(irq);
1271                 if (i8259A_irq_pending(irq))
1272                         was_pending = 1;
1273         }
1274         __unmask_IO_APIC_irq(irq);
1275         spin_unlock_irqrestore(&ioapic_lock, flags);
1276
1277         return was_pending;
1278 }
1279
1280 static int ioapic_retrigger_irq(unsigned int irq)
1281 {
1282         cpumask_t mask;
1283         unsigned vector;
1284         unsigned long flags;
1285
1286         spin_lock_irqsave(&vector_lock, flags);
1287         vector = irq_vector[irq];
1288         cpus_clear(mask);
1289         cpu_set(first_cpu(irq_domain[irq]), mask);
1290
1291         send_IPI_mask(mask, vector);
1292         spin_unlock_irqrestore(&vector_lock, flags);
1293
1294         return 1;
1295 }
1296
1297 /*
1298  * Level and edge triggered IO-APIC interrupts need different handling,
1299  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1300  * handled with the level-triggered descriptor, but that one has slightly
1301  * more overhead. Level-triggered interrupts cannot be handled with the
1302  * edge-triggered handler, without risking IRQ storms and other ugly
1303  * races.
1304  */
1305
1306 static void ack_apic_edge(unsigned int irq)
1307 {
1308         move_native_irq(irq);
1309         ack_APIC_irq();
1310 }
1311
1312 static void ack_apic_level(unsigned int irq)
1313 {
1314         int do_unmask_irq = 0;
1315
1316 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1317         /* If we are moving the irq we need to mask it */
1318         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1319                 do_unmask_irq = 1;
1320                 mask_IO_APIC_irq(irq);
1321         }
1322 #endif
1323
1324         /*
1325          * We must acknowledge the irq before we move it or the acknowledge will
1326          * not propogate properly.
1327          */
1328         ack_APIC_irq();
1329
1330         /* Now we can move and renable the irq */
1331         move_masked_irq(irq);
1332         if (unlikely(do_unmask_irq))
1333                 unmask_IO_APIC_irq(irq);
1334 }
1335
1336 static struct irq_chip ioapic_chip __read_mostly = {
1337         .name           = "IO-APIC",
1338         .startup        = startup_ioapic_irq,
1339         .mask           = mask_IO_APIC_irq,
1340         .unmask         = unmask_IO_APIC_irq,
1341         .ack            = ack_apic_edge,
1342         .eoi            = ack_apic_level,
1343 #ifdef CONFIG_SMP
1344         .set_affinity   = set_ioapic_affinity_irq,
1345 #endif
1346         .retrigger      = ioapic_retrigger_irq,
1347 };
1348
1349 static inline void init_IO_APIC_traps(void)
1350 {
1351         int irq;
1352
1353         /*
1354          * NOTE! The local APIC isn't very good at handling
1355          * multiple interrupts at the same interrupt level.
1356          * As the interrupt level is determined by taking the
1357          * vector number and shifting that right by 4, we
1358          * want to spread these out a bit so that they don't
1359          * all fall in the same interrupt level.
1360          *
1361          * Also, we've got to be careful not to trash gate
1362          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1363          */
1364         for (irq = 0; irq < NR_IRQS ; irq++) {
1365                 int tmp = irq;
1366                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1367                         /*
1368                          * Hmm.. We don't have an entry for this,
1369                          * so default to an old-fashioned 8259
1370                          * interrupt if we can..
1371                          */
1372                         if (irq < 16)
1373                                 make_8259A_irq(irq);
1374                         else
1375                                 /* Strange. Oh, well.. */
1376                                 irq_desc[irq].chip = &no_irq_chip;
1377                 }
1378         }
1379 }
1380
1381 static void enable_lapic_irq (unsigned int irq)
1382 {
1383         unsigned long v;
1384
1385         v = apic_read(APIC_LVT0);
1386         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1387 }
1388
1389 static void disable_lapic_irq (unsigned int irq)
1390 {
1391         unsigned long v;
1392
1393         v = apic_read(APIC_LVT0);
1394         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1395 }
1396
1397 static void ack_lapic_irq (unsigned int irq)
1398 {
1399         ack_APIC_irq();
1400 }
1401
1402 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1403
1404 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1405         .typename = "local-APIC-edge",
1406         .startup = NULL, /* startup_irq() not used for IRQ0 */
1407         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1408         .enable = enable_lapic_irq,
1409         .disable = disable_lapic_irq,
1410         .ack = ack_lapic_irq,
1411         .end = end_lapic_irq,
1412 };
1413
1414 static void setup_nmi (void)
1415 {
1416         /*
1417          * Dirty trick to enable the NMI watchdog ...
1418          * We put the 8259A master into AEOI mode and
1419          * unmask on all local APICs LVT0 as NMI.
1420          *
1421          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1422          * is from Maciej W. Rozycki - so we do not have to EOI from
1423          * the NMI handler or the timer interrupt.
1424          */
1425         printk(KERN_INFO "activating NMI Watchdog ...");
1426
1427         enable_NMI_through_LVT0(NULL);
1428
1429         printk(" done.\n");
1430 }
1431
1432 /*
1433  * This looks a bit hackish but it's about the only one way of sending
1434  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1435  * not support the ExtINT mode, unfortunately.  We need to send these
1436  * cycles as some i82489DX-based boards have glue logic that keeps the
1437  * 8259A interrupt line asserted until INTA.  --macro
1438  */
1439 static inline void unlock_ExtINT_logic(void)
1440 {
1441         int apic, pin, i;
1442         struct IO_APIC_route_entry entry0, entry1;
1443         unsigned char save_control, save_freq_select;
1444         unsigned long flags;
1445
1446         pin  = find_isa_irq_pin(8, mp_INT);
1447         apic = find_isa_irq_apic(8, mp_INT);
1448         if (pin == -1)
1449                 return;
1450
1451         spin_lock_irqsave(&ioapic_lock, flags);
1452         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1453         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1454         spin_unlock_irqrestore(&ioapic_lock, flags);
1455         clear_IO_APIC_pin(apic, pin);
1456
1457         memset(&entry1, 0, sizeof(entry1));
1458
1459         entry1.dest_mode = 0;                   /* physical delivery */
1460         entry1.mask = 0;                        /* unmask IRQ now */
1461         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1462         entry1.delivery_mode = dest_ExtINT;
1463         entry1.polarity = entry0.polarity;
1464         entry1.trigger = 0;
1465         entry1.vector = 0;
1466
1467         spin_lock_irqsave(&ioapic_lock, flags);
1468         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1469         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1470         spin_unlock_irqrestore(&ioapic_lock, flags);
1471
1472         save_control = CMOS_READ(RTC_CONTROL);
1473         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1474         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1475                    RTC_FREQ_SELECT);
1476         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1477
1478         i = 100;
1479         while (i-- > 0) {
1480                 mdelay(10);
1481                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1482                         i -= 10;
1483         }
1484
1485         CMOS_WRITE(save_control, RTC_CONTROL);
1486         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1487         clear_IO_APIC_pin(apic, pin);
1488
1489         spin_lock_irqsave(&ioapic_lock, flags);
1490         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1491         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1492         spin_unlock_irqrestore(&ioapic_lock, flags);
1493 }
1494
1495 /*
1496  * This code may look a bit paranoid, but it's supposed to cooperate with
1497  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1498  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1499  * fanatically on his truly buggy board.
1500  *
1501  * FIXME: really need to revamp this for modern platforms only.
1502  */
1503 static inline void check_timer(void)
1504 {
1505         int apic1, pin1, apic2, pin2;
1506         int vector;
1507         cpumask_t mask;
1508
1509         /*
1510          * get/set the timer IRQ vector:
1511          */
1512         disable_8259A_irq(0);
1513         vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1514
1515         /*
1516          * Subtle, code in do_timer_interrupt() expects an AEOI
1517          * mode for the 8259A whenever interrupts are routed
1518          * through I/O APICs.  Also IRQ0 has to be enabled in
1519          * the 8259A which implies the virtual wire has to be
1520          * disabled in the local APIC.
1521          */
1522         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1523         init_8259A(1);
1524         if (timer_over_8254 > 0)
1525                 enable_8259A_irq(0);
1526
1527         pin1  = find_isa_irq_pin(0, mp_INT);
1528         apic1 = find_isa_irq_apic(0, mp_INT);
1529         pin2  = ioapic_i8259.pin;
1530         apic2 = ioapic_i8259.apic;
1531
1532         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1533                 vector, apic1, pin1, apic2, pin2);
1534
1535         if (pin1 != -1) {
1536                 /*
1537                  * Ok, does IRQ0 through the IOAPIC work?
1538                  */
1539                 unmask_IO_APIC_irq(0);
1540                 if (!no_timer_check && timer_irq_works()) {
1541                         nmi_watchdog_default();
1542                         if (nmi_watchdog == NMI_IO_APIC) {
1543                                 disable_8259A_irq(0);
1544                                 setup_nmi();
1545                                 enable_8259A_irq(0);
1546                         }
1547                         if (disable_timer_pin_1 > 0)
1548                                 clear_IO_APIC_pin(0, pin1);
1549                         return;
1550                 }
1551                 clear_IO_APIC_pin(apic1, pin1);
1552                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1553                                 "connected to IO-APIC\n");
1554         }
1555
1556         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1557                                 "through the 8259A ... ");
1558         if (pin2 != -1) {
1559                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1560                         apic2, pin2);
1561                 /*
1562                  * legacy devices should be connected to IO APIC #0
1563                  */
1564                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1565                 if (timer_irq_works()) {
1566                         apic_printk(APIC_VERBOSE," works.\n");
1567                         nmi_watchdog_default();
1568                         if (nmi_watchdog == NMI_IO_APIC) {
1569                                 setup_nmi();
1570                         }
1571                         return;
1572                 }
1573                 /*
1574                  * Cleanup, just in case ...
1575                  */
1576                 clear_IO_APIC_pin(apic2, pin2);
1577         }
1578         apic_printk(APIC_VERBOSE," failed.\n");
1579
1580         if (nmi_watchdog == NMI_IO_APIC) {
1581                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1582                 nmi_watchdog = 0;
1583         }
1584
1585         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1586
1587         disable_8259A_irq(0);
1588         irq_desc[0].chip = &lapic_irq_type;
1589         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1590         enable_8259A_irq(0);
1591
1592         if (timer_irq_works()) {
1593                 apic_printk(APIC_VERBOSE," works.\n");
1594                 return;
1595         }
1596         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1597         apic_printk(APIC_VERBOSE," failed.\n");
1598
1599         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1600
1601         init_8259A(0);
1602         make_8259A_irq(0);
1603         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1604
1605         unlock_ExtINT_logic();
1606
1607         if (timer_irq_works()) {
1608                 apic_printk(APIC_VERBOSE," works.\n");
1609                 return;
1610         }
1611         apic_printk(APIC_VERBOSE," failed :(.\n");
1612         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1613 }
1614
1615 static int __init notimercheck(char *s)
1616 {
1617         no_timer_check = 1;
1618         return 1;
1619 }
1620 __setup("no_timer_check", notimercheck);
1621
1622 /*
1623  *
1624  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1625  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1626  *   Linux doesn't really care, as it's not actually used
1627  *   for any interrupt handling anyway.
1628  */
1629 #define PIC_IRQS        (1<<2)
1630
1631 void __init setup_IO_APIC(void)
1632 {
1633         enable_IO_APIC();
1634
1635         if (acpi_ioapic)
1636                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1637         else
1638                 io_apic_irqs = ~PIC_IRQS;
1639
1640         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1641
1642         sync_Arb_IDs();
1643         setup_IO_APIC_irqs();
1644         init_IO_APIC_traps();
1645         check_timer();
1646         if (!acpi_ioapic)
1647                 print_IO_APIC();
1648 }
1649
1650 struct sysfs_ioapic_data {
1651         struct sys_device dev;
1652         struct IO_APIC_route_entry entry[0];
1653 };
1654 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1655
1656 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1657 {
1658         struct IO_APIC_route_entry *entry;
1659         struct sysfs_ioapic_data *data;
1660         int i;
1661
1662         data = container_of(dev, struct sysfs_ioapic_data, dev);
1663         entry = data->entry;
1664         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1665                 *entry = ioapic_read_entry(dev->id, i);
1666
1667         return 0;
1668 }
1669
1670 static int ioapic_resume(struct sys_device *dev)
1671 {
1672         struct IO_APIC_route_entry *entry;
1673         struct sysfs_ioapic_data *data;
1674         unsigned long flags;
1675         union IO_APIC_reg_00 reg_00;
1676         int i;
1677
1678         data = container_of(dev, struct sysfs_ioapic_data, dev);
1679         entry = data->entry;
1680
1681         spin_lock_irqsave(&ioapic_lock, flags);
1682         reg_00.raw = io_apic_read(dev->id, 0);
1683         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1684                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1685                 io_apic_write(dev->id, 0, reg_00.raw);
1686         }
1687         spin_unlock_irqrestore(&ioapic_lock, flags);
1688         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1689                 ioapic_write_entry(dev->id, i, entry[i]);
1690
1691         return 0;
1692 }
1693
1694 static struct sysdev_class ioapic_sysdev_class = {
1695         set_kset_name("ioapic"),
1696         .suspend = ioapic_suspend,
1697         .resume = ioapic_resume,
1698 };
1699
1700 static int __init ioapic_init_sysfs(void)
1701 {
1702         struct sys_device * dev;
1703         int i, size, error = 0;
1704
1705         error = sysdev_class_register(&ioapic_sysdev_class);
1706         if (error)
1707                 return error;
1708
1709         for (i = 0; i < nr_ioapics; i++ ) {
1710                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1711                         * sizeof(struct IO_APIC_route_entry);
1712                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1713                 if (!mp_ioapic_data[i]) {
1714                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1715                         continue;
1716                 }
1717                 memset(mp_ioapic_data[i], 0, size);
1718                 dev = &mp_ioapic_data[i]->dev;
1719                 dev->id = i;
1720                 dev->cls = &ioapic_sysdev_class;
1721                 error = sysdev_register(dev);
1722                 if (error) {
1723                         kfree(mp_ioapic_data[i]);
1724                         mp_ioapic_data[i] = NULL;
1725                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1726                         continue;
1727                 }
1728         }
1729
1730         return 0;
1731 }
1732
1733 device_initcall(ioapic_init_sysfs);
1734
1735 /*
1736  * Dynamic irq allocate and deallocation
1737  */
1738 int create_irq(void)
1739 {
1740         /* Allocate an unused irq */
1741         int irq;
1742         int new;
1743         int vector = 0;
1744         unsigned long flags;
1745         cpumask_t mask;
1746
1747         irq = -ENOSPC;
1748         spin_lock_irqsave(&vector_lock, flags);
1749         for (new = (NR_IRQS - 1); new >= 0; new--) {
1750                 if (platform_legacy_irq(new))
1751                         continue;
1752                 if (irq_vector[new] != 0)
1753                         continue;
1754                 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1755                 if (likely(vector > 0))
1756                         irq = new;
1757                 break;
1758         }
1759         spin_unlock_irqrestore(&vector_lock, flags);
1760
1761         if (irq >= 0) {
1762                 dynamic_irq_init(irq);
1763         }
1764         return irq;
1765 }
1766
1767 void destroy_irq(unsigned int irq)
1768 {
1769         unsigned long flags;
1770
1771         dynamic_irq_cleanup(irq);
1772
1773         spin_lock_irqsave(&vector_lock, flags);
1774         irq_vector[irq] = 0;
1775         spin_unlock_irqrestore(&vector_lock, flags);
1776 }
1777
1778 /*
1779  * MSI mesage composition
1780  */
1781 #ifdef CONFIG_PCI_MSI
1782 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1783 {
1784         int vector;
1785         unsigned dest;
1786         cpumask_t tmp;
1787
1788         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1789         if (vector >= 0) {
1790                 dest = cpu_mask_to_apicid(tmp);
1791
1792                 msg->address_hi = MSI_ADDR_BASE_HI;
1793                 msg->address_lo =
1794                         MSI_ADDR_BASE_LO |
1795                         ((INT_DEST_MODE == 0) ?
1796                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1797                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1798                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1799                                 MSI_ADDR_REDIRECTION_CPU:
1800                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1801                         MSI_ADDR_DEST_ID(dest);
1802
1803                 msg->data =
1804                         MSI_DATA_TRIGGER_EDGE |
1805                         MSI_DATA_LEVEL_ASSERT |
1806                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1807                                 MSI_DATA_DELIVERY_FIXED:
1808                                 MSI_DATA_DELIVERY_LOWPRI) |
1809                         MSI_DATA_VECTOR(vector);
1810         }
1811         return vector;
1812 }
1813
1814 #ifdef CONFIG_SMP
1815 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1816 {
1817         struct msi_msg msg;
1818         unsigned int dest;
1819         cpumask_t tmp;
1820         int vector;
1821
1822         cpus_and(tmp, mask, cpu_online_map);
1823         if (cpus_empty(tmp))
1824                 tmp = TARGET_CPUS;
1825
1826         cpus_and(mask, tmp, CPU_MASK_ALL);
1827
1828         vector = assign_irq_vector(irq, mask, &tmp);
1829         if (vector < 0)
1830                 return;
1831
1832         dest = cpu_mask_to_apicid(tmp);
1833
1834         read_msi_msg(irq, &msg);
1835
1836         msg.data &= ~MSI_DATA_VECTOR_MASK;
1837         msg.data |= MSI_DATA_VECTOR(vector);
1838         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1839         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1840
1841         write_msi_msg(irq, &msg);
1842         set_native_irq_info(irq, mask);
1843 }
1844 #endif /* CONFIG_SMP */
1845
1846 /*
1847  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1848  * which implement the MSI or MSI-X Capability Structure.
1849  */
1850 static struct irq_chip msi_chip = {
1851         .name           = "PCI-MSI",
1852         .unmask         = unmask_msi_irq,
1853         .mask           = mask_msi_irq,
1854         .ack            = ack_apic_edge,
1855 #ifdef CONFIG_SMP
1856         .set_affinity   = set_msi_irq_affinity,
1857 #endif
1858         .retrigger      = ioapic_retrigger_irq,
1859 };
1860
1861 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1862 {
1863         struct msi_msg msg;
1864         int ret;
1865         ret = msi_compose_msg(dev, irq, &msg);
1866         if (ret < 0)
1867                 return ret;
1868
1869         write_msi_msg(irq, &msg);
1870
1871         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1872
1873         return 0;
1874 }
1875
1876 void arch_teardown_msi_irq(unsigned int irq)
1877 {
1878         return;
1879 }
1880
1881 #endif /* CONFIG_PCI_MSI */
1882
1883 /*
1884  * Hypertransport interrupt support
1885  */
1886 #ifdef CONFIG_HT_IRQ
1887
1888 #ifdef CONFIG_SMP
1889
1890 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1891 {
1892         u32 low, high;
1893         low  = read_ht_irq_low(irq);
1894         high = read_ht_irq_high(irq);
1895
1896         low  &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1897         high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1898
1899         low  |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1900         high |= HT_IRQ_HIGH_DEST_ID(dest);
1901
1902         write_ht_irq_low(irq, low);
1903         write_ht_irq_high(irq, high);
1904 }
1905
1906 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1907 {
1908         unsigned int dest;
1909         cpumask_t tmp;
1910         int vector;
1911
1912         cpus_and(tmp, mask, cpu_online_map);
1913         if (cpus_empty(tmp))
1914                 tmp = TARGET_CPUS;
1915
1916         cpus_and(mask, tmp, CPU_MASK_ALL);
1917
1918         vector = assign_irq_vector(irq, mask, &tmp);
1919         if (vector < 0)
1920                 return;
1921
1922         dest = cpu_mask_to_apicid(tmp);
1923
1924         target_ht_irq(irq, dest, vector & 0xff);
1925         set_native_irq_info(irq, mask);
1926 }
1927 #endif
1928
1929 static struct irq_chip ht_irq_chip = {
1930         .name           = "PCI-HT",
1931         .mask           = mask_ht_irq,
1932         .unmask         = unmask_ht_irq,
1933         .ack            = ack_apic_edge,
1934 #ifdef CONFIG_SMP
1935         .set_affinity   = set_ht_irq_affinity,
1936 #endif
1937         .retrigger      = ioapic_retrigger_irq,
1938 };
1939
1940 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
1941 {
1942         int vector;
1943         cpumask_t tmp;
1944
1945         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1946         if (vector >= 0) {
1947                 u32 low, high;
1948                 unsigned dest;
1949
1950                 dest = cpu_mask_to_apicid(tmp);
1951
1952                 high =  HT_IRQ_HIGH_DEST_ID(dest);
1953
1954                 low =   HT_IRQ_LOW_BASE |
1955                         HT_IRQ_LOW_DEST_ID(dest) |
1956                         HT_IRQ_LOW_VECTOR(vector) |
1957                         ((INT_DEST_MODE == 0) ?
1958                                 HT_IRQ_LOW_DM_PHYSICAL :
1959                                 HT_IRQ_LOW_DM_LOGICAL) |
1960                         HT_IRQ_LOW_RQEOI_EDGE |
1961                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1962                                 HT_IRQ_LOW_MT_FIXED :
1963                                 HT_IRQ_LOW_MT_ARBITRATED);
1964
1965                 write_ht_irq_low(irq, low);
1966                 write_ht_irq_high(irq, high);
1967
1968                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
1969                                               handle_edge_irq, "edge");
1970         }
1971         return vector;
1972 }
1973 #endif /* CONFIG_HT_IRQ */
1974
1975 /* --------------------------------------------------------------------------
1976                           ACPI-based IOAPIC Configuration
1977    -------------------------------------------------------------------------- */
1978
1979 #ifdef CONFIG_ACPI
1980
1981 #define IO_APIC_MAX_ID          0xFE
1982
1983 int __init io_apic_get_redir_entries (int ioapic)
1984 {
1985         union IO_APIC_reg_01    reg_01;
1986         unsigned long flags;
1987
1988         spin_lock_irqsave(&ioapic_lock, flags);
1989         reg_01.raw = io_apic_read(ioapic, 1);
1990         spin_unlock_irqrestore(&ioapic_lock, flags);
1991
1992         return reg_01.bits.entries;
1993 }
1994
1995
1996 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1997 {
1998         struct IO_APIC_route_entry entry;
1999         unsigned long flags;
2000         int vector;
2001         cpumask_t mask;
2002
2003         if (!IO_APIC_IRQ(irq)) {
2004                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2005                         ioapic);
2006                 return -EINVAL;
2007         }
2008
2009         /*
2010          * IRQs < 16 are already in the irq_2_pin[] map
2011          */
2012         if (irq >= 16)
2013                 add_pin_to_irq(irq, ioapic, pin);
2014
2015
2016         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
2017         if (vector < 0)
2018                 return vector;
2019
2020         /*
2021          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2022          * Note that we mask (disable) IRQs now -- these get enabled when the
2023          * corresponding device driver registers for this IRQ.
2024          */
2025
2026         memset(&entry,0,sizeof(entry));
2027
2028         entry.delivery_mode = INT_DELIVERY_MODE;
2029         entry.dest_mode = INT_DEST_MODE;
2030         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
2031         entry.trigger = triggering;
2032         entry.polarity = polarity;
2033         entry.mask = 1;                                  /* Disabled (masked) */
2034         entry.vector = vector & 0xff;
2035
2036         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2037                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2038                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2039                triggering, polarity);
2040
2041         ioapic_register_intr(irq, entry.vector, triggering);
2042
2043         if (!ioapic && (irq < 16))
2044                 disable_8259A_irq(irq);
2045
2046         ioapic_write_entry(ioapic, pin, entry);
2047
2048         spin_lock_irqsave(&ioapic_lock, flags);
2049         set_native_irq_info(irq, TARGET_CPUS);
2050         spin_unlock_irqrestore(&ioapic_lock, flags);
2051
2052         return 0;
2053 }
2054
2055 #endif /* CONFIG_ACPI */
2056
2057
2058 /*
2059  * This function currently is only a helper for the i386 smp boot process where
2060  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2061  * so mask in all cases should simply be TARGET_CPUS
2062  */
2063 #ifdef CONFIG_SMP
2064 void __init setup_ioapic_dest(void)
2065 {
2066         int pin, ioapic, irq, irq_entry;
2067
2068         if (skip_ioapic_setup == 1)
2069                 return;
2070
2071         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2072                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2073                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2074                         if (irq_entry == -1)
2075                                 continue;
2076                         irq = pin_2_irq(irq_entry, ioapic, pin);
2077                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2078                 }
2079
2080         }
2081 }
2082 #endif