arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/proto.h>
  43 #include <asm/mach_apic.h>
  44 #include <asm/acpi.h>
  45 #include <asm/dma.h>
  46 #include <asm/nmi.h>
  47 #include <asm/msidef.h>
  48 #include <asm/hypertransport.h>
  49
  50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
  51
  52 #define __apicdebuginit  __init
  53
  54 int sis_apic_bug; /* not actually supported, dummy for compile */
  55
  56 static int no_timer_check;
  57
  58 static int disable_timer_pin_1 __initdata;
  59
  60 int timer_over_8254 __initdata = 1;
  61
  62 /* Where if anywhere is the i8259 connect in external int mode */
  63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  64
  65 static DEFINE_SPINLOCK(ioapic_lock);
  66 DEFINE_SPINLOCK(vector_lock);
  67
  68 /*
  69  * # of IRQ routing registers
  70  */
  71 int nr_ioapic_registers[MAX_IO_APICS];
  72
  73 /*
  74  * Rough estimation of how many shared IRQs there are, can
  75  * be changed anytime.
  76  */
  77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  79
  80 /*
  81  * This is performance-critical, we want to do it O(1)
  82  *
  83  * the indexing order of this array favors 1:1 mappings
  84  * between pins and IRQs.
  85  */
  86
  87 static struct irq_pin_list {
  88         short apic, pin, next;
  89 } irq_2_pin[PIN_MAP_SIZE];
  90
  91 struct io_apic {
  92         unsigned int index;
  93         unsigned int unused[3];
  94         unsigned int data;
  95 };
  96
  97 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
  98 {
  99         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 100                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 101 }
 102
 103 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 104 {
 105         struct io_apic __iomem *io_apic = io_apic_base(apic);
 106         writel(reg, &io_apic->index);
 107         return readl(&io_apic->data);
 108 }
 109
 110 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 111 {
 112         struct io_apic __iomem *io_apic = io_apic_base(apic);
 113         writel(reg, &io_apic->index);
 114         writel(value, &io_apic->data);
 115 }
 116
 117 /*
 118  * Re-write a value: to be used for read-modify-write
 119  * cycles where the read already set up the index register.
 120  */
 121 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 122 {
 123         struct io_apic __iomem *io_apic = io_apic_base(apic);
 124         writel(value, &io_apic->data);
 125 }
 126
 127 /*
 128  * Synchronize the IO-APIC and the CPU by doing
 129  * a dummy read from the IO-APIC
 130  */
 131 static inline void io_apic_sync(unsigned int apic)
 132 {
 133         struct io_apic __iomem *io_apic = io_apic_base(apic);
 134         readl(&io_apic->data);
 135 }
 136
 137 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 138                                                                         \
 139 {                                                                       \
 140         int pin;                                                        \
 141         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 142                                                                         \
 143         BUG_ON(irq >= NR_IRQS);                                         \
 144         for (;;) {                                                      \
 145                 unsigned int reg;                                       \
 146                 pin = entry->pin;                                       \
 147                 if (pin == -1)                                          \
 148                         break;                                          \
 149                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 150                 reg ACTION;                                             \
 151                 io_apic_modify(entry->apic, reg);                       \
 152                 if (!entry->next)                                       \
 153                         break;                                          \
 154                 entry = irq_2_pin + entry->next;                        \
 155         }                                                               \
 156         FINAL;                                                          \
 157 }
 158
 159 union entry_union {
 160         struct { u32 w1, w2; };
 161         struct IO_APIC_route_entry entry;
 162 };
 163
 164 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 165 {
 166         union entry_union eu;
 167         unsigned long flags;
 168         spin_lock_irqsave(&ioapic_lock, flags);
 169         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 170         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 171         spin_unlock_irqrestore(&ioapic_lock, flags);
 172         return eu.entry;
 173 }
 174
 175 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 176 {
 177         unsigned long flags;
 178         union entry_union eu;
 179         eu.entry = e;
 180         spin_lock_irqsave(&ioapic_lock, flags);
 181         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 182         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 183         spin_unlock_irqrestore(&ioapic_lock, flags);
 184 }
 185
 186 #ifdef CONFIG_SMP
 187 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 188 {
 189         int apic, pin;
 190         struct irq_pin_list *entry = irq_2_pin + irq;
 191
 192         BUG_ON(irq >= NR_IRQS);
 193         for (;;) {
 194                 unsigned int reg;
 195                 apic = entry->apic;
 196                 pin = entry->pin;
 197                 if (pin == -1)
 198                         break;
 199                 io_apic_write(apic, 0x11 + pin*2, dest);
 200                 reg = io_apic_read(apic, 0x10 + pin*2);
 201                 reg &= ~0x000000ff;
 202                 reg |= vector;
 203                 io_apic_modify(apic, reg);
 204                 if (!entry->next)
 205                         break;
 206                 entry = irq_2_pin + entry->next;
 207         }
 208 }
 209
 210 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 211 {
 212         unsigned long flags;
 213         unsigned int dest;
 214         cpumask_t tmp;
 215         int vector;
 216
 217         cpus_and(tmp, mask, cpu_online_map);
 218         if (cpus_empty(tmp))
 219                 tmp = TARGET_CPUS;
 220
 221         cpus_and(mask, tmp, CPU_MASK_ALL);
 222
 223         vector = assign_irq_vector(irq, mask, &tmp);
 224         if (vector < 0)
 225                 return;
 226
 227         dest = cpu_mask_to_apicid(tmp);
 228
 229         /*
 230          * Only the high 8 bits are valid.
 231          */
 232         dest = SET_APIC_LOGICAL_ID(dest);
 233
 234         spin_lock_irqsave(&ioapic_lock, flags);
 235         __target_IO_APIC_irq(irq, dest, vector);
 236         set_native_irq_info(irq, mask);
 237         spin_unlock_irqrestore(&ioapic_lock, flags);
 238 }
 239 #endif
 240
 241 /*
 242  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 243  * shared ISA-space IRQs, so we have to support them. We are super
 244  * fast in the common case, and fast for shared ISA-space IRQs.
 245  */
 246 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 247 {
 248         static int first_free_entry = NR_IRQS;
 249         struct irq_pin_list *entry = irq_2_pin + irq;
 250
 251         BUG_ON(irq >= NR_IRQS);
 252         while (entry->next)
 253                 entry = irq_2_pin + entry->next;
 254
 255         if (entry->pin != -1) {
 256                 entry->next = first_free_entry;
 257                 entry = irq_2_pin + entry->next;
 258                 if (++first_free_entry >= PIN_MAP_SIZE)
 259                         panic("io_apic.c: ran out of irq_2_pin entries!");
 260         }
 261         entry->apic = apic;
 262         entry->pin = pin;
 263 }
 264
 265
 266 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 267                                                                         \
 268         static void name##_IO_APIC_irq (unsigned int irq)               \
 269         __DO_ACTION(R, ACTION, FINAL)
 270
 271 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 272                                                 /* mask = 1 */
 273 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 274                                                 /* mask = 0 */
 275
 276 static void mask_IO_APIC_irq (unsigned int irq)
 277 {
 278         unsigned long flags;
 279
 280         spin_lock_irqsave(&ioapic_lock, flags);
 281         __mask_IO_APIC_irq(irq);
 282         spin_unlock_irqrestore(&ioapic_lock, flags);
 283 }
 284
 285 static void unmask_IO_APIC_irq (unsigned int irq)
 286 {
 287         unsigned long flags;
 288
 289         spin_lock_irqsave(&ioapic_lock, flags);
 290         __unmask_IO_APIC_irq(irq);
 291         spin_unlock_irqrestore(&ioapic_lock, flags);
 292 }
 293
 294 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 295 {
 296         struct IO_APIC_route_entry entry;
 297
 298         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 299         entry = ioapic_read_entry(apic, pin);
 300         if (entry.delivery_mode == dest_SMI)
 301                 return;
 302         /*
 303          * Disable it in the IO-APIC irq-routing table:
 304          */
 305         memset(&entry, 0, sizeof(entry));
 306         entry.mask = 1;
 307         ioapic_write_entry(apic, pin, entry);
 308 }
 309
 310 static void clear_IO_APIC (void)
 311 {
 312         int apic, pin;
 313
 314         for (apic = 0; apic < nr_ioapics; apic++)
 315                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 316                         clear_IO_APIC_pin(apic, pin);
 317 }
 318
 319 int skip_ioapic_setup;
 320 int ioapic_force;
 321
 322 /* dummy parsing: see setup.c */
 323
 324 static int __init disable_ioapic_setup(char *str)
 325 {
 326         skip_ioapic_setup = 1;
 327         return 0;
 328 }
 329 early_param("noapic", disable_ioapic_setup);
 330
 331 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 332 static int __init disable_timer_pin_setup(char *arg)
 333 {
 334         disable_timer_pin_1 = 1;
 335         return 1;
 336 }
 337 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 338
 339 static int __init setup_disable_8254_timer(char *s)
 340 {
 341         timer_over_8254 = -1;
 342         return 1;
 343 }
 344 static int __init setup_enable_8254_timer(char *s)
 345 {
 346         timer_over_8254 = 2;
 347         return 1;
 348 }
 349
 350 __setup("disable_8254_timer", setup_disable_8254_timer);
 351 __setup("enable_8254_timer", setup_enable_8254_timer);
 352
 353
 354 /*
 355  * Find the IRQ entry number of a certain pin.
 356  */
 357 static int find_irq_entry(int apic, int pin, int type)
 358 {
 359         int i;
 360
 361         for (i = 0; i < mp_irq_entries; i++)
 362                 if (mp_irqs[i].mpc_irqtype == type &&
 363                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 364                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 365                     mp_irqs[i].mpc_dstirq == pin)
 366                         return i;
 367
 368         return -1;
 369 }
 370
 371 /*
 372  * Find the pin to which IRQ[irq] (ISA) is connected
 373  */
 374 static int __init find_isa_irq_pin(int irq, int type)
 375 {
 376         int i;
 377
 378         for (i = 0; i < mp_irq_entries; i++) {
 379                 int lbus = mp_irqs[i].mpc_srcbus;
 380
 381                 if (test_bit(lbus, mp_bus_not_pci) &&
 382                     (mp_irqs[i].mpc_irqtype == type) &&
 383                     (mp_irqs[i].mpc_srcbusirq == irq))
 384
 385                         return mp_irqs[i].mpc_dstirq;
 386         }
 387         return -1;
 388 }
 389
 390 static int __init find_isa_irq_apic(int irq, int type)
 391 {
 392         int i;
 393
 394         for (i = 0; i < mp_irq_entries; i++) {
 395                 int lbus = mp_irqs[i].mpc_srcbus;
 396
 397                 if (test_bit(lbus, mp_bus_not_pci) &&
 398                     (mp_irqs[i].mpc_irqtype == type) &&
 399                     (mp_irqs[i].mpc_srcbusirq == irq))
 400                         break;
 401         }
 402         if (i < mp_irq_entries) {
 403                 int apic;
 404                 for(apic = 0; apic < nr_ioapics; apic++) {
 405                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 406                                 return apic;
 407                 }
 408         }
 409
 410         return -1;
 411 }
 412
 413 /*
 414  * Find a specific PCI IRQ entry.
 415  * Not an __init, possibly needed by modules
 416  */
 417 static int pin_2_irq(int idx, int apic, int pin);
 418
 419 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 420 {
 421         int apic, i, best_guess = -1;
 422
 423         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 424                 bus, slot, pin);
 425         if (mp_bus_id_to_pci_bus[bus] == -1) {
 426                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 427                 return -1;
 428         }
 429         for (i = 0; i < mp_irq_entries; i++) {
 430                 int lbus = mp_irqs[i].mpc_srcbus;
 431
 432                 for (apic = 0; apic < nr_ioapics; apic++)
 433                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 434                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 435                                 break;
 436
 437                 if (!test_bit(lbus, mp_bus_not_pci) &&
 438                     !mp_irqs[i].mpc_irqtype &&
 439                     (bus == lbus) &&
 440                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 441                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 442
 443                         if (!(apic || IO_APIC_IRQ(irq)))
 444                                 continue;
 445
 446                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 447                                 return irq;
 448                         /*
 449                          * Use the first all-but-pin matching entry as a
 450                          * best-guess fuzzy result for broken mptables.
 451                          */
 452                         if (best_guess < 0)
 453                                 best_guess = irq;
 454                 }
 455         }
 456         BUG_ON(best_guess >= NR_IRQS);
 457         return best_guess;
 458 }
 459
 460 /* ISA interrupts are always polarity zero edge triggered,
 461  * when listed as conforming in the MP table. */
 462
 463 #define default_ISA_trigger(idx)        (0)
 464 #define default_ISA_polarity(idx)       (0)
 465
 466 /* PCI interrupts are always polarity one level triggered,
 467  * when listed as conforming in the MP table. */
 468
 469 #define default_PCI_trigger(idx)        (1)
 470 #define default_PCI_polarity(idx)       (1)
 471
 472 static int __init MPBIOS_polarity(int idx)
 473 {
 474         int bus = mp_irqs[idx].mpc_srcbus;
 475         int polarity;
 476
 477         /*
 478          * Determine IRQ line polarity (high active or low active):
 479          */
 480         switch (mp_irqs[idx].mpc_irqflag & 3)
 481         {
 482                 case 0: /* conforms, ie. bus-type dependent polarity */
 483                         if (test_bit(bus, mp_bus_not_pci))
 484                                 polarity = default_ISA_polarity(idx);
 485                         else
 486                                 polarity = default_PCI_polarity(idx);
 487                         break;
 488                 case 1: /* high active */
 489                 {
 490                         polarity = 0;
 491                         break;
 492                 }
 493                 case 2: /* reserved */
 494                 {
 495                         printk(KERN_WARNING "broken BIOS!!\n");
 496                         polarity = 1;
 497                         break;
 498                 }
 499                 case 3: /* low active */
 500                 {
 501                         polarity = 1;
 502                         break;
 503                 }
 504                 default: /* invalid */
 505                 {
 506                         printk(KERN_WARNING "broken BIOS!!\n");
 507                         polarity = 1;
 508                         break;
 509                 }
 510         }
 511         return polarity;
 512 }
 513
 514 static int MPBIOS_trigger(int idx)
 515 {
 516         int bus = mp_irqs[idx].mpc_srcbus;
 517         int trigger;
 518
 519         /*
 520          * Determine IRQ trigger mode (edge or level sensitive):
 521          */
 522         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 523         {
 524                 case 0: /* conforms, ie. bus-type dependent */
 525                         if (test_bit(bus, mp_bus_not_pci))
 526                                 trigger = default_ISA_trigger(idx);
 527                         else
 528                                 trigger = default_PCI_trigger(idx);
 529                         break;
 530                 case 1: /* edge */
 531                 {
 532                         trigger = 0;
 533                         break;
 534                 }
 535                 case 2: /* reserved */
 536                 {
 537                         printk(KERN_WARNING "broken BIOS!!\n");
 538                         trigger = 1;
 539                         break;
 540                 }
 541                 case 3: /* level */
 542                 {
 543                         trigger = 1;
 544                         break;
 545                 }
 546                 default: /* invalid */
 547                 {
 548                         printk(KERN_WARNING "broken BIOS!!\n");
 549                         trigger = 0;
 550                         break;
 551                 }
 552         }
 553         return trigger;
 554 }
 555
 556 static inline int irq_polarity(int idx)
 557 {
 558         return MPBIOS_polarity(idx);
 559 }
 560
 561 static inline int irq_trigger(int idx)
 562 {
 563         return MPBIOS_trigger(idx);
 564 }
 565
 566 static int pin_2_irq(int idx, int apic, int pin)
 567 {
 568         int irq, i;
 569         int bus = mp_irqs[idx].mpc_srcbus;
 570
 571         /*
 572          * Debugging check, we are in big trouble if this message pops up!
 573          */
 574         if (mp_irqs[idx].mpc_dstirq != pin)
 575                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 576
 577         if (test_bit(bus, mp_bus_not_pci)) {
 578                 irq = mp_irqs[idx].mpc_srcbusirq;
 579         } else {
 580                 /*
 581                  * PCI IRQs are mapped in order
 582                  */
 583                 i = irq = 0;
 584                 while (i < apic)
 585                         irq += nr_ioapic_registers[i++];
 586                 irq += pin;
 587         }
 588         BUG_ON(irq >= NR_IRQS);
 589         return irq;
 590 }
 591
 592 static inline int IO_APIC_irq_trigger(int irq)
 593 {
 594         int apic, idx, pin;
 595
 596         for (apic = 0; apic < nr_ioapics; apic++) {
 597                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 598                         idx = find_irq_entry(apic,pin,mp_INT);
 599                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 600                                 return irq_trigger(idx);
 601                 }
 602         }
 603         /*
 604          * nonexistent IRQs are edge default
 605          */
 606         return 0;
 607 }
 608
 609 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 610 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
 611         [0] = FIRST_EXTERNAL_VECTOR + 0,
 612         [1] = FIRST_EXTERNAL_VECTOR + 1,
 613         [2] = FIRST_EXTERNAL_VECTOR + 2,
 614         [3] = FIRST_EXTERNAL_VECTOR + 3,
 615         [4] = FIRST_EXTERNAL_VECTOR + 4,
 616         [5] = FIRST_EXTERNAL_VECTOR + 5,
 617         [6] = FIRST_EXTERNAL_VECTOR + 6,
 618         [7] = FIRST_EXTERNAL_VECTOR + 7,
 619         [8] = FIRST_EXTERNAL_VECTOR + 8,
 620         [9] = FIRST_EXTERNAL_VECTOR + 9,
 621         [10] = FIRST_EXTERNAL_VECTOR + 10,
 622         [11] = FIRST_EXTERNAL_VECTOR + 11,
 623         [12] = FIRST_EXTERNAL_VECTOR + 12,
 624         [13] = FIRST_EXTERNAL_VECTOR + 13,
 625         [14] = FIRST_EXTERNAL_VECTOR + 14,
 626         [15] = FIRST_EXTERNAL_VECTOR + 15,
 627 };
 628
 629 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
 630         [0] = CPU_MASK_ALL,
 631         [1] = CPU_MASK_ALL,
 632         [2] = CPU_MASK_ALL,
 633         [3] = CPU_MASK_ALL,
 634         [4] = CPU_MASK_ALL,
 635         [5] = CPU_MASK_ALL,
 636         [6] = CPU_MASK_ALL,
 637         [7] = CPU_MASK_ALL,
 638         [8] = CPU_MASK_ALL,
 639         [9] = CPU_MASK_ALL,
 640         [10] = CPU_MASK_ALL,
 641         [11] = CPU_MASK_ALL,
 642         [12] = CPU_MASK_ALL,
 643         [13] = CPU_MASK_ALL,
 644         [14] = CPU_MASK_ALL,
 645         [15] = CPU_MASK_ALL,
 646 };
 647
 648 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 649 {
 650         /*
 651          * NOTE! The local APIC isn't very good at handling
 652          * multiple interrupts at the same interrupt level.
 653          * As the interrupt level is determined by taking the
 654          * vector number and shifting that right by 4, we
 655          * want to spread these out a bit so that they don't
 656          * all fall in the same interrupt level.
 657          *
 658          * Also, we've got to be careful not to trash gate
 659          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 660          */
 661         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 662         int old_vector = -1;
 663         int cpu;
 664
 665         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
 666
 667         /* Only try and allocate irqs on cpus that are present */
 668         cpus_and(mask, mask, cpu_online_map);
 669
 670         if (irq_vector[irq] > 0)
 671                 old_vector = irq_vector[irq];
 672         if (old_vector > 0) {
 673                 cpus_and(*result, irq_domain[irq], mask);
 674                 if (!cpus_empty(*result))
 675                         return old_vector;
 676         }
 677
 678         for_each_cpu_mask(cpu, mask) {
 679                 cpumask_t domain, new_mask;
 680                 int new_cpu;
 681                 int vector, offset;
 682
 683                 domain = vector_allocation_domain(cpu);
 684                 cpus_and(new_mask, domain, cpu_online_map);
 685
 686                 vector = current_vector;
 687                 offset = current_offset;
 688 next:
 689                 vector += 8;
 690                 if (vector >= FIRST_SYSTEM_VECTOR) {
 691                         /* If we run out of vectors on large boxen, must share them. */
 692                         offset = (offset + 1) % 8;
 693                         vector = FIRST_DEVICE_VECTOR + offset;
 694                 }
 695                 if (unlikely(current_vector == vector))
 696                         continue;
 697                 if (vector == IA32_SYSCALL_VECTOR)
 698                         goto next;
 699                 for_each_cpu_mask(new_cpu, new_mask)
 700                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 701                                 goto next;
 702                 /* Found one! */
 703                 current_vector = vector;
 704                 current_offset = offset;
 705                 if (old_vector >= 0) {
 706                         cpumask_t old_mask;
 707                         int old_cpu;
 708                         cpus_and(old_mask, irq_domain[irq], cpu_online_map);
 709                         for_each_cpu_mask(old_cpu, old_mask)
 710                                 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
 711                 }
 712                 for_each_cpu_mask(new_cpu, new_mask)
 713                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 714                 irq_vector[irq] = vector;
 715                 irq_domain[irq] = domain;
 716                 cpus_and(*result, domain, mask);
 717                 return vector;
 718         }
 719         return -ENOSPC;
 720 }
 721
 722 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 723 {
 724         int vector;
 725         unsigned long flags;
 726
 727         spin_lock_irqsave(&vector_lock, flags);
 728         vector = __assign_irq_vector(irq, mask, result);
 729         spin_unlock_irqrestore(&vector_lock, flags);
 730         return vector;
 731 }
 732
 733 void __setup_vector_irq(int cpu)
 734 {
 735         /* Initialize vector_irq on a new cpu */
 736         /* This function must be called with vector_lock held */
 737         unsigned long flags;
 738         int irq, vector;
 739
 740
 741         /* Mark the inuse vectors */
 742         for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
 743                 if (!cpu_isset(cpu, irq_domain[irq]))
 744                         continue;
 745                 vector = irq_vector[irq];
 746                 per_cpu(vector_irq, cpu)[vector] = irq;
 747         }
 748         /* Mark the free vectors */
 749         for (vector = 0; vector < NR_VECTORS; ++vector) {
 750                 irq = per_cpu(vector_irq, cpu)[vector];
 751                 if (irq < 0)
 752                         continue;
 753                 if (!cpu_isset(cpu, irq_domain[irq]))
 754                         per_cpu(vector_irq, cpu)[vector] = -1;
 755         }
 756 }
 757
 758
 759 extern void (*interrupt[NR_IRQS])(void);
 760
 761 static struct irq_chip ioapic_chip;
 762
 763 #define IOAPIC_AUTO     -1
 764 #define IOAPIC_EDGE     0
 765 #define IOAPIC_LEVEL    1
 766
 767 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 768 {
 769         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 770                         trigger == IOAPIC_LEVEL)
 771                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 772                                               handle_fasteoi_irq, "fasteoi");
 773         else
 774                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 775                                               handle_edge_irq, "edge");
 776 }
 777
 778 static void __init setup_IO_APIC_irqs(void)
 779 {
 780         struct IO_APIC_route_entry entry;
 781         int apic, pin, idx, irq, first_notcon = 1, vector;
 782         unsigned long flags;
 783
 784         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 785
 786         for (apic = 0; apic < nr_ioapics; apic++) {
 787         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 788
 789                 /*
 790                  * add it to the IO-APIC irq-routing table:
 791                  */
 792                 memset(&entry,0,sizeof(entry));
 793
 794                 entry.delivery_mode = INT_DELIVERY_MODE;
 795                 entry.dest_mode = INT_DEST_MODE;
 796                 entry.mask = 0;                         /* enable IRQ */
 797                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 798
 799                 idx = find_irq_entry(apic,pin,mp_INT);
 800                 if (idx == -1) {
 801                         if (first_notcon) {
 802                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 803                                 first_notcon = 0;
 804                         } else
 805                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 806                         continue;
 807                 }
 808
 809                 entry.trigger = irq_trigger(idx);
 810                 entry.polarity = irq_polarity(idx);
 811
 812                 if (irq_trigger(idx)) {
 813                         entry.trigger = 1;
 814                         entry.mask = 1;
 815                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 816                 }
 817
 818                 irq = pin_2_irq(idx, apic, pin);
 819                 add_pin_to_irq(irq, apic, pin);
 820
 821                 if (!apic && !IO_APIC_IRQ(irq))
 822                         continue;
 823
 824                 if (IO_APIC_IRQ(irq)) {
 825                         cpumask_t mask;
 826                         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
 827                         if (vector < 0)
 828                                 continue;
 829
 830                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
 831                         entry.vector = vector;
 832
 833                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 834                         if (!apic && (irq < 16))
 835                                 disable_8259A_irq(irq);
 836                 }
 837                 ioapic_write_entry(apic, pin, entry);
 838
 839                 spin_lock_irqsave(&ioapic_lock, flags);
 840                 set_native_irq_info(irq, TARGET_CPUS);
 841                 spin_unlock_irqrestore(&ioapic_lock, flags);
 842         }
 843         }
 844
 845         if (!first_notcon)
 846                 apic_printk(APIC_VERBOSE," not connected.\n");
 847 }
 848
 849 /*
 850  * Set up the 8259A-master output pin as broadcast to all
 851  * CPUs.
 852  */
 853 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 854 {
 855         struct IO_APIC_route_entry entry;
 856         unsigned long flags;
 857
 858         memset(&entry,0,sizeof(entry));
 859
 860         disable_8259A_irq(0);
 861
 862         /* mask LVT0 */
 863         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 864
 865         /*
 866          * We use logical delivery to get the timer IRQ
 867          * to the first CPU.
 868          */
 869         entry.dest_mode = INT_DEST_MODE;
 870         entry.mask = 0;                                 /* unmask IRQ now */
 871         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 872         entry.delivery_mode = INT_DELIVERY_MODE;
 873         entry.polarity = 0;
 874         entry.trigger = 0;
 875         entry.vector = vector;
 876
 877         /*
 878          * The timer IRQ doesn't have to know that behind the
 879          * scene we have a 8259A-master in AEOI mode ...
 880          */
 881         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 882
 883         /*
 884          * Add it to the IO-APIC irq-routing table:
 885          */
 886         spin_lock_irqsave(&ioapic_lock, flags);
 887         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 888         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 889         spin_unlock_irqrestore(&ioapic_lock, flags);
 890
 891         enable_8259A_irq(0);
 892 }
 893
 894 void __init UNEXPECTED_IO_APIC(void)
 895 {
 896 }
 897
 898 void __apicdebuginit print_IO_APIC(void)
 899 {
 900         int apic, i;
 901         union IO_APIC_reg_00 reg_00;
 902         union IO_APIC_reg_01 reg_01;
 903         union IO_APIC_reg_02 reg_02;
 904         unsigned long flags;
 905
 906         if (apic_verbosity == APIC_QUIET)
 907                 return;
 908
 909         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 910         for (i = 0; i < nr_ioapics; i++)
 911                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 912                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 913
 914         /*
 915          * We are a bit conservative about what we expect.  We have to
 916          * know about every hardware change ASAP.
 917          */
 918         printk(KERN_INFO "testing the IO APIC.......................\n");
 919
 920         for (apic = 0; apic < nr_ioapics; apic++) {
 921
 922         spin_lock_irqsave(&ioapic_lock, flags);
 923         reg_00.raw = io_apic_read(apic, 0);
 924         reg_01.raw = io_apic_read(apic, 1);
 925         if (reg_01.bits.version >= 0x10)
 926                 reg_02.raw = io_apic_read(apic, 2);
 927         spin_unlock_irqrestore(&ioapic_lock, flags);
 928
 929         printk("\n");
 930         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 931         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 932         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 933         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 934                 UNEXPECTED_IO_APIC();
 935
 936         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 937         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 938         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 939                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 940                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 941                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 942                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 943                 (reg_01.bits.entries != 0x2E) &&
 944                 (reg_01.bits.entries != 0x3F) &&
 945                 (reg_01.bits.entries != 0x03)
 946         )
 947                 UNEXPECTED_IO_APIC();
 948
 949         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 950         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 951         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 952                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 953                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 954                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 955                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 956                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 957         )
 958                 UNEXPECTED_IO_APIC();
 959         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 960                 UNEXPECTED_IO_APIC();
 961
 962         if (reg_01.bits.version >= 0x10) {
 963                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 964                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 965                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 966                         UNEXPECTED_IO_APIC();
 967         }
 968
 969         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 970
 971         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 972                           " Stat Dest Deli Vect:   \n");
 973
 974         for (i = 0; i <= reg_01.bits.entries; i++) {
 975                 struct IO_APIC_route_entry entry;
 976
 977                 entry = ioapic_read_entry(apic, i);
 978
 979                 printk(KERN_DEBUG " %02x %03X %02X  ",
 980                         i,
 981                         entry.dest.logical.logical_dest,
 982                         entry.dest.physical.physical_dest
 983                 );
 984
 985                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 986                         entry.mask,
 987                         entry.trigger,
 988                         entry.irr,
 989                         entry.polarity,
 990                         entry.delivery_status,
 991                         entry.dest_mode,
 992                         entry.delivery_mode,
 993                         entry.vector
 994                 );
 995         }
 996         }
 997         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 998         for (i = 0; i < NR_IRQS; i++) {
 999                 struct irq_pin_list *entry = irq_2_pin + i;
1000                 if (entry->pin < 0)
1001                         continue;
1002                 printk(KERN_DEBUG "IRQ%d ", i);
1003                 for (;;) {
1004                         printk("-> %d:%d", entry->apic, entry->pin);
1005                         if (!entry->next)
1006                                 break;
1007                         entry = irq_2_pin + entry->next;
1008                 }
1009                 printk("\n");
1010         }
1011
1012         printk(KERN_INFO ".................................... done.\n");
1013
1014         return;
1015 }
1016
1017 #if 0
1018
1019 static __apicdebuginit void print_APIC_bitfield (int base)
1020 {
1021         unsigned int v;
1022         int i, j;
1023
1024         if (apic_verbosity == APIC_QUIET)
1025                 return;
1026
1027         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1028         for (i = 0; i < 8; i++) {
1029                 v = apic_read(base + i*0x10);
1030                 for (j = 0; j < 32; j++) {
1031                         if (v & (1<<j))
1032                                 printk("1");
1033                         else
1034                                 printk("0");
1035                 }
1036                 printk("\n");
1037         }
1038 }
1039
1040 void __apicdebuginit print_local_APIC(void * dummy)
1041 {
1042         unsigned int v, ver, maxlvt;
1043
1044         if (apic_verbosity == APIC_QUIET)
1045                 return;
1046
1047         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1048                 smp_processor_id(), hard_smp_processor_id());
1049         v = apic_read(APIC_ID);
1050         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1051         v = apic_read(APIC_LVR);
1052         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1053         ver = GET_APIC_VERSION(v);
1054         maxlvt = get_maxlvt();
1055
1056         v = apic_read(APIC_TASKPRI);
1057         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1058
1059         v = apic_read(APIC_ARBPRI);
1060         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1061                 v & APIC_ARBPRI_MASK);
1062         v = apic_read(APIC_PROCPRI);
1063         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1064
1065         v = apic_read(APIC_EOI);
1066         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1067         v = apic_read(APIC_RRR);
1068         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1069         v = apic_read(APIC_LDR);
1070         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1071         v = apic_read(APIC_DFR);
1072         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1073         v = apic_read(APIC_SPIV);
1074         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1075
1076         printk(KERN_DEBUG "... APIC ISR field:\n");
1077         print_APIC_bitfield(APIC_ISR);
1078         printk(KERN_DEBUG "... APIC TMR field:\n");
1079         print_APIC_bitfield(APIC_TMR);
1080         printk(KERN_DEBUG "... APIC IRR field:\n");
1081         print_APIC_bitfield(APIC_IRR);
1082
1083         v = apic_read(APIC_ESR);
1084         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1085
1086         v = apic_read(APIC_ICR);
1087         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1088         v = apic_read(APIC_ICR2);
1089         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1090
1091         v = apic_read(APIC_LVTT);
1092         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1093
1094         if (maxlvt > 3) {                       /* PC is LVT#4. */
1095                 v = apic_read(APIC_LVTPC);
1096                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1097         }
1098         v = apic_read(APIC_LVT0);
1099         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1100         v = apic_read(APIC_LVT1);
1101         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1102
1103         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1104                 v = apic_read(APIC_LVTERR);
1105                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1106         }
1107
1108         v = apic_read(APIC_TMICT);
1109         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1110         v = apic_read(APIC_TMCCT);
1111         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1112         v = apic_read(APIC_TDCR);
1113         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1114         printk("\n");
1115 }
1116
1117 void print_all_local_APICs (void)
1118 {
1119         on_each_cpu(print_local_APIC, NULL, 1, 1);
1120 }
1121
1122 void __apicdebuginit print_PIC(void)
1123 {
1124         unsigned int v;
1125         unsigned long flags;
1126
1127         if (apic_verbosity == APIC_QUIET)
1128                 return;
1129
1130         printk(KERN_DEBUG "\nprinting PIC contents\n");
1131
1132         spin_lock_irqsave(&i8259A_lock, flags);
1133
1134         v = inb(0xa1) << 8 | inb(0x21);
1135         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1136
1137         v = inb(0xa0) << 8 | inb(0x20);
1138         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1139
1140         outb(0x0b,0xa0);
1141         outb(0x0b,0x20);
1142         v = inb(0xa0) << 8 | inb(0x20);
1143         outb(0x0a,0xa0);
1144         outb(0x0a,0x20);
1145
1146         spin_unlock_irqrestore(&i8259A_lock, flags);
1147
1148         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1149
1150         v = inb(0x4d1) << 8 | inb(0x4d0);
1151         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1152 }
1153
1154 #endif  /*  0  */
1155
1156 static void __init enable_IO_APIC(void)
1157 {
1158         union IO_APIC_reg_01 reg_01;
1159         int i8259_apic, i8259_pin;
1160         int i, apic;
1161         unsigned long flags;
1162
1163         for (i = 0; i < PIN_MAP_SIZE; i++) {
1164                 irq_2_pin[i].pin = -1;
1165                 irq_2_pin[i].next = 0;
1166         }
1167
1168         /*
1169          * The number of IO-APIC IRQ registers (== #pins):
1170          */
1171         for (apic = 0; apic < nr_ioapics; apic++) {
1172                 spin_lock_irqsave(&ioapic_lock, flags);
1173                 reg_01.raw = io_apic_read(apic, 1);
1174                 spin_unlock_irqrestore(&ioapic_lock, flags);
1175                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1176         }
1177         for(apic = 0; apic < nr_ioapics; apic++) {
1178                 int pin;
1179                 /* See if any of the pins is in ExtINT mode */
1180                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1181                         struct IO_APIC_route_entry entry;
1182                         entry = ioapic_read_entry(apic, pin);
1183
1184                         /* If the interrupt line is enabled and in ExtInt mode
1185                          * I have found the pin where the i8259 is connected.
1186                          */
1187                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1188                                 ioapic_i8259.apic = apic;
1189                                 ioapic_i8259.pin  = pin;
1190                                 goto found_i8259;
1191                         }
1192                 }
1193         }
1194  found_i8259:
1195         /* Look to see what if the MP table has reported the ExtINT */
1196         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1197         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1198         /* Trust the MP table if nothing is setup in the hardware */
1199         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1200                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1201                 ioapic_i8259.pin  = i8259_pin;
1202                 ioapic_i8259.apic = i8259_apic;
1203         }
1204         /* Complain if the MP table and the hardware disagree */
1205         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1206                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1207         {
1208                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1209         }
1210
1211         /*
1212          * Do not trust the IO-APIC being empty at bootup
1213          */
1214         clear_IO_APIC();
1215 }
1216
1217 /*
1218  * Not an __init, needed by the reboot code
1219  */
1220 void disable_IO_APIC(void)
1221 {
1222         /*
1223          * Clear the IO-APIC before rebooting:
1224          */
1225         clear_IO_APIC();
1226
1227         /*
1228          * If the i8259 is routed through an IOAPIC
1229          * Put that IOAPIC in virtual wire mode
1230          * so legacy interrupts can be delivered.
1231          */
1232         if (ioapic_i8259.pin != -1) {
1233                 struct IO_APIC_route_entry entry;
1234
1235                 memset(&entry, 0, sizeof(entry));
1236                 entry.mask            = 0; /* Enabled */
1237                 entry.trigger         = 0; /* Edge */
1238                 entry.irr             = 0;
1239                 entry.polarity        = 0; /* High */
1240                 entry.delivery_status = 0;
1241                 entry.dest_mode       = 0; /* Physical */
1242                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1243                 entry.vector          = 0;
1244                 entry.dest.physical.physical_dest =
1245                                         GET_APIC_ID(apic_read(APIC_ID));
1246
1247                 /*
1248                  * Add it to the IO-APIC irq-routing table:
1249                  */
1250                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1251         }
1252
1253         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1254 }
1255
1256 /*
1257  * There is a nasty bug in some older SMP boards, their mptable lies
1258  * about the timer IRQ. We do the following to work around the situation:
1259  *
1260  *      - timer IRQ defaults to IO-APIC IRQ
1261  *      - if this function detects that timer IRQs are defunct, then we fall
1262  *        back to ISA timer IRQs
1263  */
1264 static int __init timer_irq_works(void)
1265 {
1266         unsigned long t1 = jiffies;
1267
1268         local_irq_enable();
1269         /* Let ten ticks pass... */
1270         mdelay((10 * 1000) / HZ);
1271
1272         /*
1273          * Expect a few ticks at least, to be sure some possible
1274          * glue logic does not lock up after one or two first
1275          * ticks in a non-ExtINT mode.  Also the local APIC
1276          * might have cached one ExtINT interrupt.  Finally, at
1277          * least one tick may be lost due to delays.
1278          */
1279
1280         /* jiffies wrap? */
1281         if (jiffies - t1 > 4)
1282                 return 1;
1283         return 0;
1284 }
1285
1286 /*
1287  * In the SMP+IOAPIC case it might happen that there are an unspecified
1288  * number of pending IRQ events unhandled. These cases are very rare,
1289  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1290  * better to do it this way as thus we do not have to be aware of
1291  * 'pending' interrupts in the IRQ path, except at this point.
1292  */
1293 /*
1294  * Edge triggered needs to resend any interrupt
1295  * that was delayed but this is now handled in the device
1296  * independent code.
1297  */
1298
1299 /*
1300  * Starting up a edge-triggered IO-APIC interrupt is
1301  * nasty - we need to make sure that we get the edge.
1302  * If it is already asserted for some reason, we need
1303  * return 1 to indicate that is was pending.
1304  *
1305  * This is not complete - we should be able to fake
1306  * an edge even if it isn't on the 8259A...
1307  */
1308
1309 static unsigned int startup_ioapic_irq(unsigned int irq)
1310 {
1311         int was_pending = 0;
1312         unsigned long flags;
1313
1314         spin_lock_irqsave(&ioapic_lock, flags);
1315         if (irq < 16) {
1316                 disable_8259A_irq(irq);
1317                 if (i8259A_irq_pending(irq))
1318                         was_pending = 1;
1319         }
1320         __unmask_IO_APIC_irq(irq);
1321         spin_unlock_irqrestore(&ioapic_lock, flags);
1322
1323         return was_pending;
1324 }
1325
1326 static int ioapic_retrigger_irq(unsigned int irq)
1327 {
1328         cpumask_t mask;
1329         unsigned vector;
1330         unsigned long flags;
1331
1332         spin_lock_irqsave(&vector_lock, flags);
1333         vector = irq_vector[irq];
1334         cpus_clear(mask);
1335         cpu_set(first_cpu(irq_domain[irq]), mask);
1336
1337         send_IPI_mask(mask, vector);
1338         spin_unlock_irqrestore(&vector_lock, flags);
1339
1340         return 1;
1341 }
1342
1343 /*
1344  * Level and edge triggered IO-APIC interrupts need different handling,
1345  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1346  * handled with the level-triggered descriptor, but that one has slightly
1347  * more overhead. Level-triggered interrupts cannot be handled with the
1348  * edge-triggered handler, without risking IRQ storms and other ugly
1349  * races.
1350  */
1351
1352 static void ack_apic_edge(unsigned int irq)
1353 {
1354         move_native_irq(irq);
1355         ack_APIC_irq();
1356 }
1357
1358 static void ack_apic_level(unsigned int irq)
1359 {
1360         int do_unmask_irq = 0;
1361
1362 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1363         /* If we are moving the irq we need to mask it */
1364         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1365                 do_unmask_irq = 1;
1366                 mask_IO_APIC_irq(irq);
1367         }
1368 #endif
1369
1370         /*
1371          * We must acknowledge the irq before we move it or the acknowledge will
1372          * not propogate properly.
1373          */
1374         ack_APIC_irq();
1375
1376         /* Now we can move and renable the irq */
1377         move_masked_irq(irq);
1378         if (unlikely(do_unmask_irq))
1379                 unmask_IO_APIC_irq(irq);
1380 }
1381
1382 static struct irq_chip ioapic_chip __read_mostly = {
1383         .name           = "IO-APIC",
1384         .startup        = startup_ioapic_irq,
1385         .mask           = mask_IO_APIC_irq,
1386         .unmask         = unmask_IO_APIC_irq,
1387         .ack            = ack_apic_edge,
1388         .eoi            = ack_apic_level,
1389 #ifdef CONFIG_SMP
1390         .set_affinity   = set_ioapic_affinity_irq,
1391 #endif
1392         .retrigger      = ioapic_retrigger_irq,
1393 };
1394
1395 static inline void init_IO_APIC_traps(void)
1396 {
1397         int irq;
1398
1399         /*
1400          * NOTE! The local APIC isn't very good at handling
1401          * multiple interrupts at the same interrupt level.
1402          * As the interrupt level is determined by taking the
1403          * vector number and shifting that right by 4, we
1404          * want to spread these out a bit so that they don't
1405          * all fall in the same interrupt level.
1406          *
1407          * Also, we've got to be careful not to trash gate
1408          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1409          */
1410         for (irq = 0; irq < NR_IRQS ; irq++) {
1411                 int tmp = irq;
1412                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1413                         /*
1414                          * Hmm.. We don't have an entry for this,
1415                          * so default to an old-fashioned 8259
1416                          * interrupt if we can..
1417                          */
1418                         if (irq < 16)
1419                                 make_8259A_irq(irq);
1420                         else
1421                                 /* Strange. Oh, well.. */
1422                                 irq_desc[irq].chip = &no_irq_chip;
1423                 }
1424         }
1425 }
1426
1427 static void enable_lapic_irq (unsigned int irq)
1428 {
1429         unsigned long v;
1430
1431         v = apic_read(APIC_LVT0);
1432         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1433 }
1434
1435 static void disable_lapic_irq (unsigned int irq)
1436 {
1437         unsigned long v;
1438
1439         v = apic_read(APIC_LVT0);
1440         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1441 }
1442
1443 static void ack_lapic_irq (unsigned int irq)
1444 {
1445         ack_APIC_irq();
1446 }
1447
1448 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1449
1450 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1451         .typename = "local-APIC-edge",
1452         .startup = NULL, /* startup_irq() not used for IRQ0 */
1453         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1454         .enable = enable_lapic_irq,
1455         .disable = disable_lapic_irq,
1456         .ack = ack_lapic_irq,
1457         .end = end_lapic_irq,
1458 };
1459
1460 static void setup_nmi (void)
1461 {
1462         /*
1463          * Dirty trick to enable the NMI watchdog ...
1464          * We put the 8259A master into AEOI mode and
1465          * unmask on all local APICs LVT0 as NMI.
1466          *
1467          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1468          * is from Maciej W. Rozycki - so we do not have to EOI from
1469          * the NMI handler or the timer interrupt.
1470          */
1471         printk(KERN_INFO "activating NMI Watchdog ...");
1472
1473         enable_NMI_through_LVT0(NULL);
1474
1475         printk(" done.\n");
1476 }
1477
1478 /*
1479  * This looks a bit hackish but it's about the only one way of sending
1480  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1481  * not support the ExtINT mode, unfortunately.  We need to send these
1482  * cycles as some i82489DX-based boards have glue logic that keeps the
1483  * 8259A interrupt line asserted until INTA.  --macro
1484  */
1485 static inline void unlock_ExtINT_logic(void)
1486 {
1487         int apic, pin, i;
1488         struct IO_APIC_route_entry entry0, entry1;
1489         unsigned char save_control, save_freq_select;
1490         unsigned long flags;
1491
1492         pin  = find_isa_irq_pin(8, mp_INT);
1493         apic = find_isa_irq_apic(8, mp_INT);
1494         if (pin == -1)
1495                 return;
1496
1497         spin_lock_irqsave(&ioapic_lock, flags);
1498         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1499         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1500         spin_unlock_irqrestore(&ioapic_lock, flags);
1501         clear_IO_APIC_pin(apic, pin);
1502
1503         memset(&entry1, 0, sizeof(entry1));
1504
1505         entry1.dest_mode = 0;                   /* physical delivery */
1506         entry1.mask = 0;                        /* unmask IRQ now */
1507         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1508         entry1.delivery_mode = dest_ExtINT;
1509         entry1.polarity = entry0.polarity;
1510         entry1.trigger = 0;
1511         entry1.vector = 0;
1512
1513         spin_lock_irqsave(&ioapic_lock, flags);
1514         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1515         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1516         spin_unlock_irqrestore(&ioapic_lock, flags);
1517
1518         save_control = CMOS_READ(RTC_CONTROL);
1519         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1520         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1521                    RTC_FREQ_SELECT);
1522         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1523
1524         i = 100;
1525         while (i-- > 0) {
1526                 mdelay(10);
1527                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1528                         i -= 10;
1529         }
1530
1531         CMOS_WRITE(save_control, RTC_CONTROL);
1532         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1533         clear_IO_APIC_pin(apic, pin);
1534
1535         spin_lock_irqsave(&ioapic_lock, flags);
1536         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1537         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1538         spin_unlock_irqrestore(&ioapic_lock, flags);
1539 }
1540
1541 /*
1542  * This code may look a bit paranoid, but it's supposed to cooperate with
1543  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1544  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1545  * fanatically on his truly buggy board.
1546  *
1547  * FIXME: really need to revamp this for modern platforms only.
1548  */
1549 static inline void check_timer(void)
1550 {
1551         int apic1, pin1, apic2, pin2;
1552         int vector;
1553         cpumask_t mask;
1554
1555         /*
1556          * get/set the timer IRQ vector:
1557          */
1558         disable_8259A_irq(0);
1559         vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1560
1561         /*
1562          * Subtle, code in do_timer_interrupt() expects an AEOI
1563          * mode for the 8259A whenever interrupts are routed
1564          * through I/O APICs.  Also IRQ0 has to be enabled in
1565          * the 8259A which implies the virtual wire has to be
1566          * disabled in the local APIC.
1567          */
1568         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1569         init_8259A(1);
1570         if (timer_over_8254 > 0)
1571                 enable_8259A_irq(0);
1572
1573         pin1  = find_isa_irq_pin(0, mp_INT);
1574         apic1 = find_isa_irq_apic(0, mp_INT);
1575         pin2  = ioapic_i8259.pin;
1576         apic2 = ioapic_i8259.apic;
1577
1578         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1579                 vector, apic1, pin1, apic2, pin2);
1580
1581         if (pin1 != -1) {
1582                 /*
1583                  * Ok, does IRQ0 through the IOAPIC work?
1584                  */
1585                 unmask_IO_APIC_irq(0);
1586                 if (!no_timer_check && timer_irq_works()) {
1587                         nmi_watchdog_default();
1588                         if (nmi_watchdog == NMI_IO_APIC) {
1589                                 disable_8259A_irq(0);
1590                                 setup_nmi();
1591                                 enable_8259A_irq(0);
1592                         }
1593                         if (disable_timer_pin_1 > 0)
1594                                 clear_IO_APIC_pin(0, pin1);
1595                         return;
1596                 }
1597                 clear_IO_APIC_pin(apic1, pin1);
1598                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1599                                 "connected to IO-APIC\n");
1600         }
1601
1602         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1603                                 "through the 8259A ... ");
1604         if (pin2 != -1) {
1605                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1606                         apic2, pin2);
1607                 /*
1608                  * legacy devices should be connected to IO APIC #0
1609                  */
1610                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1611                 if (timer_irq_works()) {
1612                         apic_printk(APIC_VERBOSE," works.\n");
1613                         nmi_watchdog_default();
1614                         if (nmi_watchdog == NMI_IO_APIC) {
1615                                 setup_nmi();
1616                         }
1617                         return;
1618                 }
1619                 /*
1620                  * Cleanup, just in case ...
1621                  */
1622                 clear_IO_APIC_pin(apic2, pin2);
1623         }
1624         apic_printk(APIC_VERBOSE," failed.\n");
1625
1626         if (nmi_watchdog == NMI_IO_APIC) {
1627                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1628                 nmi_watchdog = 0;
1629         }
1630
1631         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1632
1633         disable_8259A_irq(0);
1634         irq_desc[0].chip = &lapic_irq_type;
1635         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1636         enable_8259A_irq(0);
1637
1638         if (timer_irq_works()) {
1639                 apic_printk(APIC_VERBOSE," works.\n");
1640                 return;
1641         }
1642         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1643         apic_printk(APIC_VERBOSE," failed.\n");
1644
1645         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1646
1647         init_8259A(0);
1648         make_8259A_irq(0);
1649         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1650
1651         unlock_ExtINT_logic();
1652
1653         if (timer_irq_works()) {
1654                 apic_printk(APIC_VERBOSE," works.\n");
1655                 return;
1656         }
1657         apic_printk(APIC_VERBOSE," failed :(.\n");
1658         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1659 }
1660
1661 static int __init notimercheck(char *s)
1662 {
1663         no_timer_check = 1;
1664         return 1;
1665 }
1666 __setup("no_timer_check", notimercheck);
1667
1668 /*
1669  *
1670  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1671  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1672  *   Linux doesn't really care, as it's not actually used
1673  *   for any interrupt handling anyway.
1674  */
1675 #define PIC_IRQS        (1<<2)
1676
1677 void __init setup_IO_APIC(void)
1678 {
1679         enable_IO_APIC();
1680
1681         if (acpi_ioapic)
1682                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1683         else
1684                 io_apic_irqs = ~PIC_IRQS;
1685
1686         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1687
1688         sync_Arb_IDs();
1689         setup_IO_APIC_irqs();
1690         init_IO_APIC_traps();
1691         check_timer();
1692         if (!acpi_ioapic)
1693                 print_IO_APIC();
1694 }
1695
1696 struct sysfs_ioapic_data {
1697         struct sys_device dev;
1698         struct IO_APIC_route_entry entry[0];
1699 };
1700 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1701
1702 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1703 {
1704         struct IO_APIC_route_entry *entry;
1705         struct sysfs_ioapic_data *data;
1706         int i;
1707
1708         data = container_of(dev, struct sysfs_ioapic_data, dev);
1709         entry = data->entry;
1710         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1711                 *entry = ioapic_read_entry(dev->id, i);
1712
1713         return 0;
1714 }
1715
1716 static int ioapic_resume(struct sys_device *dev)
1717 {
1718         struct IO_APIC_route_entry *entry;
1719         struct sysfs_ioapic_data *data;
1720         unsigned long flags;
1721         union IO_APIC_reg_00 reg_00;
1722         int i;
1723
1724         data = container_of(dev, struct sysfs_ioapic_data, dev);
1725         entry = data->entry;
1726
1727         spin_lock_irqsave(&ioapic_lock, flags);
1728         reg_00.raw = io_apic_read(dev->id, 0);
1729         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1730                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1731                 io_apic_write(dev->id, 0, reg_00.raw);
1732         }
1733         spin_unlock_irqrestore(&ioapic_lock, flags);
1734         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1735                 ioapic_write_entry(dev->id, i, entry[i]);
1736
1737         return 0;
1738 }
1739
1740 static struct sysdev_class ioapic_sysdev_class = {
1741         set_kset_name("ioapic"),
1742         .suspend = ioapic_suspend,
1743         .resume = ioapic_resume,
1744 };
1745
1746 static int __init ioapic_init_sysfs(void)
1747 {
1748         struct sys_device * dev;
1749         int i, size, error = 0;
1750
1751         error = sysdev_class_register(&ioapic_sysdev_class);
1752         if (error)
1753                 return error;
1754
1755         for (i = 0; i < nr_ioapics; i++ ) {
1756                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1757                         * sizeof(struct IO_APIC_route_entry);
1758                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1759                 if (!mp_ioapic_data[i]) {
1760                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1761                         continue;
1762                 }
1763                 memset(mp_ioapic_data[i], 0, size);
1764                 dev = &mp_ioapic_data[i]->dev;
1765                 dev->id = i;
1766                 dev->cls = &ioapic_sysdev_class;
1767                 error = sysdev_register(dev);
1768                 if (error) {
1769                         kfree(mp_ioapic_data[i]);
1770                         mp_ioapic_data[i] = NULL;
1771                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1772                         continue;
1773                 }
1774         }
1775
1776         return 0;
1777 }
1778
1779 device_initcall(ioapic_init_sysfs);
1780
1781 /*
1782  * Dynamic irq allocate and deallocation
1783  */
1784 int create_irq(void)
1785 {
1786         /* Allocate an unused irq */
1787         int irq;
1788         int new;
1789         int vector = 0;
1790         unsigned long flags;
1791         cpumask_t mask;
1792
1793         irq = -ENOSPC;
1794         spin_lock_irqsave(&vector_lock, flags);
1795         for (new = (NR_IRQS - 1); new >= 0; new--) {
1796                 if (platform_legacy_irq(new))
1797                         continue;
1798                 if (irq_vector[new] != 0)
1799                         continue;
1800                 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1801                 if (likely(vector > 0))
1802                         irq = new;
1803                 break;
1804         }
1805         spin_unlock_irqrestore(&vector_lock, flags);
1806
1807         if (irq >= 0) {
1808                 dynamic_irq_init(irq);
1809         }
1810         return irq;
1811 }
1812
1813 void destroy_irq(unsigned int irq)
1814 {
1815         unsigned long flags;
1816
1817         dynamic_irq_cleanup(irq);
1818
1819         spin_lock_irqsave(&vector_lock, flags);
1820         irq_vector[irq] = 0;
1821         spin_unlock_irqrestore(&vector_lock, flags);
1822 }
1823
1824 /*
1825  * MSI mesage composition
1826  */
1827 #ifdef CONFIG_PCI_MSI
1828 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1829 {
1830         int vector;
1831         unsigned dest;
1832         cpumask_t tmp;
1833
1834         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1835         if (vector >= 0) {
1836                 dest = cpu_mask_to_apicid(tmp);
1837
1838                 msg->address_hi = MSI_ADDR_BASE_HI;
1839                 msg->address_lo =
1840                         MSI_ADDR_BASE_LO |
1841                         ((INT_DEST_MODE == 0) ?
1842                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1843                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1844                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1845                                 MSI_ADDR_REDIRECTION_CPU:
1846                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1847                         MSI_ADDR_DEST_ID(dest);
1848
1849                 msg->data =
1850                         MSI_DATA_TRIGGER_EDGE |
1851                         MSI_DATA_LEVEL_ASSERT |
1852                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1853                                 MSI_DATA_DELIVERY_FIXED:
1854                                 MSI_DATA_DELIVERY_LOWPRI) |
1855                         MSI_DATA_VECTOR(vector);
1856         }
1857         return vector;
1858 }
1859
1860 #ifdef CONFIG_SMP
1861 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1862 {
1863         struct msi_msg msg;
1864         unsigned int dest;
1865         cpumask_t tmp;
1866         int vector;
1867
1868         cpus_and(tmp, mask, cpu_online_map);
1869         if (cpus_empty(tmp))
1870                 tmp = TARGET_CPUS;
1871
1872         cpus_and(mask, tmp, CPU_MASK_ALL);
1873
1874         vector = assign_irq_vector(irq, mask, &tmp);
1875         if (vector < 0)
1876                 return;
1877
1878         dest = cpu_mask_to_apicid(tmp);
1879
1880         read_msi_msg(irq, &msg);
1881
1882         msg.data &= ~MSI_DATA_VECTOR_MASK;
1883         msg.data |= MSI_DATA_VECTOR(vector);
1884         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1885         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1886
1887         write_msi_msg(irq, &msg);
1888         set_native_irq_info(irq, mask);
1889 }
1890 #endif /* CONFIG_SMP */
1891
1892 /*
1893  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1894  * which implement the MSI or MSI-X Capability Structure.
1895  */
1896 static struct irq_chip msi_chip = {
1897         .name           = "PCI-MSI",
1898         .unmask         = unmask_msi_irq,
1899         .mask           = mask_msi_irq,
1900         .ack            = ack_apic_edge,
1901 #ifdef CONFIG_SMP
1902         .set_affinity   = set_msi_irq_affinity,
1903 #endif
1904         .retrigger      = ioapic_retrigger_irq,
1905 };
1906
1907 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1908 {
1909         struct msi_msg msg;
1910         int ret;
1911         ret = msi_compose_msg(dev, irq, &msg);
1912         if (ret < 0)
1913                 return ret;
1914
1915         write_msi_msg(irq, &msg);
1916
1917         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1918
1919         return 0;
1920 }
1921
1922 void arch_teardown_msi_irq(unsigned int irq)
1923 {
1924         return;
1925 }
1926
1927 #endif /* CONFIG_PCI_MSI */
1928
1929 /*
1930  * Hypertransport interrupt support
1931  */
1932 #ifdef CONFIG_HT_IRQ
1933
1934 #ifdef CONFIG_SMP
1935
1936 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1937 {
1938         u32 low, high;
1939         low  = read_ht_irq_low(irq);
1940         high = read_ht_irq_high(irq);
1941
1942         low  &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1943         high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1944
1945         low  |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1946         high |= HT_IRQ_HIGH_DEST_ID(dest);
1947
1948         write_ht_irq_low(irq, low);
1949         write_ht_irq_high(irq, high);
1950 }
1951
1952 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1953 {
1954         unsigned int dest;
1955         cpumask_t tmp;
1956         int vector;
1957
1958         cpus_and(tmp, mask, cpu_online_map);
1959         if (cpus_empty(tmp))
1960                 tmp = TARGET_CPUS;
1961
1962         cpus_and(mask, tmp, CPU_MASK_ALL);
1963
1964         vector = assign_irq_vector(irq, mask, &tmp);
1965         if (vector < 0)
1966                 return;
1967
1968         dest = cpu_mask_to_apicid(tmp);
1969
1970         target_ht_irq(irq, dest, vector & 0xff);
1971         set_native_irq_info(irq, mask);
1972 }
1973 #endif
1974
1975 static struct irq_chip ht_irq_chip = {
1976         .name           = "PCI-HT",
1977         .mask           = mask_ht_irq,
1978         .unmask         = unmask_ht_irq,
1979         .ack            = ack_apic_edge,
1980 #ifdef CONFIG_SMP
1981         .set_affinity   = set_ht_irq_affinity,
1982 #endif
1983         .retrigger      = ioapic_retrigger_irq,
1984 };
1985
1986 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
1987 {
1988         int vector;
1989         cpumask_t tmp;
1990
1991         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1992         if (vector >= 0) {
1993                 u32 low, high;
1994                 unsigned dest;
1995
1996                 dest = cpu_mask_to_apicid(tmp);
1997
1998                 high =  HT_IRQ_HIGH_DEST_ID(dest);
1999
2000                 low =   HT_IRQ_LOW_BASE |
2001                         HT_IRQ_LOW_DEST_ID(dest) |
2002                         HT_IRQ_LOW_VECTOR(vector) |
2003                         ((INT_DEST_MODE == 0) ?
2004                                 HT_IRQ_LOW_DM_PHYSICAL :
2005                                 HT_IRQ_LOW_DM_LOGICAL) |
2006                         HT_IRQ_LOW_RQEOI_EDGE |
2007                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2008                                 HT_IRQ_LOW_MT_FIXED :
2009                                 HT_IRQ_LOW_MT_ARBITRATED);
2010
2011                 write_ht_irq_low(irq, low);
2012                 write_ht_irq_high(irq, high);
2013
2014                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2015                                               handle_edge_irq, "edge");
2016         }
2017         return vector;
2018 }
2019 #endif /* CONFIG_HT_IRQ */
2020
2021 /* --------------------------------------------------------------------------
2022                           ACPI-based IOAPIC Configuration
2023    -------------------------------------------------------------------------- */
2024
2025 #ifdef CONFIG_ACPI
2026
2027 #define IO_APIC_MAX_ID          0xFE
2028
2029 int __init io_apic_get_redir_entries (int ioapic)
2030 {
2031         union IO_APIC_reg_01    reg_01;
2032         unsigned long flags;
2033
2034         spin_lock_irqsave(&ioapic_lock, flags);
2035         reg_01.raw = io_apic_read(ioapic, 1);
2036         spin_unlock_irqrestore(&ioapic_lock, flags);
2037
2038         return reg_01.bits.entries;
2039 }
2040
2041
2042 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2043 {
2044         struct IO_APIC_route_entry entry;
2045         unsigned long flags;
2046         int vector;
2047         cpumask_t mask;
2048
2049         if (!IO_APIC_IRQ(irq)) {
2050                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2051                         ioapic);
2052                 return -EINVAL;
2053         }
2054
2055         /*
2056          * IRQs < 16 are already in the irq_2_pin[] map
2057          */
2058         if (irq >= 16)
2059                 add_pin_to_irq(irq, ioapic, pin);
2060
2061
2062         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
2063         if (vector < 0)
2064                 return vector;
2065
2066         /*
2067          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2068          * Note that we mask (disable) IRQs now -- these get enabled when the
2069          * corresponding device driver registers for this IRQ.
2070          */
2071
2072         memset(&entry,0,sizeof(entry));
2073
2074         entry.delivery_mode = INT_DELIVERY_MODE;
2075         entry.dest_mode = INT_DEST_MODE;
2076         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
2077         entry.trigger = triggering;
2078         entry.polarity = polarity;
2079         entry.mask = 1;                                  /* Disabled (masked) */
2080         entry.vector = vector & 0xff;
2081
2082         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2083                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2084                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2085                triggering, polarity);
2086
2087         ioapic_register_intr(irq, entry.vector, triggering);
2088
2089         if (!ioapic && (irq < 16))
2090                 disable_8259A_irq(irq);
2091
2092         ioapic_write_entry(ioapic, pin, entry);
2093
2094         spin_lock_irqsave(&ioapic_lock, flags);
2095         set_native_irq_info(irq, TARGET_CPUS);
2096         spin_unlock_irqrestore(&ioapic_lock, flags);
2097
2098         return 0;
2099 }
2100
2101 #endif /* CONFIG_ACPI */
2102
2103
2104 /*
2105  * This function currently is only a helper for the i386 smp boot process where
2106  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2107  * so mask in all cases should simply be TARGET_CPUS
2108  */
2109 #ifdef CONFIG_SMP
2110 void __init setup_ioapic_dest(void)
2111 {
2112         int pin, ioapic, irq, irq_entry;
2113
2114         if (skip_ioapic_setup == 1)
2115                 return;
2116
2117         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2118                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2119                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2120                         if (irq_entry == -1)
2121                                 continue;
2122                         irq = pin_2_irq(irq_entry, ioapic, pin);
2123                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2124                 }
2125
2126         }
2127 }
2128 #endif