arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/asm.h>
  42 #include <asm/cpu.h>
  43 #include <asm/io.h>
  44 #include <asm/desc.h>
  45 #include <asm/vmx.h>
  46 #include <asm/virtext.h>
  47 #include <asm/mce.h>
  48 #include <asm/fpu/internal.h>
  49 #include <asm/perf_event.h>
  50 #include <asm/debugreg.h>
  51 #include <asm/kexec.h>
  52 #include <asm/apic.h>
  53 #include <asm/irq_remapping.h>
  54 #include <asm/mmu_context.h>
  55 #include <asm/spec-ctrl.h>
  56 #include <asm/mshyperv.h>
  57
  58 #include "trace.h"
  59 #include "pmu.h"
  60 #include "vmx_evmcs.h"
  61
  62 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  63 #define __ex_clear(x, reg) \
  64         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  65
  66 MODULE_AUTHOR("Qumranet");
  67 MODULE_LICENSE("GPL");
  68
  69 static const struct x86_cpu_id vmx_cpu_id[] = {
  70         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  71         {}
  72 };
  73 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  74
  75 static bool __read_mostly enable_vpid = 1;
  76 module_param_named(vpid, enable_vpid, bool, 0444);
  77
  78 static bool __read_mostly enable_vnmi = 1;
  79 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  80
  81 static bool __read_mostly flexpriority_enabled = 1;
  82 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  83
  84 static bool __read_mostly enable_ept = 1;
  85 module_param_named(ept, enable_ept, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_unrestricted_guest = 1;
  88 module_param_named(unrestricted_guest,
  89                         enable_unrestricted_guest, bool, S_IRUGO);
  90
  91 static bool __read_mostly enable_ept_ad_bits = 1;
  92 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  93
  94 static bool __read_mostly emulate_invalid_guest_state = true;
  95 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  96
  97 static bool __read_mostly fasteoi = 1;
  98 module_param(fasteoi, bool, S_IRUGO);
  99
 100 static bool __read_mostly enable_apicv = 1;
 101 module_param(enable_apicv, bool, S_IRUGO);
 102
 103 static bool __read_mostly enable_shadow_vmcs = 1;
 104 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 105 /*
 106  * If nested=1, nested virtualization is supported, i.e., guests may use
 107  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 108  * use VMX instructions.
 109  */
 110 static bool __read_mostly nested = 0;
 111 module_param(nested, bool, S_IRUGO);
 112
 113 static u64 __read_mostly host_xss;
 114
 115 static bool __read_mostly enable_pml = 1;
 116 module_param_named(pml, enable_pml, bool, S_IRUGO);
 117
 118 #define MSR_TYPE_R      1
 119 #define MSR_TYPE_W      2
 120 #define MSR_TYPE_RW     3
 121
 122 #define MSR_BITMAP_MODE_X2APIC          1
 123 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 124 #define MSR_BITMAP_MODE_LM              4
 125
 126 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 127
 128 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 129 static int __read_mostly cpu_preemption_timer_multi;
 130 static bool __read_mostly enable_preemption_timer = 1;
 131 #ifdef CONFIG_X86_64
 132 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 133 #endif
 134
 135 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 136 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 137 #define KVM_VM_CR0_ALWAYS_ON                            \
 138         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 139          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 140 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 141         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 142          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 143
 144 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 145 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 146 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 147
 148 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 149
 150 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 151
 152 /*
 153  * Hyper-V requires all of these, so mark them as supported even though
 154  * they are just treated the same as all-context.
 155  */
 156 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 157         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 158         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 159         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 160         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 161
 162 /*
 163  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 164  * ple_gap:    upper bound on the amount of time between two successive
 165  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 166  *             According to test, this time is usually smaller than 128 cycles.
 167  * ple_window: upper bound on the amount of time a guest is allowed to execute
 168  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 169  *             less than 2^12 cycles
 170  * Time is measured based on a counter that runs at the same rate as the TSC,
 171  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 172  */
 173 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 174
 175 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 176 module_param(ple_window, uint, 0444);
 177
 178 /* Default doubles per-vcpu window every exit. */
 179 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 180 module_param(ple_window_grow, uint, 0444);
 181
 182 /* Default resets per-vcpu window every exit to ple_window. */
 183 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 184 module_param(ple_window_shrink, uint, 0444);
 185
 186 /* Default is to compute the maximum so we can never overflow. */
 187 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 188 module_param(ple_window_max, uint, 0444);
 189
 190 extern const ulong vmx_return;
 191
 192 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 193 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 194 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 195
 196 /* Storage for pre module init parameter parsing */
 197 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 198
 199 static const struct {
 200         const char *option;
 201         bool for_parse;
 202 } vmentry_l1d_param[] = {
 203         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 204         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 205         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 206         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 207         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 208         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 209 };
 210
 211 #define L1D_CACHE_ORDER 4
 212 static void *vmx_l1d_flush_pages;
 213
 214 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 215 {
 216         struct page *page;
 217         unsigned int i;
 218
 219         if (!enable_ept) {
 220                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 221                 return 0;
 222         }
 223
 224         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 225                 u64 msr;
 226
 227                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 228                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 229                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 230                         return 0;
 231                 }
 232         }
 233
 234         /* If set to auto use the default l1tf mitigation method */
 235         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 236                 switch (l1tf_mitigation) {
 237                 case L1TF_MITIGATION_OFF:
 238                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 239                         break;
 240                 case L1TF_MITIGATION_FLUSH_NOWARN:
 241                 case L1TF_MITIGATION_FLUSH:
 242                 case L1TF_MITIGATION_FLUSH_NOSMT:
 243                         l1tf = VMENTER_L1D_FLUSH_COND;
 244                         break;
 245                 case L1TF_MITIGATION_FULL:
 246                 case L1TF_MITIGATION_FULL_FORCE:
 247                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 248                         break;
 249                 }
 250         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 251                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 252         }
 253
 254         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 255             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 256                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 257                 if (!page)
 258                         return -ENOMEM;
 259                 vmx_l1d_flush_pages = page_address(page);
 260
 261                 /*
 262                  * Initialize each page with a different pattern in
 263                  * order to protect against KSM in the nested
 264                  * virtualization case.
 265                  */
 266                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 267                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 268                                PAGE_SIZE);
 269                 }
 270         }
 271
 272         l1tf_vmx_mitigation = l1tf;
 273
 274         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 275                 static_branch_enable(&vmx_l1d_should_flush);
 276         else
 277                 static_branch_disable(&vmx_l1d_should_flush);
 278
 279         if (l1tf == VMENTER_L1D_FLUSH_COND)
 280                 static_branch_enable(&vmx_l1d_flush_cond);
 281         else
 282                 static_branch_disable(&vmx_l1d_flush_cond);
 283         return 0;
 284 }
 285
 286 static int vmentry_l1d_flush_parse(const char *s)
 287 {
 288         unsigned int i;
 289
 290         if (s) {
 291                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 292                         if (vmentry_l1d_param[i].for_parse &&
 293                             sysfs_streq(s, vmentry_l1d_param[i].option))
 294                                 return i;
 295                 }
 296         }
 297         return -EINVAL;
 298 }
 299
 300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 301 {
 302         int l1tf, ret;
 303
 304         l1tf = vmentry_l1d_flush_parse(s);
 305         if (l1tf < 0)
 306                 return l1tf;
 307
 308         if (!boot_cpu_has(X86_BUG_L1TF))
 309                 return 0;
 310
 311         /*
 312          * Has vmx_init() run already? If not then this is the pre init
 313          * parameter parsing. In that case just store the value and let
 314          * vmx_init() do the proper setup after enable_ept has been
 315          * established.
 316          */
 317         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 318                 vmentry_l1d_flush_param = l1tf;
 319                 return 0;
 320         }
 321
 322         mutex_lock(&vmx_l1d_flush_mutex);
 323         ret = vmx_setup_l1d_flush(l1tf);
 324         mutex_unlock(&vmx_l1d_flush_mutex);
 325         return ret;
 326 }
 327
 328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 329 {
 330         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 331                 return sprintf(s, "???\n");
 332
 333         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 334 }
 335
 336 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 337         .set = vmentry_l1d_flush_set,
 338         .get = vmentry_l1d_flush_get,
 339 };
 340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 341
 342 enum ept_pointers_status {
 343         EPT_POINTERS_CHECK = 0,
 344         EPT_POINTERS_MATCH = 1,
 345         EPT_POINTERS_MISMATCH = 2
 346 };
 347
 348 struct kvm_vmx {
 349         struct kvm kvm;
 350
 351         unsigned int tss_addr;
 352         bool ept_identity_pagetable_done;
 353         gpa_t ept_identity_map_addr;
 354
 355         enum ept_pointers_status ept_pointers_match;
 356         spinlock_t ept_pointer_lock;
 357 };
 358
 359 #define NR_AUTOLOAD_MSRS 8
 360
 361 struct vmcs_hdr {
 362         u32 revision_id:31;
 363         u32 shadow_vmcs:1;
 364 };
 365
 366 struct vmcs {
 367         struct vmcs_hdr hdr;
 368         u32 abort;
 369         char data[0];
 370 };
 371
 372 /*
 373  * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
 374  * and whose values change infrequently, but are not constant.  I.e. this is
 375  * used as a write-through cache of the corresponding VMCS fields.
 376  */
 377 struct vmcs_host_state {
 378         unsigned long cr3;      /* May not match real cr3 */
 379         unsigned long cr4;      /* May not match real cr4 */
 380         unsigned long gs_base;
 381         unsigned long fs_base;
 382
 383         u16           fs_sel, gs_sel, ldt_sel;
 384 #ifdef CONFIG_X86_64
 385         u16           ds_sel, es_sel;
 386 #endif
 387 };
 388
 389 /*
 390  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 391  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 392  * loaded on this CPU (so we can clear them if the CPU goes down).
 393  */
 394 struct loaded_vmcs {
 395         struct vmcs *vmcs;
 396         struct vmcs *shadow_vmcs;
 397         int cpu;
 398         bool launched;
 399         bool nmi_known_unmasked;
 400         bool hv_timer_armed;
 401         /* Support for vnmi-less CPUs */
 402         int soft_vnmi_blocked;
 403         ktime_t entry_time;
 404         s64 vnmi_blocked_time;
 405         unsigned long *msr_bitmap;
 406         struct list_head loaded_vmcss_on_cpu_link;
 407         struct vmcs_host_state host_state;
 408 };
 409
 410 struct shared_msr_entry {
 411         unsigned index;
 412         u64 data;
 413         u64 mask;
 414 };
 415
 416 /*
 417  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 418  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 419  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 420  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 421  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 422  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 423  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 424  * underlying hardware which will be used to run L2.
 425  * This structure is packed to ensure that its layout is identical across
 426  * machines (necessary for live migration).
 427  *
 428  * IMPORTANT: Changing the layout of existing fields in this structure
 429  * will break save/restore compatibility with older kvm releases. When
 430  * adding new fields, either use space in the reserved padding* arrays
 431  * or add the new fields to the end of the structure.
 432  */
 433 typedef u64 natural_width;
 434 struct __packed vmcs12 {
 435         /* According to the Intel spec, a VMCS region must start with the
 436          * following two fields. Then follow implementation-specific data.
 437          */
 438         struct vmcs_hdr hdr;
 439         u32 abort;
 440
 441         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 442         u32 padding[7]; /* room for future expansion */
 443
 444         u64 io_bitmap_a;
 445         u64 io_bitmap_b;
 446         u64 msr_bitmap;
 447         u64 vm_exit_msr_store_addr;
 448         u64 vm_exit_msr_load_addr;
 449         u64 vm_entry_msr_load_addr;
 450         u64 tsc_offset;
 451         u64 virtual_apic_page_addr;
 452         u64 apic_access_addr;
 453         u64 posted_intr_desc_addr;
 454         u64 ept_pointer;
 455         u64 eoi_exit_bitmap0;
 456         u64 eoi_exit_bitmap1;
 457         u64 eoi_exit_bitmap2;
 458         u64 eoi_exit_bitmap3;
 459         u64 xss_exit_bitmap;
 460         u64 guest_physical_address;
 461         u64 vmcs_link_pointer;
 462         u64 guest_ia32_debugctl;
 463         u64 guest_ia32_pat;
 464         u64 guest_ia32_efer;
 465         u64 guest_ia32_perf_global_ctrl;
 466         u64 guest_pdptr0;
 467         u64 guest_pdptr1;
 468         u64 guest_pdptr2;
 469         u64 guest_pdptr3;
 470         u64 guest_bndcfgs;
 471         u64 host_ia32_pat;
 472         u64 host_ia32_efer;
 473         u64 host_ia32_perf_global_ctrl;
 474         u64 vmread_bitmap;
 475         u64 vmwrite_bitmap;
 476         u64 vm_function_control;
 477         u64 eptp_list_address;
 478         u64 pml_address;
 479         u64 padding64[3]; /* room for future expansion */
 480         /*
 481          * To allow migration of L1 (complete with its L2 guests) between
 482          * machines of different natural widths (32 or 64 bit), we cannot have
 483          * unsigned long fields with no explict size. We use u64 (aliased
 484          * natural_width) instead. Luckily, x86 is little-endian.
 485          */
 486         natural_width cr0_guest_host_mask;
 487         natural_width cr4_guest_host_mask;
 488         natural_width cr0_read_shadow;
 489         natural_width cr4_read_shadow;
 490         natural_width cr3_target_value0;
 491         natural_width cr3_target_value1;
 492         natural_width cr3_target_value2;
 493         natural_width cr3_target_value3;
 494         natural_width exit_qualification;
 495         natural_width guest_linear_address;
 496         natural_width guest_cr0;
 497         natural_width guest_cr3;
 498         natural_width guest_cr4;
 499         natural_width guest_es_base;
 500         natural_width guest_cs_base;
 501         natural_width guest_ss_base;
 502         natural_width guest_ds_base;
 503         natural_width guest_fs_base;
 504         natural_width guest_gs_base;
 505         natural_width guest_ldtr_base;
 506         natural_width guest_tr_base;
 507         natural_width guest_gdtr_base;
 508         natural_width guest_idtr_base;
 509         natural_width guest_dr7;
 510         natural_width guest_rsp;
 511         natural_width guest_rip;
 512         natural_width guest_rflags;
 513         natural_width guest_pending_dbg_exceptions;
 514         natural_width guest_sysenter_esp;
 515         natural_width guest_sysenter_eip;
 516         natural_width host_cr0;
 517         natural_width host_cr3;
 518         natural_width host_cr4;
 519         natural_width host_fs_base;
 520         natural_width host_gs_base;
 521         natural_width host_tr_base;
 522         natural_width host_gdtr_base;
 523         natural_width host_idtr_base;
 524         natural_width host_ia32_sysenter_esp;
 525         natural_width host_ia32_sysenter_eip;
 526         natural_width host_rsp;
 527         natural_width host_rip;
 528         natural_width paddingl[8]; /* room for future expansion */
 529         u32 pin_based_vm_exec_control;
 530         u32 cpu_based_vm_exec_control;
 531         u32 exception_bitmap;
 532         u32 page_fault_error_code_mask;
 533         u32 page_fault_error_code_match;
 534         u32 cr3_target_count;
 535         u32 vm_exit_controls;
 536         u32 vm_exit_msr_store_count;
 537         u32 vm_exit_msr_load_count;
 538         u32 vm_entry_controls;
 539         u32 vm_entry_msr_load_count;
 540         u32 vm_entry_intr_info_field;
 541         u32 vm_entry_exception_error_code;
 542         u32 vm_entry_instruction_len;
 543         u32 tpr_threshold;
 544         u32 secondary_vm_exec_control;
 545         u32 vm_instruction_error;
 546         u32 vm_exit_reason;
 547         u32 vm_exit_intr_info;
 548         u32 vm_exit_intr_error_code;
 549         u32 idt_vectoring_info_field;
 550         u32 idt_vectoring_error_code;
 551         u32 vm_exit_instruction_len;
 552         u32 vmx_instruction_info;
 553         u32 guest_es_limit;
 554         u32 guest_cs_limit;
 555         u32 guest_ss_limit;
 556         u32 guest_ds_limit;
 557         u32 guest_fs_limit;
 558         u32 guest_gs_limit;
 559         u32 guest_ldtr_limit;
 560         u32 guest_tr_limit;
 561         u32 guest_gdtr_limit;
 562         u32 guest_idtr_limit;
 563         u32 guest_es_ar_bytes;
 564         u32 guest_cs_ar_bytes;
 565         u32 guest_ss_ar_bytes;
 566         u32 guest_ds_ar_bytes;
 567         u32 guest_fs_ar_bytes;
 568         u32 guest_gs_ar_bytes;
 569         u32 guest_ldtr_ar_bytes;
 570         u32 guest_tr_ar_bytes;
 571         u32 guest_interruptibility_info;
 572         u32 guest_activity_state;
 573         u32 guest_sysenter_cs;
 574         u32 host_ia32_sysenter_cs;
 575         u32 vmx_preemption_timer_value;
 576         u32 padding32[7]; /* room for future expansion */
 577         u16 virtual_processor_id;
 578         u16 posted_intr_nv;
 579         u16 guest_es_selector;
 580         u16 guest_cs_selector;
 581         u16 guest_ss_selector;
 582         u16 guest_ds_selector;
 583         u16 guest_fs_selector;
 584         u16 guest_gs_selector;
 585         u16 guest_ldtr_selector;
 586         u16 guest_tr_selector;
 587         u16 guest_intr_status;
 588         u16 host_es_selector;
 589         u16 host_cs_selector;
 590         u16 host_ss_selector;
 591         u16 host_ds_selector;
 592         u16 host_fs_selector;
 593         u16 host_gs_selector;
 594         u16 host_tr_selector;
 595         u16 guest_pml_index;
 596 };
 597
 598 /*
 599  * For save/restore compatibility, the vmcs12 field offsets must not change.
 600  */
 601 #define CHECK_OFFSET(field, loc)                                \
 602         BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc),       \
 603                 "Offset of " #field " in struct vmcs12 has changed.")
 604
 605 static inline void vmx_check_vmcs12_offsets(void) {
 606         CHECK_OFFSET(hdr, 0);
 607         CHECK_OFFSET(abort, 4);
 608         CHECK_OFFSET(launch_state, 8);
 609         CHECK_OFFSET(io_bitmap_a, 40);
 610         CHECK_OFFSET(io_bitmap_b, 48);
 611         CHECK_OFFSET(msr_bitmap, 56);
 612         CHECK_OFFSET(vm_exit_msr_store_addr, 64);
 613         CHECK_OFFSET(vm_exit_msr_load_addr, 72);
 614         CHECK_OFFSET(vm_entry_msr_load_addr, 80);
 615         CHECK_OFFSET(tsc_offset, 88);
 616         CHECK_OFFSET(virtual_apic_page_addr, 96);
 617         CHECK_OFFSET(apic_access_addr, 104);
 618         CHECK_OFFSET(posted_intr_desc_addr, 112);
 619         CHECK_OFFSET(ept_pointer, 120);
 620         CHECK_OFFSET(eoi_exit_bitmap0, 128);
 621         CHECK_OFFSET(eoi_exit_bitmap1, 136);
 622         CHECK_OFFSET(eoi_exit_bitmap2, 144);
 623         CHECK_OFFSET(eoi_exit_bitmap3, 152);
 624         CHECK_OFFSET(xss_exit_bitmap, 160);
 625         CHECK_OFFSET(guest_physical_address, 168);
 626         CHECK_OFFSET(vmcs_link_pointer, 176);
 627         CHECK_OFFSET(guest_ia32_debugctl, 184);
 628         CHECK_OFFSET(guest_ia32_pat, 192);
 629         CHECK_OFFSET(guest_ia32_efer, 200);
 630         CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
 631         CHECK_OFFSET(guest_pdptr0, 216);
 632         CHECK_OFFSET(guest_pdptr1, 224);
 633         CHECK_OFFSET(guest_pdptr2, 232);
 634         CHECK_OFFSET(guest_pdptr3, 240);
 635         CHECK_OFFSET(guest_bndcfgs, 248);
 636         CHECK_OFFSET(host_ia32_pat, 256);
 637         CHECK_OFFSET(host_ia32_efer, 264);
 638         CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
 639         CHECK_OFFSET(vmread_bitmap, 280);
 640         CHECK_OFFSET(vmwrite_bitmap, 288);
 641         CHECK_OFFSET(vm_function_control, 296);
 642         CHECK_OFFSET(eptp_list_address, 304);
 643         CHECK_OFFSET(pml_address, 312);
 644         CHECK_OFFSET(cr0_guest_host_mask, 344);
 645         CHECK_OFFSET(cr4_guest_host_mask, 352);
 646         CHECK_OFFSET(cr0_read_shadow, 360);
 647         CHECK_OFFSET(cr4_read_shadow, 368);
 648         CHECK_OFFSET(cr3_target_value0, 376);
 649         CHECK_OFFSET(cr3_target_value1, 384);
 650         CHECK_OFFSET(cr3_target_value2, 392);
 651         CHECK_OFFSET(cr3_target_value3, 400);
 652         CHECK_OFFSET(exit_qualification, 408);
 653         CHECK_OFFSET(guest_linear_address, 416);
 654         CHECK_OFFSET(guest_cr0, 424);
 655         CHECK_OFFSET(guest_cr3, 432);
 656         CHECK_OFFSET(guest_cr4, 440);
 657         CHECK_OFFSET(guest_es_base, 448);
 658         CHECK_OFFSET(guest_cs_base, 456);
 659         CHECK_OFFSET(guest_ss_base, 464);
 660         CHECK_OFFSET(guest_ds_base, 472);
 661         CHECK_OFFSET(guest_fs_base, 480);
 662         CHECK_OFFSET(guest_gs_base, 488);
 663         CHECK_OFFSET(guest_ldtr_base, 496);
 664         CHECK_OFFSET(guest_tr_base, 504);
 665         CHECK_OFFSET(guest_gdtr_base, 512);
 666         CHECK_OFFSET(guest_idtr_base, 520);
 667         CHECK_OFFSET(guest_dr7, 528);
 668         CHECK_OFFSET(guest_rsp, 536);
 669         CHECK_OFFSET(guest_rip, 544);
 670         CHECK_OFFSET(guest_rflags, 552);
 671         CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
 672         CHECK_OFFSET(guest_sysenter_esp, 568);
 673         CHECK_OFFSET(guest_sysenter_eip, 576);
 674         CHECK_OFFSET(host_cr0, 584);
 675         CHECK_OFFSET(host_cr3, 592);
 676         CHECK_OFFSET(host_cr4, 600);
 677         CHECK_OFFSET(host_fs_base, 608);
 678         CHECK_OFFSET(host_gs_base, 616);
 679         CHECK_OFFSET(host_tr_base, 624);
 680         CHECK_OFFSET(host_gdtr_base, 632);
 681         CHECK_OFFSET(host_idtr_base, 640);
 682         CHECK_OFFSET(host_ia32_sysenter_esp, 648);
 683         CHECK_OFFSET(host_ia32_sysenter_eip, 656);
 684         CHECK_OFFSET(host_rsp, 664);
 685         CHECK_OFFSET(host_rip, 672);
 686         CHECK_OFFSET(pin_based_vm_exec_control, 744);
 687         CHECK_OFFSET(cpu_based_vm_exec_control, 748);
 688         CHECK_OFFSET(exception_bitmap, 752);
 689         CHECK_OFFSET(page_fault_error_code_mask, 756);
 690         CHECK_OFFSET(page_fault_error_code_match, 760);
 691         CHECK_OFFSET(cr3_target_count, 764);
 692         CHECK_OFFSET(vm_exit_controls, 768);
 693         CHECK_OFFSET(vm_exit_msr_store_count, 772);
 694         CHECK_OFFSET(vm_exit_msr_load_count, 776);
 695         CHECK_OFFSET(vm_entry_controls, 780);
 696         CHECK_OFFSET(vm_entry_msr_load_count, 784);
 697         CHECK_OFFSET(vm_entry_intr_info_field, 788);
 698         CHECK_OFFSET(vm_entry_exception_error_code, 792);
 699         CHECK_OFFSET(vm_entry_instruction_len, 796);
 700         CHECK_OFFSET(tpr_threshold, 800);
 701         CHECK_OFFSET(secondary_vm_exec_control, 804);
 702         CHECK_OFFSET(vm_instruction_error, 808);
 703         CHECK_OFFSET(vm_exit_reason, 812);
 704         CHECK_OFFSET(vm_exit_intr_info, 816);
 705         CHECK_OFFSET(vm_exit_intr_error_code, 820);
 706         CHECK_OFFSET(idt_vectoring_info_field, 824);
 707         CHECK_OFFSET(idt_vectoring_error_code, 828);
 708         CHECK_OFFSET(vm_exit_instruction_len, 832);
 709         CHECK_OFFSET(vmx_instruction_info, 836);
 710         CHECK_OFFSET(guest_es_limit, 840);
 711         CHECK_OFFSET(guest_cs_limit, 844);
 712         CHECK_OFFSET(guest_ss_limit, 848);
 713         CHECK_OFFSET(guest_ds_limit, 852);
 714         CHECK_OFFSET(guest_fs_limit, 856);
 715         CHECK_OFFSET(guest_gs_limit, 860);
 716         CHECK_OFFSET(guest_ldtr_limit, 864);
 717         CHECK_OFFSET(guest_tr_limit, 868);
 718         CHECK_OFFSET(guest_gdtr_limit, 872);
 719         CHECK_OFFSET(guest_idtr_limit, 876);
 720         CHECK_OFFSET(guest_es_ar_bytes, 880);
 721         CHECK_OFFSET(guest_cs_ar_bytes, 884);
 722         CHECK_OFFSET(guest_ss_ar_bytes, 888);
 723         CHECK_OFFSET(guest_ds_ar_bytes, 892);
 724         CHECK_OFFSET(guest_fs_ar_bytes, 896);
 725         CHECK_OFFSET(guest_gs_ar_bytes, 900);
 726         CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
 727         CHECK_OFFSET(guest_tr_ar_bytes, 908);
 728         CHECK_OFFSET(guest_interruptibility_info, 912);
 729         CHECK_OFFSET(guest_activity_state, 916);
 730         CHECK_OFFSET(guest_sysenter_cs, 920);
 731         CHECK_OFFSET(host_ia32_sysenter_cs, 924);
 732         CHECK_OFFSET(vmx_preemption_timer_value, 928);
 733         CHECK_OFFSET(virtual_processor_id, 960);
 734         CHECK_OFFSET(posted_intr_nv, 962);
 735         CHECK_OFFSET(guest_es_selector, 964);
 736         CHECK_OFFSET(guest_cs_selector, 966);
 737         CHECK_OFFSET(guest_ss_selector, 968);
 738         CHECK_OFFSET(guest_ds_selector, 970);
 739         CHECK_OFFSET(guest_fs_selector, 972);
 740         CHECK_OFFSET(guest_gs_selector, 974);
 741         CHECK_OFFSET(guest_ldtr_selector, 976);
 742         CHECK_OFFSET(guest_tr_selector, 978);
 743         CHECK_OFFSET(guest_intr_status, 980);
 744         CHECK_OFFSET(host_es_selector, 982);
 745         CHECK_OFFSET(host_cs_selector, 984);
 746         CHECK_OFFSET(host_ss_selector, 986);
 747         CHECK_OFFSET(host_ds_selector, 988);
 748         CHECK_OFFSET(host_fs_selector, 990);
 749         CHECK_OFFSET(host_gs_selector, 992);
 750         CHECK_OFFSET(host_tr_selector, 994);
 751         CHECK_OFFSET(guest_pml_index, 996);
 752 }
 753
 754 /*
 755  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 756  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 757  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 758  *
 759  * IMPORTANT: Changing this value will break save/restore compatibility with
 760  * older kvm releases.
 761  */
 762 #define VMCS12_REVISION 0x11e57ed0
 763
 764 /*
 765  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 766  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 767  * current implementation, 4K are reserved to avoid future complications.
 768  */
 769 #define VMCS12_SIZE 0x1000
 770
 771 /*
 772  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 773  * supported VMCS12 field encoding.
 774  */
 775 #define VMCS12_MAX_FIELD_INDEX 0x17
 776
 777 struct nested_vmx_msrs {
 778         /*
 779          * We only store the "true" versions of the VMX capability MSRs. We
 780          * generate the "non-true" versions by setting the must-be-1 bits
 781          * according to the SDM.
 782          */
 783         u32 procbased_ctls_low;
 784         u32 procbased_ctls_high;
 785         u32 secondary_ctls_low;
 786         u32 secondary_ctls_high;
 787         u32 pinbased_ctls_low;
 788         u32 pinbased_ctls_high;
 789         u32 exit_ctls_low;
 790         u32 exit_ctls_high;
 791         u32 entry_ctls_low;
 792         u32 entry_ctls_high;
 793         u32 misc_low;
 794         u32 misc_high;
 795         u32 ept_caps;
 796         u32 vpid_caps;
 797         u64 basic;
 798         u64 cr0_fixed0;
 799         u64 cr0_fixed1;
 800         u64 cr4_fixed0;
 801         u64 cr4_fixed1;
 802         u64 vmcs_enum;
 803         u64 vmfunc_controls;
 804 };
 805
 806 /*
 807  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 808  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 809  */
 810 struct nested_vmx {
 811         /* Has the level1 guest done vmxon? */
 812         bool vmxon;
 813         gpa_t vmxon_ptr;
 814         bool pml_full;
 815
 816         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 817         gpa_t current_vmptr;
 818         /*
 819          * Cache of the guest's VMCS, existing outside of guest memory.
 820          * Loaded from guest memory during VMPTRLD. Flushed to guest
 821          * memory during VMCLEAR and VMPTRLD.
 822          */
 823         struct vmcs12 *cached_vmcs12;
 824         /*
 825          * Cache of the guest's shadow VMCS, existing outside of guest
 826          * memory. Loaded from guest memory during VM entry. Flushed
 827          * to guest memory during VM exit.
 828          */
 829         struct vmcs12 *cached_shadow_vmcs12;
 830         /*
 831          * Indicates if the shadow vmcs must be updated with the
 832          * data hold by vmcs12
 833          */
 834         bool sync_shadow_vmcs;
 835         bool dirty_vmcs12;
 836
 837         bool change_vmcs01_virtual_apic_mode;
 838
 839         /* L2 must run next, and mustn't decide to exit to L1. */
 840         bool nested_run_pending;
 841
 842         struct loaded_vmcs vmcs02;
 843
 844         /*
 845          * Guest pages referred to in the vmcs02 with host-physical
 846          * pointers, so we must keep them pinned while L2 runs.
 847          */
 848         struct page *apic_access_page;
 849         struct page *virtual_apic_page;
 850         struct page *pi_desc_page;
 851         struct pi_desc *pi_desc;
 852         bool pi_pending;
 853         u16 posted_intr_nv;
 854
 855         struct hrtimer preemption_timer;
 856         bool preemption_timer_expired;
 857
 858         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 859         u64 vmcs01_debugctl;
 860
 861         u16 vpid02;
 862         u16 last_vpid;
 863
 864         struct nested_vmx_msrs msrs;
 865
 866         /* SMM related state */
 867         struct {
 868                 /* in VMX operation on SMM entry? */
 869                 bool vmxon;
 870                 /* in guest mode on SMM entry? */
 871                 bool guest_mode;
 872         } smm;
 873 };
 874
 875 #define POSTED_INTR_ON  0
 876 #define POSTED_INTR_SN  1
 877
 878 /* Posted-Interrupt Descriptor */
 879 struct pi_desc {
 880         u32 pir[8];     /* Posted interrupt requested */
 881         union {
 882                 struct {
 883                                 /* bit 256 - Outstanding Notification */
 884                         u16     on      : 1,
 885                                 /* bit 257 - Suppress Notification */
 886                                 sn      : 1,
 887                                 /* bit 271:258 - Reserved */
 888                                 rsvd_1  : 14;
 889                                 /* bit 279:272 - Notification Vector */
 890                         u8      nv;
 891                                 /* bit 287:280 - Reserved */
 892                         u8      rsvd_2;
 893                                 /* bit 319:288 - Notification Destination */
 894                         u32     ndst;
 895                 };
 896                 u64 control;
 897         };
 898         u32 rsvd[6];
 899 } __aligned(64);
 900
 901 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 902 {
 903         return test_and_set_bit(POSTED_INTR_ON,
 904                         (unsigned long *)&pi_desc->control);
 905 }
 906
 907 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 908 {
 909         return test_and_clear_bit(POSTED_INTR_ON,
 910                         (unsigned long *)&pi_desc->control);
 911 }
 912
 913 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 914 {
 915         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 916 }
 917
 918 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 919 {
 920         return clear_bit(POSTED_INTR_SN,
 921                         (unsigned long *)&pi_desc->control);
 922 }
 923
 924 static inline void pi_set_sn(struct pi_desc *pi_desc)
 925 {
 926         return set_bit(POSTED_INTR_SN,
 927                         (unsigned long *)&pi_desc->control);
 928 }
 929
 930 static inline void pi_clear_on(struct pi_desc *pi_desc)
 931 {
 932         clear_bit(POSTED_INTR_ON,
 933                   (unsigned long *)&pi_desc->control);
 934 }
 935
 936 static inline int pi_test_on(struct pi_desc *pi_desc)
 937 {
 938         return test_bit(POSTED_INTR_ON,
 939                         (unsigned long *)&pi_desc->control);
 940 }
 941
 942 static inline int pi_test_sn(struct pi_desc *pi_desc)
 943 {
 944         return test_bit(POSTED_INTR_SN,
 945                         (unsigned long *)&pi_desc->control);
 946 }
 947
 948 struct vmx_msrs {
 949         unsigned int            nr;
 950         struct vmx_msr_entry    val[NR_AUTOLOAD_MSRS];
 951 };
 952
 953 struct vcpu_vmx {
 954         struct kvm_vcpu       vcpu;
 955         unsigned long         host_rsp;
 956         u8                    fail;
 957         u8                    msr_bitmap_mode;
 958         u32                   exit_intr_info;
 959         u32                   idt_vectoring_info;
 960         ulong                 rflags;
 961         struct shared_msr_entry *guest_msrs;
 962         int                   nmsrs;
 963         int                   save_nmsrs;
 964         unsigned long         host_idt_base;
 965 #ifdef CONFIG_X86_64
 966         u64                   msr_host_kernel_gs_base;
 967         u64                   msr_guest_kernel_gs_base;
 968 #endif
 969
 970         u64                   arch_capabilities;
 971         u64                   spec_ctrl;
 972
 973         u32 vm_entry_controls_shadow;
 974         u32 vm_exit_controls_shadow;
 975         u32 secondary_exec_control;
 976
 977         /*
 978          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 979          * non-nested (L1) guest, it always points to vmcs01. For a nested
 980          * guest (L2), it points to a different VMCS.  loaded_cpu_state points
 981          * to the VMCS whose state is loaded into the CPU registers that only
 982          * need to be switched when transitioning to/from the kernel; a NULL
 983          * value indicates that host state is loaded.
 984          */
 985         struct loaded_vmcs    vmcs01;
 986         struct loaded_vmcs   *loaded_vmcs;
 987         struct loaded_vmcs   *loaded_cpu_state;
 988         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 989         struct msr_autoload {
 990                 struct vmx_msrs guest;
 991                 struct vmx_msrs host;
 992         } msr_autoload;
 993
 994         struct {
 995                 int vm86_active;
 996                 ulong save_rflags;
 997                 struct kvm_segment segs[8];
 998         } rmode;
 999         struct {
1000                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
1001                 struct kvm_save_segment {
1002                         u16 selector;
1003                         unsigned long base;
1004                         u32 limit;
1005                         u32 ar;
1006                 } seg[8];
1007         } segment_cache;
1008         int vpid;
1009         bool emulation_required;
1010
1011         u32 exit_reason;
1012
1013         /* Posted interrupt descriptor */
1014         struct pi_desc pi_desc;
1015
1016         /* Support for a guest hypervisor (nested VMX) */
1017         struct nested_vmx nested;
1018
1019         /* Dynamic PLE window. */
1020         int ple_window;
1021         bool ple_window_dirty;
1022
1023         bool req_immediate_exit;
1024
1025         /* Support for PML */
1026 #define PML_ENTITY_NUM          512
1027         struct page *pml_pg;
1028
1029         /* apic deadline value in host tsc */
1030         u64 hv_deadline_tsc;
1031
1032         u64 current_tsc_ratio;
1033
1034         u32 host_pkru;
1035
1036         unsigned long host_debugctlmsr;
1037
1038         /*
1039          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
1040          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
1041          * in msr_ia32_feature_control_valid_bits.
1042          */
1043         u64 msr_ia32_feature_control;
1044         u64 msr_ia32_feature_control_valid_bits;
1045         u64 ept_pointer;
1046 };
1047
1048 enum segment_cache_field {
1049         SEG_FIELD_SEL = 0,
1050         SEG_FIELD_BASE = 1,
1051         SEG_FIELD_LIMIT = 2,
1052         SEG_FIELD_AR = 3,
1053
1054         SEG_FIELD_NR = 4
1055 };
1056
1057 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
1058 {
1059         return container_of(kvm, struct kvm_vmx, kvm);
1060 }
1061
1062 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
1063 {
1064         return container_of(vcpu, struct vcpu_vmx, vcpu);
1065 }
1066
1067 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
1068 {
1069         return &(to_vmx(vcpu)->pi_desc);
1070 }
1071
1072 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
1073 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
1074 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
1075 #define FIELD64(number, name)                                           \
1076         FIELD(number, name),                                            \
1077         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
1078
1079
1080 static u16 shadow_read_only_fields[] = {
1081 #define SHADOW_FIELD_RO(x) x,
1082 #include "vmx_shadow_fields.h"
1083 };
1084 static int max_shadow_read_only_fields =
1085         ARRAY_SIZE(shadow_read_only_fields);
1086
1087 static u16 shadow_read_write_fields[] = {
1088 #define SHADOW_FIELD_RW(x) x,
1089 #include "vmx_shadow_fields.h"
1090 };
1091 static int max_shadow_read_write_fields =
1092         ARRAY_SIZE(shadow_read_write_fields);
1093
1094 static const unsigned short vmcs_field_to_offset_table[] = {
1095         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
1096         FIELD(POSTED_INTR_NV, posted_intr_nv),
1097         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
1098         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
1099         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
1100         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
1101         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
1102         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
1103         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
1104         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
1105         FIELD(GUEST_INTR_STATUS, guest_intr_status),
1106         FIELD(GUEST_PML_INDEX, guest_pml_index),
1107         FIELD(HOST_ES_SELECTOR, host_es_selector),
1108         FIELD(HOST_CS_SELECTOR, host_cs_selector),
1109         FIELD(HOST_SS_SELECTOR, host_ss_selector),
1110         FIELD(HOST_DS_SELECTOR, host_ds_selector),
1111         FIELD(HOST_FS_SELECTOR, host_fs_selector),
1112         FIELD(HOST_GS_SELECTOR, host_gs_selector),
1113         FIELD(HOST_TR_SELECTOR, host_tr_selector),
1114         FIELD64(IO_BITMAP_A, io_bitmap_a),
1115         FIELD64(IO_BITMAP_B, io_bitmap_b),
1116         FIELD64(MSR_BITMAP, msr_bitmap),
1117         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
1118         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
1119         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
1120         FIELD64(PML_ADDRESS, pml_address),
1121         FIELD64(TSC_OFFSET, tsc_offset),
1122         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
1123         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
1124         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
1125         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
1126         FIELD64(EPT_POINTER, ept_pointer),
1127         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
1128         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
1129         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
1130         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
1131         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
1132         FIELD64(VMREAD_BITMAP, vmread_bitmap),
1133         FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
1134         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
1135         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
1136         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
1137         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
1138         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
1139         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
1140         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
1141         FIELD64(GUEST_PDPTR0, guest_pdptr0),
1142         FIELD64(GUEST_PDPTR1, guest_pdptr1),
1143         FIELD64(GUEST_PDPTR2, guest_pdptr2),
1144         FIELD64(GUEST_PDPTR3, guest_pdptr3),
1145         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
1146         FIELD64(HOST_IA32_PAT, host_ia32_pat),
1147         FIELD64(HOST_IA32_EFER, host_ia32_efer),
1148         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
1149         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
1150         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
1151         FIELD(EXCEPTION_BITMAP, exception_bitmap),
1152         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
1153         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
1154         FIELD(CR3_TARGET_COUNT, cr3_target_count),
1155         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
1156         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
1157         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
1158         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
1159         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
1160         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
1161         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
1162         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
1163         FIELD(TPR_THRESHOLD, tpr_threshold),
1164         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
1165         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
1166         FIELD(VM_EXIT_REASON, vm_exit_reason),
1167         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
1168         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
1169         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
1170         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
1171         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
1172         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
1173         FIELD(GUEST_ES_LIMIT, guest_es_limit),
1174         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
1175         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
1176         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
1177         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
1178         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
1179         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
1180         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
1181         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
1182         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
1183         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
1184         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
1185         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
1186         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
1187         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
1188         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
1189         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1190         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1191         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1192         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1193         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1194         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1195         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1196         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1197         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1198         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1199         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1200         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1201         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1202         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1203         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1204         FIELD(EXIT_QUALIFICATION, exit_qualification),
1205         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1206         FIELD(GUEST_CR0, guest_cr0),
1207         FIELD(GUEST_CR3, guest_cr3),
1208         FIELD(GUEST_CR4, guest_cr4),
1209         FIELD(GUEST_ES_BASE, guest_es_base),
1210         FIELD(GUEST_CS_BASE, guest_cs_base),
1211         FIELD(GUEST_SS_BASE, guest_ss_base),
1212         FIELD(GUEST_DS_BASE, guest_ds_base),
1213         FIELD(GUEST_FS_BASE, guest_fs_base),
1214         FIELD(GUEST_GS_BASE, guest_gs_base),
1215         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1216         FIELD(GUEST_TR_BASE, guest_tr_base),
1217         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1218         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1219         FIELD(GUEST_DR7, guest_dr7),
1220         FIELD(GUEST_RSP, guest_rsp),
1221         FIELD(GUEST_RIP, guest_rip),
1222         FIELD(GUEST_RFLAGS, guest_rflags),
1223         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1224         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1225         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1226         FIELD(HOST_CR0, host_cr0),
1227         FIELD(HOST_CR3, host_cr3),
1228         FIELD(HOST_CR4, host_cr4),
1229         FIELD(HOST_FS_BASE, host_fs_base),
1230         FIELD(HOST_GS_BASE, host_gs_base),
1231         FIELD(HOST_TR_BASE, host_tr_base),
1232         FIELD(HOST_GDTR_BASE, host_gdtr_base),
1233         FIELD(HOST_IDTR_BASE, host_idtr_base),
1234         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1235         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1236         FIELD(HOST_RSP, host_rsp),
1237         FIELD(HOST_RIP, host_rip),
1238 };
1239
1240 static inline short vmcs_field_to_offset(unsigned long field)
1241 {
1242         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1243         unsigned short offset;
1244         unsigned index;
1245
1246         if (field >> 15)
1247                 return -ENOENT;
1248
1249         index = ROL16(field, 6);
1250         if (index >= size)
1251                 return -ENOENT;
1252
1253         index = array_index_nospec(index, size);
1254         offset = vmcs_field_to_offset_table[index];
1255         if (offset == 0)
1256                 return -ENOENT;
1257         return offset;
1258 }
1259
1260 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1261 {
1262         return to_vmx(vcpu)->nested.cached_vmcs12;
1263 }
1264
1265 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
1266 {
1267         return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
1268 }
1269
1270 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1271 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1272 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1273 static bool vmx_xsaves_supported(void);
1274 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1275                             struct kvm_segment *var, int seg);
1276 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1277                             struct kvm_segment *var, int seg);
1278 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1279 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1280 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1281 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1282 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1283 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1284                                             u16 error_code);
1285 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1286 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1287                                                           u32 msr, int type);
1288
1289 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1290 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1291 /*
1292  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1293  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1294  */
1295 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1296
1297 /*
1298  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1299  * can find which vCPU should be waken up.
1300  */
1301 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1302 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1303
1304 enum {
1305         VMX_VMREAD_BITMAP,
1306         VMX_VMWRITE_BITMAP,
1307         VMX_BITMAP_NR
1308 };
1309
1310 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1311
1312 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
1313 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
1314
1315 static bool cpu_has_load_ia32_efer;
1316 static bool cpu_has_load_perf_global_ctrl;
1317
1318 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1319 static DEFINE_SPINLOCK(vmx_vpid_lock);
1320
1321 static struct vmcs_config {
1322         int size;
1323         int order;
1324         u32 basic_cap;
1325         u32 revision_id;
1326         u32 pin_based_exec_ctrl;
1327         u32 cpu_based_exec_ctrl;
1328         u32 cpu_based_2nd_exec_ctrl;
1329         u32 vmexit_ctrl;
1330         u32 vmentry_ctrl;
1331         struct nested_vmx_msrs nested;
1332 } vmcs_config;
1333
1334 static struct vmx_capability {
1335         u32 ept;
1336         u32 vpid;
1337 } vmx_capability;
1338
1339 #define VMX_SEGMENT_FIELD(seg)                                  \
1340         [VCPU_SREG_##seg] = {                                   \
1341                 .selector = GUEST_##seg##_SELECTOR,             \
1342                 .base = GUEST_##seg##_BASE,                     \
1343                 .limit = GUEST_##seg##_LIMIT,                   \
1344                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1345         }
1346
1347 static const struct kvm_vmx_segment_field {
1348         unsigned selector;
1349         unsigned base;
1350         unsigned limit;
1351         unsigned ar_bytes;
1352 } kvm_vmx_segment_fields[] = {
1353         VMX_SEGMENT_FIELD(CS),
1354         VMX_SEGMENT_FIELD(DS),
1355         VMX_SEGMENT_FIELD(ES),
1356         VMX_SEGMENT_FIELD(FS),
1357         VMX_SEGMENT_FIELD(GS),
1358         VMX_SEGMENT_FIELD(SS),
1359         VMX_SEGMENT_FIELD(TR),
1360         VMX_SEGMENT_FIELD(LDTR),
1361 };
1362
1363 static u64 host_efer;
1364
1365 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1366
1367 /*
1368  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1369  * away by decrementing the array size.
1370  */
1371 static const u32 vmx_msr_index[] = {
1372 #ifdef CONFIG_X86_64
1373         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1374 #endif
1375         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1376 };
1377
1378 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1379
1380 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1381
1382 #define KVM_EVMCS_VERSION 1
1383
1384 #if IS_ENABLED(CONFIG_HYPERV)
1385 static bool __read_mostly enlightened_vmcs = true;
1386 module_param(enlightened_vmcs, bool, 0444);
1387
1388 static inline void evmcs_write64(unsigned long field, u64 value)
1389 {
1390         u16 clean_field;
1391         int offset = get_evmcs_offset(field, &clean_field);
1392
1393         if (offset < 0)
1394                 return;
1395
1396         *(u64 *)((char *)current_evmcs + offset) = value;
1397
1398         current_evmcs->hv_clean_fields &= ~clean_field;
1399 }
1400
1401 static inline void evmcs_write32(unsigned long field, u32 value)
1402 {
1403         u16 clean_field;
1404         int offset = get_evmcs_offset(field, &clean_field);
1405
1406         if (offset < 0)
1407                 return;
1408
1409         *(u32 *)((char *)current_evmcs + offset) = value;
1410         current_evmcs->hv_clean_fields &= ~clean_field;
1411 }
1412
1413 static inline void evmcs_write16(unsigned long field, u16 value)
1414 {
1415         u16 clean_field;
1416         int offset = get_evmcs_offset(field, &clean_field);
1417
1418         if (offset < 0)
1419                 return;
1420
1421         *(u16 *)((char *)current_evmcs + offset) = value;
1422         current_evmcs->hv_clean_fields &= ~clean_field;
1423 }
1424
1425 static inline u64 evmcs_read64(unsigned long field)
1426 {
1427         int offset = get_evmcs_offset(field, NULL);
1428
1429         if (offset < 0)
1430                 return 0;
1431
1432         return *(u64 *)((char *)current_evmcs + offset);
1433 }
1434
1435 static inline u32 evmcs_read32(unsigned long field)
1436 {
1437         int offset = get_evmcs_offset(field, NULL);
1438
1439         if (offset < 0)
1440                 return 0;
1441
1442         return *(u32 *)((char *)current_evmcs + offset);
1443 }
1444
1445 static inline u16 evmcs_read16(unsigned long field)
1446 {
1447         int offset = get_evmcs_offset(field, NULL);
1448
1449         if (offset < 0)
1450                 return 0;
1451
1452         return *(u16 *)((char *)current_evmcs + offset);
1453 }
1454
1455 static inline void evmcs_touch_msr_bitmap(void)
1456 {
1457         if (unlikely(!current_evmcs))
1458                 return;
1459
1460         if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1461                 current_evmcs->hv_clean_fields &=
1462                         ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1463 }
1464
1465 static void evmcs_load(u64 phys_addr)
1466 {
1467         struct hv_vp_assist_page *vp_ap =
1468                 hv_get_vp_assist_page(smp_processor_id());
1469
1470         vp_ap->current_nested_vmcs = phys_addr;
1471         vp_ap->enlighten_vmentry = 1;
1472 }
1473
1474 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1475 {
1476         /*
1477          * Enlightened VMCSv1 doesn't support these:
1478          *
1479          *      POSTED_INTR_NV                  = 0x00000002,
1480          *      GUEST_INTR_STATUS               = 0x00000810,
1481          *      APIC_ACCESS_ADDR                = 0x00002014,
1482          *      POSTED_INTR_DESC_ADDR           = 0x00002016,
1483          *      EOI_EXIT_BITMAP0                = 0x0000201c,
1484          *      EOI_EXIT_BITMAP1                = 0x0000201e,
1485          *      EOI_EXIT_BITMAP2                = 0x00002020,
1486          *      EOI_EXIT_BITMAP3                = 0x00002022,
1487          */
1488         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1489         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1490                 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1491         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1492                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1493         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1494                 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1495
1496         /*
1497          *      GUEST_PML_INDEX                 = 0x00000812,
1498          *      PML_ADDRESS                     = 0x0000200e,
1499          */
1500         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1501
1502         /*      VM_FUNCTION_CONTROL             = 0x00002018, */
1503         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1504
1505         /*
1506          *      EPTP_LIST_ADDRESS               = 0x00002024,
1507          *      VMREAD_BITMAP                   = 0x00002026,
1508          *      VMWRITE_BITMAP                  = 0x00002028,
1509          */
1510         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1511
1512         /*
1513          *      TSC_MULTIPLIER                  = 0x00002032,
1514          */
1515         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1516
1517         /*
1518          *      PLE_GAP                         = 0x00004020,
1519          *      PLE_WINDOW                      = 0x00004022,
1520          */
1521         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1522
1523         /*
1524          *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
1525          */
1526         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1527
1528         /*
1529          *      GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
1530          *      HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
1531          */
1532         vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1533         vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1534
1535         /*
1536          * Currently unsupported in KVM:
1537          *      GUEST_IA32_RTIT_CTL             = 0x00002814,
1538          */
1539 }
1540
1541 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
1542 static void check_ept_pointer_match(struct kvm *kvm)
1543 {
1544         struct kvm_vcpu *vcpu;
1545         u64 tmp_eptp = INVALID_PAGE;
1546         int i;
1547
1548         kvm_for_each_vcpu(i, vcpu, kvm) {
1549                 if (!VALID_PAGE(tmp_eptp)) {
1550                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
1551                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
1552                         to_kvm_vmx(kvm)->ept_pointers_match
1553                                 = EPT_POINTERS_MISMATCH;
1554                         return;
1555                 }
1556         }
1557
1558         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
1559 }
1560
1561 static int vmx_hv_remote_flush_tlb(struct kvm *kvm)
1562 {
1563         int ret;
1564
1565         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1566
1567         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
1568                 check_ept_pointer_match(kvm);
1569
1570         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
1571                 ret = -ENOTSUPP;
1572                 goto out;
1573         }
1574
1575         ret = hyperv_flush_guest_mapping(
1576                         to_vmx(kvm_get_vcpu(kvm, 0))->ept_pointer);
1577
1578 out:
1579         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1580         return ret;
1581 }
1582 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1583 static inline void evmcs_write64(unsigned long field, u64 value) {}
1584 static inline void evmcs_write32(unsigned long field, u32 value) {}
1585 static inline void evmcs_write16(unsigned long field, u16 value) {}
1586 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1587 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1588 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1589 static inline void evmcs_load(u64 phys_addr) {}
1590 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1591 static inline void evmcs_touch_msr_bitmap(void) {}
1592 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1593
1594 static inline bool is_exception_n(u32 intr_info, u8 vector)
1595 {
1596         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1597                              INTR_INFO_VALID_MASK)) ==
1598                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1599 }
1600
1601 static inline bool is_debug(u32 intr_info)
1602 {
1603         return is_exception_n(intr_info, DB_VECTOR);
1604 }
1605
1606 static inline bool is_breakpoint(u32 intr_info)
1607 {
1608         return is_exception_n(intr_info, BP_VECTOR);
1609 }
1610
1611 static inline bool is_page_fault(u32 intr_info)
1612 {
1613         return is_exception_n(intr_info, PF_VECTOR);
1614 }
1615
1616 static inline bool is_no_device(u32 intr_info)
1617 {
1618         return is_exception_n(intr_info, NM_VECTOR);
1619 }
1620
1621 static inline bool is_invalid_opcode(u32 intr_info)
1622 {
1623         return is_exception_n(intr_info, UD_VECTOR);
1624 }
1625
1626 static inline bool is_gp_fault(u32 intr_info)
1627 {
1628         return is_exception_n(intr_info, GP_VECTOR);
1629 }
1630
1631 static inline bool is_external_interrupt(u32 intr_info)
1632 {
1633         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1634                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1635 }
1636
1637 static inline bool is_machine_check(u32 intr_info)
1638 {
1639         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1640                              INTR_INFO_VALID_MASK)) ==
1641                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1642 }
1643
1644 /* Undocumented: icebp/int1 */
1645 static inline bool is_icebp(u32 intr_info)
1646 {
1647         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1648                 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1649 }
1650
1651 static inline bool cpu_has_vmx_msr_bitmap(void)
1652 {
1653         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1654 }
1655
1656 static inline bool cpu_has_vmx_tpr_shadow(void)
1657 {
1658         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1659 }
1660
1661 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1662 {
1663         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1664 }
1665
1666 static inline bool cpu_has_secondary_exec_ctrls(void)
1667 {
1668         return vmcs_config.cpu_based_exec_ctrl &
1669                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1670 }
1671
1672 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1673 {
1674         return vmcs_config.cpu_based_2nd_exec_ctrl &
1675                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1676 }
1677
1678 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1679 {
1680         return vmcs_config.cpu_based_2nd_exec_ctrl &
1681                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1682 }
1683
1684 static inline bool cpu_has_vmx_apic_register_virt(void)
1685 {
1686         return vmcs_config.cpu_based_2nd_exec_ctrl &
1687                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1688 }
1689
1690 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1691 {
1692         return vmcs_config.cpu_based_2nd_exec_ctrl &
1693                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1694 }
1695
1696 static inline bool cpu_has_vmx_encls_vmexit(void)
1697 {
1698         return vmcs_config.cpu_based_2nd_exec_ctrl &
1699                 SECONDARY_EXEC_ENCLS_EXITING;
1700 }
1701
1702 /*
1703  * Comment's format: document - errata name - stepping - processor name.
1704  * Refer from
1705  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1706  */
1707 static u32 vmx_preemption_cpu_tfms[] = {
1708 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1709 0x000206E6,
1710 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1711 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1712 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1713 0x00020652,
1714 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1715 0x00020655,
1716 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1717 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1718 /*
1719  * 320767.pdf - AAP86  - B1 -
1720  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1721  */
1722 0x000106E5,
1723 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1724 0x000106A0,
1725 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1726 0x000106A1,
1727 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1728 0x000106A4,
1729  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1730  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1731  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1732 0x000106A5,
1733 };
1734
1735 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1736 {
1737         u32 eax = cpuid_eax(0x00000001), i;
1738
1739         /* Clear the reserved bits */
1740         eax &= ~(0x3U << 14 | 0xfU << 28);
1741         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1742                 if (eax == vmx_preemption_cpu_tfms[i])
1743                         return true;
1744
1745         return false;
1746 }
1747
1748 static inline bool cpu_has_vmx_preemption_timer(void)
1749 {
1750         return vmcs_config.pin_based_exec_ctrl &
1751                 PIN_BASED_VMX_PREEMPTION_TIMER;
1752 }
1753
1754 static inline bool cpu_has_vmx_posted_intr(void)
1755 {
1756         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1757                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1758 }
1759
1760 static inline bool cpu_has_vmx_apicv(void)
1761 {
1762         return cpu_has_vmx_apic_register_virt() &&
1763                 cpu_has_vmx_virtual_intr_delivery() &&
1764                 cpu_has_vmx_posted_intr();
1765 }
1766
1767 static inline bool cpu_has_vmx_flexpriority(void)
1768 {
1769         return cpu_has_vmx_tpr_shadow() &&
1770                 cpu_has_vmx_virtualize_apic_accesses();
1771 }
1772
1773 static inline bool cpu_has_vmx_ept_execute_only(void)
1774 {
1775         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1776 }
1777
1778 static inline bool cpu_has_vmx_ept_2m_page(void)
1779 {
1780         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1781 }
1782
1783 static inline bool cpu_has_vmx_ept_1g_page(void)
1784 {
1785         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1786 }
1787
1788 static inline bool cpu_has_vmx_ept_4levels(void)
1789 {
1790         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1791 }
1792
1793 static inline bool cpu_has_vmx_ept_mt_wb(void)
1794 {
1795         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1796 }
1797
1798 static inline bool cpu_has_vmx_ept_5levels(void)
1799 {
1800         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1801 }
1802
1803 static inline bool cpu_has_vmx_ept_ad_bits(void)
1804 {
1805         return vmx_capability.ept & VMX_EPT_AD_BIT;
1806 }
1807
1808 static inline bool cpu_has_vmx_invept_context(void)
1809 {
1810         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1811 }
1812
1813 static inline bool cpu_has_vmx_invept_global(void)
1814 {
1815         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1816 }
1817
1818 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1819 {
1820         return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1821 }
1822
1823 static inline bool cpu_has_vmx_invvpid_single(void)
1824 {
1825         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1826 }
1827
1828 static inline bool cpu_has_vmx_invvpid_global(void)
1829 {
1830         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1831 }
1832
1833 static inline bool cpu_has_vmx_invvpid(void)
1834 {
1835         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1836 }
1837
1838 static inline bool cpu_has_vmx_ept(void)
1839 {
1840         return vmcs_config.cpu_based_2nd_exec_ctrl &
1841                 SECONDARY_EXEC_ENABLE_EPT;
1842 }
1843
1844 static inline bool cpu_has_vmx_unrestricted_guest(void)
1845 {
1846         return vmcs_config.cpu_based_2nd_exec_ctrl &
1847                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1848 }
1849
1850 static inline bool cpu_has_vmx_ple(void)
1851 {
1852         return vmcs_config.cpu_based_2nd_exec_ctrl &
1853                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1854 }
1855
1856 static inline bool cpu_has_vmx_basic_inout(void)
1857 {
1858         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1859 }
1860
1861 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1862 {
1863         return flexpriority_enabled && lapic_in_kernel(vcpu);
1864 }
1865
1866 static inline bool cpu_has_vmx_vpid(void)
1867 {
1868         return vmcs_config.cpu_based_2nd_exec_ctrl &
1869                 SECONDARY_EXEC_ENABLE_VPID;
1870 }
1871
1872 static inline bool cpu_has_vmx_rdtscp(void)
1873 {
1874         return vmcs_config.cpu_based_2nd_exec_ctrl &
1875                 SECONDARY_EXEC_RDTSCP;
1876 }
1877
1878 static inline bool cpu_has_vmx_invpcid(void)
1879 {
1880         return vmcs_config.cpu_based_2nd_exec_ctrl &
1881                 SECONDARY_EXEC_ENABLE_INVPCID;
1882 }
1883
1884 static inline bool cpu_has_virtual_nmis(void)
1885 {
1886         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1887 }
1888
1889 static inline bool cpu_has_vmx_wbinvd_exit(void)
1890 {
1891         return vmcs_config.cpu_based_2nd_exec_ctrl &
1892                 SECONDARY_EXEC_WBINVD_EXITING;
1893 }
1894
1895 static inline bool cpu_has_vmx_shadow_vmcs(void)
1896 {
1897         u64 vmx_msr;
1898         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1899         /* check if the cpu supports writing r/o exit information fields */
1900         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1901                 return false;
1902
1903         return vmcs_config.cpu_based_2nd_exec_ctrl &
1904                 SECONDARY_EXEC_SHADOW_VMCS;
1905 }
1906
1907 static inline bool cpu_has_vmx_pml(void)
1908 {
1909         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1910 }
1911
1912 static inline bool cpu_has_vmx_tsc_scaling(void)
1913 {
1914         return vmcs_config.cpu_based_2nd_exec_ctrl &
1915                 SECONDARY_EXEC_TSC_SCALING;
1916 }
1917
1918 static inline bool cpu_has_vmx_vmfunc(void)
1919 {
1920         return vmcs_config.cpu_based_2nd_exec_ctrl &
1921                 SECONDARY_EXEC_ENABLE_VMFUNC;
1922 }
1923
1924 static bool vmx_umip_emulated(void)
1925 {
1926         return vmcs_config.cpu_based_2nd_exec_ctrl &
1927                 SECONDARY_EXEC_DESC;
1928 }
1929
1930 static inline bool report_flexpriority(void)
1931 {
1932         return flexpriority_enabled;
1933 }
1934
1935 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1936 {
1937         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1938 }
1939
1940 /*
1941  * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1942  * to modify any valid field of the VMCS, or are the VM-exit
1943  * information fields read-only?
1944  */
1945 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1946 {
1947         return to_vmx(vcpu)->nested.msrs.misc_low &
1948                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1949 }
1950
1951 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
1952 {
1953         return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
1954 }
1955
1956 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
1957 {
1958         return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
1959                         CPU_BASED_MONITOR_TRAP_FLAG;
1960 }
1961
1962 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
1963 {
1964         return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
1965                 SECONDARY_EXEC_SHADOW_VMCS;
1966 }
1967
1968 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1969 {
1970         return vmcs12->cpu_based_vm_exec_control & bit;
1971 }
1972
1973 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1974 {
1975         return (vmcs12->cpu_based_vm_exec_control &
1976                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1977                 (vmcs12->secondary_vm_exec_control & bit);
1978 }
1979
1980 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1981 {
1982         return vmcs12->pin_based_vm_exec_control &
1983                 PIN_BASED_VMX_PREEMPTION_TIMER;
1984 }
1985
1986 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1987 {
1988         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1989 }
1990
1991 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1992 {
1993         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1994 }
1995
1996 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1997 {
1998         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1999 }
2000
2001 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
2002 {
2003         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
2004 }
2005
2006 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
2007 {
2008         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
2009 }
2010
2011 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
2012 {
2013         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
2014 }
2015
2016 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
2017 {
2018         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
2019 }
2020
2021 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
2022 {
2023         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
2024 }
2025
2026 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
2027 {
2028         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2029 }
2030
2031 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
2032 {
2033         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
2034 }
2035
2036 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
2037 {
2038         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
2039 }
2040
2041 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
2042 {
2043         return nested_cpu_has_vmfunc(vmcs12) &&
2044                 (vmcs12->vm_function_control &
2045                  VMX_VMFUNC_EPTP_SWITCHING);
2046 }
2047
2048 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
2049 {
2050         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
2051 }
2052
2053 static inline bool is_nmi(u32 intr_info)
2054 {
2055         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
2056                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
2057 }
2058
2059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
2060                               u32 exit_intr_info,
2061                               unsigned long exit_qualification);
2062 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
2063                         struct vmcs12 *vmcs12,
2064                         u32 reason, unsigned long qualification);
2065
2066 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
2067 {
2068         int i;
2069
2070         for (i = 0; i < vmx->nmsrs; ++i)
2071                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
2072                         return i;
2073         return -1;
2074 }
2075
2076 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
2077 {
2078     struct {
2079         u64 vpid : 16;
2080         u64 rsvd : 48;
2081         u64 gva;
2082     } operand = { vpid, 0, gva };
2083     bool error;
2084
2085     asm volatile (__ex(ASM_VMX_INVVPID) CC_SET(na)
2086                   : CC_OUT(na) (error) : "a"(&operand), "c"(ext)
2087                   : "memory");
2088     BUG_ON(error);
2089 }
2090
2091 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
2092 {
2093         struct {
2094                 u64 eptp, gpa;
2095         } operand = {eptp, gpa};
2096         bool error;
2097
2098         asm volatile (__ex(ASM_VMX_INVEPT) CC_SET(na)
2099                       : CC_OUT(na) (error) : "a" (&operand), "c" (ext)
2100                       : "memory");
2101         BUG_ON(error);
2102 }
2103
2104 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
2105 {
2106         int i;
2107
2108         i = __find_msr_index(vmx, msr);
2109         if (i >= 0)
2110                 return &vmx->guest_msrs[i];
2111         return NULL;
2112 }
2113
2114 static void vmcs_clear(struct vmcs *vmcs)
2115 {
2116         u64 phys_addr = __pa(vmcs);
2117         bool error;
2118
2119         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) CC_SET(na)
2120                       : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2121                       : "memory");
2122         if (unlikely(error))
2123                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
2124                        vmcs, phys_addr);
2125 }
2126
2127 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
2128 {
2129         vmcs_clear(loaded_vmcs->vmcs);
2130         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
2131                 vmcs_clear(loaded_vmcs->shadow_vmcs);
2132         loaded_vmcs->cpu = -1;
2133         loaded_vmcs->launched = 0;
2134 }
2135
2136 static void vmcs_load(struct vmcs *vmcs)
2137 {
2138         u64 phys_addr = __pa(vmcs);
2139         bool error;
2140
2141         if (static_branch_unlikely(&enable_evmcs))
2142                 return evmcs_load(phys_addr);
2143
2144         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) CC_SET(na)
2145                       : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2146                       : "memory");
2147         if (unlikely(error))
2148                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
2149                        vmcs, phys_addr);
2150 }
2151
2152 #ifdef CONFIG_KEXEC_CORE
2153 /*
2154  * This bitmap is used to indicate whether the vmclear
2155  * operation is enabled on all cpus. All disabled by
2156  * default.
2157  */
2158 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
2159
2160 static inline void crash_enable_local_vmclear(int cpu)
2161 {
2162         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
2163 }
2164
2165 static inline void crash_disable_local_vmclear(int cpu)
2166 {
2167         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
2168 }
2169
2170 static inline int crash_local_vmclear_enabled(int cpu)
2171 {
2172         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
2173 }
2174
2175 static void crash_vmclear_local_loaded_vmcss(void)
2176 {
2177         int cpu = raw_smp_processor_id();
2178         struct loaded_vmcs *v;
2179
2180         if (!crash_local_vmclear_enabled(cpu))
2181                 return;
2182
2183         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
2184                             loaded_vmcss_on_cpu_link)
2185                 vmcs_clear(v->vmcs);
2186 }
2187 #else
2188 static inline void crash_enable_local_vmclear(int cpu) { }
2189 static inline void crash_disable_local_vmclear(int cpu) { }
2190 #endif /* CONFIG_KEXEC_CORE */
2191
2192 static void __loaded_vmcs_clear(void *arg)
2193 {
2194         struct loaded_vmcs *loaded_vmcs = arg;
2195         int cpu = raw_smp_processor_id();
2196
2197         if (loaded_vmcs->cpu != cpu)
2198                 return; /* vcpu migration can race with cpu offline */
2199         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
2200                 per_cpu(current_vmcs, cpu) = NULL;
2201         crash_disable_local_vmclear(cpu);
2202         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
2203
2204         /*
2205          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
2206          * is before setting loaded_vmcs->vcpu to -1 which is done in
2207          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
2208          * then adds the vmcs into percpu list before it is deleted.
2209          */
2210         smp_wmb();
2211
2212         loaded_vmcs_init(loaded_vmcs);
2213         crash_enable_local_vmclear(cpu);
2214 }
2215
2216 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
2217 {
2218         int cpu = loaded_vmcs->cpu;
2219
2220         if (cpu != -1)
2221                 smp_call_function_single(cpu,
2222                          __loaded_vmcs_clear, loaded_vmcs, 1);
2223 }
2224
2225 static inline bool vpid_sync_vcpu_addr(int vpid, gva_t addr)
2226 {
2227         if (vpid == 0)
2228                 return true;
2229
2230         if (cpu_has_vmx_invvpid_individual_addr()) {
2231                 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR, vpid, addr);
2232                 return true;
2233         }
2234
2235         return false;
2236 }
2237
2238 static inline void vpid_sync_vcpu_single(int vpid)
2239 {
2240         if (vpid == 0)
2241                 return;
2242
2243         if (cpu_has_vmx_invvpid_single())
2244                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2245 }
2246
2247 static inline void vpid_sync_vcpu_global(void)
2248 {
2249         if (cpu_has_vmx_invvpid_global())
2250                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
2251 }
2252
2253 static inline void vpid_sync_context(int vpid)
2254 {
2255         if (cpu_has_vmx_invvpid_single())
2256                 vpid_sync_vcpu_single(vpid);
2257         else
2258                 vpid_sync_vcpu_global();
2259 }
2260
2261 static inline void ept_sync_global(void)
2262 {
2263         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
2264 }
2265
2266 static inline void ept_sync_context(u64 eptp)
2267 {
2268         if (cpu_has_vmx_invept_context())
2269                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2270         else
2271                 ept_sync_global();
2272 }
2273
2274 static __always_inline void vmcs_check16(unsigned long field)
2275 {
2276         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2277                          "16-bit accessor invalid for 64-bit field");
2278         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2279                          "16-bit accessor invalid for 64-bit high field");
2280         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2281                          "16-bit accessor invalid for 32-bit high field");
2282         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2283                          "16-bit accessor invalid for natural width field");
2284 }
2285
2286 static __always_inline void vmcs_check32(unsigned long field)
2287 {
2288         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2289                          "32-bit accessor invalid for 16-bit field");
2290         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2291                          "32-bit accessor invalid for natural width field");
2292 }
2293
2294 static __always_inline void vmcs_check64(unsigned long field)
2295 {
2296         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2297                          "64-bit accessor invalid for 16-bit field");
2298         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2299                          "64-bit accessor invalid for 64-bit high field");
2300         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2301                          "64-bit accessor invalid for 32-bit field");
2302         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2303                          "64-bit accessor invalid for natural width field");
2304 }
2305
2306 static __always_inline void vmcs_checkl(unsigned long field)
2307 {
2308         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2309                          "Natural width accessor invalid for 16-bit field");
2310         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2311                          "Natural width accessor invalid for 64-bit field");
2312         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2313                          "Natural width accessor invalid for 64-bit high field");
2314         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2315                          "Natural width accessor invalid for 32-bit field");
2316 }
2317
2318 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2319 {
2320         unsigned long value;
2321
2322         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2323                       : "=a"(value) : "d"(field) : "cc");
2324         return value;
2325 }
2326
2327 static __always_inline u16 vmcs_read16(unsigned long field)
2328 {
2329         vmcs_check16(field);
2330         if (static_branch_unlikely(&enable_evmcs))
2331                 return evmcs_read16(field);
2332         return __vmcs_readl(field);
2333 }
2334
2335 static __always_inline u32 vmcs_read32(unsigned long field)
2336 {
2337         vmcs_check32(field);
2338         if (static_branch_unlikely(&enable_evmcs))
2339                 return evmcs_read32(field);
2340         return __vmcs_readl(field);
2341 }
2342
2343 static __always_inline u64 vmcs_read64(unsigned long field)
2344 {
2345         vmcs_check64(field);
2346         if (static_branch_unlikely(&enable_evmcs))
2347                 return evmcs_read64(field);
2348 #ifdef CONFIG_X86_64
2349         return __vmcs_readl(field);
2350 #else
2351         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2352 #endif
2353 }
2354
2355 static __always_inline unsigned long vmcs_readl(unsigned long field)
2356 {
2357         vmcs_checkl(field);
2358         if (static_branch_unlikely(&enable_evmcs))
2359                 return evmcs_read64(field);
2360         return __vmcs_readl(field);
2361 }
2362
2363 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2364 {
2365         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2366                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2367         dump_stack();
2368 }
2369
2370 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2371 {
2372         bool error;
2373
2374         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) CC_SET(na)
2375                       : CC_OUT(na) (error) : "a"(value), "d"(field));
2376         if (unlikely(error))
2377                 vmwrite_error(field, value);
2378 }
2379
2380 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2381 {
2382         vmcs_check16(field);
2383         if (static_branch_unlikely(&enable_evmcs))
2384                 return evmcs_write16(field, value);
2385
2386         __vmcs_writel(field, value);
2387 }
2388
2389 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2390 {
2391         vmcs_check32(field);
2392         if (static_branch_unlikely(&enable_evmcs))
2393                 return evmcs_write32(field, value);
2394
2395         __vmcs_writel(field, value);
2396 }
2397
2398 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2399 {
2400         vmcs_check64(field);
2401         if (static_branch_unlikely(&enable_evmcs))
2402                 return evmcs_write64(field, value);
2403
2404         __vmcs_writel(field, value);
2405 #ifndef CONFIG_X86_64
2406         asm volatile ("");
2407         __vmcs_writel(field+1, value >> 32);
2408 #endif
2409 }
2410
2411 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2412 {
2413         vmcs_checkl(field);
2414         if (static_branch_unlikely(&enable_evmcs))
2415                 return evmcs_write64(field, value);
2416
2417         __vmcs_writel(field, value);
2418 }
2419
2420 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2421 {
2422         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2423                          "vmcs_clear_bits does not support 64-bit fields");
2424         if (static_branch_unlikely(&enable_evmcs))
2425                 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2426
2427         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2428 }
2429
2430 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2431 {
2432         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2433                          "vmcs_set_bits does not support 64-bit fields");
2434         if (static_branch_unlikely(&enable_evmcs))
2435                 return evmcs_write32(field, evmcs_read32(field) | mask);
2436
2437         __vmcs_writel(field, __vmcs_readl(field) | mask);
2438 }
2439
2440 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2441 {
2442         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2443 }
2444
2445 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2446 {
2447         vmcs_write32(VM_ENTRY_CONTROLS, val);
2448         vmx->vm_entry_controls_shadow = val;
2449 }
2450
2451 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2452 {
2453         if (vmx->vm_entry_controls_shadow != val)
2454                 vm_entry_controls_init(vmx, val);
2455 }
2456
2457 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2458 {
2459         return vmx->vm_entry_controls_shadow;
2460 }
2461
2462
2463 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2464 {
2465         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2466 }
2467
2468 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2469 {
2470         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2471 }
2472
2473 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2474 {
2475         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2476 }
2477
2478 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2479 {
2480         vmcs_write32(VM_EXIT_CONTROLS, val);
2481         vmx->vm_exit_controls_shadow = val;
2482 }
2483
2484 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2485 {
2486         if (vmx->vm_exit_controls_shadow != val)
2487                 vm_exit_controls_init(vmx, val);
2488 }
2489
2490 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2491 {
2492         return vmx->vm_exit_controls_shadow;
2493 }
2494
2495
2496 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2497 {
2498         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2499 }
2500
2501 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2502 {
2503         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2504 }
2505
2506 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2507 {
2508         vmx->segment_cache.bitmask = 0;
2509 }
2510
2511 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2512                                        unsigned field)
2513 {
2514         bool ret;
2515         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2516
2517         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2518                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2519                 vmx->segment_cache.bitmask = 0;
2520         }
2521         ret = vmx->segment_cache.bitmask & mask;
2522         vmx->segment_cache.bitmask |= mask;
2523         return ret;
2524 }
2525
2526 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2527 {
2528         u16 *p = &vmx->segment_cache.seg[seg].selector;
2529
2530         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2531                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2532         return *p;
2533 }
2534
2535 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2536 {
2537         ulong *p = &vmx->segment_cache.seg[seg].base;
2538
2539         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2540                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2541         return *p;
2542 }
2543
2544 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2545 {
2546         u32 *p = &vmx->segment_cache.seg[seg].limit;
2547
2548         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2549                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2550         return *p;
2551 }
2552
2553 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2554 {
2555         u32 *p = &vmx->segment_cache.seg[seg].ar;
2556
2557         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2558                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2559         return *p;
2560 }
2561
2562 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2563 {
2564         u32 eb;
2565
2566         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2567              (1u << DB_VECTOR) | (1u << AC_VECTOR);
2568         /*
2569          * Guest access to VMware backdoor ports could legitimately
2570          * trigger #GP because of TSS I/O permission bitmap.
2571          * We intercept those #GP and allow access to them anyway
2572          * as VMware does.
2573          */
2574         if (enable_vmware_backdoor)
2575                 eb |= (1u << GP_VECTOR);
2576         if ((vcpu->guest_debug &
2577              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2578             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2579                 eb |= 1u << BP_VECTOR;
2580         if (to_vmx(vcpu)->rmode.vm86_active)
2581                 eb = ~0;
2582         if (enable_ept)
2583                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2584
2585         /* When we are running a nested L2 guest and L1 specified for it a
2586          * certain exception bitmap, we must trap the same exceptions and pass
2587          * them to L1. When running L2, we will only handle the exceptions
2588          * specified above if L1 did not want them.
2589          */
2590         if (is_guest_mode(vcpu))
2591                 eb |= get_vmcs12(vcpu)->exception_bitmap;
2592
2593         vmcs_write32(EXCEPTION_BITMAP, eb);
2594 }
2595
2596 /*
2597  * Check if MSR is intercepted for currently loaded MSR bitmap.
2598  */
2599 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2600 {
2601         unsigned long *msr_bitmap;
2602         int f = sizeof(unsigned long);
2603
2604         if (!cpu_has_vmx_msr_bitmap())
2605                 return true;
2606
2607         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2608
2609         if (msr <= 0x1fff) {
2610                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2611         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2612                 msr &= 0x1fff;
2613                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2614         }
2615
2616         return true;
2617 }
2618
2619 /*
2620  * Check if MSR is intercepted for L01 MSR bitmap.
2621  */
2622 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2623 {
2624         unsigned long *msr_bitmap;
2625         int f = sizeof(unsigned long);
2626
2627         if (!cpu_has_vmx_msr_bitmap())
2628                 return true;
2629
2630         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2631
2632         if (msr <= 0x1fff) {
2633                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2634         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2635                 msr &= 0x1fff;
2636                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2637         }
2638
2639         return true;
2640 }
2641
2642 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2643                 unsigned long entry, unsigned long exit)
2644 {
2645         vm_entry_controls_clearbit(vmx, entry);
2646         vm_exit_controls_clearbit(vmx, exit);
2647 }
2648
2649 static int find_msr(struct vmx_msrs *m, unsigned int msr)
2650 {
2651         unsigned int i;
2652
2653         for (i = 0; i < m->nr; ++i) {
2654                 if (m->val[i].index == msr)
2655                         return i;
2656         }
2657         return -ENOENT;
2658 }
2659
2660 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2661 {
2662         int i;
2663         struct msr_autoload *m = &vmx->msr_autoload;
2664
2665         switch (msr) {
2666         case MSR_EFER:
2667                 if (cpu_has_load_ia32_efer) {
2668                         clear_atomic_switch_msr_special(vmx,
2669                                         VM_ENTRY_LOAD_IA32_EFER,
2670                                         VM_EXIT_LOAD_IA32_EFER);
2671                         return;
2672                 }
2673                 break;
2674         case MSR_CORE_PERF_GLOBAL_CTRL:
2675                 if (cpu_has_load_perf_global_ctrl) {
2676                         clear_atomic_switch_msr_special(vmx,
2677                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2678                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2679                         return;
2680                 }
2681                 break;
2682         }
2683         i = find_msr(&m->guest, msr);
2684         if (i < 0)
2685                 goto skip_guest;
2686         --m->guest.nr;
2687         m->guest.val[i] = m->guest.val[m->guest.nr];
2688         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2689
2690 skip_guest:
2691         i = find_msr(&m->host, msr);
2692         if (i < 0)
2693                 return;
2694
2695         --m->host.nr;
2696         m->host.val[i] = m->host.val[m->host.nr];
2697         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2698 }
2699
2700 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2701                 unsigned long entry, unsigned long exit,
2702                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2703                 u64 guest_val, u64 host_val)
2704 {
2705         vmcs_write64(guest_val_vmcs, guest_val);
2706         vmcs_write64(host_val_vmcs, host_val);
2707         vm_entry_controls_setbit(vmx, entry);
2708         vm_exit_controls_setbit(vmx, exit);
2709 }
2710
2711 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2712                                   u64 guest_val, u64 host_val, bool entry_only)
2713 {
2714         int i, j = 0;
2715         struct msr_autoload *m = &vmx->msr_autoload;
2716
2717         switch (msr) {
2718         case MSR_EFER:
2719                 if (cpu_has_load_ia32_efer) {
2720                         add_atomic_switch_msr_special(vmx,
2721                                         VM_ENTRY_LOAD_IA32_EFER,
2722                                         VM_EXIT_LOAD_IA32_EFER,
2723                                         GUEST_IA32_EFER,
2724                                         HOST_IA32_EFER,
2725                                         guest_val, host_val);
2726                         return;
2727                 }
2728                 break;
2729         case MSR_CORE_PERF_GLOBAL_CTRL:
2730                 if (cpu_has_load_perf_global_ctrl) {
2731                         add_atomic_switch_msr_special(vmx,
2732                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2733                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2734                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2735                                         HOST_IA32_PERF_GLOBAL_CTRL,
2736                                         guest_val, host_val);
2737                         return;
2738                 }
2739                 break;
2740         case MSR_IA32_PEBS_ENABLE:
2741                 /* PEBS needs a quiescent period after being disabled (to write
2742                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2743                  * provide that period, so a CPU could write host's record into
2744                  * guest's memory.
2745                  */
2746                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2747         }
2748
2749         i = find_msr(&m->guest, msr);
2750         if (!entry_only)
2751                 j = find_msr(&m->host, msr);
2752
2753         if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
2754                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2755                                 "Can't add msr %x\n", msr);
2756                 return;
2757         }
2758         if (i < 0) {
2759                 i = m->guest.nr++;
2760                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2761         }
2762         m->guest.val[i].index = msr;
2763         m->guest.val[i].value = guest_val;
2764
2765         if (entry_only)
2766                 return;
2767
2768         if (j < 0) {
2769                 j = m->host.nr++;
2770                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2771         }
2772         m->host.val[j].index = msr;
2773         m->host.val[j].value = host_val;
2774 }
2775
2776 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2777 {
2778         u64 guest_efer = vmx->vcpu.arch.efer;
2779         u64 ignore_bits = 0;
2780
2781         if (!enable_ept) {
2782                 /*
2783                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2784                  * host CPUID is more efficient than testing guest CPUID
2785                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2786                  */
2787                 if (boot_cpu_has(X86_FEATURE_SMEP))
2788                         guest_efer |= EFER_NX;
2789                 else if (!(guest_efer & EFER_NX))
2790                         ignore_bits |= EFER_NX;
2791         }
2792
2793         /*
2794          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2795          */
2796         ignore_bits |= EFER_SCE;
2797 #ifdef CONFIG_X86_64
2798         ignore_bits |= EFER_LMA | EFER_LME;
2799         /* SCE is meaningful only in long mode on Intel */
2800         if (guest_efer & EFER_LMA)
2801                 ignore_bits &= ~(u64)EFER_SCE;
2802 #endif
2803
2804         clear_atomic_switch_msr(vmx, MSR_EFER);
2805
2806         /*
2807          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2808          * On CPUs that support "load IA32_EFER", always switch EFER
2809          * atomically, since it's faster than switching it manually.
2810          */
2811         if (cpu_has_load_ia32_efer ||
2812             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2813                 if (!(guest_efer & EFER_LMA))
2814                         guest_efer &= ~EFER_LME;
2815                 if (guest_efer != host_efer)
2816                         add_atomic_switch_msr(vmx, MSR_EFER,
2817                                               guest_efer, host_efer, false);
2818                 return false;
2819         } else {
2820                 guest_efer &= ~ignore_bits;
2821                 guest_efer |= host_efer & ignore_bits;
2822
2823                 vmx->guest_msrs[efer_offset].data = guest_efer;
2824                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2825
2826                 return true;
2827         }
2828 }
2829
2830 #ifdef CONFIG_X86_32
2831 /*
2832  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2833  * VMCS rather than the segment table.  KVM uses this helper to figure
2834  * out the current bases to poke them into the VMCS before entry.
2835  */
2836 static unsigned long segment_base(u16 selector)
2837 {
2838         struct desc_struct *table;
2839         unsigned long v;
2840
2841         if (!(selector & ~SEGMENT_RPL_MASK))
2842                 return 0;
2843
2844         table = get_current_gdt_ro();
2845
2846         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2847                 u16 ldt_selector = kvm_read_ldt();
2848
2849                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2850                         return 0;
2851
2852                 table = (struct desc_struct *)segment_base(ldt_selector);
2853         }
2854         v = get_desc_base(&table[selector >> 3]);
2855         return v;
2856 }
2857 #endif
2858
2859 static void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
2860 {
2861         struct vcpu_vmx *vmx = to_vmx(vcpu);
2862         struct vmcs_host_state *host_state;
2863 #ifdef CONFIG_X86_64
2864         int cpu = raw_smp_processor_id();
2865 #endif
2866         unsigned long fs_base, gs_base;
2867         u16 fs_sel, gs_sel;
2868         int i;
2869
2870         vmx->req_immediate_exit = false;
2871
2872         if (vmx->loaded_cpu_state)
2873                 return;
2874
2875         vmx->loaded_cpu_state = vmx->loaded_vmcs;
2876         host_state = &vmx->loaded_cpu_state->host_state;
2877
2878         /*
2879          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2880          * allow segment selectors with cpl > 0 or ti == 1.
2881          */
2882         host_state->ldt_sel = kvm_read_ldt();
2883
2884 #ifdef CONFIG_X86_64
2885         savesegment(ds, host_state->ds_sel);
2886         savesegment(es, host_state->es_sel);
2887
2888         gs_base = cpu_kernelmode_gs_base(cpu);
2889         if (likely(is_64bit_mm(current->mm))) {
2890                 save_fsgs_for_kvm();
2891                 fs_sel = current->thread.fsindex;
2892                 gs_sel = current->thread.gsindex;
2893                 fs_base = current->thread.fsbase;
2894                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2895         } else {
2896                 savesegment(fs, fs_sel);
2897                 savesegment(gs, gs_sel);
2898                 fs_base = read_msr(MSR_FS_BASE);
2899                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
2900         }
2901
2902         if (is_long_mode(&vmx->vcpu))
2903                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2904 #else
2905         savesegment(fs, fs_sel);
2906         savesegment(gs, gs_sel);
2907         fs_base = segment_base(fs_sel);
2908         gs_base = segment_base(gs_sel);
2909 #endif
2910
2911         if (unlikely(fs_sel != host_state->fs_sel)) {
2912                 if (!(fs_sel & 7))
2913                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
2914                 else
2915                         vmcs_write16(HOST_FS_SELECTOR, 0);
2916                 host_state->fs_sel = fs_sel;
2917         }
2918         if (unlikely(gs_sel != host_state->gs_sel)) {
2919                 if (!(gs_sel & 7))
2920                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
2921                 else
2922                         vmcs_write16(HOST_GS_SELECTOR, 0);
2923                 host_state->gs_sel = gs_sel;
2924         }
2925         if (unlikely(fs_base != host_state->fs_base)) {
2926                 vmcs_writel(HOST_FS_BASE, fs_base);
2927                 host_state->fs_base = fs_base;
2928         }
2929         if (unlikely(gs_base != host_state->gs_base)) {
2930                 vmcs_writel(HOST_GS_BASE, gs_base);
2931                 host_state->gs_base = gs_base;
2932         }
2933
2934         for (i = 0; i < vmx->save_nmsrs; ++i)
2935                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2936                                    vmx->guest_msrs[i].data,
2937                                    vmx->guest_msrs[i].mask);
2938 }
2939
2940 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
2941 {
2942         struct vmcs_host_state *host_state;
2943
2944         if (!vmx->loaded_cpu_state)
2945                 return;
2946
2947         WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
2948         host_state = &vmx->loaded_cpu_state->host_state;
2949
2950         ++vmx->vcpu.stat.host_state_reload;
2951         vmx->loaded_cpu_state = NULL;
2952
2953 #ifdef CONFIG_X86_64
2954         if (is_long_mode(&vmx->vcpu))
2955                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2956 #endif
2957         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
2958                 kvm_load_ldt(host_state->ldt_sel);
2959 #ifdef CONFIG_X86_64
2960                 load_gs_index(host_state->gs_sel);
2961 #else
2962                 loadsegment(gs, host_state->gs_sel);
2963 #endif
2964         }
2965         if (host_state->fs_sel & 7)
2966                 loadsegment(fs, host_state->fs_sel);
2967 #ifdef CONFIG_X86_64
2968         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
2969                 loadsegment(ds, host_state->ds_sel);
2970                 loadsegment(es, host_state->es_sel);
2971         }
2972 #endif
2973         invalidate_tss_limit();
2974 #ifdef CONFIG_X86_64
2975         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2976 #endif
2977         load_fixmap_gdt(raw_smp_processor_id());
2978 }
2979
2980 #ifdef CONFIG_X86_64
2981 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
2982 {
2983         if (is_long_mode(&vmx->vcpu)) {
2984                 preempt_disable();
2985                 if (vmx->loaded_cpu_state)
2986                         rdmsrl(MSR_KERNEL_GS_BASE,
2987                                vmx->msr_guest_kernel_gs_base);
2988                 preempt_enable();
2989         }
2990         return vmx->msr_guest_kernel_gs_base;
2991 }
2992
2993 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
2994 {
2995         if (is_long_mode(&vmx->vcpu)) {
2996                 preempt_disable();
2997                 if (vmx->loaded_cpu_state)
2998                         wrmsrl(MSR_KERNEL_GS_BASE, data);
2999                 preempt_enable();
3000         }
3001         vmx->msr_guest_kernel_gs_base = data;
3002 }
3003 #endif
3004
3005 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
3006 {
3007         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3008         struct pi_desc old, new;
3009         unsigned int dest;
3010
3011         /*
3012          * In case of hot-plug or hot-unplug, we may have to undo
3013          * vmx_vcpu_pi_put even if there is no assigned device.  And we
3014          * always keep PI.NDST up to date for simplicity: it makes the
3015          * code easier, and CPU migration is not a fast path.
3016          */
3017         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
3018                 return;
3019
3020         /*
3021          * First handle the simple case where no cmpxchg is necessary; just
3022          * allow posting non-urgent interrupts.
3023          *
3024          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
3025          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
3026          * expects the VCPU to be on the blocked_vcpu_list that matches
3027          * PI.NDST.
3028          */
3029         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
3030             vcpu->cpu == cpu) {
3031                 pi_clear_sn(pi_desc);
3032                 return;
3033         }
3034
3035         /* The full case.  */
3036         do {
3037                 old.control = new.control = pi_desc->control;
3038
3039                 dest = cpu_physical_id(cpu);
3040
3041                 if (x2apic_enabled())
3042                         new.ndst = dest;
3043                 else
3044                         new.ndst = (dest << 8) & 0xFF00;
3045
3046                 new.sn = 0;
3047         } while (cmpxchg64(&pi_desc->control, old.control,
3048                            new.control) != old.control);
3049 }
3050
3051 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
3052 {
3053         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
3054         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
3055 }
3056
3057 /*
3058  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
3059  * vcpu mutex is already taken.
3060  */
3061 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3062 {
3063         struct vcpu_vmx *vmx = to_vmx(vcpu);
3064         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
3065
3066         if (!already_loaded) {
3067                 loaded_vmcs_clear(vmx->loaded_vmcs);
3068                 local_irq_disable();
3069                 crash_disable_local_vmclear(cpu);
3070
3071                 /*
3072                  * Read loaded_vmcs->cpu should be before fetching
3073                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
3074                  * See the comments in __loaded_vmcs_clear().
3075                  */
3076                 smp_rmb();
3077
3078                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
3079                          &per_cpu(loaded_vmcss_on_cpu, cpu));
3080                 crash_enable_local_vmclear(cpu);
3081                 local_irq_enable();
3082         }
3083
3084         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
3085                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
3086                 vmcs_load(vmx->loaded_vmcs->vmcs);
3087                 indirect_branch_prediction_barrier();
3088         }
3089
3090         if (!already_loaded) {
3091                 void *gdt = get_current_gdt_ro();
3092                 unsigned long sysenter_esp;
3093
3094                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3095
3096                 /*
3097                  * Linux uses per-cpu TSS and GDT, so set these when switching
3098                  * processors.  See 22.2.4.
3099                  */
3100                 vmcs_writel(HOST_TR_BASE,
3101                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
3102                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
3103
3104                 /*
3105                  * VM exits change the host TR limit to 0x67 after a VM
3106                  * exit.  This is okay, since 0x67 covers everything except
3107                  * the IO bitmap and have have code to handle the IO bitmap
3108                  * being lost after a VM exit.
3109                  */
3110                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
3111
3112                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
3113                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
3114
3115                 vmx->loaded_vmcs->cpu = cpu;
3116         }
3117
3118         /* Setup TSC multiplier */
3119         if (kvm_has_tsc_control &&
3120             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
3121                 decache_tsc_multiplier(vmx);
3122
3123         vmx_vcpu_pi_load(vcpu, cpu);
3124         vmx->host_pkru = read_pkru();
3125         vmx->host_debugctlmsr = get_debugctlmsr();
3126 }
3127
3128 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
3129 {
3130         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3131
3132         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
3133                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
3134                 !kvm_vcpu_apicv_active(vcpu))
3135                 return;
3136
3137         /* Set SN when the vCPU is preempted */
3138         if (vcpu->preempted)
3139                 pi_set_sn(pi_desc);
3140 }
3141
3142 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
3143 {
3144         vmx_vcpu_pi_put(vcpu);
3145
3146         vmx_prepare_switch_to_host(to_vmx(vcpu));
3147 }
3148
3149 static bool emulation_required(struct kvm_vcpu *vcpu)
3150 {
3151         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3152 }
3153
3154 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
3155
3156 /*
3157  * Return the cr0 value that a nested guest would read. This is a combination
3158  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
3159  * its hypervisor (cr0_read_shadow).
3160  */
3161 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
3162 {
3163         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
3164                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
3165 }
3166 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
3167 {
3168         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
3169                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
3170 }
3171
3172 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
3173 {
3174         unsigned long rflags, save_rflags;
3175
3176         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
3177                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3178                 rflags = vmcs_readl(GUEST_RFLAGS);
3179                 if (to_vmx(vcpu)->rmode.vm86_active) {
3180                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3181                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
3182                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3183                 }
3184                 to_vmx(vcpu)->rflags = rflags;
3185         }
3186         return to_vmx(vcpu)->rflags;
3187 }
3188
3189 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3190 {
3191         unsigned long old_rflags = vmx_get_rflags(vcpu);
3192
3193         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3194         to_vmx(vcpu)->rflags = rflags;
3195         if (to_vmx(vcpu)->rmode.vm86_active) {
3196                 to_vmx(vcpu)->rmode.save_rflags = rflags;
3197                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3198         }
3199         vmcs_writel(GUEST_RFLAGS, rflags);
3200
3201         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
3202                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
3203 }
3204
3205 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
3206 {
3207         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3208         int ret = 0;
3209
3210         if (interruptibility & GUEST_INTR_STATE_STI)
3211                 ret |= KVM_X86_SHADOW_INT_STI;
3212         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
3213                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
3214
3215         return ret;
3216 }
3217
3218 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
3219 {
3220         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3221         u32 interruptibility = interruptibility_old;
3222
3223         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
3224
3225         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
3226                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
3227         else if (mask & KVM_X86_SHADOW_INT_STI)
3228                 interruptibility |= GUEST_INTR_STATE_STI;
3229
3230         if ((interruptibility != interruptibility_old))
3231                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
3232 }
3233
3234 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
3235 {
3236         unsigned long rip;
3237
3238         rip = kvm_rip_read(vcpu);
3239         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3240         kvm_rip_write(vcpu, rip);
3241
3242         /* skipping an emulated instruction also counts */
3243         vmx_set_interrupt_shadow(vcpu, 0);
3244 }
3245
3246 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3247                                                unsigned long exit_qual)
3248 {
3249         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3250         unsigned int nr = vcpu->arch.exception.nr;
3251         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3252
3253         if (vcpu->arch.exception.has_error_code) {
3254                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3255                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3256         }
3257
3258         if (kvm_exception_is_soft(nr))
3259                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3260         else
3261                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3262
3263         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3264             vmx_get_nmi_mask(vcpu))
3265                 intr_info |= INTR_INFO_UNBLOCK_NMI;
3266
3267         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3268 }
3269
3270 /*
3271  * KVM wants to inject page-faults which it got to the guest. This function
3272  * checks whether in a nested guest, we need to inject them to L1 or L2.
3273  */
3274 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
3275 {
3276         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3277         unsigned int nr = vcpu->arch.exception.nr;
3278
3279         if (nr == PF_VECTOR) {
3280                 if (vcpu->arch.exception.nested_apf) {
3281                         *exit_qual = vcpu->arch.apf.nested_apf_token;
3282                         return 1;
3283                 }
3284                 /*
3285                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
3286                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
3287                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
3288                  * can be written only when inject_pending_event runs.  This should be
3289                  * conditional on a new capability---if the capability is disabled,
3290                  * kvm_multiple_exception would write the ancillary information to
3291                  * CR2 or DR6, for backwards ABI-compatibility.
3292                  */
3293                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
3294                                                     vcpu->arch.exception.error_code)) {
3295                         *exit_qual = vcpu->arch.cr2;
3296                         return 1;
3297                 }
3298         } else {
3299                 if (vmcs12->exception_bitmap & (1u << nr)) {
3300                         if (nr == DB_VECTOR)
3301                                 *exit_qual = vcpu->arch.dr6;
3302                         else
3303                                 *exit_qual = 0;
3304                         return 1;
3305                 }
3306         }
3307
3308         return 0;
3309 }
3310
3311 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
3312 {
3313         /*
3314          * Ensure that we clear the HLT state in the VMCS.  We don't need to
3315          * explicitly skip the instruction because if the HLT state is set,
3316          * then the instruction is already executing and RIP has already been
3317          * advanced.
3318          */
3319         if (kvm_hlt_in_guest(vcpu->kvm) &&
3320                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
3321                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3322 }
3323
3324 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
3325 {
3326         struct vcpu_vmx *vmx = to_vmx(vcpu);
3327         unsigned nr = vcpu->arch.exception.nr;
3328         bool has_error_code = vcpu->arch.exception.has_error_code;
3329         u32 error_code = vcpu->arch.exception.error_code;
3330         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3331
3332         if (has_error_code) {
3333                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3334                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3335         }
3336
3337         if (vmx->rmode.vm86_active) {
3338                 int inc_eip = 0;
3339                 if (kvm_exception_is_soft(nr))
3340                         inc_eip = vcpu->arch.event_exit_inst_len;
3341                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3342                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3343                 return;
3344         }
3345
3346         WARN_ON_ONCE(vmx->emulation_required);
3347
3348         if (kvm_exception_is_soft(nr)) {
3349                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3350                              vmx->vcpu.arch.event_exit_inst_len);
3351                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3352         } else
3353                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3354
3355         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3356
3357         vmx_clear_hlt(vcpu);
3358 }
3359
3360 static bool vmx_rdtscp_supported(void)
3361 {
3362         return cpu_has_vmx_rdtscp();
3363 }
3364
3365 static bool vmx_invpcid_supported(void)
3366 {
3367         return cpu_has_vmx_invpcid();
3368 }
3369
3370 /*
3371  * Swap MSR entry in host/guest MSR entry array.
3372  */
3373 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3374 {
3375         struct shared_msr_entry tmp;
3376
3377         tmp = vmx->guest_msrs[to];
3378         vmx->guest_msrs[to] = vmx->guest_msrs[from];
3379         vmx->guest_msrs[from] = tmp;
3380 }
3381
3382 /*
3383  * Set up the vmcs to automatically save and restore system
3384  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
3385  * mode, as fiddling with msrs is very expensive.
3386  */
3387 static void setup_msrs(struct vcpu_vmx *vmx)
3388 {
3389         int save_nmsrs, index;
3390
3391         save_nmsrs = 0;
3392 #ifdef CONFIG_X86_64
3393         if (is_long_mode(&vmx->vcpu)) {
3394                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3395                 if (index >= 0)
3396                         move_msr_up(vmx, index, save_nmsrs++);
3397                 index = __find_msr_index(vmx, MSR_LSTAR);
3398                 if (index >= 0)
3399                         move_msr_up(vmx, index, save_nmsrs++);
3400                 index = __find_msr_index(vmx, MSR_CSTAR);
3401                 if (index >= 0)
3402                         move_msr_up(vmx, index, save_nmsrs++);
3403                 index = __find_msr_index(vmx, MSR_TSC_AUX);
3404                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3405                         move_msr_up(vmx, index, save_nmsrs++);
3406                 /*
3407                  * MSR_STAR is only needed on long mode guests, and only
3408                  * if efer.sce is enabled.
3409                  */
3410                 index = __find_msr_index(vmx, MSR_STAR);
3411                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3412                         move_msr_up(vmx, index, save_nmsrs++);
3413         }
3414 #endif
3415         index = __find_msr_index(vmx, MSR_EFER);
3416         if (index >= 0 && update_transition_efer(vmx, index))
3417                 move_msr_up(vmx, index, save_nmsrs++);
3418
3419         vmx->save_nmsrs = save_nmsrs;
3420
3421         if (cpu_has_vmx_msr_bitmap())
3422                 vmx_update_msr_bitmap(&vmx->vcpu);
3423 }
3424
3425 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3426 {
3427         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3428
3429         if (is_guest_mode(vcpu) &&
3430             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3431                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3432
3433         return vcpu->arch.tsc_offset;
3434 }
3435
3436 /*
3437  * writes 'offset' into guest's timestamp counter offset register
3438  */
3439 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3440 {
3441         if (is_guest_mode(vcpu)) {
3442                 /*
3443                  * We're here if L1 chose not to trap WRMSR to TSC. According
3444                  * to the spec, this should set L1's TSC; The offset that L1
3445                  * set for L2 remains unchanged, and still needs to be added
3446                  * to the newly set TSC to get L2's TSC.
3447                  */
3448                 struct vmcs12 *vmcs12;
3449                 /* recalculate vmcs02.TSC_OFFSET: */
3450                 vmcs12 = get_vmcs12(vcpu);
3451                 vmcs_write64(TSC_OFFSET, offset +
3452                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3453                          vmcs12->tsc_offset : 0));
3454         } else {
3455                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3456                                            vmcs_read64(TSC_OFFSET), offset);
3457                 vmcs_write64(TSC_OFFSET, offset);
3458         }
3459 }
3460
3461 /*
3462  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3463  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3464  * all guests if the "nested" module option is off, and can also be disabled
3465  * for a single guest by disabling its VMX cpuid bit.
3466  */
3467 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3468 {
3469         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3470 }
3471
3472 /*
3473  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3474  * returned for the various VMX controls MSRs when nested VMX is enabled.
3475  * The same values should also be used to verify that vmcs12 control fields are
3476  * valid during nested entry from L1 to L2.
3477  * Each of these control msrs has a low and high 32-bit half: A low bit is on
3478  * if the corresponding bit in the (32-bit) control field *must* be on, and a
3479  * bit in the high half is on if the corresponding bit in the control field
3480  * may be on. See also vmx_control_verify().
3481  */
3482 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3483 {
3484         if (!nested) {
3485                 memset(msrs, 0, sizeof(*msrs));
3486                 return;
3487         }
3488
3489         /*
3490          * Note that as a general rule, the high half of the MSRs (bits in
3491          * the control fields which may be 1) should be initialized by the
3492          * intersection of the underlying hardware's MSR (i.e., features which
3493          * can be supported) and the list of features we want to expose -
3494          * because they are known to be properly supported in our code.
3495          * Also, usually, the low half of the MSRs (bits which must be 1) can
3496          * be set to 0, meaning that L1 may turn off any of these bits. The
3497          * reason is that if one of these bits is necessary, it will appear
3498          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3499          * fields of vmcs01 and vmcs02, will turn these bits off - and
3500          * nested_vmx_exit_reflected() will not pass related exits to L1.
3501          * These rules have exceptions below.
3502          */
3503
3504         /* pin-based controls */
3505         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3506                 msrs->pinbased_ctls_low,
3507                 msrs->pinbased_ctls_high);
3508         msrs->pinbased_ctls_low |=
3509                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3510         msrs->pinbased_ctls_high &=
3511                 PIN_BASED_EXT_INTR_MASK |
3512                 PIN_BASED_NMI_EXITING |
3513                 PIN_BASED_VIRTUAL_NMIS |
3514                 (apicv ? PIN_BASED_POSTED_INTR : 0);
3515         msrs->pinbased_ctls_high |=
3516                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3517                 PIN_BASED_VMX_PREEMPTION_TIMER;
3518
3519         /* exit controls */
3520         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3521                 msrs->exit_ctls_low,
3522                 msrs->exit_ctls_high);
3523         msrs->exit_ctls_low =
3524                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3525
3526         msrs->exit_ctls_high &=
3527 #ifdef CONFIG_X86_64
3528                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3529 #endif
3530                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3531         msrs->exit_ctls_high |=
3532                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3533                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3534                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3535
3536         if (kvm_mpx_supported())
3537                 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
3538
3539         /* We support free control of debug control saving. */
3540         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3541
3542         /* entry controls */
3543         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3544                 msrs->entry_ctls_low,
3545                 msrs->entry_ctls_high);
3546         msrs->entry_ctls_low =
3547                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3548         msrs->entry_ctls_high &=
3549 #ifdef CONFIG_X86_64
3550                 VM_ENTRY_IA32E_MODE |
3551 #endif
3552                 VM_ENTRY_LOAD_IA32_PAT;
3553         msrs->entry_ctls_high |=
3554                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3555         if (kvm_mpx_supported())
3556                 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3557
3558         /* We support free control of debug control loading. */
3559         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3560
3561         /* cpu-based controls */
3562         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3563                 msrs->procbased_ctls_low,
3564                 msrs->procbased_ctls_high);
3565         msrs->procbased_ctls_low =
3566                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3567         msrs->procbased_ctls_high &=
3568                 CPU_BASED_VIRTUAL_INTR_PENDING |
3569                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3570                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3571                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3572                 CPU_BASED_CR3_STORE_EXITING |
3573 #ifdef CONFIG_X86_64
3574                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3575 #endif
3576                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3577                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3578                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3579                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3580                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3581         /*
3582          * We can allow some features even when not supported by the
3583          * hardware. For example, L1 can specify an MSR bitmap - and we
3584          * can use it to avoid exits to L1 - even when L0 runs L2
3585          * without MSR bitmaps.
3586          */
3587         msrs->procbased_ctls_high |=
3588                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3589                 CPU_BASED_USE_MSR_BITMAPS;
3590
3591         /* We support free control of CR3 access interception. */
3592         msrs->procbased_ctls_low &=
3593                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3594
3595         /*
3596          * secondary cpu-based controls.  Do not include those that
3597          * depend on CPUID bits, they are added later by vmx_cpuid_update.
3598          */
3599         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3600                 msrs->secondary_ctls_low,
3601                 msrs->secondary_ctls_high);
3602         msrs->secondary_ctls_low = 0;
3603         msrs->secondary_ctls_high &=
3604                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3605                 SECONDARY_EXEC_DESC |
3606                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3607                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3608                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3609                 SECONDARY_EXEC_WBINVD_EXITING;
3610         /*
3611          * We can emulate "VMCS shadowing," even if the hardware
3612          * doesn't support it.
3613          */
3614         msrs->secondary_ctls_high |=
3615                 SECONDARY_EXEC_SHADOW_VMCS;
3616
3617         if (enable_ept) {
3618                 /* nested EPT: emulate EPT also to L1 */
3619                 msrs->secondary_ctls_high |=
3620                         SECONDARY_EXEC_ENABLE_EPT;
3621                 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3622                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3623                 if (cpu_has_vmx_ept_execute_only())
3624                         msrs->ept_caps |=
3625                                 VMX_EPT_EXECUTE_ONLY_BIT;
3626                 msrs->ept_caps &= vmx_capability.ept;
3627                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3628                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3629                         VMX_EPT_1GB_PAGE_BIT;
3630                 if (enable_ept_ad_bits) {
3631                         msrs->secondary_ctls_high |=
3632                                 SECONDARY_EXEC_ENABLE_PML;
3633                         msrs->ept_caps |= VMX_EPT_AD_BIT;
3634                 }
3635         }
3636
3637         if (cpu_has_vmx_vmfunc()) {
3638                 msrs->secondary_ctls_high |=
3639                         SECONDARY_EXEC_ENABLE_VMFUNC;
3640                 /*
3641                  * Advertise EPTP switching unconditionally
3642                  * since we emulate it
3643                  */
3644                 if (enable_ept)
3645                         msrs->vmfunc_controls =
3646                                 VMX_VMFUNC_EPTP_SWITCHING;
3647         }
3648
3649         /*
3650          * Old versions of KVM use the single-context version without
3651          * checking for support, so declare that it is supported even
3652          * though it is treated as global context.  The alternative is
3653          * not failing the single-context invvpid, and it is worse.
3654          */
3655         if (enable_vpid) {
3656                 msrs->secondary_ctls_high |=
3657                         SECONDARY_EXEC_ENABLE_VPID;
3658                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3659                         VMX_VPID_EXTENT_SUPPORTED_MASK;
3660         }
3661
3662         if (enable_unrestricted_guest)
3663                 msrs->secondary_ctls_high |=
3664                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
3665
3666         /* miscellaneous data */
3667         rdmsr(MSR_IA32_VMX_MISC,
3668                 msrs->misc_low,
3669                 msrs->misc_high);
3670         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3671         msrs->misc_low |=
3672                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3673                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3674                 VMX_MISC_ACTIVITY_HLT;
3675         msrs->misc_high = 0;
3676
3677         /*
3678          * This MSR reports some information about VMX support. We
3679          * should return information about the VMX we emulate for the
3680          * guest, and the VMCS structure we give it - not about the
3681          * VMX support of the underlying hardware.
3682          */
3683         msrs->basic =
3684                 VMCS12_REVISION |
3685                 VMX_BASIC_TRUE_CTLS |
3686                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3687                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3688
3689         if (cpu_has_vmx_basic_inout())
3690                 msrs->basic |= VMX_BASIC_INOUT;
3691
3692         /*
3693          * These MSRs specify bits which the guest must keep fixed on
3694          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3695          * We picked the standard core2 setting.
3696          */
3697 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3698 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
3699         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3700         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3701
3702         /* These MSRs specify bits which the guest must keep fixed off. */
3703         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3704         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3705
3706         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3707         msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3708 }
3709
3710 /*
3711  * if fixed0[i] == 1: val[i] must be 1
3712  * if fixed1[i] == 0: val[i] must be 0
3713  */
3714 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3715 {
3716         return ((val & fixed1) | fixed0) == val;
3717 }
3718
3719 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3720 {
3721         return fixed_bits_valid(control, low, high);
3722 }
3723
3724 static inline u64 vmx_control_msr(u32 low, u32 high)
3725 {
3726         return low | ((u64)high << 32);
3727 }
3728
3729 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3730 {
3731         superset &= mask;
3732         subset &= mask;
3733
3734         return (superset | subset) == superset;
3735 }
3736
3737 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3738 {
3739         const u64 feature_and_reserved =
3740                 /* feature (except bit 48; see below) */
3741                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3742                 /* reserved */
3743                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3744         u64 vmx_basic = vmx->nested.msrs.basic;
3745
3746         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3747                 return -EINVAL;
3748
3749         /*
3750          * KVM does not emulate a version of VMX that constrains physical
3751          * addresses of VMX structures (e.g. VMCS) to 32-bits.
3752          */
3753         if (data & BIT_ULL(48))
3754                 return -EINVAL;
3755
3756         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3757             vmx_basic_vmcs_revision_id(data))
3758                 return -EINVAL;
3759
3760         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3761                 return -EINVAL;
3762
3763         vmx->nested.msrs.basic = data;
3764         return 0;
3765 }
3766
3767 static int
3768 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3769 {
3770         u64 supported;
3771         u32 *lowp, *highp;
3772
3773         switch (msr_index) {
3774         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3775                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3776                 highp = &vmx->nested.msrs.pinbased_ctls_high;
3777                 break;
3778         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3779                 lowp = &vmx->nested.msrs.procbased_ctls_low;
3780                 highp = &vmx->nested.msrs.procbased_ctls_high;
3781                 break;
3782         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3783                 lowp = &vmx->nested.msrs.exit_ctls_low;
3784                 highp = &vmx->nested.msrs.exit_ctls_high;
3785                 break;
3786         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3787                 lowp = &vmx->nested.msrs.entry_ctls_low;
3788                 highp = &vmx->nested.msrs.entry_ctls_high;
3789                 break;
3790         case MSR_IA32_VMX_PROCBASED_CTLS2:
3791                 lowp = &vmx->nested.msrs.secondary_ctls_low;
3792                 highp = &vmx->nested.msrs.secondary_ctls_high;
3793                 break;
3794         default:
3795                 BUG();
3796         }
3797
3798         supported = vmx_control_msr(*lowp, *highp);
3799
3800         /* Check must-be-1 bits are still 1. */
3801         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3802                 return -EINVAL;
3803
3804         /* Check must-be-0 bits are still 0. */
3805         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3806                 return -EINVAL;
3807
3808         *lowp = data;
3809         *highp = data >> 32;
3810         return 0;
3811 }
3812
3813 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3814 {
3815         const u64 feature_and_reserved_bits =
3816                 /* feature */
3817                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3818                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3819                 /* reserved */
3820                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3821         u64 vmx_misc;
3822
3823         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3824                                    vmx->nested.msrs.misc_high);
3825
3826         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3827                 return -EINVAL;
3828
3829         if ((vmx->nested.msrs.pinbased_ctls_high &
3830              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3831             vmx_misc_preemption_timer_rate(data) !=
3832             vmx_misc_preemption_timer_rate(vmx_misc))
3833                 return -EINVAL;
3834
3835         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3836                 return -EINVAL;
3837
3838         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3839                 return -EINVAL;
3840
3841         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3842                 return -EINVAL;
3843
3844         vmx->nested.msrs.misc_low = data;
3845         vmx->nested.msrs.misc_high = data >> 32;
3846
3847         /*
3848          * If L1 has read-only VM-exit information fields, use the
3849          * less permissive vmx_vmwrite_bitmap to specify write
3850          * permissions for the shadow VMCS.
3851          */
3852         if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3853                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3854
3855         return 0;
3856 }
3857
3858 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3859 {
3860         u64 vmx_ept_vpid_cap;
3861
3862         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3863                                            vmx->nested.msrs.vpid_caps);
3864
3865         /* Every bit is either reserved or a feature bit. */
3866         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3867                 return -EINVAL;
3868
3869         vmx->nested.msrs.ept_caps = data;
3870         vmx->nested.msrs.vpid_caps = data >> 32;
3871         return 0;
3872 }
3873
3874 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3875 {
3876         u64 *msr;
3877
3878         switch (msr_index) {
3879         case MSR_IA32_VMX_CR0_FIXED0:
3880                 msr = &vmx->nested.msrs.cr0_fixed0;
3881                 break;
3882         case MSR_IA32_VMX_CR4_FIXED0:
3883                 msr = &vmx->nested.msrs.cr4_fixed0;
3884                 break;
3885         default:
3886                 BUG();
3887         }
3888
3889         /*
3890          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3891          * must be 1 in the restored value.
3892          */
3893         if (!is_bitwise_subset(data, *msr, -1ULL))
3894                 return -EINVAL;
3895
3896         *msr = data;
3897         return 0;
3898 }
3899
3900 /*
3901  * Called when userspace is restoring VMX MSRs.
3902  *
3903  * Returns 0 on success, non-0 otherwise.
3904  */
3905 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3906 {
3907         struct vcpu_vmx *vmx = to_vmx(vcpu);
3908
3909         /*
3910          * Don't allow changes to the VMX capability MSRs while the vCPU
3911          * is in VMX operation.
3912          */
3913         if (vmx->nested.vmxon)
3914                 return -EBUSY;
3915
3916         switch (msr_index) {
3917         case MSR_IA32_VMX_BASIC:
3918                 return vmx_restore_vmx_basic(vmx, data);
3919         case MSR_IA32_VMX_PINBASED_CTLS:
3920         case MSR_IA32_VMX_PROCBASED_CTLS:
3921         case MSR_IA32_VMX_EXIT_CTLS:
3922         case MSR_IA32_VMX_ENTRY_CTLS:
3923                 /*
3924                  * The "non-true" VMX capability MSRs are generated from the
3925                  * "true" MSRs, so we do not support restoring them directly.
3926                  *
3927                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3928                  * should restore the "true" MSRs with the must-be-1 bits
3929                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3930                  * DEFAULT SETTINGS".
3931                  */
3932                 return -EINVAL;
3933         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3934         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3935         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3936         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3937         case MSR_IA32_VMX_PROCBASED_CTLS2:
3938                 return vmx_restore_control_msr(vmx, msr_index, data);
3939         case MSR_IA32_VMX_MISC:
3940                 return vmx_restore_vmx_misc(vmx, data);
3941         case MSR_IA32_VMX_CR0_FIXED0:
3942         case MSR_IA32_VMX_CR4_FIXED0:
3943                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3944         case MSR_IA32_VMX_CR0_FIXED1:
3945         case MSR_IA32_VMX_CR4_FIXED1:
3946                 /*
3947                  * These MSRs are generated based on the vCPU's CPUID, so we
3948                  * do not support restoring them directly.
3949                  */
3950                 return -EINVAL;
3951         case MSR_IA32_VMX_EPT_VPID_CAP:
3952                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3953         case MSR_IA32_VMX_VMCS_ENUM:
3954                 vmx->nested.msrs.vmcs_enum = data;
3955                 return 0;
3956         default:
3957                 /*
3958                  * The rest of the VMX capability MSRs do not support restore.
3959                  */
3960                 return -EINVAL;
3961         }
3962 }
3963
3964 /* Returns 0 on success, non-0 otherwise. */
3965 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3966 {
3967         switch (msr_index) {
3968         case MSR_IA32_VMX_BASIC:
3969                 *pdata = msrs->basic;
3970                 break;
3971         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3972         case MSR_IA32_VMX_PINBASED_CTLS:
3973                 *pdata = vmx_control_msr(
3974                         msrs->pinbased_ctls_low,
3975                         msrs->pinbased_ctls_high);
3976                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3977                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3978                 break;
3979         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3980         case MSR_IA32_VMX_PROCBASED_CTLS:
3981                 *pdata = vmx_control_msr(
3982                         msrs->procbased_ctls_low,
3983                         msrs->procbased_ctls_high);
3984                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3985                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3986                 break;
3987         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3988         case MSR_IA32_VMX_EXIT_CTLS:
3989                 *pdata = vmx_control_msr(
3990                         msrs->exit_ctls_low,
3991                         msrs->exit_ctls_high);
3992                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3993                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3994                 break;
3995         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3996         case MSR_IA32_VMX_ENTRY_CTLS:
3997                 *pdata = vmx_control_msr(
3998                         msrs->entry_ctls_low,
3999                         msrs->entry_ctls_high);
4000                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
4001                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
4002                 break;
4003         case MSR_IA32_VMX_MISC:
4004                 *pdata = vmx_control_msr(
4005                         msrs->misc_low,
4006                         msrs->misc_high);
4007                 break;
4008         case MSR_IA32_VMX_CR0_FIXED0:
4009                 *pdata = msrs->cr0_fixed0;
4010                 break;
4011         case MSR_IA32_VMX_CR0_FIXED1:
4012                 *pdata = msrs->cr0_fixed1;
4013                 break;
4014         case MSR_IA32_VMX_CR4_FIXED0:
4015                 *pdata = msrs->cr4_fixed0;
4016                 break;
4017         case MSR_IA32_VMX_CR4_FIXED1:
4018                 *pdata = msrs->cr4_fixed1;
4019                 break;
4020         case MSR_IA32_VMX_VMCS_ENUM:
4021                 *pdata = msrs->vmcs_enum;
4022                 break;
4023         case MSR_IA32_VMX_PROCBASED_CTLS2:
4024                 *pdata = vmx_control_msr(
4025                         msrs->secondary_ctls_low,
4026                         msrs->secondary_ctls_high);
4027                 break;
4028         case MSR_IA32_VMX_EPT_VPID_CAP:
4029                 *pdata = msrs->ept_caps |
4030                         ((u64)msrs->vpid_caps << 32);
4031                 break;
4032         case MSR_IA32_VMX_VMFUNC:
4033                 *pdata = msrs->vmfunc_controls;
4034                 break;
4035         default:
4036                 return 1;
4037         }
4038
4039         return 0;
4040 }
4041
4042 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
4043                                                  uint64_t val)
4044 {
4045         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
4046
4047         return !(val & ~valid_bits);
4048 }
4049
4050 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
4051 {
4052         switch (msr->index) {
4053         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4054                 if (!nested)
4055                         return 1;
4056                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
4057         default:
4058                 return 1;
4059         }
4060
4061         return 0;
4062 }
4063
4064 /*
4065  * Reads an msr value (of 'msr_index') into 'pdata'.
4066  * Returns 0 on success, non-0 otherwise.
4067  * Assumes vcpu_load() was already called.
4068  */
4069 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4070 {
4071         struct vcpu_vmx *vmx = to_vmx(vcpu);
4072         struct shared_msr_entry *msr;
4073
4074         switch (msr_info->index) {
4075 #ifdef CONFIG_X86_64
4076         case MSR_FS_BASE:
4077                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
4078                 break;
4079         case MSR_GS_BASE:
4080                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
4081                 break;
4082         case MSR_KERNEL_GS_BASE:
4083                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
4084                 break;
4085 #endif
4086         case MSR_EFER:
4087                 return kvm_get_msr_common(vcpu, msr_info);
4088         case MSR_IA32_SPEC_CTRL:
4089                 if (!msr_info->host_initiated &&
4090                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4091                         return 1;
4092
4093                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
4094                 break;
4095         case MSR_IA32_ARCH_CAPABILITIES:
4096                 if (!msr_info->host_initiated &&
4097                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4098                         return 1;
4099                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
4100                 break;
4101         case MSR_IA32_SYSENTER_CS:
4102                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
4103                 break;
4104         case MSR_IA32_SYSENTER_EIP:
4105                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
4106                 break;
4107         case MSR_IA32_SYSENTER_ESP:
4108                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
4109                 break;
4110         case MSR_IA32_BNDCFGS:
4111                 if (!kvm_mpx_supported() ||
4112                     (!msr_info->host_initiated &&
4113                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4114                         return 1;
4115                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
4116                 break;
4117         case MSR_IA32_MCG_EXT_CTL:
4118                 if (!msr_info->host_initiated &&
4119                     !(vmx->msr_ia32_feature_control &
4120                       FEATURE_CONTROL_LMCE))
4121                         return 1;
4122                 msr_info->data = vcpu->arch.mcg_ext_ctl;
4123                 break;
4124         case MSR_IA32_FEATURE_CONTROL:
4125                 msr_info->data = vmx->msr_ia32_feature_control;
4126                 break;
4127         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4128                 if (!nested_vmx_allowed(vcpu))
4129                         return 1;
4130                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
4131                                        &msr_info->data);
4132         case MSR_IA32_XSS:
4133                 if (!vmx_xsaves_supported())
4134                         return 1;
4135                 msr_info->data = vcpu->arch.ia32_xss;
4136                 break;
4137         case MSR_TSC_AUX:
4138                 if (!msr_info->host_initiated &&
4139                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4140                         return 1;
4141                 /* Otherwise falls through */
4142         default:
4143                 msr = find_msr_entry(vmx, msr_info->index);
4144                 if (msr) {
4145                         msr_info->data = msr->data;
4146                         break;
4147                 }
4148                 return kvm_get_msr_common(vcpu, msr_info);
4149         }
4150
4151         return 0;
4152 }
4153
4154 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
4155
4156 /*
4157  * Writes msr value into into the appropriate "register".
4158  * Returns 0 on success, non-0 otherwise.
4159  * Assumes vcpu_load() was already called.
4160  */
4161 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4162 {
4163         struct vcpu_vmx *vmx = to_vmx(vcpu);
4164         struct shared_msr_entry *msr;
4165         int ret = 0;
4166         u32 msr_index = msr_info->index;
4167         u64 data = msr_info->data;
4168
4169         switch (msr_index) {
4170         case MSR_EFER:
4171                 ret = kvm_set_msr_common(vcpu, msr_info);
4172                 break;
4173 #ifdef CONFIG_X86_64
4174         case MSR_FS_BASE:
4175                 vmx_segment_cache_clear(vmx);
4176                 vmcs_writel(GUEST_FS_BASE, data);
4177                 break;
4178         case MSR_GS_BASE:
4179                 vmx_segment_cache_clear(vmx);
4180                 vmcs_writel(GUEST_GS_BASE, data);
4181                 break;
4182         case MSR_KERNEL_GS_BASE:
4183                 vmx_write_guest_kernel_gs_base(vmx, data);
4184                 break;
4185 #endif
4186         case MSR_IA32_SYSENTER_CS:
4187                 vmcs_write32(GUEST_SYSENTER_CS, data);
4188                 break;
4189         case MSR_IA32_SYSENTER_EIP:
4190                 vmcs_writel(GUEST_SYSENTER_EIP, data);
4191                 break;
4192         case MSR_IA32_SYSENTER_ESP:
4193                 vmcs_writel(GUEST_SYSENTER_ESP, data);
4194                 break;
4195         case MSR_IA32_BNDCFGS:
4196                 if (!kvm_mpx_supported() ||
4197                     (!msr_info->host_initiated &&
4198                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4199                         return 1;
4200                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4201                     (data & MSR_IA32_BNDCFGS_RSVD))
4202                         return 1;
4203                 vmcs_write64(GUEST_BNDCFGS, data);
4204                 break;
4205         case MSR_IA32_SPEC_CTRL:
4206                 if (!msr_info->host_initiated &&
4207                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4208                         return 1;
4209
4210                 /* The STIBP bit doesn't fault even if it's not advertised */
4211                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4212                         return 1;
4213
4214                 vmx->spec_ctrl = data;
4215
4216                 if (!data)
4217                         break;
4218
4219                 /*
4220                  * For non-nested:
4221                  * When it's written (to non-zero) for the first time, pass
4222                  * it through.
4223                  *
4224                  * For nested:
4225                  * The handling of the MSR bitmap for L2 guests is done in
4226                  * nested_vmx_merge_msr_bitmap. We should not touch the
4227                  * vmcs02.msr_bitmap here since it gets completely overwritten
4228                  * in the merging. We update the vmcs01 here for L1 as well
4229                  * since it will end up touching the MSR anyway now.
4230                  */
4231                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
4232                                               MSR_IA32_SPEC_CTRL,
4233                                               MSR_TYPE_RW);
4234                 break;
4235         case MSR_IA32_PRED_CMD:
4236                 if (!msr_info->host_initiated &&
4237                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4238                         return 1;
4239
4240                 if (data & ~PRED_CMD_IBPB)
4241                         return 1;
4242
4243                 if (!data)
4244                         break;
4245
4246                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4247
4248                 /*
4249                  * For non-nested:
4250                  * When it's written (to non-zero) for the first time, pass
4251                  * it through.
4252                  *
4253                  * For nested:
4254                  * The handling of the MSR bitmap for L2 guests is done in
4255                  * nested_vmx_merge_msr_bitmap. We should not touch the
4256                  * vmcs02.msr_bitmap here since it gets completely overwritten
4257                  * in the merging.
4258                  */
4259                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
4260                                               MSR_TYPE_W);
4261                 break;
4262         case MSR_IA32_ARCH_CAPABILITIES:
4263                 if (!msr_info->host_initiated)
4264                         return 1;
4265                 vmx->arch_capabilities = data;
4266                 break;
4267         case MSR_IA32_CR_PAT:
4268                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4269                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4270                                 return 1;
4271                         vmcs_write64(GUEST_IA32_PAT, data);
4272                         vcpu->arch.pat = data;
4273                         break;
4274                 }
4275                 ret = kvm_set_msr_common(vcpu, msr_info);
4276                 break;
4277         case MSR_IA32_TSC_ADJUST:
4278                 ret = kvm_set_msr_common(vcpu, msr_info);
4279                 break;
4280         case MSR_IA32_MCG_EXT_CTL:
4281                 if ((!msr_info->host_initiated &&
4282                      !(to_vmx(vcpu)->msr_ia32_feature_control &
4283                        FEATURE_CONTROL_LMCE)) ||
4284                     (data & ~MCG_EXT_CTL_LMCE_EN))
4285                         return 1;
4286                 vcpu->arch.mcg_ext_ctl = data;
4287                 break;
4288         case MSR_IA32_FEATURE_CONTROL:
4289                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
4290                     (to_vmx(vcpu)->msr_ia32_feature_control &
4291                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
4292                         return 1;
4293                 vmx->msr_ia32_feature_control = data;
4294                 if (msr_info->host_initiated && data == 0)
4295                         vmx_leave_nested(vcpu);
4296                 break;
4297         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4298                 if (!msr_info->host_initiated)
4299                         return 1; /* they are read-only */
4300                 if (!nested_vmx_allowed(vcpu))
4301                         return 1;
4302                 return vmx_set_vmx_msr(vcpu, msr_index, data);
4303         case MSR_IA32_XSS:
4304                 if (!vmx_xsaves_supported())
4305                         return 1;
4306                 /*
4307                  * The only supported bit as of Skylake is bit 8, but
4308                  * it is not supported on KVM.
4309                  */
4310                 if (data != 0)
4311                         return 1;
4312                 vcpu->arch.ia32_xss = data;
4313                 if (vcpu->arch.ia32_xss != host_xss)
4314                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
4315                                 vcpu->arch.ia32_xss, host_xss, false);
4316                 else
4317                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
4318                 break;
4319         case MSR_TSC_AUX:
4320                 if (!msr_info->host_initiated &&
4321                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4322                         return 1;
4323                 /* Check reserved bit, higher 32 bits should be zero */
4324                 if ((data >> 32) != 0)
4325                         return 1;
4326                 /* Otherwise falls through */
4327         default:
4328                 msr = find_msr_entry(vmx, msr_index);
4329                 if (msr) {
4330                         u64 old_msr_data = msr->data;
4331                         msr->data = data;
4332                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4333                                 preempt_disable();
4334                                 ret = kvm_set_shared_msr(msr->index, msr->data,
4335                                                          msr->mask);
4336                                 preempt_enable();
4337                                 if (ret)
4338                                         msr->data = old_msr_data;
4339                         }
4340                         break;
4341                 }
4342                 ret = kvm_set_msr_common(vcpu, msr_info);
4343         }
4344
4345         return ret;
4346 }
4347
4348 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4349 {
4350         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4351         switch (reg) {
4352         case VCPU_REGS_RSP:
4353                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4354                 break;
4355         case VCPU_REGS_RIP:
4356                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4357                 break;
4358         case VCPU_EXREG_PDPTR:
4359                 if (enable_ept)
4360                         ept_save_pdptrs(vcpu);
4361                 break;
4362         default:
4363                 break;
4364         }
4365 }
4366
4367 static __init int cpu_has_kvm_support(void)
4368 {
4369         return cpu_has_vmx();
4370 }
4371
4372 static __init int vmx_disabled_by_bios(void)
4373 {
4374         u64 msr;
4375
4376         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4377         if (msr & FEATURE_CONTROL_LOCKED) {
4378                 /* launched w/ TXT and VMX disabled */
4379                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4380                         && tboot_enabled())
4381                         return 1;
4382                 /* launched w/o TXT and VMX only enabled w/ TXT */
4383                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4384                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4385                         && !tboot_enabled()) {
4386                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4387                                 "activate TXT before enabling KVM\n");
4388                         return 1;
4389                 }
4390                 /* launched w/o TXT and VMX disabled */
4391                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4392                         && !tboot_enabled())
4393                         return 1;
4394         }
4395
4396         return 0;
4397 }
4398
4399 static void kvm_cpu_vmxon(u64 addr)
4400 {
4401         cr4_set_bits(X86_CR4_VMXE);
4402         intel_pt_handle_vmx(1);
4403
4404         asm volatile (ASM_VMX_VMXON_RAX
4405                         : : "a"(&addr), "m"(addr)
4406                         : "memory", "cc");
4407 }
4408
4409 static int hardware_enable(void)
4410 {
4411         int cpu = raw_smp_processor_id();
4412         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4413         u64 old, test_bits;
4414
4415         if (cr4_read_shadow() & X86_CR4_VMXE)
4416                 return -EBUSY;
4417
4418         /*
4419          * This can happen if we hot-added a CPU but failed to allocate
4420          * VP assist page for it.
4421          */
4422         if (static_branch_unlikely(&enable_evmcs) &&
4423             !hv_get_vp_assist_page(cpu))
4424                 return -EFAULT;
4425
4426         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4427         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4428         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4429
4430         /*
4431          * Now we can enable the vmclear operation in kdump
4432          * since the loaded_vmcss_on_cpu list on this cpu
4433          * has been initialized.
4434          *
4435          * Though the cpu is not in VMX operation now, there
4436          * is no problem to enable the vmclear operation
4437          * for the loaded_vmcss_on_cpu list is empty!
4438          */
4439         crash_enable_local_vmclear(cpu);
4440
4441         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4442
4443         test_bits = FEATURE_CONTROL_LOCKED;
4444         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4445         if (tboot_enabled())
4446                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4447
4448         if ((old & test_bits) != test_bits) {
4449                 /* enable and lock */
4450                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4451         }
4452         kvm_cpu_vmxon(phys_addr);
4453         if (enable_ept)
4454                 ept_sync_global();
4455
4456         return 0;
4457 }
4458
4459 static void vmclear_local_loaded_vmcss(void)
4460 {
4461         int cpu = raw_smp_processor_id();
4462         struct loaded_vmcs *v, *n;
4463
4464         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4465                                  loaded_vmcss_on_cpu_link)
4466                 __loaded_vmcs_clear(v);
4467 }
4468
4469
4470 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4471  * tricks.
4472  */
4473 static void kvm_cpu_vmxoff(void)
4474 {
4475         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4476
4477         intel_pt_handle_vmx(0);
4478         cr4_clear_bits(X86_CR4_VMXE);
4479 }
4480
4481 static void hardware_disable(void)
4482 {
4483         vmclear_local_loaded_vmcss();
4484         kvm_cpu_vmxoff();
4485 }
4486
4487 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4488                                       u32 msr, u32 *result)
4489 {
4490         u32 vmx_msr_low, vmx_msr_high;
4491         u32 ctl = ctl_min | ctl_opt;
4492
4493         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4494
4495         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4496         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
4497
4498         /* Ensure minimum (required) set of control bits are supported. */
4499         if (ctl_min & ~ctl)
4500                 return -EIO;
4501
4502         *result = ctl;
4503         return 0;
4504 }
4505
4506 static __init bool allow_1_setting(u32 msr, u32 ctl)
4507 {
4508         u32 vmx_msr_low, vmx_msr_high;
4509
4510         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4511         return vmx_msr_high & ctl;
4512 }
4513
4514 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4515 {
4516         u32 vmx_msr_low, vmx_msr_high;
4517         u32 min, opt, min2, opt2;
4518         u32 _pin_based_exec_control = 0;
4519         u32 _cpu_based_exec_control = 0;
4520         u32 _cpu_based_2nd_exec_control = 0;
4521         u32 _vmexit_control = 0;
4522         u32 _vmentry_control = 0;
4523
4524         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4525         min = CPU_BASED_HLT_EXITING |
4526 #ifdef CONFIG_X86_64
4527               CPU_BASED_CR8_LOAD_EXITING |
4528               CPU_BASED_CR8_STORE_EXITING |
4529 #endif
4530               CPU_BASED_CR3_LOAD_EXITING |
4531               CPU_BASED_CR3_STORE_EXITING |
4532               CPU_BASED_UNCOND_IO_EXITING |
4533               CPU_BASED_MOV_DR_EXITING |
4534               CPU_BASED_USE_TSC_OFFSETING |
4535               CPU_BASED_MWAIT_EXITING |
4536               CPU_BASED_MONITOR_EXITING |
4537               CPU_BASED_INVLPG_EXITING |
4538               CPU_BASED_RDPMC_EXITING;
4539
4540         opt = CPU_BASED_TPR_SHADOW |
4541               CPU_BASED_USE_MSR_BITMAPS |
4542               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4543         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4544                                 &_cpu_based_exec_control) < 0)
4545                 return -EIO;
4546 #ifdef CONFIG_X86_64
4547         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4548                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4549                                            ~CPU_BASED_CR8_STORE_EXITING;
4550 #endif
4551         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4552                 min2 = 0;
4553                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4554                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4555                         SECONDARY_EXEC_WBINVD_EXITING |
4556                         SECONDARY_EXEC_ENABLE_VPID |
4557                         SECONDARY_EXEC_ENABLE_EPT |
4558                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
4559                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4560                         SECONDARY_EXEC_DESC |
4561                         SECONDARY_EXEC_RDTSCP |
4562                         SECONDARY_EXEC_ENABLE_INVPCID |
4563                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4564                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4565                         SECONDARY_EXEC_SHADOW_VMCS |
4566                         SECONDARY_EXEC_XSAVES |
4567                         SECONDARY_EXEC_RDSEED_EXITING |
4568                         SECONDARY_EXEC_RDRAND_EXITING |
4569                         SECONDARY_EXEC_ENABLE_PML |
4570                         SECONDARY_EXEC_TSC_SCALING |
4571                         SECONDARY_EXEC_ENABLE_VMFUNC |
4572                         SECONDARY_EXEC_ENCLS_EXITING;
4573                 if (adjust_vmx_controls(min2, opt2,
4574                                         MSR_IA32_VMX_PROCBASED_CTLS2,
4575                                         &_cpu_based_2nd_exec_control) < 0)
4576                         return -EIO;
4577         }
4578 #ifndef CONFIG_X86_64
4579         if (!(_cpu_based_2nd_exec_control &
4580                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4581                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4582 #endif
4583
4584         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4585                 _cpu_based_2nd_exec_control &= ~(
4586                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4587                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4588                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4589
4590         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4591                 &vmx_capability.ept, &vmx_capability.vpid);
4592
4593         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4594                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4595                    enabled */
4596                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4597                                              CPU_BASED_CR3_STORE_EXITING |
4598                                              CPU_BASED_INVLPG_EXITING);
4599         } else if (vmx_capability.ept) {
4600                 vmx_capability.ept = 0;
4601                 pr_warn_once("EPT CAP should not exist if not support "
4602                                 "1-setting enable EPT VM-execution control\n");
4603         }
4604         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4605                 vmx_capability.vpid) {
4606                 vmx_capability.vpid = 0;
4607                 pr_warn_once("VPID CAP should not exist if not support "
4608                                 "1-setting enable VPID VM-execution control\n");
4609         }
4610
4611         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4612 #ifdef CONFIG_X86_64
4613         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4614 #endif
4615         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4616                 VM_EXIT_CLEAR_BNDCFGS;
4617         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4618                                 &_vmexit_control) < 0)
4619                 return -EIO;
4620
4621         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4622         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4623                  PIN_BASED_VMX_PREEMPTION_TIMER;
4624         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4625                                 &_pin_based_exec_control) < 0)
4626                 return -EIO;
4627
4628         if (cpu_has_broken_vmx_preemption_timer())
4629                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4630         if (!(_cpu_based_2nd_exec_control &
4631                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4632                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4633
4634         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4635         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4636         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4637                                 &_vmentry_control) < 0)
4638                 return -EIO;
4639
4640         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4641
4642         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4643         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4644                 return -EIO;
4645
4646 #ifdef CONFIG_X86_64
4647         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4648         if (vmx_msr_high & (1u<<16))
4649                 return -EIO;
4650 #endif
4651
4652         /* Require Write-Back (WB) memory type for VMCS accesses. */
4653         if (((vmx_msr_high >> 18) & 15) != 6)
4654                 return -EIO;
4655
4656         vmcs_conf->size = vmx_msr_high & 0x1fff;
4657         vmcs_conf->order = get_order(vmcs_conf->size);
4658         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4659
4660         vmcs_conf->revision_id = vmx_msr_low;
4661
4662         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4663         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4664         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4665         vmcs_conf->vmexit_ctrl         = _vmexit_control;
4666         vmcs_conf->vmentry_ctrl        = _vmentry_control;
4667
4668         if (static_branch_unlikely(&enable_evmcs))
4669                 evmcs_sanitize_exec_ctrls(vmcs_conf);
4670
4671         cpu_has_load_ia32_efer =
4672                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4673                                 VM_ENTRY_LOAD_IA32_EFER)
4674                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4675                                    VM_EXIT_LOAD_IA32_EFER);
4676
4677         cpu_has_load_perf_global_ctrl =
4678                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4679                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4680                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4681                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4682
4683         /*
4684          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4685          * but due to errata below it can't be used. Workaround is to use
4686          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4687          *
4688          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4689          *
4690          * AAK155             (model 26)
4691          * AAP115             (model 30)
4692          * AAT100             (model 37)
4693          * BC86,AAY89,BD102   (model 44)
4694          * BA97               (model 46)
4695          *
4696          */
4697         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4698                 switch (boot_cpu_data.x86_model) {
4699                 case 26:
4700                 case 30:
4701                 case 37:
4702                 case 44:
4703                 case 46:
4704                         cpu_has_load_perf_global_ctrl = false;
4705                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4706                                         "does not work properly. Using workaround\n");
4707                         break;
4708                 default:
4709                         break;
4710                 }
4711         }
4712
4713         if (boot_cpu_has(X86_FEATURE_XSAVES))
4714                 rdmsrl(MSR_IA32_XSS, host_xss);
4715
4716         return 0;
4717 }
4718
4719 static struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu)
4720 {
4721         int node = cpu_to_node(cpu);
4722         struct page *pages;
4723         struct vmcs *vmcs;
4724
4725         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4726         if (!pages)
4727                 return NULL;
4728         vmcs = page_address(pages);
4729         memset(vmcs, 0, vmcs_config.size);
4730
4731         /* KVM supports Enlightened VMCS v1 only */
4732         if (static_branch_unlikely(&enable_evmcs))
4733                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
4734         else
4735                 vmcs->hdr.revision_id = vmcs_config.revision_id;
4736
4737         if (shadow)
4738                 vmcs->hdr.shadow_vmcs = 1;
4739         return vmcs;
4740 }
4741
4742 static void free_vmcs(struct vmcs *vmcs)
4743 {
4744         free_pages((unsigned long)vmcs, vmcs_config.order);
4745 }
4746
4747 /*
4748  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4749  */
4750 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4751 {
4752         if (!loaded_vmcs->vmcs)
4753                 return;
4754         loaded_vmcs_clear(loaded_vmcs);
4755         free_vmcs(loaded_vmcs->vmcs);
4756         loaded_vmcs->vmcs = NULL;
4757         if (loaded_vmcs->msr_bitmap)
4758                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4759         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4760 }
4761
4762 static struct vmcs *alloc_vmcs(bool shadow)
4763 {
4764         return alloc_vmcs_cpu(shadow, raw_smp_processor_id());
4765 }
4766
4767 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4768 {
4769         loaded_vmcs->vmcs = alloc_vmcs(false);
4770         if (!loaded_vmcs->vmcs)
4771                 return -ENOMEM;
4772
4773         loaded_vmcs->shadow_vmcs = NULL;
4774         loaded_vmcs_init(loaded_vmcs);
4775
4776         if (cpu_has_vmx_msr_bitmap()) {
4777                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4778                 if (!loaded_vmcs->msr_bitmap)
4779                         goto out_vmcs;
4780                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4781
4782                 if (IS_ENABLED(CONFIG_HYPERV) &&
4783                     static_branch_unlikely(&enable_evmcs) &&
4784                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4785                         struct hv_enlightened_vmcs *evmcs =
4786                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4787
4788                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
4789                 }
4790         }
4791
4792         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
4793
4794         return 0;
4795
4796 out_vmcs:
4797         free_loaded_vmcs(loaded_vmcs);
4798         return -ENOMEM;
4799 }
4800
4801 static void free_kvm_area(void)
4802 {
4803         int cpu;
4804
4805         for_each_possible_cpu(cpu) {
4806                 free_vmcs(per_cpu(vmxarea, cpu));
4807                 per_cpu(vmxarea, cpu) = NULL;
4808         }
4809 }
4810
4811 enum vmcs_field_width {
4812         VMCS_FIELD_WIDTH_U16 = 0,
4813         VMCS_FIELD_WIDTH_U64 = 1,
4814         VMCS_FIELD_WIDTH_U32 = 2,
4815         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4816 };
4817
4818 static inline int vmcs_field_width(unsigned long field)
4819 {
4820         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4821                 return VMCS_FIELD_WIDTH_U32;
4822         return (field >> 13) & 0x3 ;
4823 }
4824
4825 static inline int vmcs_field_readonly(unsigned long field)
4826 {
4827         return (((field >> 10) & 0x3) == 1);
4828 }
4829
4830 static void init_vmcs_shadow_fields(void)
4831 {
4832         int i, j;
4833
4834         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4835                 u16 field = shadow_read_only_fields[i];
4836                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4837                     (i + 1 == max_shadow_read_only_fields ||
4838                      shadow_read_only_fields[i + 1] != field + 1))
4839                         pr_err("Missing field from shadow_read_only_field %x\n",
4840                                field + 1);
4841
4842                 clear_bit(field, vmx_vmread_bitmap);
4843 #ifdef CONFIG_X86_64
4844                 if (field & 1)
4845                         continue;
4846 #endif
4847                 if (j < i)
4848                         shadow_read_only_fields[j] = field;
4849                 j++;
4850         }
4851         max_shadow_read_only_fields = j;
4852
4853         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4854                 u16 field = shadow_read_write_fields[i];
4855                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4856                     (i + 1 == max_shadow_read_write_fields ||
4857                      shadow_read_write_fields[i + 1] != field + 1))
4858                         pr_err("Missing field from shadow_read_write_field %x\n",
4859                                field + 1);
4860
4861                 /*
4862                  * PML and the preemption timer can be emulated, but the
4863                  * processor cannot vmwrite to fields that don't exist
4864                  * on bare metal.
4865                  */
4866                 switch (field) {
4867                 case GUEST_PML_INDEX:
4868                         if (!cpu_has_vmx_pml())
4869                                 continue;
4870                         break;
4871                 case VMX_PREEMPTION_TIMER_VALUE:
4872                         if (!cpu_has_vmx_preemption_timer())
4873                                 continue;
4874                         break;
4875                 case GUEST_INTR_STATUS:
4876                         if (!cpu_has_vmx_apicv())
4877                                 continue;
4878                         break;
4879                 default:
4880                         break;
4881                 }
4882
4883                 clear_bit(field, vmx_vmwrite_bitmap);
4884                 clear_bit(field, vmx_vmread_bitmap);
4885 #ifdef CONFIG_X86_64
4886                 if (field & 1)
4887                         continue;
4888 #endif
4889                 if (j < i)
4890                         shadow_read_write_fields[j] = field;
4891                 j++;
4892         }
4893         max_shadow_read_write_fields = j;
4894 }
4895
4896 static __init int alloc_kvm_area(void)
4897 {
4898         int cpu;
4899
4900         for_each_possible_cpu(cpu) {
4901                 struct vmcs *vmcs;
4902
4903                 vmcs = alloc_vmcs_cpu(false, cpu);
4904                 if (!vmcs) {
4905                         free_kvm_area();
4906                         return -ENOMEM;
4907                 }
4908
4909                 /*
4910                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
4911                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
4912                  * revision_id reported by MSR_IA32_VMX_BASIC.
4913                  *
4914                  * However, even though not explictly documented by
4915                  * TLFS, VMXArea passed as VMXON argument should
4916                  * still be marked with revision_id reported by
4917                  * physical CPU.
4918                  */
4919                 if (static_branch_unlikely(&enable_evmcs))
4920                         vmcs->hdr.revision_id = vmcs_config.revision_id;
4921
4922                 per_cpu(vmxarea, cpu) = vmcs;
4923         }
4924         return 0;
4925 }
4926
4927 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4928                 struct kvm_segment *save)
4929 {
4930         if (!emulate_invalid_guest_state) {
4931                 /*
4932                  * CS and SS RPL should be equal during guest entry according
4933                  * to VMX spec, but in reality it is not always so. Since vcpu
4934                  * is in the middle of the transition from real mode to
4935                  * protected mode it is safe to assume that RPL 0 is a good
4936                  * default value.
4937                  */
4938                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4939                         save->selector &= ~SEGMENT_RPL_MASK;
4940                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4941                 save->s = 1;
4942         }
4943         vmx_set_segment(vcpu, save, seg);
4944 }
4945
4946 static void enter_pmode(struct kvm_vcpu *vcpu)
4947 {
4948         unsigned long flags;
4949         struct vcpu_vmx *vmx = to_vmx(vcpu);
4950
4951         /*
4952          * Update real mode segment cache. It may be not up-to-date if sement
4953          * register was written while vcpu was in a guest mode.
4954          */
4955         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4956         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4957         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4958         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4959         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4960         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4961
4962         vmx->rmode.vm86_active = 0;
4963
4964         vmx_segment_cache_clear(vmx);
4965
4966         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4967
4968         flags = vmcs_readl(GUEST_RFLAGS);
4969         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4970         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4971         vmcs_writel(GUEST_RFLAGS, flags);
4972
4973         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4974                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4975
4976         update_exception_bitmap(vcpu);
4977
4978         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4979         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4980         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4981         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4982         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4983         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4984 }
4985
4986 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4987 {
4988         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4989         struct kvm_segment var = *save;
4990
4991         var.dpl = 0x3;
4992         if (seg == VCPU_SREG_CS)
4993                 var.type = 0x3;
4994
4995         if (!emulate_invalid_guest_state) {
4996                 var.selector = var.base >> 4;
4997                 var.base = var.base & 0xffff0;
4998                 var.limit = 0xffff;
4999                 var.g = 0;
5000                 var.db = 0;
5001                 var.present = 1;
5002                 var.s = 1;
5003                 var.l = 0;
5004                 var.unusable = 0;
5005                 var.type = 0x3;
5006                 var.avl = 0;
5007                 if (save->base & 0xf)
5008                         printk_once(KERN_WARNING "kvm: segment base is not "
5009                                         "paragraph aligned when entering "
5010                                         "protected mode (seg=%d)", seg);
5011         }
5012
5013         vmcs_write16(sf->selector, var.selector);
5014         vmcs_writel(sf->base, var.base);
5015         vmcs_write32(sf->limit, var.limit);
5016         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
5017 }
5018
5019 static void enter_rmode(struct kvm_vcpu *vcpu)
5020 {
5021         unsigned long flags;
5022         struct vcpu_vmx *vmx = to_vmx(vcpu);
5023         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
5024
5025         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
5026         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
5027         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
5028         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
5029         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
5030         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
5031         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
5032
5033         vmx->rmode.vm86_active = 1;
5034
5035         /*
5036          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
5037          * vcpu. Warn the user that an update is overdue.
5038          */
5039         if (!kvm_vmx->tss_addr)
5040                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
5041                              "called before entering vcpu\n");
5042
5043         vmx_segment_cache_clear(vmx);
5044
5045         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
5046         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
5047         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5048
5049         flags = vmcs_readl(GUEST_RFLAGS);
5050         vmx->rmode.save_rflags = flags;
5051
5052         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
5053
5054         vmcs_writel(GUEST_RFLAGS, flags);
5055         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
5056         update_exception_bitmap(vcpu);
5057
5058         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
5059         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
5060         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
5061         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
5062         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
5063         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
5064
5065         kvm_mmu_reset_context(vcpu);
5066 }
5067
5068 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
5069 {
5070         struct vcpu_vmx *vmx = to_vmx(vcpu);
5071         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
5072
5073         if (!msr)
5074                 return;
5075
5076         /*
5077          * MSR_KERNEL_GS_BASE is not intercepted when the guest is in
5078          * 64-bit mode as a 64-bit kernel may frequently access the
5079          * MSR.  This means we need to manually save/restore the MSR
5080          * when switching between guest and host state, but only if
5081          * the guest is in 64-bit mode.  Sync our cached value if the
5082          * guest is transitioning to 32-bit mode and the CPU contains
5083          * guest state, i.e. the cache is stale.
5084          */
5085 #ifdef CONFIG_X86_64
5086         if (!(efer & EFER_LMA))
5087                 (void)vmx_read_guest_kernel_gs_base(vmx);
5088 #endif
5089         vcpu->arch.efer = efer;
5090         if (efer & EFER_LMA) {
5091                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5092                 msr->data = efer;
5093         } else {
5094                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5095
5096                 msr->data = efer & ~EFER_LME;
5097         }
5098         setup_msrs(vmx);
5099 }
5100
5101 #ifdef CONFIG_X86_64
5102
5103 static void enter_lmode(struct kvm_vcpu *vcpu)
5104 {
5105         u32 guest_tr_ar;
5106
5107         vmx_segment_cache_clear(to_vmx(vcpu));
5108
5109         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
5110         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
5111                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
5112                                      __func__);
5113                 vmcs_write32(GUEST_TR_AR_BYTES,
5114                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
5115                              | VMX_AR_TYPE_BUSY_64_TSS);
5116         }
5117         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
5118 }
5119
5120 static void exit_lmode(struct kvm_vcpu *vcpu)
5121 {
5122         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5123         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
5124 }
5125
5126 #endif
5127
5128 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
5129                                 bool invalidate_gpa)
5130 {
5131         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
5132                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
5133                         return;
5134                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
5135         } else {
5136                 vpid_sync_context(vpid);
5137         }
5138 }
5139
5140 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5141 {
5142         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
5143 }
5144
5145 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
5146 {
5147         int vpid = to_vmx(vcpu)->vpid;
5148
5149         if (!vpid_sync_vcpu_addr(vpid, addr))
5150                 vpid_sync_context(vpid);
5151
5152         /*
5153          * If VPIDs are not supported or enabled, then the above is a no-op.
5154          * But we don't really need a TLB flush in that case anyway, because
5155          * each VM entry/exit includes an implicit flush when VPID is 0.
5156          */
5157 }
5158
5159 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
5160 {
5161         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
5162
5163         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
5164         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
5165 }
5166
5167 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
5168 {
5169         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
5170                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
5171         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5172 }
5173
5174 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
5175 {
5176         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
5177
5178         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
5179         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
5180 }
5181
5182 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
5183 {
5184         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5185
5186         if (!test_bit(VCPU_EXREG_PDPTR,
5187                       (unsigned long *)&vcpu->arch.regs_dirty))
5188                 return;
5189
5190         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5191                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
5192                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
5193                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
5194                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
5195         }
5196 }
5197
5198 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
5199 {
5200         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5201
5202         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5203                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
5204                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
5205                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
5206                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
5207         }
5208
5209         __set_bit(VCPU_EXREG_PDPTR,
5210                   (unsigned long *)&vcpu->arch.regs_avail);
5211         __set_bit(VCPU_EXREG_PDPTR,
5212                   (unsigned long *)&vcpu->arch.regs_dirty);
5213 }
5214
5215 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5216 {
5217         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5218         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5219         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5220
5221         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
5222                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5223             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5224                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5225
5226         return fixed_bits_valid(val, fixed0, fixed1);
5227 }
5228
5229 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5230 {
5231         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5232         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5233
5234         return fixed_bits_valid(val, fixed0, fixed1);
5235 }
5236
5237 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
5238 {
5239         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
5240         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
5241
5242         return fixed_bits_valid(val, fixed0, fixed1);
5243 }
5244
5245 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
5246 #define nested_guest_cr4_valid  nested_cr4_valid
5247 #define nested_host_cr4_valid   nested_cr4_valid
5248
5249 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
5250
5251 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
5252                                         unsigned long cr0,
5253                                         struct kvm_vcpu *vcpu)
5254 {
5255         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
5256                 vmx_decache_cr3(vcpu);
5257         if (!(cr0 & X86_CR0_PG)) {
5258                 /* From paging/starting to nonpaging */
5259                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5260                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
5261                              (CPU_BASED_CR3_LOAD_EXITING |
5262                               CPU_BASED_CR3_STORE_EXITING));
5263                 vcpu->arch.cr0 = cr0;
5264                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5265         } else if (!is_paging(vcpu)) {
5266                 /* From nonpaging to paging */
5267                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5268                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
5269                              ~(CPU_BASED_CR3_LOAD_EXITING |
5270                                CPU_BASED_CR3_STORE_EXITING));
5271                 vcpu->arch.cr0 = cr0;
5272                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5273         }
5274
5275         if (!(cr0 & X86_CR0_WP))
5276                 *hw_cr0 &= ~X86_CR0_WP;
5277 }
5278
5279 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
5280 {
5281         struct vcpu_vmx *vmx = to_vmx(vcpu);
5282         unsigned long hw_cr0;
5283
5284         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
5285         if (enable_unrestricted_guest)
5286                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
5287         else {
5288                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
5289
5290                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
5291                         enter_pmode(vcpu);
5292
5293                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
5294                         enter_rmode(vcpu);
5295         }
5296
5297 #ifdef CONFIG_X86_64
5298         if (vcpu->arch.efer & EFER_LME) {
5299                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
5300                         enter_lmode(vcpu);
5301                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
5302                         exit_lmode(vcpu);
5303         }
5304 #endif
5305
5306         if (enable_ept && !enable_unrestricted_guest)
5307                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
5308
5309         vmcs_writel(CR0_READ_SHADOW, cr0);
5310         vmcs_writel(GUEST_CR0, hw_cr0);
5311         vcpu->arch.cr0 = cr0;
5312
5313         /* depends on vcpu->arch.cr0 to be set to a new value */
5314         vmx->emulation_required = emulation_required(vcpu);
5315 }
5316
5317 static int get_ept_level(struct kvm_vcpu *vcpu)
5318 {
5319         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
5320                 return 5;
5321         return 4;
5322 }
5323
5324 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
5325 {
5326         u64 eptp = VMX_EPTP_MT_WB;
5327
5328         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
5329
5330         if (enable_ept_ad_bits &&
5331             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
5332                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
5333         eptp |= (root_hpa & PAGE_MASK);
5334
5335         return eptp;
5336 }
5337
5338 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
5339 {
5340         struct kvm *kvm = vcpu->kvm;
5341         unsigned long guest_cr3;
5342         u64 eptp;
5343
5344         guest_cr3 = cr3;
5345         if (enable_ept) {
5346                 eptp = construct_eptp(vcpu, cr3);
5347                 vmcs_write64(EPT_POINTER, eptp);
5348
5349                 if (kvm_x86_ops->tlb_remote_flush) {
5350                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5351                         to_vmx(vcpu)->ept_pointer = eptp;
5352                         to_kvm_vmx(kvm)->ept_pointers_match
5353                                 = EPT_POINTERS_CHECK;
5354                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5355                 }
5356
5357                 if (enable_unrestricted_guest || is_paging(vcpu) ||
5358                     is_guest_mode(vcpu))
5359                         guest_cr3 = kvm_read_cr3(vcpu);
5360                 else
5361                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
5362                 ept_load_pdptrs(vcpu);
5363         }
5364
5365         vmcs_writel(GUEST_CR3, guest_cr3);
5366 }
5367
5368 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
5369 {
5370         /*
5371          * Pass through host's Machine Check Enable value to hw_cr4, which
5372          * is in force while we are in guest mode.  Do not let guests control
5373          * this bit, even if host CR4.MCE == 0.
5374          */
5375         unsigned long hw_cr4;
5376
5377         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
5378         if (enable_unrestricted_guest)
5379                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
5380         else if (to_vmx(vcpu)->rmode.vm86_active)
5381                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
5382         else
5383                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
5384
5385         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5386                 if (cr4 & X86_CR4_UMIP) {
5387                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5388                                 SECONDARY_EXEC_DESC);
5389                         hw_cr4 &= ~X86_CR4_UMIP;
5390                 } else if (!is_guest_mode(vcpu) ||
5391                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5392                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5393                                         SECONDARY_EXEC_DESC);
5394         }
5395
5396         if (cr4 & X86_CR4_VMXE) {
5397                 /*
5398                  * To use VMXON (and later other VMX instructions), a guest
5399                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
5400                  * So basically the check on whether to allow nested VMX
5401                  * is here.  We operate under the default treatment of SMM,
5402                  * so VMX cannot be enabled under SMM.
5403                  */
5404                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5405                         return 1;
5406         }
5407
5408         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5409                 return 1;
5410
5411         vcpu->arch.cr4 = cr4;
5412
5413         if (!enable_unrestricted_guest) {
5414                 if (enable_ept) {
5415                         if (!is_paging(vcpu)) {
5416                                 hw_cr4 &= ~X86_CR4_PAE;
5417                                 hw_cr4 |= X86_CR4_PSE;
5418                         } else if (!(cr4 & X86_CR4_PAE)) {
5419                                 hw_cr4 &= ~X86_CR4_PAE;
5420                         }
5421                 }
5422
5423                 /*
5424                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5425                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
5426                  * to be manually disabled when guest switches to non-paging
5427                  * mode.
5428                  *
5429                  * If !enable_unrestricted_guest, the CPU is always running
5430                  * with CR0.PG=1 and CR4 needs to be modified.
5431                  * If enable_unrestricted_guest, the CPU automatically
5432                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5433                  */
5434                 if (!is_paging(vcpu))
5435                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5436         }
5437
5438         vmcs_writel(CR4_READ_SHADOW, cr4);
5439         vmcs_writel(GUEST_CR4, hw_cr4);
5440         return 0;
5441 }
5442
5443 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5444                             struct kvm_segment *var, int seg)
5445 {
5446         struct vcpu_vmx *vmx = to_vmx(vcpu);
5447         u32 ar;
5448
5449         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5450                 *var = vmx->rmode.segs[seg];
5451                 if (seg == VCPU_SREG_TR
5452                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5453                         return;
5454                 var->base = vmx_read_guest_seg_base(vmx, seg);
5455                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5456                 return;
5457         }
5458         var->base = vmx_read_guest_seg_base(vmx, seg);
5459         var->limit = vmx_read_guest_seg_limit(vmx, seg);
5460         var->selector = vmx_read_guest_seg_selector(vmx, seg);
5461         ar = vmx_read_guest_seg_ar(vmx, seg);
5462         var->unusable = (ar >> 16) & 1;
5463         var->type = ar & 15;
5464         var->s = (ar >> 4) & 1;
5465         var->dpl = (ar >> 5) & 3;
5466         /*
5467          * Some userspaces do not preserve unusable property. Since usable
5468          * segment has to be present according to VMX spec we can use present
5469          * property to amend userspace bug by making unusable segment always
5470          * nonpresent. vmx_segment_access_rights() already marks nonpresent
5471          * segment as unusable.
5472          */
5473         var->present = !var->unusable;
5474         var->avl = (ar >> 12) & 1;
5475         var->l = (ar >> 13) & 1;
5476         var->db = (ar >> 14) & 1;
5477         var->g = (ar >> 15) & 1;
5478 }
5479
5480 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5481 {
5482         struct kvm_segment s;
5483
5484         if (to_vmx(vcpu)->rmode.vm86_active) {
5485                 vmx_get_segment(vcpu, &s, seg);
5486                 return s.base;
5487         }
5488         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5489 }
5490
5491 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5492 {
5493         struct vcpu_vmx *vmx = to_vmx(vcpu);
5494
5495         if (unlikely(vmx->rmode.vm86_active))
5496                 return 0;
5497         else {
5498                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5499                 return VMX_AR_DPL(ar);
5500         }
5501 }
5502
5503 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5504 {
5505         u32 ar;
5506
5507         if (var->unusable || !var->present)
5508                 ar = 1 << 16;
5509         else {
5510                 ar = var->type & 15;
5511                 ar |= (var->s & 1) << 4;
5512                 ar |= (var->dpl & 3) << 5;
5513                 ar |= (var->present & 1) << 7;
5514                 ar |= (var->avl & 1) << 12;
5515                 ar |= (var->l & 1) << 13;
5516                 ar |= (var->db & 1) << 14;
5517                 ar |= (var->g & 1) << 15;
5518         }
5519
5520         return ar;
5521 }
5522
5523 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5524                             struct kvm_segment *var, int seg)
5525 {
5526         struct vcpu_vmx *vmx = to_vmx(vcpu);
5527         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5528
5529         vmx_segment_cache_clear(vmx);
5530
5531         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5532                 vmx->rmode.segs[seg] = *var;
5533                 if (seg == VCPU_SREG_TR)
5534                         vmcs_write16(sf->selector, var->selector);
5535                 else if (var->s)
5536                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5537                 goto out;
5538         }
5539
5540         vmcs_writel(sf->base, var->base);
5541         vmcs_write32(sf->limit, var->limit);
5542         vmcs_write16(sf->selector, var->selector);
5543
5544         /*
5545          *   Fix the "Accessed" bit in AR field of segment registers for older
5546          * qemu binaries.
5547          *   IA32 arch specifies that at the time of processor reset the
5548          * "Accessed" bit in the AR field of segment registers is 1. And qemu
5549          * is setting it to 0 in the userland code. This causes invalid guest
5550          * state vmexit when "unrestricted guest" mode is turned on.
5551          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
5552          * tree. Newer qemu binaries with that qemu fix would not need this
5553          * kvm hack.
5554          */
5555         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5556                 var->type |= 0x1; /* Accessed */
5557
5558         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5559
5560 out:
5561         vmx->emulation_required = emulation_required(vcpu);
5562 }
5563
5564 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5565 {
5566         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5567
5568         *db = (ar >> 14) & 1;
5569         *l = (ar >> 13) & 1;
5570 }
5571
5572 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5573 {
5574         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5575         dt->address = vmcs_readl(GUEST_IDTR_BASE);
5576 }
5577
5578 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5579 {
5580         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5581         vmcs_writel(GUEST_IDTR_BASE, dt->address);
5582 }
5583
5584 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5585 {
5586         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5587         dt->address = vmcs_readl(GUEST_GDTR_BASE);
5588 }
5589
5590 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5591 {
5592         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5593         vmcs_writel(GUEST_GDTR_BASE, dt->address);
5594 }
5595
5596 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5597 {
5598         struct kvm_segment var;
5599         u32 ar;
5600
5601         vmx_get_segment(vcpu, &var, seg);
5602         var.dpl = 0x3;
5603         if (seg == VCPU_SREG_CS)
5604                 var.type = 0x3;
5605         ar = vmx_segment_access_rights(&var);
5606
5607         if (var.base != (var.selector << 4))
5608                 return false;
5609         if (var.limit != 0xffff)
5610                 return false;
5611         if (ar != 0xf3)
5612                 return false;
5613
5614         return true;
5615 }
5616
5617 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5618 {
5619         struct kvm_segment cs;
5620         unsigned int cs_rpl;
5621
5622         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5623         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5624
5625         if (cs.unusable)
5626                 return false;
5627         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5628                 return false;
5629         if (!cs.s)
5630                 return false;
5631         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5632                 if (cs.dpl > cs_rpl)
5633                         return false;
5634         } else {
5635                 if (cs.dpl != cs_rpl)
5636                         return false;
5637         }
5638         if (!cs.present)
5639                 return false;
5640
5641         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5642         return true;
5643 }
5644
5645 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5646 {
5647         struct kvm_segment ss;
5648         unsigned int ss_rpl;
5649
5650         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5651         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5652
5653         if (ss.unusable)
5654                 return true;
5655         if (ss.type != 3 && ss.type != 7)
5656                 return false;
5657         if (!ss.s)
5658                 return false;
5659         if (ss.dpl != ss_rpl) /* DPL != RPL */
5660                 return false;
5661         if (!ss.present)
5662                 return false;
5663
5664         return true;
5665 }
5666
5667 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5668 {
5669         struct kvm_segment var;
5670         unsigned int rpl;
5671
5672         vmx_get_segment(vcpu, &var, seg);
5673         rpl = var.selector & SEGMENT_RPL_MASK;
5674
5675         if (var.unusable)
5676                 return true;
5677         if (!var.s)
5678                 return false;
5679         if (!var.present)
5680                 return false;
5681         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5682                 if (var.dpl < rpl) /* DPL < RPL */
5683                         return false;
5684         }
5685
5686         /* TODO: Add other members to kvm_segment_field to allow checking for other access
5687          * rights flags
5688          */
5689         return true;
5690 }
5691
5692 static bool tr_valid(struct kvm_vcpu *vcpu)
5693 {
5694         struct kvm_segment tr;
5695
5696         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5697
5698         if (tr.unusable)
5699                 return false;
5700         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
5701                 return false;
5702         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5703                 return false;
5704         if (!tr.present)
5705                 return false;
5706
5707         return true;
5708 }
5709
5710 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5711 {
5712         struct kvm_segment ldtr;
5713
5714         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5715
5716         if (ldtr.unusable)
5717                 return true;
5718         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
5719                 return false;
5720         if (ldtr.type != 2)
5721                 return false;
5722         if (!ldtr.present)
5723                 return false;
5724
5725         return true;
5726 }
5727
5728 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5729 {
5730         struct kvm_segment cs, ss;
5731
5732         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5733         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5734
5735         return ((cs.selector & SEGMENT_RPL_MASK) ==
5736                  (ss.selector & SEGMENT_RPL_MASK));
5737 }
5738
5739 /*
5740  * Check if guest state is valid. Returns true if valid, false if
5741  * not.
5742  * We assume that registers are always usable
5743  */
5744 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5745 {
5746         if (enable_unrestricted_guest)
5747                 return true;
5748
5749         /* real mode guest state checks */
5750         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5751                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5752                         return false;
5753                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5754                         return false;
5755                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5756                         return false;
5757                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5758                         return false;
5759                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5760                         return false;
5761                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5762                         return false;
5763         } else {
5764         /* protected mode guest state checks */
5765                 if (!cs_ss_rpl_check(vcpu))
5766                         return false;
5767                 if (!code_segment_valid(vcpu))
5768                         return false;
5769                 if (!stack_segment_valid(vcpu))
5770                         return false;
5771                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5772                         return false;
5773                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5774                         return false;
5775                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5776                         return false;
5777                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5778                         return false;
5779                 if (!tr_valid(vcpu))
5780                         return false;
5781                 if (!ldtr_valid(vcpu))
5782                         return false;
5783         }
5784         /* TODO:
5785          * - Add checks on RIP
5786          * - Add checks on RFLAGS
5787          */
5788
5789         return true;
5790 }
5791
5792 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5793 {
5794         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5795 }
5796
5797 static int init_rmode_tss(struct kvm *kvm)
5798 {
5799         gfn_t fn;
5800         u16 data = 0;
5801         int idx, r;
5802
5803         idx = srcu_read_lock(&kvm->srcu);
5804         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5805         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5806         if (r < 0)
5807                 goto out;
5808         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5809         r = kvm_write_guest_page(kvm, fn++, &data,
5810                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
5811         if (r < 0)
5812                 goto out;
5813         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5814         if (r < 0)
5815                 goto out;
5816         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5817         if (r < 0)
5818                 goto out;
5819         data = ~0;
5820         r = kvm_write_guest_page(kvm, fn, &data,
5821                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5822                                  sizeof(u8));
5823 out:
5824         srcu_read_unlock(&kvm->srcu, idx);
5825         return r;
5826 }
5827
5828 static int init_rmode_identity_map(struct kvm *kvm)
5829 {
5830         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5831         int i, idx, r = 0;
5832         kvm_pfn_t identity_map_pfn;
5833         u32 tmp;
5834
5835         /* Protect kvm_vmx->ept_identity_pagetable_done. */
5836         mutex_lock(&kvm->slots_lock);
5837
5838         if (likely(kvm_vmx->ept_identity_pagetable_done))
5839                 goto out2;
5840
5841         if (!kvm_vmx->ept_identity_map_addr)
5842                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5843         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5844
5845         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5846                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5847         if (r < 0)
5848                 goto out2;
5849
5850         idx = srcu_read_lock(&kvm->srcu);
5851         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5852         if (r < 0)
5853                 goto out;
5854         /* Set up identity-mapping pagetable for EPT in real mode */
5855         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5856                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5857                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5858                 r = kvm_write_guest_page(kvm, identity_map_pfn,
5859                                 &tmp, i * sizeof(tmp), sizeof(tmp));
5860                 if (r < 0)
5861                         goto out;
5862         }
5863         kvm_vmx->ept_identity_pagetable_done = true;
5864
5865 out:
5866         srcu_read_unlock(&kvm->srcu, idx);
5867
5868 out2:
5869         mutex_unlock(&kvm->slots_lock);
5870         return r;
5871 }
5872
5873 static void seg_setup(int seg)
5874 {
5875         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5876         unsigned int ar;
5877
5878         vmcs_write16(sf->selector, 0);
5879         vmcs_writel(sf->base, 0);
5880         vmcs_write32(sf->limit, 0xffff);
5881         ar = 0x93;
5882         if (seg == VCPU_SREG_CS)
5883                 ar |= 0x08; /* code segment */
5884
5885         vmcs_write32(sf->ar_bytes, ar);
5886 }
5887
5888 static int alloc_apic_access_page(struct kvm *kvm)
5889 {
5890         struct page *page;
5891         int r = 0;
5892
5893         mutex_lock(&kvm->slots_lock);
5894         if (kvm->arch.apic_access_page_done)
5895                 goto out;
5896         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5897                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5898         if (r)
5899                 goto out;
5900
5901         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5902         if (is_error_page(page)) {
5903                 r = -EFAULT;
5904                 goto out;
5905         }
5906
5907         /*
5908          * Do not pin the page in memory, so that memory hot-unplug
5909          * is able to migrate it.
5910          */
5911         put_page(page);
5912         kvm->arch.apic_access_page_done = true;
5913 out:
5914         mutex_unlock(&kvm->slots_lock);
5915         return r;
5916 }
5917
5918 static int allocate_vpid(void)
5919 {
5920         int vpid;
5921
5922         if (!enable_vpid)
5923                 return 0;
5924         spin_lock(&vmx_vpid_lock);
5925         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5926         if (vpid < VMX_NR_VPIDS)
5927                 __set_bit(vpid, vmx_vpid_bitmap);
5928         else
5929                 vpid = 0;
5930         spin_unlock(&vmx_vpid_lock);
5931         return vpid;
5932 }
5933
5934 static void free_vpid(int vpid)
5935 {
5936         if (!enable_vpid || vpid == 0)
5937                 return;
5938         spin_lock(&vmx_vpid_lock);
5939         __clear_bit(vpid, vmx_vpid_bitmap);
5940         spin_unlock(&vmx_vpid_lock);
5941 }
5942
5943 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5944                                                           u32 msr, int type)
5945 {
5946         int f = sizeof(unsigned long);
5947
5948         if (!cpu_has_vmx_msr_bitmap())
5949                 return;
5950
5951         if (static_branch_unlikely(&enable_evmcs))
5952                 evmcs_touch_msr_bitmap();
5953
5954         /*
5955          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5956          * have the write-low and read-high bitmap offsets the wrong way round.
5957          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5958          */
5959         if (msr <= 0x1fff) {
5960                 if (type & MSR_TYPE_R)
5961                         /* read-low */
5962                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5963
5964                 if (type & MSR_TYPE_W)
5965                         /* write-low */
5966                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5967
5968         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5969                 msr &= 0x1fff;
5970                 if (type & MSR_TYPE_R)
5971                         /* read-high */
5972                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5973
5974                 if (type & MSR_TYPE_W)
5975                         /* write-high */
5976                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5977
5978         }
5979 }
5980
5981 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5982                                                          u32 msr, int type)
5983 {
5984         int f = sizeof(unsigned long);
5985
5986         if (!cpu_has_vmx_msr_bitmap())
5987                 return;
5988
5989         if (static_branch_unlikely(&enable_evmcs))
5990                 evmcs_touch_msr_bitmap();
5991
5992         /*
5993          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5994          * have the write-low and read-high bitmap offsets the wrong way round.
5995          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5996          */
5997         if (msr <= 0x1fff) {
5998                 if (type & MSR_TYPE_R)
5999                         /* read-low */
6000                         __set_bit(msr, msr_bitmap + 0x000 / f);
6001
6002                 if (type & MSR_TYPE_W)
6003                         /* write-low */
6004                         __set_bit(msr, msr_bitmap + 0x800 / f);
6005
6006         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
6007                 msr &= 0x1fff;
6008                 if (type & MSR_TYPE_R)
6009                         /* read-high */
6010                         __set_bit(msr, msr_bitmap + 0x400 / f);
6011
6012                 if (type & MSR_TYPE_W)
6013                         /* write-high */
6014                         __set_bit(msr, msr_bitmap + 0xc00 / f);
6015
6016         }
6017 }
6018
6019 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
6020                                                       u32 msr, int type, bool value)
6021 {
6022         if (value)
6023                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
6024         else
6025                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
6026 }
6027
6028 /*
6029  * If a msr is allowed by L0, we should check whether it is allowed by L1.
6030  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
6031  */
6032 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
6033                                                unsigned long *msr_bitmap_nested,
6034                                                u32 msr, int type)
6035 {
6036         int f = sizeof(unsigned long);
6037
6038         /*
6039          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
6040          * have the write-low and read-high bitmap offsets the wrong way round.
6041          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
6042          */
6043         if (msr <= 0x1fff) {
6044                 if (type & MSR_TYPE_R &&
6045                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
6046                         /* read-low */
6047                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
6048
6049                 if (type & MSR_TYPE_W &&
6050                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
6051                         /* write-low */
6052                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
6053
6054         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
6055                 msr &= 0x1fff;
6056                 if (type & MSR_TYPE_R &&
6057                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
6058                         /* read-high */
6059                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
6060
6061                 if (type & MSR_TYPE_W &&
6062                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
6063                         /* write-high */
6064                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
6065
6066         }
6067 }
6068
6069 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
6070 {
6071         u8 mode = 0;
6072
6073         if (cpu_has_secondary_exec_ctrls() &&
6074             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
6075              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
6076                 mode |= MSR_BITMAP_MODE_X2APIC;
6077                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
6078                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
6079         }
6080
6081         if (is_long_mode(vcpu))
6082                 mode |= MSR_BITMAP_MODE_LM;
6083
6084         return mode;
6085 }
6086
6087 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
6088
6089 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
6090                                          u8 mode)
6091 {
6092         int msr;
6093
6094         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
6095                 unsigned word = msr / BITS_PER_LONG;
6096                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
6097                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
6098         }
6099
6100         if (mode & MSR_BITMAP_MODE_X2APIC) {
6101                 /*
6102                  * TPR reads and writes can be virtualized even if virtual interrupt
6103                  * delivery is not in use.
6104                  */
6105                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
6106                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
6107                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
6108                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
6109                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
6110                 }
6111         }
6112 }
6113
6114 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
6115 {
6116         struct vcpu_vmx *vmx = to_vmx(vcpu);
6117         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
6118         u8 mode = vmx_msr_bitmap_mode(vcpu);
6119         u8 changed = mode ^ vmx->msr_bitmap_mode;
6120
6121         if (!changed)
6122                 return;
6123
6124         vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
6125                                   !(mode & MSR_BITMAP_MODE_LM));
6126
6127         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
6128                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
6129
6130         vmx->msr_bitmap_mode = mode;
6131 }
6132
6133 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
6134 {
6135         return enable_apicv;
6136 }
6137
6138 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
6139 {
6140         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6141         gfn_t gfn;
6142
6143         /*
6144          * Don't need to mark the APIC access page dirty; it is never
6145          * written to by the CPU during APIC virtualization.
6146          */
6147
6148         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
6149                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
6150                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6151         }
6152
6153         if (nested_cpu_has_posted_intr(vmcs12)) {
6154                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
6155                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6156         }
6157 }
6158
6159
6160 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
6161 {
6162         struct vcpu_vmx *vmx = to_vmx(vcpu);
6163         int max_irr;
6164         void *vapic_page;
6165         u16 status;
6166
6167         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
6168                 return;
6169
6170         vmx->nested.pi_pending = false;
6171         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6172                 return;
6173
6174         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
6175         if (max_irr != 256) {
6176                 vapic_page = kmap(vmx->nested.virtual_apic_page);
6177                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
6178                         vapic_page, &max_irr);
6179                 kunmap(vmx->nested.virtual_apic_page);
6180
6181                 status = vmcs_read16(GUEST_INTR_STATUS);
6182                 if ((u8)max_irr > ((u8)status & 0xff)) {
6183                         status &= ~0xff;
6184                         status |= (u8)max_irr;
6185                         vmcs_write16(GUEST_INTR_STATUS, status);
6186                 }
6187         }
6188
6189         nested_mark_vmcs12_pages_dirty(vcpu);
6190 }
6191
6192 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
6193 {
6194         struct vcpu_vmx *vmx = to_vmx(vcpu);
6195         void *vapic_page;
6196         u32 vppr;
6197         int rvi;
6198
6199         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
6200                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
6201                 WARN_ON_ONCE(!vmx->nested.virtual_apic_page))
6202                 return false;
6203
6204         rvi = vmcs_read16(GUEST_INTR_STATUS) & 0xff;
6205
6206         vapic_page = kmap(vmx->nested.virtual_apic_page);
6207         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
6208         kunmap(vmx->nested.virtual_apic_page);
6209
6210         return ((rvi & 0xf0) > (vppr & 0xf0));
6211 }
6212
6213 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
6214                                                      bool nested)
6215 {
6216 #ifdef CONFIG_SMP
6217         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
6218
6219         if (vcpu->mode == IN_GUEST_MODE) {
6220                 /*
6221                  * The vector of interrupt to be delivered to vcpu had
6222                  * been set in PIR before this function.
6223                  *
6224                  * Following cases will be reached in this block, and
6225                  * we always send a notification event in all cases as
6226                  * explained below.
6227                  *
6228                  * Case 1: vcpu keeps in non-root mode. Sending a
6229                  * notification event posts the interrupt to vcpu.
6230                  *
6231                  * Case 2: vcpu exits to root mode and is still
6232                  * runnable. PIR will be synced to vIRR before the
6233                  * next vcpu entry. Sending a notification event in
6234                  * this case has no effect, as vcpu is not in root
6235                  * mode.
6236                  *
6237                  * Case 3: vcpu exits to root mode and is blocked.
6238                  * vcpu_block() has already synced PIR to vIRR and
6239                  * never blocks vcpu if vIRR is not cleared. Therefore,
6240                  * a blocked vcpu here does not wait for any requested
6241                  * interrupts in PIR, and sending a notification event
6242                  * which has no effect is safe here.
6243                  */
6244
6245                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
6246                 return true;
6247         }
6248 #endif
6249         return false;
6250 }
6251
6252 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
6253                                                 int vector)
6254 {
6255         struct vcpu_vmx *vmx = to_vmx(vcpu);
6256
6257         if (is_guest_mode(vcpu) &&
6258             vector == vmx->nested.posted_intr_nv) {
6259                 /*
6260                  * If a posted intr is not recognized by hardware,
6261                  * we will accomplish it in the next vmentry.
6262                  */
6263                 vmx->nested.pi_pending = true;
6264                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6265                 /* the PIR and ON have been set by L1. */
6266                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
6267                         kvm_vcpu_kick(vcpu);
6268                 return 0;
6269         }
6270         return -1;
6271 }
6272 /*
6273  * Send interrupt to vcpu via posted interrupt way.
6274  * 1. If target vcpu is running(non-root mode), send posted interrupt
6275  * notification to vcpu and hardware will sync PIR to vIRR atomically.
6276  * 2. If target vcpu isn't running(root mode), kick it to pick up the
6277  * interrupt from PIR in next vmentry.
6278  */
6279 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
6280 {
6281         struct vcpu_vmx *vmx = to_vmx(vcpu);
6282         int r;
6283
6284         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
6285         if (!r)
6286                 return;
6287
6288         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
6289                 return;
6290
6291         /* If a previous notification has sent the IPI, nothing to do.  */
6292         if (pi_test_and_set_on(&vmx->pi_desc))
6293                 return;
6294
6295         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
6296                 kvm_vcpu_kick(vcpu);
6297 }
6298
6299 /*
6300  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
6301  * will not change in the lifetime of the guest.
6302  * Note that host-state that does change is set elsewhere. E.g., host-state
6303  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
6304  */
6305 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
6306 {
6307         u32 low32, high32;
6308         unsigned long tmpl;
6309         struct desc_ptr dt;
6310         unsigned long cr0, cr3, cr4;
6311
6312         cr0 = read_cr0();
6313         WARN_ON(cr0 & X86_CR0_TS);
6314         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
6315
6316         /*
6317          * Save the most likely value for this task's CR3 in the VMCS.
6318          * We can't use __get_current_cr3_fast() because we're not atomic.
6319          */
6320         cr3 = __read_cr3();
6321         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
6322         vmx->loaded_vmcs->host_state.cr3 = cr3;
6323
6324         /* Save the most likely value for this task's CR4 in the VMCS. */
6325         cr4 = cr4_read_shadow();
6326         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
6327         vmx->loaded_vmcs->host_state.cr4 = cr4;
6328
6329         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
6330 #ifdef CONFIG_X86_64
6331         /*
6332          * Load null selectors, so we can avoid reloading them in
6333          * vmx_prepare_switch_to_host(), in case userspace uses
6334          * the null selectors too (the expected case).
6335          */
6336         vmcs_write16(HOST_DS_SELECTOR, 0);
6337         vmcs_write16(HOST_ES_SELECTOR, 0);
6338 #else
6339         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6340         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6341 #endif
6342         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6343         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
6344
6345         store_idt(&dt);
6346         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
6347         vmx->host_idt_base = dt.address;
6348
6349         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
6350
6351         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
6352         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
6353         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
6354         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
6355
6356         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
6357                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
6358                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
6359         }
6360 }
6361
6362 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
6363 {
6364         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
6365         if (enable_ept)
6366                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
6367         if (is_guest_mode(&vmx->vcpu))
6368                 vmx->vcpu.arch.cr4_guest_owned_bits &=
6369                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
6370         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
6371 }
6372
6373 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
6374 {
6375         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
6376
6377         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
6378                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
6379
6380         if (!enable_vnmi)
6381                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
6382
6383         /* Enable the preemption timer dynamically */
6384         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
6385         return pin_based_exec_ctrl;
6386 }
6387
6388 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
6389 {
6390         struct vcpu_vmx *vmx = to_vmx(vcpu);
6391
6392         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6393         if (cpu_has_secondary_exec_ctrls()) {
6394                 if (kvm_vcpu_apicv_active(vcpu))
6395                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
6396                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
6397                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6398                 else
6399                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6400                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
6401                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6402         }
6403
6404         if (cpu_has_vmx_msr_bitmap())
6405                 vmx_update_msr_bitmap(vcpu);
6406 }
6407
6408 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6409 {
6410         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6411
6412         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6413                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6414
6415         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6416                 exec_control &= ~CPU_BASED_TPR_SHADOW;
6417 #ifdef CONFIG_X86_64
6418                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6419                                 CPU_BASED_CR8_LOAD_EXITING;
6420 #endif
6421         }
6422         if (!enable_ept)
6423                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6424                                 CPU_BASED_CR3_LOAD_EXITING  |
6425                                 CPU_BASED_INVLPG_EXITING;
6426         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6427                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6428                                 CPU_BASED_MONITOR_EXITING);
6429         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6430                 exec_control &= ~CPU_BASED_HLT_EXITING;
6431         return exec_control;
6432 }
6433
6434 static bool vmx_rdrand_supported(void)
6435 {
6436         return vmcs_config.cpu_based_2nd_exec_ctrl &
6437                 SECONDARY_EXEC_RDRAND_EXITING;
6438 }
6439
6440 static bool vmx_rdseed_supported(void)
6441 {
6442         return vmcs_config.cpu_based_2nd_exec_ctrl &
6443                 SECONDARY_EXEC_RDSEED_EXITING;
6444 }
6445
6446 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6447 {
6448         struct kvm_vcpu *vcpu = &vmx->vcpu;
6449
6450         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6451
6452         if (!cpu_need_virtualize_apic_accesses(vcpu))
6453                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6454         if (vmx->vpid == 0)
6455                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6456         if (!enable_ept) {
6457                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6458                 enable_unrestricted_guest = 0;
6459         }
6460         if (!enable_unrestricted_guest)
6461                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6462         if (kvm_pause_in_guest(vmx->vcpu.kvm))
6463                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6464         if (!kvm_vcpu_apicv_active(vcpu))
6465                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6466                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6467         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6468
6469         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6470          * in vmx_set_cr4.  */
6471         exec_control &= ~SECONDARY_EXEC_DESC;
6472
6473         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6474            (handle_vmptrld).
6475            We can NOT enable shadow_vmcs here because we don't have yet
6476            a current VMCS12
6477         */
6478         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6479
6480         if (!enable_pml)
6481                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6482
6483         if (vmx_xsaves_supported()) {
6484                 /* Exposing XSAVES only when XSAVE is exposed */
6485                 bool xsaves_enabled =
6486                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6487                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6488
6489                 if (!xsaves_enabled)
6490                         exec_control &= ~SECONDARY_EXEC_XSAVES;
6491
6492                 if (nested) {
6493                         if (xsaves_enabled)
6494                                 vmx->nested.msrs.secondary_ctls_high |=
6495                                         SECONDARY_EXEC_XSAVES;
6496                         else
6497                                 vmx->nested.msrs.secondary_ctls_high &=
6498                                         ~SECONDARY_EXEC_XSAVES;
6499                 }
6500         }
6501
6502         if (vmx_rdtscp_supported()) {
6503                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6504                 if (!rdtscp_enabled)
6505                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6506
6507                 if (nested) {
6508                         if (rdtscp_enabled)
6509                                 vmx->nested.msrs.secondary_ctls_high |=
6510                                         SECONDARY_EXEC_RDTSCP;
6511                         else
6512                                 vmx->nested.msrs.secondary_ctls_high &=
6513                                         ~SECONDARY_EXEC_RDTSCP;
6514                 }
6515         }
6516
6517         if (vmx_invpcid_supported()) {
6518                 /* Exposing INVPCID only when PCID is exposed */
6519                 bool invpcid_enabled =
6520                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6521                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6522
6523                 if (!invpcid_enabled) {
6524                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6525                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6526                 }
6527
6528                 if (nested) {
6529                         if (invpcid_enabled)
6530                                 vmx->nested.msrs.secondary_ctls_high |=
6531                                         SECONDARY_EXEC_ENABLE_INVPCID;
6532                         else
6533                                 vmx->nested.msrs.secondary_ctls_high &=
6534                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
6535                 }
6536         }
6537
6538         if (vmx_rdrand_supported()) {
6539                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6540                 if (rdrand_enabled)
6541                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6542
6543                 if (nested) {
6544                         if (rdrand_enabled)
6545                                 vmx->nested.msrs.secondary_ctls_high |=
6546                                         SECONDARY_EXEC_RDRAND_EXITING;
6547                         else
6548                                 vmx->nested.msrs.secondary_ctls_high &=
6549                                         ~SECONDARY_EXEC_RDRAND_EXITING;
6550                 }
6551         }
6552
6553         if (vmx_rdseed_supported()) {
6554                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6555                 if (rdseed_enabled)
6556                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6557
6558                 if (nested) {
6559                         if (rdseed_enabled)
6560                                 vmx->nested.msrs.secondary_ctls_high |=
6561                                         SECONDARY_EXEC_RDSEED_EXITING;
6562                         else
6563                                 vmx->nested.msrs.secondary_ctls_high &=
6564                                         ~SECONDARY_EXEC_RDSEED_EXITING;
6565                 }
6566         }
6567
6568         vmx->secondary_exec_control = exec_control;
6569 }
6570
6571 static void ept_set_mmio_spte_mask(void)
6572 {
6573         /*
6574          * EPT Misconfigurations can be generated if the value of bits 2:0
6575          * of an EPT paging-structure entry is 110b (write/execute).
6576          */
6577         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6578                                    VMX_EPT_MISCONFIG_WX_VALUE);
6579 }
6580
6581 #define VMX_XSS_EXIT_BITMAP 0
6582 /*
6583  * Sets up the vmcs for emulated real mode.
6584  */
6585 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6586 {
6587         int i;
6588
6589         if (enable_shadow_vmcs) {
6590                 /*
6591                  * At vCPU creation, "VMWRITE to any supported field
6592                  * in the VMCS" is supported, so use the more
6593                  * permissive vmx_vmread_bitmap to specify both read
6594                  * and write permissions for the shadow VMCS.
6595                  */
6596                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6597                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6598         }
6599         if (cpu_has_vmx_msr_bitmap())
6600                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6601
6602         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6603
6604         /* Control */
6605         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6606         vmx->hv_deadline_tsc = -1;
6607
6608         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6609
6610         if (cpu_has_secondary_exec_ctrls()) {
6611                 vmx_compute_secondary_exec_control(vmx);
6612                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6613                              vmx->secondary_exec_control);
6614         }
6615
6616         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6617                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6618                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6619                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6620                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6621
6622                 vmcs_write16(GUEST_INTR_STATUS, 0);
6623
6624                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6625                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6626         }
6627
6628         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6629                 vmcs_write32(PLE_GAP, ple_gap);
6630                 vmx->ple_window = ple_window;
6631                 vmx->ple_window_dirty = true;
6632         }
6633
6634         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6635         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6636         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
6637
6638         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
6639         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
6640         vmx_set_constant_host_state(vmx);
6641         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6642         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6643
6644         if (cpu_has_vmx_vmfunc())
6645                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6646
6647         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6648         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6649         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
6650         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6651         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6652
6653         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6654                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6655
6656         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6657                 u32 index = vmx_msr_index[i];
6658                 u32 data_low, data_high;
6659                 int j = vmx->nmsrs;
6660
6661                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6662                         continue;
6663                 if (wrmsr_safe(index, data_low, data_high) < 0)
6664                         continue;
6665                 vmx->guest_msrs[j].index = i;
6666                 vmx->guest_msrs[j].data = 0;
6667                 vmx->guest_msrs[j].mask = -1ull;
6668                 ++vmx->nmsrs;
6669         }
6670
6671         vmx->arch_capabilities = kvm_get_arch_capabilities();
6672
6673         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6674
6675         /* 22.2.1, 20.8.1 */
6676         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6677
6678         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6679         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6680
6681         set_cr4_guest_host_mask(vmx);
6682
6683         if (vmx_xsaves_supported())
6684                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6685
6686         if (enable_pml) {
6687                 ASSERT(vmx->pml_pg);
6688                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6689                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6690         }
6691
6692         if (cpu_has_vmx_encls_vmexit())
6693                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
6694 }
6695
6696 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6697 {
6698         struct vcpu_vmx *vmx = to_vmx(vcpu);
6699         struct msr_data apic_base_msr;
6700         u64 cr0;
6701
6702         vmx->rmode.vm86_active = 0;
6703         vmx->spec_ctrl = 0;
6704
6705         vcpu->arch.microcode_version = 0x100000000ULL;
6706         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6707         kvm_set_cr8(vcpu, 0);
6708
6709         if (!init_event) {
6710                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6711                                      MSR_IA32_APICBASE_ENABLE;
6712                 if (kvm_vcpu_is_reset_bsp(vcpu))
6713                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6714                 apic_base_msr.host_initiated = true;
6715                 kvm_set_apic_base(vcpu, &apic_base_msr);
6716         }
6717
6718         vmx_segment_cache_clear(vmx);
6719
6720         seg_setup(VCPU_SREG_CS);
6721         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6722         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6723
6724         seg_setup(VCPU_SREG_DS);
6725         seg_setup(VCPU_SREG_ES);
6726         seg_setup(VCPU_SREG_FS);
6727         seg_setup(VCPU_SREG_GS);
6728         seg_setup(VCPU_SREG_SS);
6729
6730         vmcs_write16(GUEST_TR_SELECTOR, 0);
6731         vmcs_writel(GUEST_TR_BASE, 0);
6732         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6733         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6734
6735         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6736         vmcs_writel(GUEST_LDTR_BASE, 0);
6737         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6738         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6739
6740         if (!init_event) {
6741                 vmcs_write32(GUEST_SYSENTER_CS, 0);
6742                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6743                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6744                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6745         }
6746
6747         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6748         kvm_rip_write(vcpu, 0xfff0);
6749
6750         vmcs_writel(GUEST_GDTR_BASE, 0);
6751         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6752
6753         vmcs_writel(GUEST_IDTR_BASE, 0);
6754         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6755
6756         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6757         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6758         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6759         if (kvm_mpx_supported())
6760                 vmcs_write64(GUEST_BNDCFGS, 0);
6761
6762         setup_msrs(vmx);
6763
6764         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
6765
6766         if (cpu_has_vmx_tpr_shadow() && !init_event) {
6767                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6768                 if (cpu_need_tpr_shadow(vcpu))
6769                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6770                                      __pa(vcpu->arch.apic->regs));
6771                 vmcs_write32(TPR_THRESHOLD, 0);
6772         }
6773
6774         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6775
6776         if (vmx->vpid != 0)
6777                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6778
6779         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6780         vmx->vcpu.arch.cr0 = cr0;
6781         vmx_set_cr0(vcpu, cr0); /* enter rmode */
6782         vmx_set_cr4(vcpu, 0);
6783         vmx_set_efer(vcpu, 0);
6784
6785         update_exception_bitmap(vcpu);
6786
6787         vpid_sync_context(vmx->vpid);
6788         if (init_event)
6789                 vmx_clear_hlt(vcpu);
6790 }
6791
6792 /*
6793  * In nested virtualization, check if L1 asked to exit on external interrupts.
6794  * For most existing hypervisors, this will always return true.
6795  */
6796 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6797 {
6798         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6799                 PIN_BASED_EXT_INTR_MASK;
6800 }
6801
6802 /*
6803  * In nested virtualization, check if L1 has set
6804  * VM_EXIT_ACK_INTR_ON_EXIT
6805  */
6806 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6807 {
6808         return get_vmcs12(vcpu)->vm_exit_controls &
6809                 VM_EXIT_ACK_INTR_ON_EXIT;
6810 }
6811
6812 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6813 {
6814         return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6815 }
6816
6817 static void enable_irq_window(struct kvm_vcpu *vcpu)
6818 {
6819         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6820                       CPU_BASED_VIRTUAL_INTR_PENDING);
6821 }
6822
6823 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6824 {
6825         if (!enable_vnmi ||
6826             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6827                 enable_irq_window(vcpu);
6828                 return;
6829         }
6830
6831         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6832                       CPU_BASED_VIRTUAL_NMI_PENDING);
6833 }
6834
6835 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6836 {
6837         struct vcpu_vmx *vmx = to_vmx(vcpu);
6838         uint32_t intr;
6839         int irq = vcpu->arch.interrupt.nr;
6840
6841         trace_kvm_inj_virq(irq);
6842
6843         ++vcpu->stat.irq_injections;
6844         if (vmx->rmode.vm86_active) {
6845                 int inc_eip = 0;
6846                 if (vcpu->arch.interrupt.soft)
6847                         inc_eip = vcpu->arch.event_exit_inst_len;
6848                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6849                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6850                 return;
6851         }
6852         intr = irq | INTR_INFO_VALID_MASK;
6853         if (vcpu->arch.interrupt.soft) {
6854                 intr |= INTR_TYPE_SOFT_INTR;
6855                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6856                              vmx->vcpu.arch.event_exit_inst_len);
6857         } else
6858                 intr |= INTR_TYPE_EXT_INTR;
6859         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6860
6861         vmx_clear_hlt(vcpu);
6862 }
6863
6864 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6865 {
6866         struct vcpu_vmx *vmx = to_vmx(vcpu);
6867
6868         if (!enable_vnmi) {
6869                 /*
6870                  * Tracking the NMI-blocked state in software is built upon
6871                  * finding the next open IRQ window. This, in turn, depends on
6872                  * well-behaving guests: They have to keep IRQs disabled at
6873                  * least as long as the NMI handler runs. Otherwise we may
6874                  * cause NMI nesting, maybe breaking the guest. But as this is
6875                  * highly unlikely, we can live with the residual risk.
6876                  */
6877                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6878                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6879         }
6880
6881         ++vcpu->stat.nmi_injections;
6882         vmx->loaded_vmcs->nmi_known_unmasked = false;
6883
6884         if (vmx->rmode.vm86_active) {
6885                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6886                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6887                 return;
6888         }
6889
6890         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6891                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6892
6893         vmx_clear_hlt(vcpu);
6894 }
6895
6896 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6897 {
6898         struct vcpu_vmx *vmx = to_vmx(vcpu);
6899         bool masked;
6900
6901         if (!enable_vnmi)
6902                 return vmx->loaded_vmcs->soft_vnmi_blocked;
6903         if (vmx->loaded_vmcs->nmi_known_unmasked)
6904                 return false;
6905         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6906         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6907         return masked;
6908 }
6909
6910 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6911 {
6912         struct vcpu_vmx *vmx = to_vmx(vcpu);
6913
6914         if (!enable_vnmi) {
6915                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6916                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6917                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
6918                 }
6919         } else {
6920                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6921                 if (masked)
6922                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6923                                       GUEST_INTR_STATE_NMI);
6924                 else
6925                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6926                                         GUEST_INTR_STATE_NMI);
6927         }
6928 }
6929
6930 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6931 {
6932         if (to_vmx(vcpu)->nested.nested_run_pending)
6933                 return 0;
6934
6935         if (!enable_vnmi &&
6936             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6937                 return 0;
6938
6939         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6940                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6941                    | GUEST_INTR_STATE_NMI));
6942 }
6943
6944 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6945 {
6946         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6947                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6948                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6949                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6950 }
6951
6952 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6953 {
6954         int ret;
6955
6956         if (enable_unrestricted_guest)
6957                 return 0;
6958
6959         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6960                                     PAGE_SIZE * 3);
6961         if (ret)
6962                 return ret;
6963         to_kvm_vmx(kvm)->tss_addr = addr;
6964         return init_rmode_tss(kvm);
6965 }
6966
6967 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6968 {
6969         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6970         return 0;
6971 }
6972
6973 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6974 {
6975         switch (vec) {
6976         case BP_VECTOR:
6977                 /*
6978                  * Update instruction length as we may reinject the exception
6979                  * from user space while in guest debugging mode.
6980                  */
6981                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6982                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6983                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6984                         return false;
6985                 /* fall through */
6986         case DB_VECTOR:
6987                 if (vcpu->guest_debug &
6988                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6989                         return false;
6990                 /* fall through */
6991         case DE_VECTOR:
6992         case OF_VECTOR:
6993         case BR_VECTOR:
6994         case UD_VECTOR:
6995         case DF_VECTOR:
6996         case SS_VECTOR:
6997         case GP_VECTOR:
6998         case MF_VECTOR:
6999                 return true;
7000         break;
7001         }
7002         return false;
7003 }
7004
7005 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
7006                                   int vec, u32 err_code)
7007 {
7008         /*
7009          * Instruction with address size override prefix opcode 0x67
7010          * Cause the #SS fault with 0 error code in VM86 mode.
7011          */
7012         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
7013                 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
7014                         if (vcpu->arch.halt_request) {
7015                                 vcpu->arch.halt_request = 0;
7016                                 return kvm_vcpu_halt(vcpu);
7017                         }
7018                         return 1;
7019                 }
7020                 return 0;
7021         }
7022
7023         /*
7024          * Forward all other exceptions that are valid in real mode.
7025          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
7026          *        the required debugging infrastructure rework.
7027          */
7028         kvm_queue_exception(vcpu, vec);
7029         return 1;
7030 }
7031
7032 /*
7033  * Trigger machine check on the host. We assume all the MSRs are already set up
7034  * by the CPU and that we still run on the same CPU as the MCE occurred on.
7035  * We pass a fake environment to the machine check handler because we want
7036  * the guest to be always treated like user space, no matter what context
7037  * it used internally.
7038  */
7039 static void kvm_machine_check(void)
7040 {
7041 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
7042         struct pt_regs regs = {
7043                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
7044                 .flags = X86_EFLAGS_IF,
7045         };
7046
7047         do_machine_check(&regs, 0);
7048 #endif
7049 }
7050
7051 static int handle_machine_check(struct kvm_vcpu *vcpu)
7052 {
7053         /* already handled by vcpu_run */
7054         return 1;
7055 }
7056
7057 static int handle_exception(struct kvm_vcpu *vcpu)
7058 {
7059         struct vcpu_vmx *vmx = to_vmx(vcpu);
7060         struct kvm_run *kvm_run = vcpu->run;
7061         u32 intr_info, ex_no, error_code;
7062         unsigned long cr2, rip, dr6;
7063         u32 vect_info;
7064         enum emulation_result er;
7065
7066         vect_info = vmx->idt_vectoring_info;
7067         intr_info = vmx->exit_intr_info;
7068
7069         if (is_machine_check(intr_info))
7070                 return handle_machine_check(vcpu);
7071
7072         if (is_nmi(intr_info))
7073                 return 1;  /* already handled by vmx_vcpu_run() */
7074
7075         if (is_invalid_opcode(intr_info))
7076                 return handle_ud(vcpu);
7077
7078         error_code = 0;
7079         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
7080                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7081
7082         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
7083                 WARN_ON_ONCE(!enable_vmware_backdoor);
7084                 er = kvm_emulate_instruction(vcpu,
7085                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
7086                 if (er == EMULATE_USER_EXIT)
7087                         return 0;
7088                 else if (er != EMULATE_DONE)
7089                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
7090                 return 1;
7091         }
7092
7093         /*
7094          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
7095          * MMIO, it is better to report an internal error.
7096          * See the comments in vmx_handle_exit.
7097          */
7098         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
7099             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
7100                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7101                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
7102                 vcpu->run->internal.ndata = 3;
7103                 vcpu->run->internal.data[0] = vect_info;
7104                 vcpu->run->internal.data[1] = intr_info;
7105                 vcpu->run->internal.data[2] = error_code;
7106                 return 0;
7107         }
7108
7109         if (is_page_fault(intr_info)) {
7110                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
7111                 /* EPT won't cause page fault directly */
7112                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
7113                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
7114         }
7115
7116         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
7117
7118         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
7119                 return handle_rmode_exception(vcpu, ex_no, error_code);
7120
7121         switch (ex_no) {
7122         case AC_VECTOR:
7123                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
7124                 return 1;
7125         case DB_VECTOR:
7126                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
7127                 if (!(vcpu->guest_debug &
7128                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
7129                         vcpu->arch.dr6 &= ~15;
7130                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
7131                         if (is_icebp(intr_info))
7132                                 skip_emulated_instruction(vcpu);
7133
7134                         kvm_queue_exception(vcpu, DB_VECTOR);
7135                         return 1;
7136                 }
7137                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
7138                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
7139                 /* fall through */
7140         case BP_VECTOR:
7141                 /*
7142                  * Update instruction length as we may reinject #BP from
7143                  * user space while in guest debugging mode. Reading it for
7144                  * #DB as well causes no harm, it is not used in that case.
7145                  */
7146                 vmx->vcpu.arch.event_exit_inst_len =
7147                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7148                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7149                 rip = kvm_rip_read(vcpu);
7150                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
7151                 kvm_run->debug.arch.exception = ex_no;
7152                 break;
7153         default:
7154                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
7155                 kvm_run->ex.exception = ex_no;
7156                 kvm_run->ex.error_code = error_code;
7157                 break;
7158         }
7159         return 0;
7160 }
7161
7162 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
7163 {
7164         ++vcpu->stat.irq_exits;
7165         return 1;
7166 }
7167
7168 static int handle_triple_fault(struct kvm_vcpu *vcpu)
7169 {
7170         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7171         vcpu->mmio_needed = 0;
7172         return 0;
7173 }
7174
7175 static int handle_io(struct kvm_vcpu *vcpu)
7176 {
7177         unsigned long exit_qualification;
7178         int size, in, string;
7179         unsigned port;
7180
7181         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7182         string = (exit_qualification & 16) != 0;
7183
7184         ++vcpu->stat.io_exits;
7185
7186         if (string)
7187                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7188
7189         port = exit_qualification >> 16;
7190         size = (exit_qualification & 7) + 1;
7191         in = (exit_qualification & 8) != 0;
7192
7193         return kvm_fast_pio(vcpu, size, port, in);
7194 }
7195
7196 static void
7197 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
7198 {
7199         /*
7200          * Patch in the VMCALL instruction:
7201          */
7202         hypercall[0] = 0x0f;
7203         hypercall[1] = 0x01;
7204         hypercall[2] = 0xc1;
7205 }
7206
7207 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
7208 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
7209 {
7210         if (is_guest_mode(vcpu)) {
7211                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7212                 unsigned long orig_val = val;
7213
7214                 /*
7215                  * We get here when L2 changed cr0 in a way that did not change
7216                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
7217                  * but did change L0 shadowed bits. So we first calculate the
7218                  * effective cr0 value that L1 would like to write into the
7219                  * hardware. It consists of the L2-owned bits from the new
7220                  * value combined with the L1-owned bits from L1's guest_cr0.
7221                  */
7222                 val = (val & ~vmcs12->cr0_guest_host_mask) |
7223                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
7224
7225                 if (!nested_guest_cr0_valid(vcpu, val))
7226                         return 1;
7227
7228                 if (kvm_set_cr0(vcpu, val))
7229                         return 1;
7230                 vmcs_writel(CR0_READ_SHADOW, orig_val);
7231                 return 0;
7232         } else {
7233                 if (to_vmx(vcpu)->nested.vmxon &&
7234                     !nested_host_cr0_valid(vcpu, val))
7235                         return 1;
7236
7237                 return kvm_set_cr0(vcpu, val);
7238         }
7239 }
7240
7241 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
7242 {
7243         if (is_guest_mode(vcpu)) {
7244                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7245                 unsigned long orig_val = val;
7246
7247                 /* analogously to handle_set_cr0 */
7248                 val = (val & ~vmcs12->cr4_guest_host_mask) |
7249                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
7250                 if (kvm_set_cr4(vcpu, val))
7251                         return 1;
7252                 vmcs_writel(CR4_READ_SHADOW, orig_val);
7253                 return 0;
7254         } else
7255                 return kvm_set_cr4(vcpu, val);
7256 }
7257
7258 static int handle_desc(struct kvm_vcpu *vcpu)
7259 {
7260         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
7261         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7262 }
7263
7264 static int handle_cr(struct kvm_vcpu *vcpu)
7265 {
7266         unsigned long exit_qualification, val;
7267         int cr;
7268         int reg;
7269         int err;
7270         int ret;
7271
7272         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7273         cr = exit_qualification & 15;
7274         reg = (exit_qualification >> 8) & 15;
7275         switch ((exit_qualification >> 4) & 3) {
7276         case 0: /* mov to cr */
7277                 val = kvm_register_readl(vcpu, reg);
7278                 trace_kvm_cr_write(cr, val);
7279                 switch (cr) {
7280                 case 0:
7281                         err = handle_set_cr0(vcpu, val);
7282                         return kvm_complete_insn_gp(vcpu, err);
7283                 case 3:
7284                         WARN_ON_ONCE(enable_unrestricted_guest);
7285                         err = kvm_set_cr3(vcpu, val);
7286                         return kvm_complete_insn_gp(vcpu, err);
7287                 case 4:
7288                         err = handle_set_cr4(vcpu, val);
7289                         return kvm_complete_insn_gp(vcpu, err);
7290                 case 8: {
7291                                 u8 cr8_prev = kvm_get_cr8(vcpu);
7292                                 u8 cr8 = (u8)val;
7293                                 err = kvm_set_cr8(vcpu, cr8);
7294                                 ret = kvm_complete_insn_gp(vcpu, err);
7295                                 if (lapic_in_kernel(vcpu))
7296                                         return ret;
7297                                 if (cr8_prev <= cr8)
7298                                         return ret;
7299                                 /*
7300                                  * TODO: we might be squashing a
7301                                  * KVM_GUESTDBG_SINGLESTEP-triggered
7302                                  * KVM_EXIT_DEBUG here.
7303                                  */
7304                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
7305                                 return 0;
7306                         }
7307                 }
7308                 break;
7309         case 2: /* clts */
7310                 WARN_ONCE(1, "Guest should always own CR0.TS");
7311                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
7312                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
7313                 return kvm_skip_emulated_instruction(vcpu);
7314         case 1: /*mov from cr*/
7315                 switch (cr) {
7316                 case 3:
7317                         WARN_ON_ONCE(enable_unrestricted_guest);
7318                         val = kvm_read_cr3(vcpu);
7319                         kvm_register_write(vcpu, reg, val);
7320                         trace_kvm_cr_read(cr, val);
7321                         return kvm_skip_emulated_instruction(vcpu);
7322                 case 8:
7323                         val = kvm_get_cr8(vcpu);
7324                         kvm_register_write(vcpu, reg, val);
7325                         trace_kvm_cr_read(cr, val);
7326                         return kvm_skip_emulated_instruction(vcpu);
7327                 }
7328                 break;
7329         case 3: /* lmsw */
7330                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
7331                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
7332                 kvm_lmsw(vcpu, val);
7333
7334                 return kvm_skip_emulated_instruction(vcpu);
7335         default:
7336                 break;
7337         }
7338         vcpu->run->exit_reason = 0;
7339         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
7340                (int)(exit_qualification >> 4) & 3, cr);
7341         return 0;
7342 }
7343
7344 static int handle_dr(struct kvm_vcpu *vcpu)
7345 {
7346         unsigned long exit_qualification;
7347         int dr, dr7, reg;
7348
7349         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7350         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
7351
7352         /* First, if DR does not exist, trigger UD */
7353         if (!kvm_require_dr(vcpu, dr))
7354                 return 1;
7355
7356         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
7357         if (!kvm_require_cpl(vcpu, 0))
7358                 return 1;
7359         dr7 = vmcs_readl(GUEST_DR7);
7360         if (dr7 & DR7_GD) {
7361                 /*
7362                  * As the vm-exit takes precedence over the debug trap, we
7363                  * need to emulate the latter, either for the host or the
7364                  * guest debugging itself.
7365                  */
7366                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7367                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
7368                         vcpu->run->debug.arch.dr7 = dr7;
7369                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7370                         vcpu->run->debug.arch.exception = DB_VECTOR;
7371                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
7372                         return 0;
7373                 } else {
7374                         vcpu->arch.dr6 &= ~15;
7375                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
7376                         kvm_queue_exception(vcpu, DB_VECTOR);
7377                         return 1;
7378                 }
7379         }
7380
7381         if (vcpu->guest_debug == 0) {
7382                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7383                                 CPU_BASED_MOV_DR_EXITING);
7384
7385                 /*
7386                  * No more DR vmexits; force a reload of the debug registers
7387                  * and reenter on this instruction.  The next vmexit will
7388                  * retrieve the full state of the debug registers.
7389                  */
7390                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
7391                 return 1;
7392         }
7393
7394         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
7395         if (exit_qualification & TYPE_MOV_FROM_DR) {
7396                 unsigned long val;
7397
7398                 if (kvm_get_dr(vcpu, dr, &val))
7399                         return 1;
7400                 kvm_register_write(vcpu, reg, val);
7401         } else
7402                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7403                         return 1;
7404
7405         return kvm_skip_emulated_instruction(vcpu);
7406 }
7407
7408 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7409 {
7410         return vcpu->arch.dr6;
7411 }
7412
7413 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7414 {
7415 }
7416
7417 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7418 {
7419         get_debugreg(vcpu->arch.db[0], 0);
7420         get_debugreg(vcpu->arch.db[1], 1);
7421         get_debugreg(vcpu->arch.db[2], 2);
7422         get_debugreg(vcpu->arch.db[3], 3);
7423         get_debugreg(vcpu->arch.dr6, 6);
7424         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7425
7426         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7427         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7428 }
7429
7430 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7431 {
7432         vmcs_writel(GUEST_DR7, val);
7433 }
7434
7435 static int handle_cpuid(struct kvm_vcpu *vcpu)
7436 {
7437         return kvm_emulate_cpuid(vcpu);
7438 }
7439
7440 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7441 {
7442         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7443         struct msr_data msr_info;
7444
7445         msr_info.index = ecx;
7446         msr_info.host_initiated = false;
7447         if (vmx_get_msr(vcpu, &msr_info)) {
7448                 trace_kvm_msr_read_ex(ecx);
7449                 kvm_inject_gp(vcpu, 0);
7450                 return 1;
7451         }
7452
7453         trace_kvm_msr_read(ecx, msr_info.data);
7454
7455         /* FIXME: handling of bits 32:63 of rax, rdx */
7456         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7457         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7458         return kvm_skip_emulated_instruction(vcpu);
7459 }
7460
7461 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7462 {
7463         struct msr_data msr;
7464         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7465         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7466                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7467
7468         msr.data = data;
7469         msr.index = ecx;
7470         msr.host_initiated = false;
7471         if (kvm_set_msr(vcpu, &msr) != 0) {
7472                 trace_kvm_msr_write_ex(ecx, data);
7473                 kvm_inject_gp(vcpu, 0);
7474                 return 1;
7475         }
7476
7477         trace_kvm_msr_write(ecx, data);
7478         return kvm_skip_emulated_instruction(vcpu);
7479 }
7480
7481 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7482 {
7483         kvm_apic_update_ppr(vcpu);
7484         return 1;
7485 }
7486
7487 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7488 {
7489         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7490                         CPU_BASED_VIRTUAL_INTR_PENDING);
7491
7492         kvm_make_request(KVM_REQ_EVENT, vcpu);
7493
7494         ++vcpu->stat.irq_window_exits;
7495         return 1;
7496 }
7497
7498 static int handle_halt(struct kvm_vcpu *vcpu)
7499 {
7500         return kvm_emulate_halt(vcpu);
7501 }
7502
7503 static int handle_vmcall(struct kvm_vcpu *vcpu)
7504 {
7505         return kvm_emulate_hypercall(vcpu);
7506 }
7507
7508 static int handle_invd(struct kvm_vcpu *vcpu)
7509 {
7510         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7511 }
7512
7513 static int handle_invlpg(struct kvm_vcpu *vcpu)
7514 {
7515         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7516
7517         kvm_mmu_invlpg(vcpu, exit_qualification);
7518         return kvm_skip_emulated_instruction(vcpu);
7519 }
7520
7521 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7522 {
7523         int err;
7524
7525         err = kvm_rdpmc(vcpu);
7526         return kvm_complete_insn_gp(vcpu, err);
7527 }
7528
7529 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7530 {
7531         return kvm_emulate_wbinvd(vcpu);
7532 }
7533
7534 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7535 {
7536         u64 new_bv = kvm_read_edx_eax(vcpu);
7537         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7538
7539         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7540                 return kvm_skip_emulated_instruction(vcpu);
7541         return 1;
7542 }
7543
7544 static int handle_xsaves(struct kvm_vcpu *vcpu)
7545 {
7546         kvm_skip_emulated_instruction(vcpu);
7547         WARN(1, "this should never happen\n");
7548         return 1;
7549 }
7550
7551 static int handle_xrstors(struct kvm_vcpu *vcpu)
7552 {
7553         kvm_skip_emulated_instruction(vcpu);
7554         WARN(1, "this should never happen\n");
7555         return 1;
7556 }
7557
7558 static int handle_apic_access(struct kvm_vcpu *vcpu)
7559 {
7560         if (likely(fasteoi)) {
7561                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7562                 int access_type, offset;
7563
7564                 access_type = exit_qualification & APIC_ACCESS_TYPE;
7565                 offset = exit_qualification & APIC_ACCESS_OFFSET;
7566                 /*
7567                  * Sane guest uses MOV to write EOI, with written value
7568                  * not cared. So make a short-circuit here by avoiding
7569                  * heavy instruction emulation.
7570                  */
7571                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7572                     (offset == APIC_EOI)) {
7573                         kvm_lapic_set_eoi(vcpu);
7574                         return kvm_skip_emulated_instruction(vcpu);
7575                 }
7576         }
7577         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7578 }
7579
7580 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7581 {
7582         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7583         int vector = exit_qualification & 0xff;
7584
7585         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7586         kvm_apic_set_eoi_accelerated(vcpu, vector);
7587         return 1;
7588 }
7589
7590 static int handle_apic_write(struct kvm_vcpu *vcpu)
7591 {
7592         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7593         u32 offset = exit_qualification & 0xfff;
7594
7595         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7596         kvm_apic_write_nodecode(vcpu, offset);
7597         return 1;
7598 }
7599
7600 static int handle_task_switch(struct kvm_vcpu *vcpu)
7601 {
7602         struct vcpu_vmx *vmx = to_vmx(vcpu);
7603         unsigned long exit_qualification;
7604         bool has_error_code = false;
7605         u32 error_code = 0;
7606         u16 tss_selector;
7607         int reason, type, idt_v, idt_index;
7608
7609         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7610         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7611         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7612
7613         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7614
7615         reason = (u32)exit_qualification >> 30;
7616         if (reason == TASK_SWITCH_GATE && idt_v) {
7617                 switch (type) {
7618                 case INTR_TYPE_NMI_INTR:
7619                         vcpu->arch.nmi_injected = false;
7620                         vmx_set_nmi_mask(vcpu, true);
7621                         break;
7622                 case INTR_TYPE_EXT_INTR:
7623                 case INTR_TYPE_SOFT_INTR:
7624                         kvm_clear_interrupt_queue(vcpu);
7625                         break;
7626                 case INTR_TYPE_HARD_EXCEPTION:
7627                         if (vmx->idt_vectoring_info &
7628                             VECTORING_INFO_DELIVER_CODE_MASK) {
7629                                 has_error_code = true;
7630                                 error_code =
7631                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
7632                         }
7633                         /* fall through */
7634                 case INTR_TYPE_SOFT_EXCEPTION:
7635                         kvm_clear_exception_queue(vcpu);
7636                         break;
7637                 default:
7638                         break;
7639                 }
7640         }
7641         tss_selector = exit_qualification;
7642
7643         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7644                        type != INTR_TYPE_EXT_INTR &&
7645                        type != INTR_TYPE_NMI_INTR))
7646                 skip_emulated_instruction(vcpu);
7647
7648         if (kvm_task_switch(vcpu, tss_selector,
7649                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7650                             has_error_code, error_code) == EMULATE_FAIL) {
7651                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7652                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7653                 vcpu->run->internal.ndata = 0;
7654                 return 0;
7655         }
7656
7657         /*
7658          * TODO: What about debug traps on tss switch?
7659          *       Are we supposed to inject them and update dr6?
7660          */
7661
7662         return 1;
7663 }
7664
7665 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7666 {
7667         unsigned long exit_qualification;
7668         gpa_t gpa;
7669         u64 error_code;
7670
7671         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7672
7673         /*
7674          * EPT violation happened while executing iret from NMI,
7675          * "blocked by NMI" bit has to be set before next VM entry.
7676          * There are errata that may cause this bit to not be set:
7677          * AAK134, BY25.
7678          */
7679         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7680                         enable_vnmi &&
7681                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7682                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7683
7684         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7685         trace_kvm_page_fault(gpa, exit_qualification);
7686
7687         /* Is it a read fault? */
7688         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7689                      ? PFERR_USER_MASK : 0;
7690         /* Is it a write fault? */
7691         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7692                       ? PFERR_WRITE_MASK : 0;
7693         /* Is it a fetch fault? */
7694         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7695                       ? PFERR_FETCH_MASK : 0;
7696         /* ept page table entry is present? */
7697         error_code |= (exit_qualification &
7698                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7699                         EPT_VIOLATION_EXECUTABLE))
7700                       ? PFERR_PRESENT_MASK : 0;
7701
7702         error_code |= (exit_qualification & 0x100) != 0 ?
7703                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7704
7705         vcpu->arch.exit_qualification = exit_qualification;
7706         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7707 }
7708
7709 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7710 {
7711         gpa_t gpa;
7712
7713         /*
7714          * A nested guest cannot optimize MMIO vmexits, because we have an
7715          * nGPA here instead of the required GPA.
7716          */
7717         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7718         if (!is_guest_mode(vcpu) &&
7719             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7720                 trace_kvm_fast_mmio(gpa);
7721                 /*
7722                  * Doing kvm_skip_emulated_instruction() depends on undefined
7723                  * behavior: Intel's manual doesn't mandate
7724                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7725                  * occurs and while on real hardware it was observed to be set,
7726                  * other hypervisors (namely Hyper-V) don't set it, we end up
7727                  * advancing IP with some random value. Disable fast mmio when
7728                  * running nested and keep it for real hardware in hope that
7729                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7730                  */
7731                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7732                         return kvm_skip_emulated_instruction(vcpu);
7733                 else
7734                         return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
7735                                                                 EMULATE_DONE;
7736         }
7737
7738         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7739 }
7740
7741 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7742 {
7743         WARN_ON_ONCE(!enable_vnmi);
7744         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7745                         CPU_BASED_VIRTUAL_NMI_PENDING);
7746         ++vcpu->stat.nmi_window_exits;
7747         kvm_make_request(KVM_REQ_EVENT, vcpu);
7748
7749         return 1;
7750 }
7751
7752 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7753 {
7754         struct vcpu_vmx *vmx = to_vmx(vcpu);
7755         enum emulation_result err = EMULATE_DONE;
7756         int ret = 1;
7757         u32 cpu_exec_ctrl;
7758         bool intr_window_requested;
7759         unsigned count = 130;
7760
7761         /*
7762          * We should never reach the point where we are emulating L2
7763          * due to invalid guest state as that means we incorrectly
7764          * allowed a nested VMEntry with an invalid vmcs12.
7765          */
7766         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7767
7768         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7769         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7770
7771         while (vmx->emulation_required && count-- != 0) {
7772                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7773                         return handle_interrupt_window(&vmx->vcpu);
7774
7775                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7776                         return 1;
7777
7778                 err = kvm_emulate_instruction(vcpu, 0);
7779
7780                 if (err == EMULATE_USER_EXIT) {
7781                         ++vcpu->stat.mmio_exits;
7782                         ret = 0;
7783                         goto out;
7784                 }
7785
7786                 if (err != EMULATE_DONE)
7787                         goto emulation_error;
7788
7789                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7790                     vcpu->arch.exception.pending)
7791                         goto emulation_error;
7792
7793                 if (vcpu->arch.halt_request) {
7794                         vcpu->arch.halt_request = 0;
7795                         ret = kvm_vcpu_halt(vcpu);
7796                         goto out;
7797                 }
7798
7799                 if (signal_pending(current))
7800                         goto out;
7801                 if (need_resched())
7802                         schedule();
7803         }
7804
7805 out:
7806         return ret;
7807
7808 emulation_error:
7809         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7810         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7811         vcpu->run->internal.ndata = 0;
7812         return 0;
7813 }
7814
7815 static void grow_ple_window(struct kvm_vcpu *vcpu)
7816 {
7817         struct vcpu_vmx *vmx = to_vmx(vcpu);
7818         int old = vmx->ple_window;
7819
7820         vmx->ple_window = __grow_ple_window(old, ple_window,
7821                                             ple_window_grow,
7822                                             ple_window_max);
7823
7824         if (vmx->ple_window != old)
7825                 vmx->ple_window_dirty = true;
7826
7827         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7828 }
7829
7830 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7831 {
7832         struct vcpu_vmx *vmx = to_vmx(vcpu);
7833         int old = vmx->ple_window;
7834
7835         vmx->ple_window = __shrink_ple_window(old, ple_window,
7836                                               ple_window_shrink,
7837                                               ple_window);
7838
7839         if (vmx->ple_window != old)
7840                 vmx->ple_window_dirty = true;
7841
7842         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7843 }
7844
7845 /*
7846  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7847  */
7848 static void wakeup_handler(void)
7849 {
7850         struct kvm_vcpu *vcpu;
7851         int cpu = smp_processor_id();
7852
7853         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7854         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7855                         blocked_vcpu_list) {
7856                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7857
7858                 if (pi_test_on(pi_desc) == 1)
7859                         kvm_vcpu_kick(vcpu);
7860         }
7861         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7862 }
7863
7864 static void vmx_enable_tdp(void)
7865 {
7866         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7867                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7868                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7869                 0ull, VMX_EPT_EXECUTABLE_MASK,
7870                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7871                 VMX_EPT_RWX_MASK, 0ull);
7872
7873         ept_set_mmio_spte_mask();
7874         kvm_enable_tdp();
7875 }
7876
7877 static __init int hardware_setup(void)
7878 {
7879         unsigned long host_bndcfgs;
7880         int r = -ENOMEM, i;
7881
7882         rdmsrl_safe(MSR_EFER, &host_efer);
7883
7884         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7885                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7886
7887         for (i = 0; i < VMX_BITMAP_NR; i++) {
7888                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7889                 if (!vmx_bitmap[i])
7890                         goto out;
7891         }
7892
7893         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7894         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7895
7896         if (setup_vmcs_config(&vmcs_config) < 0) {
7897                 r = -EIO;
7898                 goto out;
7899         }
7900
7901         if (boot_cpu_has(X86_FEATURE_NX))
7902                 kvm_enable_efer_bits(EFER_NX);
7903
7904         if (boot_cpu_has(X86_FEATURE_MPX)) {
7905                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7906                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7907         }
7908
7909         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7910                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7911                 enable_vpid = 0;
7912
7913         if (!cpu_has_vmx_ept() ||
7914             !cpu_has_vmx_ept_4levels() ||
7915             !cpu_has_vmx_ept_mt_wb() ||
7916             !cpu_has_vmx_invept_global())
7917                 enable_ept = 0;
7918
7919         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7920                 enable_ept_ad_bits = 0;
7921
7922         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7923                 enable_unrestricted_guest = 0;
7924
7925         if (!cpu_has_vmx_flexpriority())
7926                 flexpriority_enabled = 0;
7927
7928         if (!cpu_has_virtual_nmis())
7929                 enable_vnmi = 0;
7930
7931         /*
7932          * set_apic_access_page_addr() is used to reload apic access
7933          * page upon invalidation.  No need to do anything if not
7934          * using the APIC_ACCESS_ADDR VMCS field.
7935          */
7936         if (!flexpriority_enabled)
7937                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7938
7939         if (!cpu_has_vmx_tpr_shadow())
7940                 kvm_x86_ops->update_cr8_intercept = NULL;
7941
7942         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7943                 kvm_disable_largepages();
7944
7945 #if IS_ENABLED(CONFIG_HYPERV)
7946         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7947             && enable_ept)
7948                 kvm_x86_ops->tlb_remote_flush = vmx_hv_remote_flush_tlb;
7949 #endif
7950
7951         if (!cpu_has_vmx_ple()) {
7952                 ple_gap = 0;
7953                 ple_window = 0;
7954                 ple_window_grow = 0;
7955                 ple_window_max = 0;
7956                 ple_window_shrink = 0;
7957         }
7958
7959         if (!cpu_has_vmx_apicv()) {
7960                 enable_apicv = 0;
7961                 kvm_x86_ops->sync_pir_to_irr = NULL;
7962         }
7963
7964         if (cpu_has_vmx_tsc_scaling()) {
7965                 kvm_has_tsc_control = true;
7966                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7967                 kvm_tsc_scaling_ratio_frac_bits = 48;
7968         }
7969
7970         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7971
7972         if (enable_ept)
7973                 vmx_enable_tdp();
7974         else
7975                 kvm_disable_tdp();
7976
7977         if (!nested) {
7978                 kvm_x86_ops->get_nested_state = NULL;
7979                 kvm_x86_ops->set_nested_state = NULL;
7980         }
7981
7982         /*
7983          * Only enable PML when hardware supports PML feature, and both EPT
7984          * and EPT A/D bit features are enabled -- PML depends on them to work.
7985          */
7986         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7987                 enable_pml = 0;
7988
7989         if (!enable_pml) {
7990                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7991                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7992                 kvm_x86_ops->flush_log_dirty = NULL;
7993                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7994         }
7995
7996         if (!cpu_has_vmx_preemption_timer())
7997                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7998
7999         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
8000                 u64 vmx_msr;
8001
8002                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
8003                 cpu_preemption_timer_multi =
8004                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
8005         } else {
8006                 kvm_x86_ops->set_hv_timer = NULL;
8007                 kvm_x86_ops->cancel_hv_timer = NULL;
8008         }
8009
8010         if (!cpu_has_vmx_shadow_vmcs())
8011                 enable_shadow_vmcs = 0;
8012         if (enable_shadow_vmcs)
8013                 init_vmcs_shadow_fields();
8014
8015         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
8016         nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
8017
8018         kvm_mce_cap_supported |= MCG_LMCE_P;
8019
8020         return alloc_kvm_area();
8021
8022 out:
8023         for (i = 0; i < VMX_BITMAP_NR; i++)
8024                 free_page((unsigned long)vmx_bitmap[i]);
8025
8026     return r;
8027 }
8028
8029 static __exit void hardware_unsetup(void)
8030 {
8031         int i;
8032
8033         for (i = 0; i < VMX_BITMAP_NR; i++)
8034                 free_page((unsigned long)vmx_bitmap[i]);
8035
8036         free_kvm_area();
8037 }
8038
8039 /*
8040  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
8041  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
8042  */
8043 static int handle_pause(struct kvm_vcpu *vcpu)
8044 {
8045         if (!kvm_pause_in_guest(vcpu->kvm))
8046                 grow_ple_window(vcpu);
8047
8048         /*
8049          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
8050          * VM-execution control is ignored if CPL > 0. OTOH, KVM
8051          * never set PAUSE_EXITING and just set PLE if supported,
8052          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
8053          */
8054         kvm_vcpu_on_spin(vcpu, true);
8055         return kvm_skip_emulated_instruction(vcpu);
8056 }
8057
8058 static int handle_nop(struct kvm_vcpu *vcpu)
8059 {
8060         return kvm_skip_emulated_instruction(vcpu);
8061 }
8062
8063 static int handle_mwait(struct kvm_vcpu *vcpu)
8064 {
8065         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
8066         return handle_nop(vcpu);
8067 }
8068
8069 static int handle_invalid_op(struct kvm_vcpu *vcpu)
8070 {
8071         kvm_queue_exception(vcpu, UD_VECTOR);
8072         return 1;
8073 }
8074
8075 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
8076 {
8077         return 1;
8078 }
8079
8080 static int handle_monitor(struct kvm_vcpu *vcpu)
8081 {
8082         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
8083         return handle_nop(vcpu);
8084 }
8085
8086 /*
8087  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
8088  * set the success or error code of an emulated VMX instruction, as specified
8089  * by Vol 2B, VMX Instruction Reference, "Conventions".
8090  */
8091 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
8092 {
8093         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
8094                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8095                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
8096 }
8097
8098 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
8099 {
8100         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8101                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
8102                             X86_EFLAGS_SF | X86_EFLAGS_OF))
8103                         | X86_EFLAGS_CF);
8104 }
8105
8106 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
8107                                         u32 vm_instruction_error)
8108 {
8109         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
8110                 /*
8111                  * failValid writes the error number to the current VMCS, which
8112                  * can't be done there isn't a current VMCS.
8113                  */
8114                 nested_vmx_failInvalid(vcpu);
8115                 return;
8116         }
8117         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8118                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8119                             X86_EFLAGS_SF | X86_EFLAGS_OF))
8120                         | X86_EFLAGS_ZF);
8121         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
8122         /*
8123          * We don't need to force a shadow sync because
8124          * VM_INSTRUCTION_ERROR is not shadowed
8125          */
8126 }
8127
8128 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
8129 {
8130         /* TODO: not to reset guest simply here. */
8131         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8132         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
8133 }
8134
8135 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
8136 {
8137         struct vcpu_vmx *vmx =
8138                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
8139
8140         vmx->nested.preemption_timer_expired = true;
8141         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
8142         kvm_vcpu_kick(&vmx->vcpu);
8143
8144         return HRTIMER_NORESTART;
8145 }
8146
8147 /*
8148  * Decode the memory-address operand of a vmx instruction, as recorded on an
8149  * exit caused by such an instruction (run by a guest hypervisor).
8150  * On success, returns 0. When the operand is invalid, returns 1 and throws
8151  * #UD or #GP.
8152  */
8153 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
8154                                  unsigned long exit_qualification,
8155                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
8156 {
8157         gva_t off;
8158         bool exn;
8159         struct kvm_segment s;
8160
8161         /*
8162          * According to Vol. 3B, "Information for VM Exits Due to Instruction
8163          * Execution", on an exit, vmx_instruction_info holds most of the
8164          * addressing components of the operand. Only the displacement part
8165          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
8166          * For how an actual address is calculated from all these components,
8167          * refer to Vol. 1, "Operand Addressing".
8168          */
8169         int  scaling = vmx_instruction_info & 3;
8170         int  addr_size = (vmx_instruction_info >> 7) & 7;
8171         bool is_reg = vmx_instruction_info & (1u << 10);
8172         int  seg_reg = (vmx_instruction_info >> 15) & 7;
8173         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
8174         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
8175         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
8176         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
8177
8178         if (is_reg) {
8179                 kvm_queue_exception(vcpu, UD_VECTOR);
8180                 return 1;
8181         }
8182
8183         /* Addr = segment_base + offset */
8184         /* offset = base + [index * scale] + displacement */
8185         off = exit_qualification; /* holds the displacement */
8186         if (base_is_valid)
8187                 off += kvm_register_read(vcpu, base_reg);
8188         if (index_is_valid)
8189                 off += kvm_register_read(vcpu, index_reg)<<scaling;
8190         vmx_get_segment(vcpu, &s, seg_reg);
8191         *ret = s.base + off;
8192
8193         if (addr_size == 1) /* 32 bit */
8194                 *ret &= 0xffffffff;
8195
8196         /* Checks for #GP/#SS exceptions. */
8197         exn = false;
8198         if (is_long_mode(vcpu)) {
8199                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
8200                  * non-canonical form. This is the only check on the memory
8201                  * destination for long mode!
8202                  */
8203                 exn = is_noncanonical_address(*ret, vcpu);
8204         } else if (is_protmode(vcpu)) {
8205                 /* Protected mode: apply checks for segment validity in the
8206                  * following order:
8207                  * - segment type check (#GP(0) may be thrown)
8208                  * - usability check (#GP(0)/#SS(0))
8209                  * - limit check (#GP(0)/#SS(0))
8210                  */
8211                 if (wr)
8212                         /* #GP(0) if the destination operand is located in a
8213                          * read-only data segment or any code segment.
8214                          */
8215                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
8216                 else
8217                         /* #GP(0) if the source operand is located in an
8218                          * execute-only code segment
8219                          */
8220                         exn = ((s.type & 0xa) == 8);
8221                 if (exn) {
8222                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8223                         return 1;
8224                 }
8225                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
8226                  */
8227                 exn = (s.unusable != 0);
8228                 /* Protected mode: #GP(0)/#SS(0) if the memory
8229                  * operand is outside the segment limit.
8230                  */
8231                 exn = exn || (off + sizeof(u64) > s.limit);
8232         }
8233         if (exn) {
8234                 kvm_queue_exception_e(vcpu,
8235                                       seg_reg == VCPU_SREG_SS ?
8236                                                 SS_VECTOR : GP_VECTOR,
8237                                       0);
8238                 return 1;
8239         }
8240
8241         return 0;
8242 }
8243
8244 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
8245 {
8246         gva_t gva;
8247         struct x86_exception e;
8248
8249         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8250                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
8251                 return 1;
8252
8253         if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
8254                 kvm_inject_page_fault(vcpu, &e);
8255                 return 1;
8256         }
8257
8258         return 0;
8259 }
8260
8261 /*
8262  * Allocate a shadow VMCS and associate it with the currently loaded
8263  * VMCS, unless such a shadow VMCS already exists. The newly allocated
8264  * VMCS is also VMCLEARed, so that it is ready for use.
8265  */
8266 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
8267 {
8268         struct vcpu_vmx *vmx = to_vmx(vcpu);
8269         struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
8270
8271         /*
8272          * We should allocate a shadow vmcs for vmcs01 only when L1
8273          * executes VMXON and free it when L1 executes VMXOFF.
8274          * As it is invalid to execute VMXON twice, we shouldn't reach
8275          * here when vmcs01 already have an allocated shadow vmcs.
8276          */
8277         WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs);
8278
8279         if (!loaded_vmcs->shadow_vmcs) {
8280                 loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
8281                 if (loaded_vmcs->shadow_vmcs)
8282                         vmcs_clear(loaded_vmcs->shadow_vmcs);
8283         }
8284         return loaded_vmcs->shadow_vmcs;
8285 }
8286
8287 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
8288 {
8289         struct vcpu_vmx *vmx = to_vmx(vcpu);
8290         int r;
8291
8292         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
8293         if (r < 0)
8294                 goto out_vmcs02;
8295
8296         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8297         if (!vmx->nested.cached_vmcs12)
8298                 goto out_cached_vmcs12;
8299
8300         vmx->nested.cached_shadow_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8301         if (!vmx->nested.cached_shadow_vmcs12)
8302                 goto out_cached_shadow_vmcs12;
8303
8304         if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
8305                 goto out_shadow_vmcs;
8306
8307         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
8308                      HRTIMER_MODE_REL_PINNED);
8309         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
8310
8311         vmx->nested.vpid02 = allocate_vpid();
8312
8313         vmx->nested.vmxon = true;
8314         return 0;
8315
8316 out_shadow_vmcs:
8317         kfree(vmx->nested.cached_shadow_vmcs12);
8318
8319 out_cached_shadow_vmcs12:
8320         kfree(vmx->nested.cached_vmcs12);
8321
8322 out_cached_vmcs12:
8323         free_loaded_vmcs(&vmx->nested.vmcs02);
8324
8325 out_vmcs02:
8326         return -ENOMEM;
8327 }
8328
8329 /*
8330  * Emulate the VMXON instruction.
8331  * Currently, we just remember that VMX is active, and do not save or even
8332  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
8333  * do not currently need to store anything in that guest-allocated memory
8334  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
8335  * argument is different from the VMXON pointer (which the spec says they do).
8336  */
8337 static int handle_vmon(struct kvm_vcpu *vcpu)
8338 {
8339         int ret;
8340         gpa_t vmptr;
8341         struct page *page;
8342         struct vcpu_vmx *vmx = to_vmx(vcpu);
8343         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
8344                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8345
8346         /*
8347          * The Intel VMX Instruction Reference lists a bunch of bits that are
8348          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
8349          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
8350          * Otherwise, we should fail with #UD.  But most faulting conditions
8351          * have already been checked by hardware, prior to the VM-exit for
8352          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
8353          * that bit set to 1 in non-root mode.
8354          */
8355         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
8356                 kvm_queue_exception(vcpu, UD_VECTOR);
8357                 return 1;
8358         }
8359
8360         /* CPL=0 must be checked manually. */
8361         if (vmx_get_cpl(vcpu)) {
8362                 kvm_inject_gp(vcpu, 0);
8363                 return 1;
8364         }
8365
8366         if (vmx->nested.vmxon) {
8367                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
8368                 return kvm_skip_emulated_instruction(vcpu);
8369         }
8370
8371         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
8372                         != VMXON_NEEDED_FEATURES) {
8373                 kvm_inject_gp(vcpu, 0);
8374                 return 1;
8375         }
8376
8377         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8378                 return 1;
8379
8380         /*
8381          * SDM 3: 24.11.5
8382          * The first 4 bytes of VMXON region contain the supported
8383          * VMCS revision identifier
8384          *
8385          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
8386          * which replaces physical address width with 32
8387          */
8388         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8389                 nested_vmx_failInvalid(vcpu);
8390                 return kvm_skip_emulated_instruction(vcpu);
8391         }
8392
8393         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8394         if (is_error_page(page)) {
8395                 nested_vmx_failInvalid(vcpu);
8396                 return kvm_skip_emulated_instruction(vcpu);
8397         }
8398         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
8399                 kunmap(page);
8400                 kvm_release_page_clean(page);
8401                 nested_vmx_failInvalid(vcpu);
8402                 return kvm_skip_emulated_instruction(vcpu);
8403         }
8404         kunmap(page);
8405         kvm_release_page_clean(page);
8406
8407         vmx->nested.vmxon_ptr = vmptr;
8408         ret = enter_vmx_operation(vcpu);
8409         if (ret)
8410                 return ret;
8411
8412         nested_vmx_succeed(vcpu);
8413         return kvm_skip_emulated_instruction(vcpu);
8414 }
8415
8416 /*
8417  * Intel's VMX Instruction Reference specifies a common set of prerequisites
8418  * for running VMX instructions (except VMXON, whose prerequisites are
8419  * slightly different). It also specifies what exception to inject otherwise.
8420  * Note that many of these exceptions have priority over VM exits, so they
8421  * don't have to be checked again here.
8422  */
8423 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
8424 {
8425         if (!to_vmx(vcpu)->nested.vmxon) {
8426                 kvm_queue_exception(vcpu, UD_VECTOR);
8427                 return 0;
8428         }
8429
8430         if (vmx_get_cpl(vcpu)) {
8431                 kvm_inject_gp(vcpu, 0);
8432                 return 0;
8433         }
8434
8435         return 1;
8436 }
8437
8438 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
8439 {
8440         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
8441         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8442 }
8443
8444 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
8445 {
8446         if (vmx->nested.current_vmptr == -1ull)
8447                 return;
8448
8449         if (enable_shadow_vmcs) {
8450                 /* copy to memory all shadowed fields in case
8451                    they were modified */
8452                 copy_shadow_to_vmcs12(vmx);
8453                 vmx->nested.sync_shadow_vmcs = false;
8454                 vmx_disable_shadow_vmcs(vmx);
8455         }
8456         vmx->nested.posted_intr_nv = -1;
8457
8458         /* Flush VMCS12 to guest memory */
8459         kvm_vcpu_write_guest_page(&vmx->vcpu,
8460                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
8461                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8462
8463         vmx->nested.current_vmptr = -1ull;
8464 }
8465
8466 /*
8467  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8468  * just stops using VMX.
8469  */
8470 static void free_nested(struct vcpu_vmx *vmx)
8471 {
8472         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8473                 return;
8474
8475         vmx->nested.vmxon = false;
8476         vmx->nested.smm.vmxon = false;
8477         free_vpid(vmx->nested.vpid02);
8478         vmx->nested.posted_intr_nv = -1;
8479         vmx->nested.current_vmptr = -1ull;
8480         if (enable_shadow_vmcs) {
8481                 vmx_disable_shadow_vmcs(vmx);
8482                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8483                 free_vmcs(vmx->vmcs01.shadow_vmcs);
8484                 vmx->vmcs01.shadow_vmcs = NULL;
8485         }
8486         kfree(vmx->nested.cached_vmcs12);
8487         kfree(vmx->nested.cached_shadow_vmcs12);
8488         /* Unpin physical memory we referred to in the vmcs02 */
8489         if (vmx->nested.apic_access_page) {
8490                 kvm_release_page_dirty(vmx->nested.apic_access_page);
8491                 vmx->nested.apic_access_page = NULL;
8492         }
8493         if (vmx->nested.virtual_apic_page) {
8494                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8495                 vmx->nested.virtual_apic_page = NULL;
8496         }
8497         if (vmx->nested.pi_desc_page) {
8498                 kunmap(vmx->nested.pi_desc_page);
8499                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8500                 vmx->nested.pi_desc_page = NULL;
8501                 vmx->nested.pi_desc = NULL;
8502         }
8503
8504         free_loaded_vmcs(&vmx->nested.vmcs02);
8505 }
8506
8507 /* Emulate the VMXOFF instruction */
8508 static int handle_vmoff(struct kvm_vcpu *vcpu)
8509 {
8510         if (!nested_vmx_check_permission(vcpu))
8511                 return 1;
8512         free_nested(to_vmx(vcpu));
8513         nested_vmx_succeed(vcpu);
8514         return kvm_skip_emulated_instruction(vcpu);
8515 }
8516
8517 /* Emulate the VMCLEAR instruction */
8518 static int handle_vmclear(struct kvm_vcpu *vcpu)
8519 {
8520         struct vcpu_vmx *vmx = to_vmx(vcpu);
8521         u32 zero = 0;
8522         gpa_t vmptr;
8523
8524         if (!nested_vmx_check_permission(vcpu))
8525                 return 1;
8526
8527         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8528                 return 1;
8529
8530         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8531                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
8532                 return kvm_skip_emulated_instruction(vcpu);
8533         }
8534
8535         if (vmptr == vmx->nested.vmxon_ptr) {
8536                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
8537                 return kvm_skip_emulated_instruction(vcpu);
8538         }
8539
8540         if (vmptr == vmx->nested.current_vmptr)
8541                 nested_release_vmcs12(vmx);
8542
8543         kvm_vcpu_write_guest(vcpu,
8544                         vmptr + offsetof(struct vmcs12, launch_state),
8545                         &zero, sizeof(zero));
8546
8547         nested_vmx_succeed(vcpu);
8548         return kvm_skip_emulated_instruction(vcpu);
8549 }
8550
8551 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8552
8553 /* Emulate the VMLAUNCH instruction */
8554 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8555 {
8556         return nested_vmx_run(vcpu, true);
8557 }
8558
8559 /* Emulate the VMRESUME instruction */
8560 static int handle_vmresume(struct kvm_vcpu *vcpu)
8561 {
8562
8563         return nested_vmx_run(vcpu, false);
8564 }
8565
8566 /*
8567  * Read a vmcs12 field. Since these can have varying lengths and we return
8568  * one type, we chose the biggest type (u64) and zero-extend the return value
8569  * to that size. Note that the caller, handle_vmread, might need to use only
8570  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8571  * 64-bit fields are to be returned).
8572  */
8573 static inline int vmcs12_read_any(struct vmcs12 *vmcs12,
8574                                   unsigned long field, u64 *ret)
8575 {
8576         short offset = vmcs_field_to_offset(field);
8577         char *p;
8578
8579         if (offset < 0)
8580                 return offset;
8581
8582         p = (char *)vmcs12 + offset;
8583
8584         switch (vmcs_field_width(field)) {
8585         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8586                 *ret = *((natural_width *)p);
8587                 return 0;
8588         case VMCS_FIELD_WIDTH_U16:
8589                 *ret = *((u16 *)p);
8590                 return 0;
8591         case VMCS_FIELD_WIDTH_U32:
8592                 *ret = *((u32 *)p);
8593                 return 0;
8594         case VMCS_FIELD_WIDTH_U64:
8595                 *ret = *((u64 *)p);
8596                 return 0;
8597         default:
8598                 WARN_ON(1);
8599                 return -ENOENT;
8600         }
8601 }
8602
8603
8604 static inline int vmcs12_write_any(struct vmcs12 *vmcs12,
8605                                    unsigned long field, u64 field_value){
8606         short offset = vmcs_field_to_offset(field);
8607         char *p = (char *)vmcs12 + offset;
8608         if (offset < 0)
8609                 return offset;
8610
8611         switch (vmcs_field_width(field)) {
8612         case VMCS_FIELD_WIDTH_U16:
8613                 *(u16 *)p = field_value;
8614                 return 0;
8615         case VMCS_FIELD_WIDTH_U32:
8616                 *(u32 *)p = field_value;
8617                 return 0;
8618         case VMCS_FIELD_WIDTH_U64:
8619                 *(u64 *)p = field_value;
8620                 return 0;
8621         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8622                 *(natural_width *)p = field_value;
8623                 return 0;
8624         default:
8625                 WARN_ON(1);
8626                 return -ENOENT;
8627         }
8628
8629 }
8630
8631 /*
8632  * Copy the writable VMCS shadow fields back to the VMCS12, in case
8633  * they have been modified by the L1 guest. Note that the "read-only"
8634  * VM-exit information fields are actually writable if the vCPU is
8635  * configured to support "VMWRITE to any supported field in the VMCS."
8636  */
8637 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8638 {
8639         const u16 *fields[] = {
8640                 shadow_read_write_fields,
8641                 shadow_read_only_fields
8642         };
8643         const int max_fields[] = {
8644                 max_shadow_read_write_fields,
8645                 max_shadow_read_only_fields
8646         };
8647         int i, q;
8648         unsigned long field;
8649         u64 field_value;
8650         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8651
8652         preempt_disable();
8653
8654         vmcs_load(shadow_vmcs);
8655
8656         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8657                 for (i = 0; i < max_fields[q]; i++) {
8658                         field = fields[q][i];
8659                         field_value = __vmcs_readl(field);
8660                         vmcs12_write_any(get_vmcs12(&vmx->vcpu), field, field_value);
8661                 }
8662                 /*
8663                  * Skip the VM-exit information fields if they are read-only.
8664                  */
8665                 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8666                         break;
8667         }
8668
8669         vmcs_clear(shadow_vmcs);
8670         vmcs_load(vmx->loaded_vmcs->vmcs);
8671
8672         preempt_enable();
8673 }
8674
8675 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8676 {
8677         const u16 *fields[] = {
8678                 shadow_read_write_fields,
8679                 shadow_read_only_fields
8680         };
8681         const int max_fields[] = {
8682                 max_shadow_read_write_fields,
8683                 max_shadow_read_only_fields
8684         };
8685         int i, q;
8686         unsigned long field;
8687         u64 field_value = 0;
8688         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8689
8690         vmcs_load(shadow_vmcs);
8691
8692         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8693                 for (i = 0; i < max_fields[q]; i++) {
8694                         field = fields[q][i];
8695                         vmcs12_read_any(get_vmcs12(&vmx->vcpu), field, &field_value);
8696                         __vmcs_writel(field, field_value);
8697                 }
8698         }
8699
8700         vmcs_clear(shadow_vmcs);
8701         vmcs_load(vmx->loaded_vmcs->vmcs);
8702 }
8703
8704 /*
8705  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8706  * used before) all generate the same failure when it is missing.
8707  */
8708 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8709 {
8710         struct vcpu_vmx *vmx = to_vmx(vcpu);
8711         if (vmx->nested.current_vmptr == -1ull) {
8712                 nested_vmx_failInvalid(vcpu);
8713                 return 0;
8714         }
8715         return 1;
8716 }
8717
8718 static int handle_vmread(struct kvm_vcpu *vcpu)
8719 {
8720         unsigned long field;
8721         u64 field_value;
8722         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8723         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8724         gva_t gva = 0;
8725         struct vmcs12 *vmcs12;
8726
8727         if (!nested_vmx_check_permission(vcpu))
8728                 return 1;
8729
8730         if (!nested_vmx_check_vmcs12(vcpu))
8731                 return kvm_skip_emulated_instruction(vcpu);
8732
8733         if (!is_guest_mode(vcpu))
8734                 vmcs12 = get_vmcs12(vcpu);
8735         else {
8736                 /*
8737                  * When vmcs->vmcs_link_pointer is -1ull, any VMREAD
8738                  * to shadowed-field sets the ALU flags for VMfailInvalid.
8739                  */
8740                 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull) {
8741                         nested_vmx_failInvalid(vcpu);
8742                         return kvm_skip_emulated_instruction(vcpu);
8743                 }
8744                 vmcs12 = get_shadow_vmcs12(vcpu);
8745         }
8746
8747         /* Decode instruction info and find the field to read */
8748         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8749         /* Read the field, zero-extended to a u64 field_value */
8750         if (vmcs12_read_any(vmcs12, field, &field_value) < 0) {
8751                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8752                 return kvm_skip_emulated_instruction(vcpu);
8753         }
8754         /*
8755          * Now copy part of this value to register or memory, as requested.
8756          * Note that the number of bits actually copied is 32 or 64 depending
8757          * on the guest's mode (32 or 64 bit), not on the given field's length.
8758          */
8759         if (vmx_instruction_info & (1u << 10)) {
8760                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8761                         field_value);
8762         } else {
8763                 if (get_vmx_mem_address(vcpu, exit_qualification,
8764                                 vmx_instruction_info, true, &gva))
8765                         return 1;
8766                 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8767                 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8768                                             (is_long_mode(vcpu) ? 8 : 4), NULL);
8769         }
8770
8771         nested_vmx_succeed(vcpu);
8772         return kvm_skip_emulated_instruction(vcpu);
8773 }
8774
8775
8776 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8777 {
8778         unsigned long field;
8779         gva_t gva;
8780         struct vcpu_vmx *vmx = to_vmx(vcpu);
8781         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8782         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8783
8784         /* The value to write might be 32 or 64 bits, depending on L1's long
8785          * mode, and eventually we need to write that into a field of several
8786          * possible lengths. The code below first zero-extends the value to 64
8787          * bit (field_value), and then copies only the appropriate number of
8788          * bits into the vmcs12 field.
8789          */
8790         u64 field_value = 0;
8791         struct x86_exception e;
8792         struct vmcs12 *vmcs12;
8793
8794         if (!nested_vmx_check_permission(vcpu))
8795                 return 1;
8796
8797         if (!nested_vmx_check_vmcs12(vcpu))
8798                 return kvm_skip_emulated_instruction(vcpu);
8799
8800         if (vmx_instruction_info & (1u << 10))
8801                 field_value = kvm_register_readl(vcpu,
8802                         (((vmx_instruction_info) >> 3) & 0xf));
8803         else {
8804                 if (get_vmx_mem_address(vcpu, exit_qualification,
8805                                 vmx_instruction_info, false, &gva))
8806                         return 1;
8807                 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8808                                         (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8809                         kvm_inject_page_fault(vcpu, &e);
8810                         return 1;
8811                 }
8812         }
8813
8814
8815         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8816         /*
8817          * If the vCPU supports "VMWRITE to any supported field in the
8818          * VMCS," then the "read-only" fields are actually read/write.
8819          */
8820         if (vmcs_field_readonly(field) &&
8821             !nested_cpu_has_vmwrite_any_field(vcpu)) {
8822                 nested_vmx_failValid(vcpu,
8823                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8824                 return kvm_skip_emulated_instruction(vcpu);
8825         }
8826
8827         if (!is_guest_mode(vcpu))
8828                 vmcs12 = get_vmcs12(vcpu);
8829         else {
8830                 /*
8831                  * When vmcs->vmcs_link_pointer is -1ull, any VMWRITE
8832                  * to shadowed-field sets the ALU flags for VMfailInvalid.
8833                  */
8834                 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull) {
8835                         nested_vmx_failInvalid(vcpu);
8836                         return kvm_skip_emulated_instruction(vcpu);
8837                 }
8838                 vmcs12 = get_shadow_vmcs12(vcpu);
8839
8840         }
8841
8842         if (vmcs12_write_any(vmcs12, field, field_value) < 0) {
8843                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8844                 return kvm_skip_emulated_instruction(vcpu);
8845         }
8846
8847         /*
8848          * Do not track vmcs12 dirty-state if in guest-mode
8849          * as we actually dirty shadow vmcs12 instead of vmcs12.
8850          */
8851         if (!is_guest_mode(vcpu)) {
8852                 switch (field) {
8853 #define SHADOW_FIELD_RW(x) case x:
8854 #include "vmx_shadow_fields.h"
8855                         /*
8856                          * The fields that can be updated by L1 without a vmexit are
8857                          * always updated in the vmcs02, the others go down the slow
8858                          * path of prepare_vmcs02.
8859                          */
8860                         break;
8861                 default:
8862                         vmx->nested.dirty_vmcs12 = true;
8863                         break;
8864                 }
8865         }
8866
8867         nested_vmx_succeed(vcpu);
8868         return kvm_skip_emulated_instruction(vcpu);
8869 }
8870
8871 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8872 {
8873         vmx->nested.current_vmptr = vmptr;
8874         if (enable_shadow_vmcs) {
8875                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8876                               SECONDARY_EXEC_SHADOW_VMCS);
8877                 vmcs_write64(VMCS_LINK_POINTER,
8878                              __pa(vmx->vmcs01.shadow_vmcs));
8879                 vmx->nested.sync_shadow_vmcs = true;
8880         }
8881         vmx->nested.dirty_vmcs12 = true;
8882 }
8883
8884 /* Emulate the VMPTRLD instruction */
8885 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8886 {
8887         struct vcpu_vmx *vmx = to_vmx(vcpu);
8888         gpa_t vmptr;
8889
8890         if (!nested_vmx_check_permission(vcpu))
8891                 return 1;
8892
8893         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8894                 return 1;
8895
8896         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8897                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8898                 return kvm_skip_emulated_instruction(vcpu);
8899         }
8900
8901         if (vmptr == vmx->nested.vmxon_ptr) {
8902                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8903                 return kvm_skip_emulated_instruction(vcpu);
8904         }
8905
8906         if (vmx->nested.current_vmptr != vmptr) {
8907                 struct vmcs12 *new_vmcs12;
8908                 struct page *page;
8909                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8910                 if (is_error_page(page)) {
8911                         nested_vmx_failInvalid(vcpu);
8912                         return kvm_skip_emulated_instruction(vcpu);
8913                 }
8914                 new_vmcs12 = kmap(page);
8915                 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION ||
8916                     (new_vmcs12->hdr.shadow_vmcs &&
8917                      !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
8918                         kunmap(page);
8919                         kvm_release_page_clean(page);
8920                         nested_vmx_failValid(vcpu,
8921                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8922                         return kvm_skip_emulated_instruction(vcpu);
8923                 }
8924
8925                 nested_release_vmcs12(vmx);
8926                 /*
8927                  * Load VMCS12 from guest memory since it is not already
8928                  * cached.
8929                  */
8930                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8931                 kunmap(page);
8932                 kvm_release_page_clean(page);
8933
8934                 set_current_vmptr(vmx, vmptr);
8935         }
8936
8937         nested_vmx_succeed(vcpu);
8938         return kvm_skip_emulated_instruction(vcpu);
8939 }
8940
8941 /* Emulate the VMPTRST instruction */
8942 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8943 {
8944         unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION);
8945         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8946         gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
8947         struct x86_exception e;
8948         gva_t gva;
8949
8950         if (!nested_vmx_check_permission(vcpu))
8951                 return 1;
8952
8953         if (get_vmx_mem_address(vcpu, exit_qual, instr_info, true, &gva))
8954                 return 1;
8955         /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8956         if (kvm_write_guest_virt_system(vcpu, gva, (void *)&current_vmptr,
8957                                         sizeof(gpa_t), &e)) {
8958                 kvm_inject_page_fault(vcpu, &e);
8959                 return 1;
8960         }
8961         nested_vmx_succeed(vcpu);
8962         return kvm_skip_emulated_instruction(vcpu);
8963 }
8964
8965 /* Emulate the INVEPT instruction */
8966 static int handle_invept(struct kvm_vcpu *vcpu)
8967 {
8968         struct vcpu_vmx *vmx = to_vmx(vcpu);
8969         u32 vmx_instruction_info, types;
8970         unsigned long type;
8971         gva_t gva;
8972         struct x86_exception e;
8973         struct {
8974                 u64 eptp, gpa;
8975         } operand;
8976
8977         if (!(vmx->nested.msrs.secondary_ctls_high &
8978               SECONDARY_EXEC_ENABLE_EPT) ||
8979             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8980                 kvm_queue_exception(vcpu, UD_VECTOR);
8981                 return 1;
8982         }
8983
8984         if (!nested_vmx_check_permission(vcpu))
8985                 return 1;
8986
8987         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8988         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8989
8990         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8991
8992         if (type >= 32 || !(types & (1 << type))) {
8993                 nested_vmx_failValid(vcpu,
8994                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8995                 return kvm_skip_emulated_instruction(vcpu);
8996         }
8997
8998         /* According to the Intel VMX instruction reference, the memory
8999          * operand is read even if it isn't needed (e.g., for type==global)
9000          */
9001         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9002                         vmx_instruction_info, false, &gva))
9003                 return 1;
9004         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9005                 kvm_inject_page_fault(vcpu, &e);
9006                 return 1;
9007         }
9008
9009         switch (type) {
9010         case VMX_EPT_EXTENT_GLOBAL:
9011         /*
9012          * TODO: track mappings and invalidate
9013          * single context requests appropriately
9014          */
9015         case VMX_EPT_EXTENT_CONTEXT:
9016                 kvm_mmu_sync_roots(vcpu);
9017                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
9018                 nested_vmx_succeed(vcpu);
9019                 break;
9020         default:
9021                 BUG_ON(1);
9022                 break;
9023         }
9024
9025         return kvm_skip_emulated_instruction(vcpu);
9026 }
9027
9028 static int handle_invvpid(struct kvm_vcpu *vcpu)
9029 {
9030         struct vcpu_vmx *vmx = to_vmx(vcpu);
9031         u32 vmx_instruction_info;
9032         unsigned long type, types;
9033         gva_t gva;
9034         struct x86_exception e;
9035         struct {
9036                 u64 vpid;
9037                 u64 gla;
9038         } operand;
9039
9040         if (!(vmx->nested.msrs.secondary_ctls_high &
9041               SECONDARY_EXEC_ENABLE_VPID) ||
9042                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
9043                 kvm_queue_exception(vcpu, UD_VECTOR);
9044                 return 1;
9045         }
9046
9047         if (!nested_vmx_check_permission(vcpu))
9048                 return 1;
9049
9050         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9051         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9052
9053         types = (vmx->nested.msrs.vpid_caps &
9054                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
9055
9056         if (type >= 32 || !(types & (1 << type))) {
9057                 nested_vmx_failValid(vcpu,
9058                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9059                 return kvm_skip_emulated_instruction(vcpu);
9060         }
9061
9062         /* according to the intel vmx instruction reference, the memory
9063          * operand is read even if it isn't needed (e.g., for type==global)
9064          */
9065         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9066                         vmx_instruction_info, false, &gva))
9067                 return 1;
9068         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9069                 kvm_inject_page_fault(vcpu, &e);
9070                 return 1;
9071         }
9072         if (operand.vpid >> 16) {
9073                 nested_vmx_failValid(vcpu,
9074                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9075                 return kvm_skip_emulated_instruction(vcpu);
9076         }
9077
9078         switch (type) {
9079         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
9080                 if (!operand.vpid ||
9081                     is_noncanonical_address(operand.gla, vcpu)) {
9082                         nested_vmx_failValid(vcpu,
9083                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9084                         return kvm_skip_emulated_instruction(vcpu);
9085                 }
9086                 if (cpu_has_vmx_invvpid_individual_addr() &&
9087                     vmx->nested.vpid02) {
9088                         __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
9089                                 vmx->nested.vpid02, operand.gla);
9090                 } else
9091                         __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9092                 break;
9093         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
9094         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
9095                 if (!operand.vpid) {
9096                         nested_vmx_failValid(vcpu,
9097                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9098                         return kvm_skip_emulated_instruction(vcpu);
9099                 }
9100                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9101                 break;
9102         case VMX_VPID_EXTENT_ALL_CONTEXT:
9103                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9104                 break;
9105         default:
9106                 WARN_ON_ONCE(1);
9107                 return kvm_skip_emulated_instruction(vcpu);
9108         }
9109
9110         nested_vmx_succeed(vcpu);
9111
9112         return kvm_skip_emulated_instruction(vcpu);
9113 }
9114
9115 static int handle_invpcid(struct kvm_vcpu *vcpu)
9116 {
9117         u32 vmx_instruction_info;
9118         unsigned long type;
9119         bool pcid_enabled;
9120         gva_t gva;
9121         struct x86_exception e;
9122         unsigned i;
9123         unsigned long roots_to_free = 0;
9124         struct {
9125                 u64 pcid;
9126                 u64 gla;
9127         } operand;
9128
9129         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
9130                 kvm_queue_exception(vcpu, UD_VECTOR);
9131                 return 1;
9132         }
9133
9134         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9135         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9136
9137         if (type > 3) {
9138                 kvm_inject_gp(vcpu, 0);
9139                 return 1;
9140         }
9141
9142         /* According to the Intel instruction reference, the memory operand
9143          * is read even if it isn't needed (e.g., for type==all)
9144          */
9145         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9146                                 vmx_instruction_info, false, &gva))
9147                 return 1;
9148
9149         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9150                 kvm_inject_page_fault(vcpu, &e);
9151                 return 1;
9152         }
9153
9154         if (operand.pcid >> 12 != 0) {
9155                 kvm_inject_gp(vcpu, 0);
9156                 return 1;
9157         }
9158
9159         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
9160
9161         switch (type) {
9162         case INVPCID_TYPE_INDIV_ADDR:
9163                 if ((!pcid_enabled && (operand.pcid != 0)) ||
9164                     is_noncanonical_address(operand.gla, vcpu)) {
9165                         kvm_inject_gp(vcpu, 0);
9166                         return 1;
9167                 }
9168                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
9169                 return kvm_skip_emulated_instruction(vcpu);
9170
9171         case INVPCID_TYPE_SINGLE_CTXT:
9172                 if (!pcid_enabled && (operand.pcid != 0)) {
9173                         kvm_inject_gp(vcpu, 0);
9174                         return 1;
9175                 }
9176
9177                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
9178                         kvm_mmu_sync_roots(vcpu);
9179                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
9180                 }
9181
9182                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
9183                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu.prev_roots[i].cr3)
9184                             == operand.pcid)
9185                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
9186
9187                 kvm_mmu_free_roots(vcpu, roots_to_free);
9188                 /*
9189                  * If neither the current cr3 nor any of the prev_roots use the
9190                  * given PCID, then nothing needs to be done here because a
9191                  * resync will happen anyway before switching to any other CR3.
9192                  */
9193
9194                 return kvm_skip_emulated_instruction(vcpu);
9195
9196         case INVPCID_TYPE_ALL_NON_GLOBAL:
9197                 /*
9198                  * Currently, KVM doesn't mark global entries in the shadow
9199                  * page tables, so a non-global flush just degenerates to a
9200                  * global flush. If needed, we could optimize this later by
9201                  * keeping track of global entries in shadow page tables.
9202                  */
9203
9204                 /* fall-through */
9205         case INVPCID_TYPE_ALL_INCL_GLOBAL:
9206                 kvm_mmu_unload(vcpu);
9207                 return kvm_skip_emulated_instruction(vcpu);
9208
9209         default:
9210                 BUG(); /* We have already checked above that type <= 3 */
9211         }
9212 }
9213
9214 static int handle_pml_full(struct kvm_vcpu *vcpu)
9215 {
9216         unsigned long exit_qualification;
9217
9218         trace_kvm_pml_full(vcpu->vcpu_id);
9219
9220         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9221
9222         /*
9223          * PML buffer FULL happened while executing iret from NMI,
9224          * "blocked by NMI" bit has to be set before next VM entry.
9225          */
9226         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
9227                         enable_vnmi &&
9228                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
9229                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9230                                 GUEST_INTR_STATE_NMI);
9231
9232         /*
9233          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
9234          * here.., and there's no userspace involvement needed for PML.
9235          */
9236         return 1;
9237 }
9238
9239 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
9240 {
9241         if (!to_vmx(vcpu)->req_immediate_exit)
9242                 kvm_lapic_expired_hv_timer(vcpu);
9243         return 1;
9244 }
9245
9246 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
9247 {
9248         struct vcpu_vmx *vmx = to_vmx(vcpu);
9249         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9250
9251         /* Check for memory type validity */
9252         switch (address & VMX_EPTP_MT_MASK) {
9253         case VMX_EPTP_MT_UC:
9254                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
9255                         return false;
9256                 break;
9257         case VMX_EPTP_MT_WB:
9258                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
9259                         return false;
9260                 break;
9261         default:
9262                 return false;
9263         }
9264
9265         /* only 4 levels page-walk length are valid */
9266         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
9267                 return false;
9268
9269         /* Reserved bits should not be set */
9270         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
9271                 return false;
9272
9273         /* AD, if set, should be supported */
9274         if (address & VMX_EPTP_AD_ENABLE_BIT) {
9275                 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
9276                         return false;
9277         }
9278
9279         return true;
9280 }
9281
9282 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
9283                                      struct vmcs12 *vmcs12)
9284 {
9285         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
9286         u64 address;
9287         bool accessed_dirty;
9288         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
9289
9290         if (!nested_cpu_has_eptp_switching(vmcs12) ||
9291             !nested_cpu_has_ept(vmcs12))
9292                 return 1;
9293
9294         if (index >= VMFUNC_EPTP_ENTRIES)
9295                 return 1;
9296
9297
9298         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
9299                                      &address, index * 8, 8))
9300                 return 1;
9301
9302         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
9303
9304         /*
9305          * If the (L2) guest does a vmfunc to the currently
9306          * active ept pointer, we don't have to do anything else
9307          */
9308         if (vmcs12->ept_pointer != address) {
9309                 if (!valid_ept_address(vcpu, address))
9310                         return 1;
9311
9312                 kvm_mmu_unload(vcpu);
9313                 mmu->ept_ad = accessed_dirty;
9314                 mmu->base_role.ad_disabled = !accessed_dirty;
9315                 vmcs12->ept_pointer = address;
9316                 /*
9317                  * TODO: Check what's the correct approach in case
9318                  * mmu reload fails. Currently, we just let the next
9319                  * reload potentially fail
9320                  */
9321                 kvm_mmu_reload(vcpu);
9322         }
9323
9324         return 0;
9325 }
9326
9327 static int handle_vmfunc(struct kvm_vcpu *vcpu)
9328 {
9329         struct vcpu_vmx *vmx = to_vmx(vcpu);
9330         struct vmcs12 *vmcs12;
9331         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
9332
9333         /*
9334          * VMFUNC is only supported for nested guests, but we always enable the
9335          * secondary control for simplicity; for non-nested mode, fake that we
9336          * didn't by injecting #UD.
9337          */
9338         if (!is_guest_mode(vcpu)) {
9339                 kvm_queue_exception(vcpu, UD_VECTOR);
9340                 return 1;
9341         }
9342
9343         vmcs12 = get_vmcs12(vcpu);
9344         if ((vmcs12->vm_function_control & (1 << function)) == 0)
9345                 goto fail;
9346
9347         switch (function) {
9348         case 0:
9349                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
9350                         goto fail;
9351                 break;
9352         default:
9353                 goto fail;
9354         }
9355         return kvm_skip_emulated_instruction(vcpu);
9356
9357 fail:
9358         nested_vmx_vmexit(vcpu, vmx->exit_reason,
9359                           vmcs_read32(VM_EXIT_INTR_INFO),
9360                           vmcs_readl(EXIT_QUALIFICATION));
9361         return 1;
9362 }
9363
9364 static int handle_encls(struct kvm_vcpu *vcpu)
9365 {
9366         /*
9367          * SGX virtualization is not yet supported.  There is no software
9368          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
9369          * to prevent the guest from executing ENCLS.
9370          */
9371         kvm_queue_exception(vcpu, UD_VECTOR);
9372         return 1;
9373 }
9374
9375 /*
9376  * The exit handlers return 1 if the exit was handled fully and guest execution
9377  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
9378  * to be done to userspace and return 0.
9379  */
9380 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
9381         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
9382         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
9383         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
9384         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
9385         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
9386         [EXIT_REASON_CR_ACCESS]               = handle_cr,
9387         [EXIT_REASON_DR_ACCESS]               = handle_dr,
9388         [EXIT_REASON_CPUID]                   = handle_cpuid,
9389         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
9390         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
9391         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
9392         [EXIT_REASON_HLT]                     = handle_halt,
9393         [EXIT_REASON_INVD]                    = handle_invd,
9394         [EXIT_REASON_INVLPG]                  = handle_invlpg,
9395         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
9396         [EXIT_REASON_VMCALL]                  = handle_vmcall,
9397         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
9398         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
9399         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
9400         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
9401         [EXIT_REASON_VMREAD]                  = handle_vmread,
9402         [EXIT_REASON_VMRESUME]                = handle_vmresume,
9403         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
9404         [EXIT_REASON_VMOFF]                   = handle_vmoff,
9405         [EXIT_REASON_VMON]                    = handle_vmon,
9406         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
9407         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
9408         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
9409         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
9410         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
9411         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
9412         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
9413         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
9414         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
9415         [EXIT_REASON_LDTR_TR]                 = handle_desc,
9416         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
9417         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
9418         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
9419         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
9420         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
9421         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
9422         [EXIT_REASON_INVEPT]                  = handle_invept,
9423         [EXIT_REASON_INVVPID]                 = handle_invvpid,
9424         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
9425         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
9426         [EXIT_REASON_XSAVES]                  = handle_xsaves,
9427         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
9428         [EXIT_REASON_PML_FULL]                = handle_pml_full,
9429         [EXIT_REASON_INVPCID]                 = handle_invpcid,
9430         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
9431         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
9432         [EXIT_REASON_ENCLS]                   = handle_encls,
9433 };
9434
9435 static const int kvm_vmx_max_exit_handlers =
9436         ARRAY_SIZE(kvm_vmx_exit_handlers);
9437
9438 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
9439                                        struct vmcs12 *vmcs12)
9440 {
9441         unsigned long exit_qualification;
9442         gpa_t bitmap, last_bitmap;
9443         unsigned int port;
9444         int size;
9445         u8 b;
9446
9447         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9448                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
9449
9450         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9451
9452         port = exit_qualification >> 16;
9453         size = (exit_qualification & 7) + 1;
9454
9455         last_bitmap = (gpa_t)-1;
9456         b = -1;
9457
9458         while (size > 0) {
9459                 if (port < 0x8000)
9460                         bitmap = vmcs12->io_bitmap_a;
9461                 else if (port < 0x10000)
9462                         bitmap = vmcs12->io_bitmap_b;
9463                 else
9464                         return true;
9465                 bitmap += (port & 0x7fff) / 8;
9466
9467                 if (last_bitmap != bitmap)
9468                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
9469                                 return true;
9470                 if (b & (1 << (port & 7)))
9471                         return true;
9472
9473                 port++;
9474                 size--;
9475                 last_bitmap = bitmap;
9476         }
9477
9478         return false;
9479 }
9480
9481 /*
9482  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
9483  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
9484  * disinterest in the current event (read or write a specific MSR) by using an
9485  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
9486  */
9487 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
9488         struct vmcs12 *vmcs12, u32 exit_reason)
9489 {
9490         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
9491         gpa_t bitmap;
9492
9493         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9494                 return true;
9495
9496         /*
9497          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
9498          * for the four combinations of read/write and low/high MSR numbers.
9499          * First we need to figure out which of the four to use:
9500          */
9501         bitmap = vmcs12->msr_bitmap;
9502         if (exit_reason == EXIT_REASON_MSR_WRITE)
9503                 bitmap += 2048;
9504         if (msr_index >= 0xc0000000) {
9505                 msr_index -= 0xc0000000;
9506                 bitmap += 1024;
9507         }
9508
9509         /* Then read the msr_index'th bit from this bitmap: */
9510         if (msr_index < 1024*8) {
9511                 unsigned char b;
9512                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
9513                         return true;
9514                 return 1 & (b >> (msr_index & 7));
9515         } else
9516                 return true; /* let L1 handle the wrong parameter */
9517 }
9518
9519 /*
9520  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
9521  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
9522  * intercept (via guest_host_mask etc.) the current event.
9523  */
9524 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
9525         struct vmcs12 *vmcs12)
9526 {
9527         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9528         int cr = exit_qualification & 15;
9529         int reg;
9530         unsigned long val;
9531
9532         switch ((exit_qualification >> 4) & 3) {
9533         case 0: /* mov to cr */
9534                 reg = (exit_qualification >> 8) & 15;
9535                 val = kvm_register_readl(vcpu, reg);
9536                 switch (cr) {
9537                 case 0:
9538                         if (vmcs12->cr0_guest_host_mask &
9539                             (val ^ vmcs12->cr0_read_shadow))
9540                                 return true;
9541                         break;
9542                 case 3:
9543                         if ((vmcs12->cr3_target_count >= 1 &&
9544                                         vmcs12->cr3_target_value0 == val) ||
9545                                 (vmcs12->cr3_target_count >= 2 &&
9546                                         vmcs12->cr3_target_value1 == val) ||
9547                                 (vmcs12->cr3_target_count >= 3 &&
9548                                         vmcs12->cr3_target_value2 == val) ||
9549                                 (vmcs12->cr3_target_count >= 4 &&
9550                                         vmcs12->cr3_target_value3 == val))
9551                                 return false;
9552                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
9553                                 return true;
9554                         break;
9555                 case 4:
9556                         if (vmcs12->cr4_guest_host_mask &
9557                             (vmcs12->cr4_read_shadow ^ val))
9558                                 return true;
9559                         break;
9560                 case 8:
9561                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
9562                                 return true;
9563                         break;
9564                 }
9565                 break;
9566         case 2: /* clts */
9567                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
9568                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
9569                         return true;
9570                 break;
9571         case 1: /* mov from cr */
9572                 switch (cr) {
9573                 case 3:
9574                         if (vmcs12->cpu_based_vm_exec_control &
9575                             CPU_BASED_CR3_STORE_EXITING)
9576                                 return true;
9577                         break;
9578                 case 8:
9579                         if (vmcs12->cpu_based_vm_exec_control &
9580                             CPU_BASED_CR8_STORE_EXITING)
9581                                 return true;
9582                         break;
9583                 }
9584                 break;
9585         case 3: /* lmsw */
9586                 /*
9587                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
9588                  * cr0. Other attempted changes are ignored, with no exit.
9589                  */
9590                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
9591                 if (vmcs12->cr0_guest_host_mask & 0xe &
9592                     (val ^ vmcs12->cr0_read_shadow))
9593                         return true;
9594                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
9595                     !(vmcs12->cr0_read_shadow & 0x1) &&
9596                     (val & 0x1))
9597                         return true;
9598                 break;
9599         }
9600         return false;
9601 }
9602
9603 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
9604         struct vmcs12 *vmcs12, gpa_t bitmap)
9605 {
9606         u32 vmx_instruction_info;
9607         unsigned long field;
9608         u8 b;
9609
9610         if (!nested_cpu_has_shadow_vmcs(vmcs12))
9611                 return true;
9612
9613         /* Decode instruction info and find the field to access */
9614         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9615         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
9616
9617         /* Out-of-range fields always cause a VM exit from L2 to L1 */
9618         if (field >> 15)
9619                 return true;
9620
9621         if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
9622                 return true;
9623
9624         return 1 & (b >> (field & 7));
9625 }
9626
9627 /*
9628  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9629  * should handle it ourselves in L0 (and then continue L2). Only call this
9630  * when in is_guest_mode (L2).
9631  */
9632 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9633 {
9634         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9635         struct vcpu_vmx *vmx = to_vmx(vcpu);
9636         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9637
9638         if (vmx->nested.nested_run_pending)
9639                 return false;
9640
9641         if (unlikely(vmx->fail)) {
9642                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9643                                     vmcs_read32(VM_INSTRUCTION_ERROR));
9644                 return true;
9645         }
9646
9647         /*
9648          * The host physical addresses of some pages of guest memory
9649          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9650          * Page). The CPU may write to these pages via their host
9651          * physical address while L2 is running, bypassing any
9652          * address-translation-based dirty tracking (e.g. EPT write
9653          * protection).
9654          *
9655          * Mark them dirty on every exit from L2 to prevent them from
9656          * getting out of sync with dirty tracking.
9657          */
9658         nested_mark_vmcs12_pages_dirty(vcpu);
9659
9660         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9661                                 vmcs_readl(EXIT_QUALIFICATION),
9662                                 vmx->idt_vectoring_info,
9663                                 intr_info,
9664                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9665                                 KVM_ISA_VMX);
9666
9667         switch (exit_reason) {
9668         case EXIT_REASON_EXCEPTION_NMI:
9669                 if (is_nmi(intr_info))
9670                         return false;
9671                 else if (is_page_fault(intr_info))
9672                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9673                 else if (is_no_device(intr_info) &&
9674                          !(vmcs12->guest_cr0 & X86_CR0_TS))
9675                         return false;
9676                 else if (is_debug(intr_info) &&
9677                          vcpu->guest_debug &
9678                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9679                         return false;
9680                 else if (is_breakpoint(intr_info) &&
9681                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9682                         return false;
9683                 return vmcs12->exception_bitmap &
9684                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9685         case EXIT_REASON_EXTERNAL_INTERRUPT:
9686                 return false;
9687         case EXIT_REASON_TRIPLE_FAULT:
9688                 return true;
9689         case EXIT_REASON_PENDING_INTERRUPT:
9690                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9691         case EXIT_REASON_NMI_WINDOW:
9692                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9693         case EXIT_REASON_TASK_SWITCH:
9694                 return true;
9695         case EXIT_REASON_CPUID:
9696                 return true;
9697         case EXIT_REASON_HLT:
9698                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9699         case EXIT_REASON_INVD:
9700                 return true;
9701         case EXIT_REASON_INVLPG:
9702                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9703         case EXIT_REASON_RDPMC:
9704                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9705         case EXIT_REASON_RDRAND:
9706                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9707         case EXIT_REASON_RDSEED:
9708                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9709         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9710                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9711         case EXIT_REASON_VMREAD:
9712                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9713                         vmcs12->vmread_bitmap);
9714         case EXIT_REASON_VMWRITE:
9715                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9716                         vmcs12->vmwrite_bitmap);
9717         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9718         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9719         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
9720         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9721         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9722                 /*
9723                  * VMX instructions trap unconditionally. This allows L1 to
9724                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
9725                  */
9726                 return true;
9727         case EXIT_REASON_CR_ACCESS:
9728                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9729         case EXIT_REASON_DR_ACCESS:
9730                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9731         case EXIT_REASON_IO_INSTRUCTION:
9732                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9733         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9734                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9735         case EXIT_REASON_MSR_READ:
9736         case EXIT_REASON_MSR_WRITE:
9737                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9738         case EXIT_REASON_INVALID_STATE:
9739                 return true;
9740         case EXIT_REASON_MWAIT_INSTRUCTION:
9741                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9742         case EXIT_REASON_MONITOR_TRAP_FLAG:
9743                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9744         case EXIT_REASON_MONITOR_INSTRUCTION:
9745                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9746         case EXIT_REASON_PAUSE_INSTRUCTION:
9747                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9748                         nested_cpu_has2(vmcs12,
9749                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9750         case EXIT_REASON_MCE_DURING_VMENTRY:
9751                 return false;
9752         case EXIT_REASON_TPR_BELOW_THRESHOLD:
9753                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9754         case EXIT_REASON_APIC_ACCESS:
9755         case EXIT_REASON_APIC_WRITE:
9756         case EXIT_REASON_EOI_INDUCED:
9757                 /*
9758                  * The controls for "virtualize APIC accesses," "APIC-
9759                  * register virtualization," and "virtual-interrupt
9760                  * delivery" only come from vmcs12.
9761                  */
9762                 return true;
9763         case EXIT_REASON_EPT_VIOLATION:
9764                 /*
9765                  * L0 always deals with the EPT violation. If nested EPT is
9766                  * used, and the nested mmu code discovers that the address is
9767                  * missing in the guest EPT table (EPT12), the EPT violation
9768                  * will be injected with nested_ept_inject_page_fault()
9769                  */
9770                 return false;
9771         case EXIT_REASON_EPT_MISCONFIG:
9772                 /*
9773                  * L2 never uses directly L1's EPT, but rather L0's own EPT
9774                  * table (shadow on EPT) or a merged EPT table that L0 built
9775                  * (EPT on EPT). So any problems with the structure of the
9776                  * table is L0's fault.
9777                  */
9778                 return false;
9779         case EXIT_REASON_INVPCID:
9780                 return
9781                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9782                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9783         case EXIT_REASON_WBINVD:
9784                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9785         case EXIT_REASON_XSETBV:
9786                 return true;
9787         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9788                 /*
9789                  * This should never happen, since it is not possible to
9790                  * set XSS to a non-zero value---neither in L1 nor in L2.
9791                  * If if it were, XSS would have to be checked against
9792                  * the XSS exit bitmap in vmcs12.
9793                  */
9794                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9795         case EXIT_REASON_PREEMPTION_TIMER:
9796                 return false;
9797         case EXIT_REASON_PML_FULL:
9798                 /* We emulate PML support to L1. */
9799                 return false;
9800         case EXIT_REASON_VMFUNC:
9801                 /* VM functions are emulated through L2->L0 vmexits. */
9802                 return false;
9803         case EXIT_REASON_ENCLS:
9804                 /* SGX is never exposed to L1 */
9805                 return false;
9806         default:
9807                 return true;
9808         }
9809 }
9810
9811 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9812 {
9813         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9814
9815         /*
9816          * At this point, the exit interruption info in exit_intr_info
9817          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
9818          * we need to query the in-kernel LAPIC.
9819          */
9820         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9821         if ((exit_intr_info &
9822              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9823             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9824                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9825                 vmcs12->vm_exit_intr_error_code =
9826                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9827         }
9828
9829         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9830                           vmcs_readl(EXIT_QUALIFICATION));
9831         return 1;
9832 }
9833
9834 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9835 {
9836         *info1 = vmcs_readl(EXIT_QUALIFICATION);
9837         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9838 }
9839
9840 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9841 {
9842         if (vmx->pml_pg) {
9843                 __free_page(vmx->pml_pg);
9844                 vmx->pml_pg = NULL;
9845         }
9846 }
9847
9848 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9849 {
9850         struct vcpu_vmx *vmx = to_vmx(vcpu);
9851         u64 *pml_buf;
9852         u16 pml_idx;
9853
9854         pml_idx = vmcs_read16(GUEST_PML_INDEX);
9855
9856         /* Do nothing if PML buffer is empty */
9857         if (pml_idx == (PML_ENTITY_NUM - 1))
9858                 return;
9859
9860         /* PML index always points to next available PML buffer entity */
9861         if (pml_idx >= PML_ENTITY_NUM)
9862                 pml_idx = 0;
9863         else
9864                 pml_idx++;
9865
9866         pml_buf = page_address(vmx->pml_pg);
9867         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9868                 u64 gpa;
9869
9870                 gpa = pml_buf[pml_idx];
9871                 WARN_ON(gpa & (PAGE_SIZE - 1));
9872                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9873         }
9874
9875         /* reset PML index */
9876         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9877 }
9878
9879 /*
9880  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9881  * Called before reporting dirty_bitmap to userspace.
9882  */
9883 static void kvm_flush_pml_buffers(struct kvm *kvm)
9884 {
9885         int i;
9886         struct kvm_vcpu *vcpu;
9887         /*
9888          * We only need to kick vcpu out of guest mode here, as PML buffer
9889          * is flushed at beginning of all VMEXITs, and it's obvious that only
9890          * vcpus running in guest are possible to have unflushed GPAs in PML
9891          * buffer.
9892          */
9893         kvm_for_each_vcpu(i, vcpu, kvm)
9894                 kvm_vcpu_kick(vcpu);
9895 }
9896
9897 static void vmx_dump_sel(char *name, uint32_t sel)
9898 {
9899         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9900                name, vmcs_read16(sel),
9901                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9902                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9903                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9904 }
9905
9906 static void vmx_dump_dtsel(char *name, uint32_t limit)
9907 {
9908         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
9909                name, vmcs_read32(limit),
9910                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9911 }
9912
9913 static void dump_vmcs(void)
9914 {
9915         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9916         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9917         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9918         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9919         u32 secondary_exec_control = 0;
9920         unsigned long cr4 = vmcs_readl(GUEST_CR4);
9921         u64 efer = vmcs_read64(GUEST_IA32_EFER);
9922         int i, n;
9923
9924         if (cpu_has_secondary_exec_ctrls())
9925                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9926
9927         pr_err("*** Guest State ***\n");
9928         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9929                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9930                vmcs_readl(CR0_GUEST_HOST_MASK));
9931         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9932                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9933         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9934         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9935             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9936         {
9937                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
9938                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9939                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
9940                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9941         }
9942         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
9943                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9944         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
9945                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9946         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9947                vmcs_readl(GUEST_SYSENTER_ESP),
9948                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9949         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
9950         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
9951         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
9952         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
9953         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
9954         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
9955         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9956         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9957         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9958         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
9959         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9960             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9961                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
9962                        efer, vmcs_read64(GUEST_IA32_PAT));
9963         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
9964                vmcs_read64(GUEST_IA32_DEBUGCTL),
9965                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9966         if (cpu_has_load_perf_global_ctrl &&
9967             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9968                 pr_err("PerfGlobCtl = 0x%016llx\n",
9969                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9970         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9971                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9972         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
9973                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9974                vmcs_read32(GUEST_ACTIVITY_STATE));
9975         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9976                 pr_err("InterruptStatus = %04x\n",
9977                        vmcs_read16(GUEST_INTR_STATUS));
9978
9979         pr_err("*** Host State ***\n");
9980         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
9981                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9982         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9983                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9984                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9985                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9986                vmcs_read16(HOST_TR_SELECTOR));
9987         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9988                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9989                vmcs_readl(HOST_TR_BASE));
9990         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9991                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9992         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9993                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9994                vmcs_readl(HOST_CR4));
9995         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9996                vmcs_readl(HOST_IA32_SYSENTER_ESP),
9997                vmcs_read32(HOST_IA32_SYSENTER_CS),
9998                vmcs_readl(HOST_IA32_SYSENTER_EIP));
9999         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
10000                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
10001                        vmcs_read64(HOST_IA32_EFER),
10002                        vmcs_read64(HOST_IA32_PAT));
10003         if (cpu_has_load_perf_global_ctrl &&
10004             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10005                 pr_err("PerfGlobCtl = 0x%016llx\n",
10006                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
10007
10008         pr_err("*** Control State ***\n");
10009         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
10010                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
10011         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
10012         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
10013                vmcs_read32(EXCEPTION_BITMAP),
10014                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
10015                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
10016         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
10017                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
10018                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
10019                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
10020         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
10021                vmcs_read32(VM_EXIT_INTR_INFO),
10022                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
10023                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
10024         pr_err("        reason=%08x qualification=%016lx\n",
10025                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
10026         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
10027                vmcs_read32(IDT_VECTORING_INFO_FIELD),
10028                vmcs_read32(IDT_VECTORING_ERROR_CODE));
10029         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
10030         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
10031                 pr_err("TSC Multiplier = 0x%016llx\n",
10032                        vmcs_read64(TSC_MULTIPLIER));
10033         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
10034                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
10035         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
10036                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
10037         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
10038                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
10039         n = vmcs_read32(CR3_TARGET_COUNT);
10040         for (i = 0; i + 1 < n; i += 4)
10041                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
10042                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
10043                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
10044         if (i < n)
10045                 pr_err("CR3 target%u=%016lx\n",
10046                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
10047         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
10048                 pr_err("PLE Gap=%08x Window=%08x\n",
10049                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
10050         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
10051                 pr_err("Virtual processor ID = 0x%04x\n",
10052                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
10053 }
10054
10055 /*
10056  * The guest has exited.  See if we can fix it or if we need userspace
10057  * assistance.
10058  */
10059 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
10060 {
10061         struct vcpu_vmx *vmx = to_vmx(vcpu);
10062         u32 exit_reason = vmx->exit_reason;
10063         u32 vectoring_info = vmx->idt_vectoring_info;
10064
10065         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
10066
10067         /*
10068          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
10069          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
10070          * querying dirty_bitmap, we only need to kick all vcpus out of guest
10071          * mode as if vcpus is in root mode, the PML buffer must has been
10072          * flushed already.
10073          */
10074         if (enable_pml)
10075                 vmx_flush_pml_buffer(vcpu);
10076
10077         /* If guest state is invalid, start emulating */
10078         if (vmx->emulation_required)
10079                 return handle_invalid_guest_state(vcpu);
10080
10081         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
10082                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
10083
10084         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
10085                 dump_vmcs();
10086                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10087                 vcpu->run->fail_entry.hardware_entry_failure_reason
10088                         = exit_reason;
10089                 return 0;
10090         }
10091
10092         if (unlikely(vmx->fail)) {
10093                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10094                 vcpu->run->fail_entry.hardware_entry_failure_reason
10095                         = vmcs_read32(VM_INSTRUCTION_ERROR);
10096                 return 0;
10097         }
10098
10099         /*
10100          * Note:
10101          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
10102          * delivery event since it indicates guest is accessing MMIO.
10103          * The vm-exit can be triggered again after return to guest that
10104          * will cause infinite loop.
10105          */
10106         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
10107                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
10108                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
10109                         exit_reason != EXIT_REASON_PML_FULL &&
10110                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
10111                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10112                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
10113                 vcpu->run->internal.ndata = 3;
10114                 vcpu->run->internal.data[0] = vectoring_info;
10115                 vcpu->run->internal.data[1] = exit_reason;
10116                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
10117                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
10118                         vcpu->run->internal.ndata++;
10119                         vcpu->run->internal.data[3] =
10120                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
10121                 }
10122                 return 0;
10123         }
10124
10125         if (unlikely(!enable_vnmi &&
10126                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
10127                 if (vmx_interrupt_allowed(vcpu)) {
10128                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10129                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
10130                            vcpu->arch.nmi_pending) {
10131                         /*
10132                          * This CPU don't support us in finding the end of an
10133                          * NMI-blocked window if the guest runs with IRQs
10134                          * disabled. So we pull the trigger after 1 s of
10135                          * futile waiting, but inform the user about this.
10136                          */
10137                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
10138                                "state on VCPU %d after 1 s timeout\n",
10139                                __func__, vcpu->vcpu_id);
10140                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10141                 }
10142         }
10143
10144         if (exit_reason < kvm_vmx_max_exit_handlers
10145             && kvm_vmx_exit_handlers[exit_reason])
10146                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
10147         else {
10148                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
10149                                 exit_reason);
10150                 kvm_queue_exception(vcpu, UD_VECTOR);
10151                 return 1;
10152         }
10153 }
10154
10155 /*
10156  * Software based L1D cache flush which is used when microcode providing
10157  * the cache control MSR is not loaded.
10158  *
10159  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
10160  * flush it is required to read in 64 KiB because the replacement algorithm
10161  * is not exactly LRU. This could be sized at runtime via topology
10162  * information but as all relevant affected CPUs have 32KiB L1D cache size
10163  * there is no point in doing so.
10164  */
10165 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
10166 {
10167         int size = PAGE_SIZE << L1D_CACHE_ORDER;
10168
10169         /*
10170          * This code is only executed when the the flush mode is 'cond' or
10171          * 'always'
10172          */
10173         if (static_branch_likely(&vmx_l1d_flush_cond)) {
10174                 bool flush_l1d;
10175
10176                 /*
10177                  * Clear the per-vcpu flush bit, it gets set again
10178                  * either from vcpu_run() or from one of the unsafe
10179                  * VMEXIT handlers.
10180                  */
10181                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
10182                 vcpu->arch.l1tf_flush_l1d = false;
10183
10184                 /*
10185                  * Clear the per-cpu flush bit, it gets set again from
10186                  * the interrupt handlers.
10187                  */
10188                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
10189                 kvm_clear_cpu_l1tf_flush_l1d();
10190
10191                 if (!flush_l1d)
10192                         return;
10193         }
10194
10195         vcpu->stat.l1d_flush++;
10196
10197         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
10198                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
10199                 return;
10200         }
10201
10202         asm volatile(
10203                 /* First ensure the pages are in the TLB */
10204                 "xorl   %%eax, %%eax\n"
10205                 ".Lpopulate_tlb:\n\t"
10206                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10207                 "addl   $4096, %%eax\n\t"
10208                 "cmpl   %%eax, %[size]\n\t"
10209                 "jne    .Lpopulate_tlb\n\t"
10210                 "xorl   %%eax, %%eax\n\t"
10211                 "cpuid\n\t"
10212                 /* Now fill the cache */
10213                 "xorl   %%eax, %%eax\n"
10214                 ".Lfill_cache:\n"
10215                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10216                 "addl   $64, %%eax\n\t"
10217                 "cmpl   %%eax, %[size]\n\t"
10218                 "jne    .Lfill_cache\n\t"
10219                 "lfence\n"
10220                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
10221                     [size] "r" (size)
10222                 : "eax", "ebx", "ecx", "edx");
10223 }
10224
10225 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
10226 {
10227         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10228
10229         if (is_guest_mode(vcpu) &&
10230                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10231                 return;
10232
10233         if (irr == -1 || tpr < irr) {
10234                 vmcs_write32(TPR_THRESHOLD, 0);
10235                 return;
10236         }
10237
10238         vmcs_write32(TPR_THRESHOLD, irr);
10239 }
10240
10241 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
10242 {
10243         u32 sec_exec_control;
10244
10245         if (!lapic_in_kernel(vcpu))
10246                 return;
10247
10248         /* Postpone execution until vmcs01 is the current VMCS. */
10249         if (is_guest_mode(vcpu)) {
10250                 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
10251                 return;
10252         }
10253
10254         if (!cpu_need_tpr_shadow(vcpu))
10255                 return;
10256
10257         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10258         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10259                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
10260
10261         switch (kvm_get_apic_mode(vcpu)) {
10262         case LAPIC_MODE_INVALID:
10263                 WARN_ONCE(true, "Invalid local APIC state");
10264         case LAPIC_MODE_DISABLED:
10265                 break;
10266         case LAPIC_MODE_XAPIC:
10267                 if (flexpriority_enabled) {
10268                         sec_exec_control |=
10269                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10270                         vmx_flush_tlb(vcpu, true);
10271                 }
10272                 break;
10273         case LAPIC_MODE_X2APIC:
10274                 if (cpu_has_vmx_virtualize_x2apic_mode())
10275                         sec_exec_control |=
10276                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
10277                 break;
10278         }
10279         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
10280
10281         vmx_update_msr_bitmap(vcpu);
10282 }
10283
10284 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
10285 {
10286         if (!is_guest_mode(vcpu)) {
10287                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10288                 vmx_flush_tlb(vcpu, true);
10289         }
10290 }
10291
10292 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
10293 {
10294         u16 status;
10295         u8 old;
10296
10297         if (max_isr == -1)
10298                 max_isr = 0;
10299
10300         status = vmcs_read16(GUEST_INTR_STATUS);
10301         old = status >> 8;
10302         if (max_isr != old) {
10303                 status &= 0xff;
10304                 status |= max_isr << 8;
10305                 vmcs_write16(GUEST_INTR_STATUS, status);
10306         }
10307 }
10308
10309 static void vmx_set_rvi(int vector)
10310 {
10311         u16 status;
10312         u8 old;
10313
10314         if (vector == -1)
10315                 vector = 0;
10316
10317         status = vmcs_read16(GUEST_INTR_STATUS);
10318         old = (u8)status & 0xff;
10319         if ((u8)vector != old) {
10320                 status &= ~0xff;
10321                 status |= (u8)vector;
10322                 vmcs_write16(GUEST_INTR_STATUS, status);
10323         }
10324 }
10325
10326 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
10327 {
10328         /*
10329          * When running L2, updating RVI is only relevant when
10330          * vmcs12 virtual-interrupt-delivery enabled.
10331          * However, it can be enabled only when L1 also
10332          * intercepts external-interrupts and in that case
10333          * we should not update vmcs02 RVI but instead intercept
10334          * interrupt. Therefore, do nothing when running L2.
10335          */
10336         if (!is_guest_mode(vcpu))
10337                 vmx_set_rvi(max_irr);
10338 }
10339
10340 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
10341 {
10342         struct vcpu_vmx *vmx = to_vmx(vcpu);
10343         int max_irr;
10344         bool max_irr_updated;
10345
10346         WARN_ON(!vcpu->arch.apicv_active);
10347         if (pi_test_on(&vmx->pi_desc)) {
10348                 pi_clear_on(&vmx->pi_desc);
10349                 /*
10350                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
10351                  * But on x86 this is just a compiler barrier anyway.
10352                  */
10353                 smp_mb__after_atomic();
10354                 max_irr_updated =
10355                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
10356
10357                 /*
10358                  * If we are running L2 and L1 has a new pending interrupt
10359                  * which can be injected, we should re-evaluate
10360                  * what should be done with this new L1 interrupt.
10361                  * If L1 intercepts external-interrupts, we should
10362                  * exit from L2 to L1. Otherwise, interrupt should be
10363                  * delivered directly to L2.
10364                  */
10365                 if (is_guest_mode(vcpu) && max_irr_updated) {
10366                         if (nested_exit_on_intr(vcpu))
10367                                 kvm_vcpu_exiting_guest_mode(vcpu);
10368                         else
10369                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
10370                 }
10371         } else {
10372                 max_irr = kvm_lapic_find_highest_irr(vcpu);
10373         }
10374         vmx_hwapic_irr_update(vcpu, max_irr);
10375         return max_irr;
10376 }
10377
10378 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
10379 {
10380         if (!kvm_vcpu_apicv_active(vcpu))
10381                 return;
10382
10383         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
10384         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
10385         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
10386         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
10387 }
10388
10389 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
10390 {
10391         struct vcpu_vmx *vmx = to_vmx(vcpu);
10392
10393         pi_clear_on(&vmx->pi_desc);
10394         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
10395 }
10396
10397 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
10398 {
10399         u32 exit_intr_info = 0;
10400         u16 basic_exit_reason = (u16)vmx->exit_reason;
10401
10402         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
10403               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
10404                 return;
10405
10406         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10407                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10408         vmx->exit_intr_info = exit_intr_info;
10409
10410         /* if exit due to PF check for async PF */
10411         if (is_page_fault(exit_intr_info))
10412                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
10413
10414         /* Handle machine checks before interrupts are enabled */
10415         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
10416             is_machine_check(exit_intr_info))
10417                 kvm_machine_check();
10418
10419         /* We need to handle NMIs before interrupts are enabled */
10420         if (is_nmi(exit_intr_info)) {
10421                 kvm_before_interrupt(&vmx->vcpu);
10422                 asm("int $2");
10423                 kvm_after_interrupt(&vmx->vcpu);
10424         }
10425 }
10426
10427 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
10428 {
10429         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10430
10431         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
10432                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
10433                 unsigned int vector;
10434                 unsigned long entry;
10435                 gate_desc *desc;
10436                 struct vcpu_vmx *vmx = to_vmx(vcpu);
10437 #ifdef CONFIG_X86_64
10438                 unsigned long tmp;
10439 #endif
10440
10441                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
10442                 desc = (gate_desc *)vmx->host_idt_base + vector;
10443                 entry = gate_offset(desc);
10444                 asm volatile(
10445 #ifdef CONFIG_X86_64
10446                         "mov %%" _ASM_SP ", %[sp]\n\t"
10447                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
10448                         "push $%c[ss]\n\t"
10449                         "push %[sp]\n\t"
10450 #endif
10451                         "pushf\n\t"
10452                         __ASM_SIZE(push) " $%c[cs]\n\t"
10453                         CALL_NOSPEC
10454                         :
10455 #ifdef CONFIG_X86_64
10456                         [sp]"=&r"(tmp),
10457 #endif
10458                         ASM_CALL_CONSTRAINT
10459                         :
10460                         THUNK_TARGET(entry),
10461                         [ss]"i"(__KERNEL_DS),
10462                         [cs]"i"(__KERNEL_CS)
10463                         );
10464         }
10465 }
10466 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
10467
10468 static bool vmx_has_emulated_msr(int index)
10469 {
10470         switch (index) {
10471         case MSR_IA32_SMBASE:
10472                 /*
10473                  * We cannot do SMM unless we can run the guest in big
10474                  * real mode.
10475                  */
10476                 return enable_unrestricted_guest || emulate_invalid_guest_state;
10477         case MSR_AMD64_VIRT_SPEC_CTRL:
10478                 /* This is AMD only.  */
10479                 return false;
10480         default:
10481                 return true;
10482         }
10483 }
10484
10485 static bool vmx_mpx_supported(void)
10486 {
10487         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
10488                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
10489 }
10490
10491 static bool vmx_xsaves_supported(void)
10492 {
10493         return vmcs_config.cpu_based_2nd_exec_ctrl &
10494                 SECONDARY_EXEC_XSAVES;
10495 }
10496
10497 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
10498 {
10499         u32 exit_intr_info;
10500         bool unblock_nmi;
10501         u8 vector;
10502         bool idtv_info_valid;
10503
10504         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10505
10506         if (enable_vnmi) {
10507                 if (vmx->loaded_vmcs->nmi_known_unmasked)
10508                         return;
10509                 /*
10510                  * Can't use vmx->exit_intr_info since we're not sure what
10511                  * the exit reason is.
10512                  */
10513                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10514                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
10515                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
10516                 /*
10517                  * SDM 3: 27.7.1.2 (September 2008)
10518                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
10519                  * a guest IRET fault.
10520                  * SDM 3: 23.2.2 (September 2008)
10521                  * Bit 12 is undefined in any of the following cases:
10522                  *  If the VM exit sets the valid bit in the IDT-vectoring
10523                  *   information field.
10524                  *  If the VM exit is due to a double fault.
10525                  */
10526                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
10527                     vector != DF_VECTOR && !idtv_info_valid)
10528                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
10529                                       GUEST_INTR_STATE_NMI);
10530                 else
10531                         vmx->loaded_vmcs->nmi_known_unmasked =
10532                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
10533                                   & GUEST_INTR_STATE_NMI);
10534         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
10535                 vmx->loaded_vmcs->vnmi_blocked_time +=
10536                         ktime_to_ns(ktime_sub(ktime_get(),
10537                                               vmx->loaded_vmcs->entry_time));
10538 }
10539
10540 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
10541                                       u32 idt_vectoring_info,
10542                                       int instr_len_field,
10543                                       int error_code_field)
10544 {
10545         u8 vector;
10546         int type;
10547         bool idtv_info_valid;
10548
10549         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10550
10551         vcpu->arch.nmi_injected = false;
10552         kvm_clear_exception_queue(vcpu);
10553         kvm_clear_interrupt_queue(vcpu);
10554
10555         if (!idtv_info_valid)
10556                 return;
10557
10558         kvm_make_request(KVM_REQ_EVENT, vcpu);
10559
10560         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
10561         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
10562
10563         switch (type) {
10564         case INTR_TYPE_NMI_INTR:
10565                 vcpu->arch.nmi_injected = true;
10566                 /*
10567                  * SDM 3: 27.7.1.2 (September 2008)
10568                  * Clear bit "block by NMI" before VM entry if a NMI
10569                  * delivery faulted.
10570                  */
10571                 vmx_set_nmi_mask(vcpu, false);
10572                 break;
10573         case INTR_TYPE_SOFT_EXCEPTION:
10574                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10575                 /* fall through */
10576         case INTR_TYPE_HARD_EXCEPTION:
10577                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
10578                         u32 err = vmcs_read32(error_code_field);
10579                         kvm_requeue_exception_e(vcpu, vector, err);
10580                 } else
10581                         kvm_requeue_exception(vcpu, vector);
10582                 break;
10583         case INTR_TYPE_SOFT_INTR:
10584                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10585                 /* fall through */
10586         case INTR_TYPE_EXT_INTR:
10587                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
10588                 break;
10589         default:
10590                 break;
10591         }
10592 }
10593
10594 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
10595 {
10596         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
10597                                   VM_EXIT_INSTRUCTION_LEN,
10598                                   IDT_VECTORING_ERROR_CODE);
10599 }
10600
10601 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
10602 {
10603         __vmx_complete_interrupts(vcpu,
10604                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
10605                                   VM_ENTRY_INSTRUCTION_LEN,
10606                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
10607
10608         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10609 }
10610
10611 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
10612 {
10613         int i, nr_msrs;
10614         struct perf_guest_switch_msr *msrs;
10615
10616         msrs = perf_guest_get_msrs(&nr_msrs);
10617
10618         if (!msrs)
10619                 return;
10620
10621         for (i = 0; i < nr_msrs; i++)
10622                 if (msrs[i].host == msrs[i].guest)
10623                         clear_atomic_switch_msr(vmx, msrs[i].msr);
10624                 else
10625                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
10626                                         msrs[i].host, false);
10627 }
10628
10629 static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
10630 {
10631         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
10632         if (!vmx->loaded_vmcs->hv_timer_armed)
10633                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10634                               PIN_BASED_VMX_PREEMPTION_TIMER);
10635         vmx->loaded_vmcs->hv_timer_armed = true;
10636 }
10637
10638 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
10639 {
10640         struct vcpu_vmx *vmx = to_vmx(vcpu);
10641         u64 tscl;
10642         u32 delta_tsc;
10643
10644         if (vmx->req_immediate_exit) {
10645                 vmx_arm_hv_timer(vmx, 0);
10646                 return;
10647         }
10648
10649         if (vmx->hv_deadline_tsc != -1) {
10650                 tscl = rdtsc();
10651                 if (vmx->hv_deadline_tsc > tscl)
10652                         /* set_hv_timer ensures the delta fits in 32-bits */
10653                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
10654                                 cpu_preemption_timer_multi);
10655                 else
10656                         delta_tsc = 0;
10657
10658                 vmx_arm_hv_timer(vmx, delta_tsc);
10659                 return;
10660         }
10661
10662         if (vmx->loaded_vmcs->hv_timer_armed)
10663                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10664                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10665         vmx->loaded_vmcs->hv_timer_armed = false;
10666 }
10667
10668 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
10669 {
10670         struct vcpu_vmx *vmx = to_vmx(vcpu);
10671         unsigned long cr3, cr4, evmcs_rsp;
10672
10673         /* Record the guest's net vcpu time for enforced NMI injections. */
10674         if (unlikely(!enable_vnmi &&
10675                      vmx->loaded_vmcs->soft_vnmi_blocked))
10676                 vmx->loaded_vmcs->entry_time = ktime_get();
10677
10678         /* Don't enter VMX if guest state is invalid, let the exit handler
10679            start emulation until we arrive back to a valid state */
10680         if (vmx->emulation_required)
10681                 return;
10682
10683         if (vmx->ple_window_dirty) {
10684                 vmx->ple_window_dirty = false;
10685                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
10686         }
10687
10688         if (vmx->nested.sync_shadow_vmcs) {
10689                 copy_vmcs12_to_shadow(vmx);
10690                 vmx->nested.sync_shadow_vmcs = false;
10691         }
10692
10693         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
10694                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
10695         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
10696                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
10697
10698         cr3 = __get_current_cr3_fast();
10699         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
10700                 vmcs_writel(HOST_CR3, cr3);
10701                 vmx->loaded_vmcs->host_state.cr3 = cr3;
10702         }
10703
10704         cr4 = cr4_read_shadow();
10705         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
10706                 vmcs_writel(HOST_CR4, cr4);
10707                 vmx->loaded_vmcs->host_state.cr4 = cr4;
10708         }
10709
10710         /* When single-stepping over STI and MOV SS, we must clear the
10711          * corresponding interruptibility bits in the guest state. Otherwise
10712          * vmentry fails as it then expects bit 14 (BS) in pending debug
10713          * exceptions being set, but that's not correct for the guest debugging
10714          * case. */
10715         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10716                 vmx_set_interrupt_shadow(vcpu, 0);
10717
10718         if (static_cpu_has(X86_FEATURE_PKU) &&
10719             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
10720             vcpu->arch.pkru != vmx->host_pkru)
10721                 __write_pkru(vcpu->arch.pkru);
10722
10723         atomic_switch_perf_msrs(vmx);
10724
10725         vmx_update_hv_timer(vcpu);
10726
10727         /*
10728          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10729          * it's non-zero. Since vmentry is serialising on affected CPUs, there
10730          * is no need to worry about the conditional branch over the wrmsr
10731          * being speculatively taken.
10732          */
10733         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10734
10735         vmx->__launched = vmx->loaded_vmcs->launched;
10736
10737         evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10738                 (unsigned long)&current_evmcs->host_rsp : 0;
10739
10740         if (static_branch_unlikely(&vmx_l1d_should_flush))
10741                 vmx_l1d_flush(vcpu);
10742
10743         asm(
10744                 /* Store host registers */
10745                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10746                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10747                 "push %%" _ASM_CX " \n\t"
10748                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10749                 "je 1f \n\t"
10750                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10751                 /* Avoid VMWRITE when Enlightened VMCS is in use */
10752                 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10753                 "jz 2f \n\t"
10754                 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10755                 "jmp 1f \n\t"
10756                 "2: \n\t"
10757                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10758                 "1: \n\t"
10759                 /* Reload cr2 if changed */
10760                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10761                 "mov %%cr2, %%" _ASM_DX " \n\t"
10762                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10763                 "je 3f \n\t"
10764                 "mov %%" _ASM_AX", %%cr2 \n\t"
10765                 "3: \n\t"
10766                 /* Check if vmlaunch of vmresume is needed */
10767                 "cmpl $0, %c[launched](%0) \n\t"
10768                 /* Load guest registers.  Don't clobber flags. */
10769                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10770                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10771                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10772                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10773                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10774                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10775 #ifdef CONFIG_X86_64
10776                 "mov %c[r8](%0),  %%r8  \n\t"
10777                 "mov %c[r9](%0),  %%r9  \n\t"
10778                 "mov %c[r10](%0), %%r10 \n\t"
10779                 "mov %c[r11](%0), %%r11 \n\t"
10780                 "mov %c[r12](%0), %%r12 \n\t"
10781                 "mov %c[r13](%0), %%r13 \n\t"
10782                 "mov %c[r14](%0), %%r14 \n\t"
10783                 "mov %c[r15](%0), %%r15 \n\t"
10784 #endif
10785                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10786
10787                 /* Enter guest mode */
10788                 "jne 1f \n\t"
10789                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10790                 "jmp 2f \n\t"
10791                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10792                 "2: "
10793                 /* Save guest registers, load host registers, keep flags */
10794                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10795                 "pop %0 \n\t"
10796                 "setbe %c[fail](%0)\n\t"
10797                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10798                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10799                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10800                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10801                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10802                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10803                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10804 #ifdef CONFIG_X86_64
10805                 "mov %%r8,  %c[r8](%0) \n\t"
10806                 "mov %%r9,  %c[r9](%0) \n\t"
10807                 "mov %%r10, %c[r10](%0) \n\t"
10808                 "mov %%r11, %c[r11](%0) \n\t"
10809                 "mov %%r12, %c[r12](%0) \n\t"
10810                 "mov %%r13, %c[r13](%0) \n\t"
10811                 "mov %%r14, %c[r14](%0) \n\t"
10812                 "mov %%r15, %c[r15](%0) \n\t"
10813                 "xor %%r8d,  %%r8d \n\t"
10814                 "xor %%r9d,  %%r9d \n\t"
10815                 "xor %%r10d, %%r10d \n\t"
10816                 "xor %%r11d, %%r11d \n\t"
10817                 "xor %%r12d, %%r12d \n\t"
10818                 "xor %%r13d, %%r13d \n\t"
10819                 "xor %%r14d, %%r14d \n\t"
10820                 "xor %%r15d, %%r15d \n\t"
10821 #endif
10822                 "mov %%cr2, %%" _ASM_AX "   \n\t"
10823                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10824
10825                 "xor %%eax, %%eax \n\t"
10826                 "xor %%ebx, %%ebx \n\t"
10827                 "xor %%esi, %%esi \n\t"
10828                 "xor %%edi, %%edi \n\t"
10829                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
10830                 ".pushsection .rodata \n\t"
10831                 ".global vmx_return \n\t"
10832                 "vmx_return: " _ASM_PTR " 2b \n\t"
10833                 ".popsection"
10834               : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10835                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10836                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10837                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10838                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10839                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10840                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10841                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10842                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10843                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10844                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10845 #ifdef CONFIG_X86_64
10846                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10847                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10848                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10849                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10850                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10851                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10852                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10853                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10854 #endif
10855                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10856                 [wordsize]"i"(sizeof(ulong))
10857               : "cc", "memory"
10858 #ifdef CONFIG_X86_64
10859                 , "rax", "rbx", "rdi"
10860                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10861 #else
10862                 , "eax", "ebx", "edi"
10863 #endif
10864               );
10865
10866         /*
10867          * We do not use IBRS in the kernel. If this vCPU has used the
10868          * SPEC_CTRL MSR it may have left it on; save the value and
10869          * turn it off. This is much more efficient than blindly adding
10870          * it to the atomic save/restore list. Especially as the former
10871          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10872          *
10873          * For non-nested case:
10874          * If the L01 MSR bitmap does not intercept the MSR, then we need to
10875          * save it.
10876          *
10877          * For nested case:
10878          * If the L02 MSR bitmap does not intercept the MSR, then we need to
10879          * save it.
10880          */
10881         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10882                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10883
10884         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10885
10886         /* Eliminate branch target predictions from guest mode */
10887         vmexit_fill_RSB();
10888
10889         /* All fields are clean at this point */
10890         if (static_branch_unlikely(&enable_evmcs))
10891                 current_evmcs->hv_clean_fields |=
10892                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10893
10894         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10895         if (vmx->host_debugctlmsr)
10896                 update_debugctlmsr(vmx->host_debugctlmsr);
10897
10898 #ifndef CONFIG_X86_64
10899         /*
10900          * The sysexit path does not restore ds/es, so we must set them to
10901          * a reasonable value ourselves.
10902          *
10903          * We can't defer this to vmx_prepare_switch_to_host() since that
10904          * function may be executed in interrupt context, which saves and
10905          * restore segments around it, nullifying its effect.
10906          */
10907         loadsegment(ds, __USER_DS);
10908         loadsegment(es, __USER_DS);
10909 #endif
10910
10911         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10912                                   | (1 << VCPU_EXREG_RFLAGS)
10913                                   | (1 << VCPU_EXREG_PDPTR)
10914                                   | (1 << VCPU_EXREG_SEGMENTS)
10915                                   | (1 << VCPU_EXREG_CR3));
10916         vcpu->arch.regs_dirty = 0;
10917
10918         /*
10919          * eager fpu is enabled if PKEY is supported and CR4 is switched
10920          * back on host, so it is safe to read guest PKRU from current
10921          * XSAVE.
10922          */
10923         if (static_cpu_has(X86_FEATURE_PKU) &&
10924             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10925                 vcpu->arch.pkru = __read_pkru();
10926                 if (vcpu->arch.pkru != vmx->host_pkru)
10927                         __write_pkru(vmx->host_pkru);
10928         }
10929
10930         vmx->nested.nested_run_pending = 0;
10931         vmx->idt_vectoring_info = 0;
10932
10933         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10934         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10935                 return;
10936
10937         vmx->loaded_vmcs->launched = 1;
10938         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10939
10940         vmx_complete_atomic_exit(vmx);
10941         vmx_recover_nmi_blocking(vmx);
10942         vmx_complete_interrupts(vmx);
10943 }
10944 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10945
10946 static struct kvm *vmx_vm_alloc(void)
10947 {
10948         struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10949         return &kvm_vmx->kvm;
10950 }
10951
10952 static void vmx_vm_free(struct kvm *kvm)
10953 {
10954         vfree(to_kvm_vmx(kvm));
10955 }
10956
10957 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10958 {
10959         struct vcpu_vmx *vmx = to_vmx(vcpu);
10960         int cpu;
10961
10962         if (vmx->loaded_vmcs == vmcs)
10963                 return;
10964
10965         cpu = get_cpu();
10966         vmx_vcpu_put(vcpu);
10967         vmx->loaded_vmcs = vmcs;
10968         vmx_vcpu_load(vcpu, cpu);
10969         put_cpu();
10970 }
10971
10972 /*
10973  * Ensure that the current vmcs of the logical processor is the
10974  * vmcs01 of the vcpu before calling free_nested().
10975  */
10976 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10977 {
10978        struct vcpu_vmx *vmx = to_vmx(vcpu);
10979
10980        vcpu_load(vcpu);
10981        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10982        free_nested(vmx);
10983        vcpu_put(vcpu);
10984 }
10985
10986 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10987 {
10988         struct vcpu_vmx *vmx = to_vmx(vcpu);
10989
10990         if (enable_pml)
10991                 vmx_destroy_pml_buffer(vmx);
10992         free_vpid(vmx->vpid);
10993         leave_guest_mode(vcpu);
10994         vmx_free_vcpu_nested(vcpu);
10995         free_loaded_vmcs(vmx->loaded_vmcs);
10996         kfree(vmx->guest_msrs);
10997         kvm_vcpu_uninit(vcpu);
10998         kmem_cache_free(kvm_vcpu_cache, vmx);
10999 }
11000
11001 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
11002 {
11003         int err;
11004         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
11005         unsigned long *msr_bitmap;
11006         int cpu;
11007
11008         if (!vmx)
11009                 return ERR_PTR(-ENOMEM);
11010
11011         vmx->vpid = allocate_vpid();
11012
11013         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
11014         if (err)
11015                 goto free_vcpu;
11016
11017         err = -ENOMEM;
11018
11019         /*
11020          * If PML is turned on, failure on enabling PML just results in failure
11021          * of creating the vcpu, therefore we can simplify PML logic (by
11022          * avoiding dealing with cases, such as enabling PML partially on vcpus
11023          * for the guest, etc.
11024          */
11025         if (enable_pml) {
11026                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
11027                 if (!vmx->pml_pg)
11028                         goto uninit_vcpu;
11029         }
11030
11031         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
11032         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
11033                      > PAGE_SIZE);
11034
11035         if (!vmx->guest_msrs)
11036                 goto free_pml;
11037
11038         err = alloc_loaded_vmcs(&vmx->vmcs01);
11039         if (err < 0)
11040                 goto free_msrs;
11041
11042         msr_bitmap = vmx->vmcs01.msr_bitmap;
11043         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
11044         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
11045         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
11046         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
11047         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
11048         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
11049         vmx->msr_bitmap_mode = 0;
11050
11051         vmx->loaded_vmcs = &vmx->vmcs01;
11052         cpu = get_cpu();
11053         vmx_vcpu_load(&vmx->vcpu, cpu);
11054         vmx->vcpu.cpu = cpu;
11055         vmx_vcpu_setup(vmx);
11056         vmx_vcpu_put(&vmx->vcpu);
11057         put_cpu();
11058         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
11059                 err = alloc_apic_access_page(kvm);
11060                 if (err)
11061                         goto free_vmcs;
11062         }
11063
11064         if (enable_ept && !enable_unrestricted_guest) {
11065                 err = init_rmode_identity_map(kvm);
11066                 if (err)
11067                         goto free_vmcs;
11068         }
11069
11070         if (nested)
11071                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
11072                                            kvm_vcpu_apicv_active(&vmx->vcpu));
11073
11074         vmx->nested.posted_intr_nv = -1;
11075         vmx->nested.current_vmptr = -1ull;
11076
11077         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
11078
11079         /*
11080          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
11081          * or POSTED_INTR_WAKEUP_VECTOR.
11082          */
11083         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
11084         vmx->pi_desc.sn = 1;
11085
11086         return &vmx->vcpu;
11087
11088 free_vmcs:
11089         free_loaded_vmcs(vmx->loaded_vmcs);
11090 free_msrs:
11091         kfree(vmx->guest_msrs);
11092 free_pml:
11093         vmx_destroy_pml_buffer(vmx);
11094 uninit_vcpu:
11095         kvm_vcpu_uninit(&vmx->vcpu);
11096 free_vcpu:
11097         free_vpid(vmx->vpid);
11098         kmem_cache_free(kvm_vcpu_cache, vmx);
11099         return ERR_PTR(err);
11100 }
11101
11102 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11103 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11104
11105 static int vmx_vm_init(struct kvm *kvm)
11106 {
11107         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
11108
11109         if (!ple_gap)
11110                 kvm->arch.pause_in_guest = true;
11111
11112         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
11113                 switch (l1tf_mitigation) {
11114                 case L1TF_MITIGATION_OFF:
11115                 case L1TF_MITIGATION_FLUSH_NOWARN:
11116                         /* 'I explicitly don't care' is set */
11117                         break;
11118                 case L1TF_MITIGATION_FLUSH:
11119                 case L1TF_MITIGATION_FLUSH_NOSMT:
11120                 case L1TF_MITIGATION_FULL:
11121                         /*
11122                          * Warn upon starting the first VM in a potentially
11123                          * insecure environment.
11124                          */
11125                         if (cpu_smt_control == CPU_SMT_ENABLED)
11126                                 pr_warn_once(L1TF_MSG_SMT);
11127                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
11128                                 pr_warn_once(L1TF_MSG_L1D);
11129                         break;
11130                 case L1TF_MITIGATION_FULL_FORCE:
11131                         /* Flush is enforced */
11132                         break;
11133                 }
11134         }
11135         return 0;
11136 }
11137
11138 static void __init vmx_check_processor_compat(void *rtn)
11139 {
11140         struct vmcs_config vmcs_conf;
11141
11142         *(int *)rtn = 0;
11143         if (setup_vmcs_config(&vmcs_conf) < 0)
11144                 *(int *)rtn = -EIO;
11145         nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
11146         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
11147                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
11148                                 smp_processor_id());
11149                 *(int *)rtn = -EIO;
11150         }
11151 }
11152
11153 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
11154 {
11155         u8 cache;
11156         u64 ipat = 0;
11157
11158         /* For VT-d and EPT combination
11159          * 1. MMIO: always map as UC
11160          * 2. EPT with VT-d:
11161          *   a. VT-d without snooping control feature: can't guarantee the
11162          *      result, try to trust guest.
11163          *   b. VT-d with snooping control feature: snooping control feature of
11164          *      VT-d engine can guarantee the cache correctness. Just set it
11165          *      to WB to keep consistent with host. So the same as item 3.
11166          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
11167          *    consistent with host MTRR
11168          */
11169         if (is_mmio) {
11170                 cache = MTRR_TYPE_UNCACHABLE;
11171                 goto exit;
11172         }
11173
11174         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
11175                 ipat = VMX_EPT_IPAT_BIT;
11176                 cache = MTRR_TYPE_WRBACK;
11177                 goto exit;
11178         }
11179
11180         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
11181                 ipat = VMX_EPT_IPAT_BIT;
11182                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
11183                         cache = MTRR_TYPE_WRBACK;
11184                 else
11185                         cache = MTRR_TYPE_UNCACHABLE;
11186                 goto exit;
11187         }
11188
11189         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
11190
11191 exit:
11192         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
11193 }
11194
11195 static int vmx_get_lpage_level(void)
11196 {
11197         if (enable_ept && !cpu_has_vmx_ept_1g_page())
11198                 return PT_DIRECTORY_LEVEL;
11199         else
11200                 /* For shadow and EPT supported 1GB page */
11201                 return PT_PDPE_LEVEL;
11202 }
11203
11204 static void vmcs_set_secondary_exec_control(u32 new_ctl)
11205 {
11206         /*
11207          * These bits in the secondary execution controls field
11208          * are dynamic, the others are mostly based on the hypervisor
11209          * architecture and the guest's CPUID.  Do not touch the
11210          * dynamic bits.
11211          */
11212         u32 mask =
11213                 SECONDARY_EXEC_SHADOW_VMCS |
11214                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
11215                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11216                 SECONDARY_EXEC_DESC;
11217
11218         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
11219
11220         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
11221                      (new_ctl & ~mask) | (cur_ctl & mask));
11222 }
11223
11224 /*
11225  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
11226  * (indicating "allowed-1") if they are supported in the guest's CPUID.
11227  */
11228 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
11229 {
11230         struct vcpu_vmx *vmx = to_vmx(vcpu);
11231         struct kvm_cpuid_entry2 *entry;
11232
11233         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
11234         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
11235
11236 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
11237         if (entry && (entry->_reg & (_cpuid_mask)))                     \
11238                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
11239 } while (0)
11240
11241         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
11242         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
11243         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
11244         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
11245         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
11246         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
11247         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
11248         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
11249         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
11250         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
11251         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
11252         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
11253         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
11254         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
11255         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
11256
11257         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
11258         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
11259         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
11260         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
11261         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
11262         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
11263
11264 #undef cr4_fixed1_update
11265 }
11266
11267 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
11268 {
11269         struct vcpu_vmx *vmx = to_vmx(vcpu);
11270
11271         if (cpu_has_secondary_exec_ctrls()) {
11272                 vmx_compute_secondary_exec_control(vmx);
11273                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
11274         }
11275
11276         if (nested_vmx_allowed(vcpu))
11277                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11278                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11279         else
11280                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11281                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11282
11283         if (nested_vmx_allowed(vcpu))
11284                 nested_vmx_cr_fixed1_bits_update(vcpu);
11285 }
11286
11287 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
11288 {
11289         if (func == 1 && nested)
11290                 entry->ecx |= bit(X86_FEATURE_VMX);
11291 }
11292
11293 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
11294                 struct x86_exception *fault)
11295 {
11296         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11297         struct vcpu_vmx *vmx = to_vmx(vcpu);
11298         u32 exit_reason;
11299         unsigned long exit_qualification = vcpu->arch.exit_qualification;
11300
11301         if (vmx->nested.pml_full) {
11302                 exit_reason = EXIT_REASON_PML_FULL;
11303                 vmx->nested.pml_full = false;
11304                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
11305         } else if (fault->error_code & PFERR_RSVD_MASK)
11306                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
11307         else
11308                 exit_reason = EXIT_REASON_EPT_VIOLATION;
11309
11310         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
11311         vmcs12->guest_physical_address = fault->address;
11312 }
11313
11314 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
11315 {
11316         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
11317 }
11318
11319 /* Callbacks for nested_ept_init_mmu_context: */
11320
11321 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
11322 {
11323         /* return the page table to be shadowed - in our case, EPT12 */
11324         return get_vmcs12(vcpu)->ept_pointer;
11325 }
11326
11327 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
11328 {
11329         WARN_ON(mmu_is_nested(vcpu));
11330         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
11331                 return 1;
11332
11333         kvm_init_shadow_ept_mmu(vcpu,
11334                         to_vmx(vcpu)->nested.msrs.ept_caps &
11335                         VMX_EPT_EXECUTE_ONLY_BIT,
11336                         nested_ept_ad_enabled(vcpu),
11337                         nested_ept_get_cr3(vcpu));
11338         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
11339         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
11340         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
11341
11342         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
11343         return 0;
11344 }
11345
11346 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
11347 {
11348         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
11349 }
11350
11351 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
11352                                             u16 error_code)
11353 {
11354         bool inequality, bit;
11355
11356         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
11357         inequality =
11358                 (error_code & vmcs12->page_fault_error_code_mask) !=
11359                  vmcs12->page_fault_error_code_match;
11360         return inequality ^ bit;
11361 }
11362
11363 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
11364                 struct x86_exception *fault)
11365 {
11366         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11367
11368         WARN_ON(!is_guest_mode(vcpu));
11369
11370         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
11371                 !to_vmx(vcpu)->nested.nested_run_pending) {
11372                 vmcs12->vm_exit_intr_error_code = fault->error_code;
11373                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11374                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
11375                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
11376                                   fault->address);
11377         } else {
11378                 kvm_inject_page_fault(vcpu, fault);
11379         }
11380 }
11381
11382 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11383                                                  struct vmcs12 *vmcs12);
11384
11385 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
11386 {
11387         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11388         struct vcpu_vmx *vmx = to_vmx(vcpu);
11389         struct page *page;
11390         u64 hpa;
11391
11392         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11393                 /*
11394                  * Translate L1 physical address to host physical
11395                  * address for vmcs02. Keep the page pinned, so this
11396                  * physical address remains valid. We keep a reference
11397                  * to it so we can release it later.
11398                  */
11399                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
11400                         kvm_release_page_dirty(vmx->nested.apic_access_page);
11401                         vmx->nested.apic_access_page = NULL;
11402                 }
11403                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
11404                 /*
11405                  * If translation failed, no matter: This feature asks
11406                  * to exit when accessing the given address, and if it
11407                  * can never be accessed, this feature won't do
11408                  * anything anyway.
11409                  */
11410                 if (!is_error_page(page)) {
11411                         vmx->nested.apic_access_page = page;
11412                         hpa = page_to_phys(vmx->nested.apic_access_page);
11413                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
11414                 } else {
11415                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
11416                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
11417                 }
11418         }
11419
11420         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
11421                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
11422                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11423                         vmx->nested.virtual_apic_page = NULL;
11424                 }
11425                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
11426
11427                 /*
11428                  * If translation failed, VM entry will fail because
11429                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
11430                  * Failing the vm entry is _not_ what the processor
11431                  * does but it's basically the only possibility we
11432                  * have.  We could still enter the guest if CR8 load
11433                  * exits are enabled, CR8 store exits are enabled, and
11434                  * virtualize APIC access is disabled; in this case
11435                  * the processor would never use the TPR shadow and we
11436                  * could simply clear the bit from the execution
11437                  * control.  But such a configuration is useless, so
11438                  * let's keep the code simple.
11439                  */
11440                 if (!is_error_page(page)) {
11441                         vmx->nested.virtual_apic_page = page;
11442                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
11443                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
11444                 }
11445         }
11446
11447         if (nested_cpu_has_posted_intr(vmcs12)) {
11448                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
11449                         kunmap(vmx->nested.pi_desc_page);
11450                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
11451                         vmx->nested.pi_desc_page = NULL;
11452                 }
11453                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
11454                 if (is_error_page(page))
11455                         return;
11456                 vmx->nested.pi_desc_page = page;
11457                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
11458                 vmx->nested.pi_desc =
11459                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
11460                         (unsigned long)(vmcs12->posted_intr_desc_addr &
11461                         (PAGE_SIZE - 1)));
11462                 vmcs_write64(POSTED_INTR_DESC_ADDR,
11463                         page_to_phys(vmx->nested.pi_desc_page) +
11464                         (unsigned long)(vmcs12->posted_intr_desc_addr &
11465                         (PAGE_SIZE - 1)));
11466         }
11467         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
11468                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
11469                               CPU_BASED_USE_MSR_BITMAPS);
11470         else
11471                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
11472                                 CPU_BASED_USE_MSR_BITMAPS);
11473 }
11474
11475 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
11476 {
11477         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
11478         struct vcpu_vmx *vmx = to_vmx(vcpu);
11479
11480         /*
11481          * A timer value of zero is architecturally guaranteed to cause
11482          * a VMExit prior to executing any instructions in the guest.
11483          */
11484         if (preemption_timeout == 0) {
11485                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
11486                 return;
11487         }
11488
11489         if (vcpu->arch.virtual_tsc_khz == 0)
11490                 return;
11491
11492         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11493         preemption_timeout *= 1000000;
11494         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
11495         hrtimer_start(&vmx->nested.preemption_timer,
11496                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
11497 }
11498
11499 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
11500                                                struct vmcs12 *vmcs12)
11501 {
11502         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
11503                 return 0;
11504
11505         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
11506             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
11507                 return -EINVAL;
11508
11509         return 0;
11510 }
11511
11512 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
11513                                                 struct vmcs12 *vmcs12)
11514 {
11515         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11516                 return 0;
11517
11518         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
11519                 return -EINVAL;
11520
11521         return 0;
11522 }
11523
11524 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
11525                                                 struct vmcs12 *vmcs12)
11526 {
11527         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11528                 return 0;
11529
11530         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
11531                 return -EINVAL;
11532
11533         return 0;
11534 }
11535
11536 /*
11537  * Merge L0's and L1's MSR bitmap, return false to indicate that
11538  * we do not use the hardware.
11539  */
11540 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11541                                                  struct vmcs12 *vmcs12)
11542 {
11543         int msr;
11544         struct page *page;
11545         unsigned long *msr_bitmap_l1;
11546         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
11547         /*
11548          * pred_cmd & spec_ctrl are trying to verify two things:
11549          *
11550          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
11551          *    ensures that we do not accidentally generate an L02 MSR bitmap
11552          *    from the L12 MSR bitmap that is too permissive.
11553          * 2. That L1 or L2s have actually used the MSR. This avoids
11554          *    unnecessarily merging of the bitmap if the MSR is unused. This
11555          *    works properly because we only update the L01 MSR bitmap lazily.
11556          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
11557          *    updated to reflect this when L1 (or its L2s) actually write to
11558          *    the MSR.
11559          */
11560         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
11561         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
11562
11563         /* Nothing to do if the MSR bitmap is not in use.  */
11564         if (!cpu_has_vmx_msr_bitmap() ||
11565             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11566                 return false;
11567
11568         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11569             !pred_cmd && !spec_ctrl)
11570                 return false;
11571
11572         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
11573         if (is_error_page(page))
11574                 return false;
11575
11576         msr_bitmap_l1 = (unsigned long *)kmap(page);
11577         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
11578                 /*
11579                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
11580                  * just lets the processor take the value from the virtual-APIC page;
11581                  * take those 256 bits directly from the L1 bitmap.
11582                  */
11583                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11584                         unsigned word = msr / BITS_PER_LONG;
11585                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
11586                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11587                 }
11588         } else {
11589                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11590                         unsigned word = msr / BITS_PER_LONG;
11591                         msr_bitmap_l0[word] = ~0;
11592                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11593                 }
11594         }
11595
11596         nested_vmx_disable_intercept_for_msr(
11597                 msr_bitmap_l1, msr_bitmap_l0,
11598                 X2APIC_MSR(APIC_TASKPRI),
11599                 MSR_TYPE_W);
11600
11601         if (nested_cpu_has_vid(vmcs12)) {
11602                 nested_vmx_disable_intercept_for_msr(
11603                         msr_bitmap_l1, msr_bitmap_l0,
11604                         X2APIC_MSR(APIC_EOI),
11605                         MSR_TYPE_W);
11606                 nested_vmx_disable_intercept_for_msr(
11607                         msr_bitmap_l1, msr_bitmap_l0,
11608                         X2APIC_MSR(APIC_SELF_IPI),
11609                         MSR_TYPE_W);
11610         }
11611
11612         if (spec_ctrl)
11613                 nested_vmx_disable_intercept_for_msr(
11614                                         msr_bitmap_l1, msr_bitmap_l0,
11615                                         MSR_IA32_SPEC_CTRL,
11616                                         MSR_TYPE_R | MSR_TYPE_W);
11617
11618         if (pred_cmd)
11619                 nested_vmx_disable_intercept_for_msr(
11620                                         msr_bitmap_l1, msr_bitmap_l0,
11621                                         MSR_IA32_PRED_CMD,
11622                                         MSR_TYPE_W);
11623
11624         kunmap(page);
11625         kvm_release_page_clean(page);
11626
11627         return true;
11628 }
11629
11630 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
11631                                        struct vmcs12 *vmcs12)
11632 {
11633         struct vmcs12 *shadow;
11634         struct page *page;
11635
11636         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11637             vmcs12->vmcs_link_pointer == -1ull)
11638                 return;
11639
11640         shadow = get_shadow_vmcs12(vcpu);
11641         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
11642
11643         memcpy(shadow, kmap(page), VMCS12_SIZE);
11644
11645         kunmap(page);
11646         kvm_release_page_clean(page);
11647 }
11648
11649 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
11650                                               struct vmcs12 *vmcs12)
11651 {
11652         struct vcpu_vmx *vmx = to_vmx(vcpu);
11653
11654         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11655             vmcs12->vmcs_link_pointer == -1ull)
11656                 return;
11657
11658         kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer,
11659                         get_shadow_vmcs12(vcpu), VMCS12_SIZE);
11660 }
11661
11662 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
11663                                           struct vmcs12 *vmcs12)
11664 {
11665         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
11666             !page_address_valid(vcpu, vmcs12->apic_access_addr))
11667                 return -EINVAL;
11668         else
11669                 return 0;
11670 }
11671
11672 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
11673                                            struct vmcs12 *vmcs12)
11674 {
11675         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11676             !nested_cpu_has_apic_reg_virt(vmcs12) &&
11677             !nested_cpu_has_vid(vmcs12) &&
11678             !nested_cpu_has_posted_intr(vmcs12))
11679                 return 0;
11680
11681         /*
11682          * If virtualize x2apic mode is enabled,
11683          * virtualize apic access must be disabled.
11684          */
11685         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11686             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
11687                 return -EINVAL;
11688
11689         /*
11690          * If virtual interrupt delivery is enabled,
11691          * we must exit on external interrupts.
11692          */
11693         if (nested_cpu_has_vid(vmcs12) &&
11694            !nested_exit_on_intr(vcpu))
11695                 return -EINVAL;
11696
11697         /*
11698          * bits 15:8 should be zero in posted_intr_nv,
11699          * the descriptor address has been already checked
11700          * in nested_get_vmcs12_pages.
11701          *
11702          * bits 5:0 of posted_intr_desc_addr should be zero.
11703          */
11704         if (nested_cpu_has_posted_intr(vmcs12) &&
11705            (!nested_cpu_has_vid(vmcs12) ||
11706             !nested_exit_intr_ack_set(vcpu) ||
11707             (vmcs12->posted_intr_nv & 0xff00) ||
11708             (vmcs12->posted_intr_desc_addr & 0x3f) ||
11709             (!page_address_valid(vcpu, vmcs12->posted_intr_desc_addr))))
11710                 return -EINVAL;
11711
11712         /* tpr shadow is needed by all apicv features. */
11713         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11714                 return -EINVAL;
11715
11716         return 0;
11717 }
11718
11719 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
11720                                        unsigned long count_field,
11721                                        unsigned long addr_field)
11722 {
11723         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11724         int maxphyaddr;
11725         u64 count, addr;
11726
11727         if (vmcs12_read_any(vmcs12, count_field, &count) ||
11728             vmcs12_read_any(vmcs12, addr_field, &addr)) {
11729                 WARN_ON(1);
11730                 return -EINVAL;
11731         }
11732         if (count == 0)
11733                 return 0;
11734         maxphyaddr = cpuid_maxphyaddr(vcpu);
11735         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
11736             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
11737                 pr_debug_ratelimited(
11738                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
11739                         addr_field, maxphyaddr, count, addr);
11740                 return -EINVAL;
11741         }
11742         return 0;
11743 }
11744
11745 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
11746                                                 struct vmcs12 *vmcs12)
11747 {
11748         if (vmcs12->vm_exit_msr_load_count == 0 &&
11749             vmcs12->vm_exit_msr_store_count == 0 &&
11750             vmcs12->vm_entry_msr_load_count == 0)
11751                 return 0; /* Fast path */
11752         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
11753                                         VM_EXIT_MSR_LOAD_ADDR) ||
11754             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
11755                                         VM_EXIT_MSR_STORE_ADDR) ||
11756             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
11757                                         VM_ENTRY_MSR_LOAD_ADDR))
11758                 return -EINVAL;
11759         return 0;
11760 }
11761
11762 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
11763                                          struct vmcs12 *vmcs12)
11764 {
11765         u64 address = vmcs12->pml_address;
11766         int maxphyaddr = cpuid_maxphyaddr(vcpu);
11767
11768         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
11769                 if (!nested_cpu_has_ept(vmcs12) ||
11770                     !IS_ALIGNED(address, 4096)  ||
11771                     address >> maxphyaddr)
11772                         return -EINVAL;
11773         }
11774
11775         return 0;
11776 }
11777
11778 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
11779                                                  struct vmcs12 *vmcs12)
11780 {
11781         if (!nested_cpu_has_shadow_vmcs(vmcs12))
11782                 return 0;
11783
11784         if (!page_address_valid(vcpu, vmcs12->vmread_bitmap) ||
11785             !page_address_valid(vcpu, vmcs12->vmwrite_bitmap))
11786                 return -EINVAL;
11787
11788         return 0;
11789 }
11790
11791 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
11792                                        struct vmx_msr_entry *e)
11793 {
11794         /* x2APIC MSR accesses are not allowed */
11795         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
11796                 return -EINVAL;
11797         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
11798             e->index == MSR_IA32_UCODE_REV)
11799                 return -EINVAL;
11800         if (e->reserved != 0)
11801                 return -EINVAL;
11802         return 0;
11803 }
11804
11805 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
11806                                      struct vmx_msr_entry *e)
11807 {
11808         if (e->index == MSR_FS_BASE ||
11809             e->index == MSR_GS_BASE ||
11810             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11811             nested_vmx_msr_check_common(vcpu, e))
11812                 return -EINVAL;
11813         return 0;
11814 }
11815
11816 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11817                                       struct vmx_msr_entry *e)
11818 {
11819         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11820             nested_vmx_msr_check_common(vcpu, e))
11821                 return -EINVAL;
11822         return 0;
11823 }
11824
11825 /*
11826  * Load guest's/host's msr at nested entry/exit.
11827  * return 0 for success, entry index for failure.
11828  */
11829 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11830 {
11831         u32 i;
11832         struct vmx_msr_entry e;
11833         struct msr_data msr;
11834
11835         msr.host_initiated = false;
11836         for (i = 0; i < count; i++) {
11837                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11838                                         &e, sizeof(e))) {
11839                         pr_debug_ratelimited(
11840                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11841                                 __func__, i, gpa + i * sizeof(e));
11842                         goto fail;
11843                 }
11844                 if (nested_vmx_load_msr_check(vcpu, &e)) {
11845                         pr_debug_ratelimited(
11846                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11847                                 __func__, i, e.index, e.reserved);
11848                         goto fail;
11849                 }
11850                 msr.index = e.index;
11851                 msr.data = e.value;
11852                 if (kvm_set_msr(vcpu, &msr)) {
11853                         pr_debug_ratelimited(
11854                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11855                                 __func__, i, e.index, e.value);
11856                         goto fail;
11857                 }
11858         }
11859         return 0;
11860 fail:
11861         return i + 1;
11862 }
11863
11864 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11865 {
11866         u32 i;
11867         struct vmx_msr_entry e;
11868
11869         for (i = 0; i < count; i++) {
11870                 struct msr_data msr_info;
11871                 if (kvm_vcpu_read_guest(vcpu,
11872                                         gpa + i * sizeof(e),
11873                                         &e, 2 * sizeof(u32))) {
11874                         pr_debug_ratelimited(
11875                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11876                                 __func__, i, gpa + i * sizeof(e));
11877                         return -EINVAL;
11878                 }
11879                 if (nested_vmx_store_msr_check(vcpu, &e)) {
11880                         pr_debug_ratelimited(
11881                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11882                                 __func__, i, e.index, e.reserved);
11883                         return -EINVAL;
11884                 }
11885                 msr_info.host_initiated = false;
11886                 msr_info.index = e.index;
11887                 if (kvm_get_msr(vcpu, &msr_info)) {
11888                         pr_debug_ratelimited(
11889                                 "%s cannot read MSR (%u, 0x%x)\n",
11890                                 __func__, i, e.index);
11891                         return -EINVAL;
11892                 }
11893                 if (kvm_vcpu_write_guest(vcpu,
11894                                          gpa + i * sizeof(e) +
11895                                              offsetof(struct vmx_msr_entry, value),
11896                                          &msr_info.data, sizeof(msr_info.data))) {
11897                         pr_debug_ratelimited(
11898                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11899                                 __func__, i, e.index, msr_info.data);
11900                         return -EINVAL;
11901                 }
11902         }
11903         return 0;
11904 }
11905
11906 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11907 {
11908         unsigned long invalid_mask;
11909
11910         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11911         return (val & invalid_mask) == 0;
11912 }
11913
11914 /*
11915  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11916  * emulating VM entry into a guest with EPT enabled.
11917  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11918  * is assigned to entry_failure_code on failure.
11919  */
11920 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11921                                u32 *entry_failure_code)
11922 {
11923         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11924                 if (!nested_cr3_valid(vcpu, cr3)) {
11925                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11926                         return 1;
11927                 }
11928
11929                 /*
11930                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11931                  * must not be dereferenced.
11932                  */
11933                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11934                     !nested_ept) {
11935                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11936                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
11937                                 return 1;
11938                         }
11939                 }
11940         }
11941
11942         if (!nested_ept)
11943                 kvm_mmu_new_cr3(vcpu, cr3, false);
11944
11945         vcpu->arch.cr3 = cr3;
11946         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11947
11948         kvm_init_mmu(vcpu, false);
11949
11950         return 0;
11951 }
11952
11953 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11954 {
11955         struct vcpu_vmx *vmx = to_vmx(vcpu);
11956
11957         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11958         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11959         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11960         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11961         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11962         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11963         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11964         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11965         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11966         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11967         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11968         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11969         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11970         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11971         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11972         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11973         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11974         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11975         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11976         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11977         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11978         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11979         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11980         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11981         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11982         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11983         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11984         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11985         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11986         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11987         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11988
11989         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11990         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11991                 vmcs12->guest_pending_dbg_exceptions);
11992         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11993         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
11994
11995         if (nested_cpu_has_xsaves(vmcs12))
11996                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
11997         vmcs_write64(VMCS_LINK_POINTER, -1ull);
11998
11999         if (cpu_has_vmx_posted_intr())
12000                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
12001
12002         /*
12003          * Whether page-faults are trapped is determined by a combination of
12004          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
12005          * If enable_ept, L0 doesn't care about page faults and we should
12006          * set all of these to L1's desires. However, if !enable_ept, L0 does
12007          * care about (at least some) page faults, and because it is not easy
12008          * (if at all possible?) to merge L0 and L1's desires, we simply ask
12009          * to exit on each and every L2 page fault. This is done by setting
12010          * MASK=MATCH=0 and (see below) EB.PF=1.
12011          * Note that below we don't need special code to set EB.PF beyond the
12012          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
12013          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
12014          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
12015          */
12016         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
12017                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
12018         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
12019                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
12020
12021         /* All VMFUNCs are currently emulated through L0 vmexits.  */
12022         if (cpu_has_vmx_vmfunc())
12023                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
12024
12025         if (cpu_has_vmx_apicv()) {
12026                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
12027                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
12028                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
12029                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
12030         }
12031
12032         /*
12033          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
12034          * Some constant fields are set here by vmx_set_constant_host_state().
12035          * Other fields are different per CPU, and will be set later when
12036          * vmx_vcpu_load() is called, and when vmx_prepare_switch_to_guest()
12037          * is called.
12038          */
12039         vmx_set_constant_host_state(vmx);
12040
12041         /*
12042          * Set the MSR load/store lists to match L0's settings.
12043          */
12044         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
12045         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
12046         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
12047         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
12048         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
12049
12050         set_cr4_guest_host_mask(vmx);
12051
12052         if (vmx_mpx_supported())
12053                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
12054
12055         if (enable_vpid) {
12056                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
12057                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
12058                 else
12059                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
12060         }
12061
12062         /*
12063          * L1 may access the L2's PDPTR, so save them to construct vmcs12
12064          */
12065         if (enable_ept) {
12066                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
12067                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
12068                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
12069                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
12070         }
12071
12072         if (cpu_has_vmx_msr_bitmap())
12073                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
12074 }
12075
12076 /*
12077  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
12078  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
12079  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
12080  * guest in a way that will both be appropriate to L1's requests, and our
12081  * needs. In addition to modifying the active vmcs (which is vmcs02), this
12082  * function also has additional necessary side-effects, like setting various
12083  * vcpu->arch fields.
12084  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
12085  * is assigned to entry_failure_code on failure.
12086  */
12087 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12088                           u32 *entry_failure_code)
12089 {
12090         struct vcpu_vmx *vmx = to_vmx(vcpu);
12091         u32 exec_control, vmcs12_exec_ctrl;
12092
12093         if (vmx->nested.dirty_vmcs12) {
12094                 prepare_vmcs02_full(vcpu, vmcs12);
12095                 vmx->nested.dirty_vmcs12 = false;
12096         }
12097
12098         /*
12099          * First, the fields that are shadowed.  This must be kept in sync
12100          * with vmx_shadow_fields.h.
12101          */
12102
12103         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
12104         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
12105         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
12106         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
12107         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
12108
12109         if (vmx->nested.nested_run_pending &&
12110             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
12111                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
12112                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
12113         } else {
12114                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
12115                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
12116         }
12117         if (vmx->nested.nested_run_pending) {
12118                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
12119                              vmcs12->vm_entry_intr_info_field);
12120                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
12121                              vmcs12->vm_entry_exception_error_code);
12122                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
12123                              vmcs12->vm_entry_instruction_len);
12124                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
12125                              vmcs12->guest_interruptibility_info);
12126                 vmx->loaded_vmcs->nmi_known_unmasked =
12127                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
12128         } else {
12129                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
12130         }
12131         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
12132
12133         exec_control = vmcs12->pin_based_vm_exec_control;
12134
12135         /* Preemption timer setting is computed directly in vmx_vcpu_run.  */
12136         exec_control |= vmcs_config.pin_based_exec_ctrl;
12137         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
12138         vmx->loaded_vmcs->hv_timer_armed = false;
12139
12140         /* Posted interrupts setting is only taken from vmcs12.  */
12141         if (nested_cpu_has_posted_intr(vmcs12)) {
12142                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
12143                 vmx->nested.pi_pending = false;
12144         } else {
12145                 exec_control &= ~PIN_BASED_POSTED_INTR;
12146         }
12147
12148         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
12149
12150         vmx->nested.preemption_timer_expired = false;
12151         if (nested_cpu_has_preemption_timer(vmcs12))
12152                 vmx_start_preemption_timer(vcpu);
12153
12154         if (cpu_has_secondary_exec_ctrls()) {
12155                 exec_control = vmx->secondary_exec_control;
12156
12157                 /* Take the following fields only from vmcs12 */
12158                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
12159                                   SECONDARY_EXEC_ENABLE_INVPCID |
12160                                   SECONDARY_EXEC_RDTSCP |
12161                                   SECONDARY_EXEC_XSAVES |
12162                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
12163                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
12164                                   SECONDARY_EXEC_ENABLE_VMFUNC);
12165                 if (nested_cpu_has(vmcs12,
12166                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
12167                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
12168                                 ~SECONDARY_EXEC_ENABLE_PML;
12169                         exec_control |= vmcs12_exec_ctrl;
12170                 }
12171
12172                 /* VMCS shadowing for L2 is emulated for now */
12173                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
12174
12175                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
12176                         vmcs_write16(GUEST_INTR_STATUS,
12177                                 vmcs12->guest_intr_status);
12178
12179                 /*
12180                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
12181                  * nested_get_vmcs12_pages will either fix it up or
12182                  * remove the VM execution control.
12183                  */
12184                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
12185                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
12186
12187                 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
12188                         vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
12189
12190                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
12191         }
12192
12193         /*
12194          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
12195          * entry, but only if the current (host) sp changed from the value
12196          * we wrote last (vmx->host_rsp). This cache is no longer relevant
12197          * if we switch vmcs, and rather than hold a separate cache per vmcs,
12198          * here we just force the write to happen on entry.
12199          */
12200         vmx->host_rsp = 0;
12201
12202         exec_control = vmx_exec_control(vmx); /* L0's desires */
12203         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
12204         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
12205         exec_control &= ~CPU_BASED_TPR_SHADOW;
12206         exec_control |= vmcs12->cpu_based_vm_exec_control;
12207
12208         /*
12209          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
12210          * nested_get_vmcs12_pages can't fix it up, the illegal value
12211          * will result in a VM entry failure.
12212          */
12213         if (exec_control & CPU_BASED_TPR_SHADOW) {
12214                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
12215                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
12216         } else {
12217 #ifdef CONFIG_X86_64
12218                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
12219                                 CPU_BASED_CR8_STORE_EXITING;
12220 #endif
12221         }
12222
12223         /*
12224          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
12225          * for I/O port accesses.
12226          */
12227         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
12228         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
12229
12230         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
12231
12232         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
12233          * bitwise-or of what L1 wants to trap for L2, and what we want to
12234          * trap. Note that CR0.TS also needs updating - we do this later.
12235          */
12236         update_exception_bitmap(vcpu);
12237         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
12238         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
12239
12240         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
12241          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
12242          * bits are further modified by vmx_set_efer() below.
12243          */
12244         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
12245
12246         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
12247          * emulated by vmx_set_efer(), below.
12248          */
12249         vm_entry_controls_init(vmx,
12250                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
12251                         ~VM_ENTRY_IA32E_MODE) |
12252                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
12253
12254         if (vmx->nested.nested_run_pending &&
12255             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
12256                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
12257                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
12258         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
12259                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
12260         }
12261
12262         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12263
12264         if (kvm_has_tsc_control)
12265                 decache_tsc_multiplier(vmx);
12266
12267         if (enable_vpid) {
12268                 /*
12269                  * There is no direct mapping between vpid02 and vpid12, the
12270                  * vpid02 is per-vCPU for L0 and reused while the value of
12271                  * vpid12 is changed w/ one invvpid during nested vmentry.
12272                  * The vpid12 is allocated by L1 for L2, so it will not
12273                  * influence global bitmap(for vpid01 and vpid02 allocation)
12274                  * even if spawn a lot of nested vCPUs.
12275                  */
12276                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
12277                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
12278                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
12279                                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
12280                         }
12281                 } else {
12282                         vmx_flush_tlb(vcpu, true);
12283                 }
12284         }
12285
12286         if (enable_pml) {
12287                 /*
12288                  * Conceptually we want to copy the PML address and index from
12289                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
12290                  * since we always flush the log on each vmexit, this happens
12291                  * to be equivalent to simply resetting the fields in vmcs02.
12292                  */
12293                 ASSERT(vmx->pml_pg);
12294                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
12295                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
12296         }
12297
12298         if (nested_cpu_has_ept(vmcs12)) {
12299                 if (nested_ept_init_mmu_context(vcpu)) {
12300                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
12301                         return 1;
12302                 }
12303         } else if (nested_cpu_has2(vmcs12,
12304                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12305                 vmx_flush_tlb(vcpu, true);
12306         }
12307
12308         /*
12309          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
12310          * bits which we consider mandatory enabled.
12311          * The CR0_READ_SHADOW is what L2 should have expected to read given
12312          * the specifications by L1; It's not enough to take
12313          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
12314          * have more bits than L1 expected.
12315          */
12316         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
12317         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
12318
12319         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
12320         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
12321
12322         if (vmx->nested.nested_run_pending &&
12323             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
12324                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
12325         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
12326                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
12327         else
12328                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
12329         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
12330         vmx_set_efer(vcpu, vcpu->arch.efer);
12331
12332         /*
12333          * Guest state is invalid and unrestricted guest is disabled,
12334          * which means L1 attempted VMEntry to L2 with invalid state.
12335          * Fail the VMEntry.
12336          */
12337         if (vmx->emulation_required) {
12338                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
12339                 return 1;
12340         }
12341
12342         /* Shadow page tables on either EPT or shadow page tables. */
12343         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
12344                                 entry_failure_code))
12345                 return 1;
12346
12347         if (!enable_ept)
12348                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
12349
12350         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
12351         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
12352         return 0;
12353 }
12354
12355 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
12356 {
12357         if (!nested_cpu_has_nmi_exiting(vmcs12) &&
12358             nested_cpu_has_virtual_nmis(vmcs12))
12359                 return -EINVAL;
12360
12361         if (!nested_cpu_has_virtual_nmis(vmcs12) &&
12362             nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
12363                 return -EINVAL;
12364
12365         return 0;
12366 }
12367
12368 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12369 {
12370         struct vcpu_vmx *vmx = to_vmx(vcpu);
12371
12372         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
12373             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
12374                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12375
12376         if (nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id)
12377                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12378
12379         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
12380                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12381
12382         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
12383                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12384
12385         if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
12386                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12387
12388         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
12389                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12390
12391         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
12392                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12393
12394         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
12395                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12396
12397         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
12398                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12399
12400         if (nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12))
12401                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12402
12403         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
12404                                 vmx->nested.msrs.procbased_ctls_low,
12405                                 vmx->nested.msrs.procbased_ctls_high) ||
12406             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
12407              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
12408                                  vmx->nested.msrs.secondary_ctls_low,
12409                                  vmx->nested.msrs.secondary_ctls_high)) ||
12410             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
12411                                 vmx->nested.msrs.pinbased_ctls_low,
12412                                 vmx->nested.msrs.pinbased_ctls_high) ||
12413             !vmx_control_verify(vmcs12->vm_exit_controls,
12414                                 vmx->nested.msrs.exit_ctls_low,
12415                                 vmx->nested.msrs.exit_ctls_high) ||
12416             !vmx_control_verify(vmcs12->vm_entry_controls,
12417                                 vmx->nested.msrs.entry_ctls_low,
12418                                 vmx->nested.msrs.entry_ctls_high))
12419                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12420
12421         if (nested_vmx_check_nmi_controls(vmcs12))
12422                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12423
12424         if (nested_cpu_has_vmfunc(vmcs12)) {
12425                 if (vmcs12->vm_function_control &
12426                     ~vmx->nested.msrs.vmfunc_controls)
12427                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12428
12429                 if (nested_cpu_has_eptp_switching(vmcs12)) {
12430                         if (!nested_cpu_has_ept(vmcs12) ||
12431                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
12432                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12433                 }
12434         }
12435
12436         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
12437                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12438
12439         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
12440             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
12441             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
12442                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
12443
12444         /*
12445          * From the Intel SDM, volume 3:
12446          * Fields relevant to VM-entry event injection must be set properly.
12447          * These fields are the VM-entry interruption-information field, the
12448          * VM-entry exception error code, and the VM-entry instruction length.
12449          */
12450         if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
12451                 u32 intr_info = vmcs12->vm_entry_intr_info_field;
12452                 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
12453                 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
12454                 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
12455                 bool should_have_error_code;
12456                 bool urg = nested_cpu_has2(vmcs12,
12457                                            SECONDARY_EXEC_UNRESTRICTED_GUEST);
12458                 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
12459
12460                 /* VM-entry interruption-info field: interruption type */
12461                 if (intr_type == INTR_TYPE_RESERVED ||
12462                     (intr_type == INTR_TYPE_OTHER_EVENT &&
12463                      !nested_cpu_supports_monitor_trap_flag(vcpu)))
12464                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12465
12466                 /* VM-entry interruption-info field: vector */
12467                 if ((intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
12468                     (intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
12469                     (intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
12470                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12471
12472                 /* VM-entry interruption-info field: deliver error code */
12473                 should_have_error_code =
12474                         intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
12475                         x86_exception_has_error_code(vector);
12476                 if (has_error_code != should_have_error_code)
12477                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12478
12479                 /* VM-entry exception error code */
12480                 if (has_error_code &&
12481                     vmcs12->vm_entry_exception_error_code & GENMASK(31, 15))
12482                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12483
12484                 /* VM-entry interruption-info field: reserved bits */
12485                 if (intr_info & INTR_INFO_RESVD_BITS_MASK)
12486                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12487
12488                 /* VM-entry instruction length */
12489                 switch (intr_type) {
12490                 case INTR_TYPE_SOFT_EXCEPTION:
12491                 case INTR_TYPE_SOFT_INTR:
12492                 case INTR_TYPE_PRIV_SW_EXCEPTION:
12493                         if ((vmcs12->vm_entry_instruction_len > 15) ||
12494                             (vmcs12->vm_entry_instruction_len == 0 &&
12495                              !nested_cpu_has_zero_length_injection(vcpu)))
12496                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12497                 }
12498         }
12499
12500         return 0;
12501 }
12502
12503 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
12504                                           struct vmcs12 *vmcs12)
12505 {
12506         int r;
12507         struct page *page;
12508         struct vmcs12 *shadow;
12509
12510         if (vmcs12->vmcs_link_pointer == -1ull)
12511                 return 0;
12512
12513         if (!page_address_valid(vcpu, vmcs12->vmcs_link_pointer))
12514                 return -EINVAL;
12515
12516         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
12517         if (is_error_page(page))
12518                 return -EINVAL;
12519
12520         r = 0;
12521         shadow = kmap(page);
12522         if (shadow->hdr.revision_id != VMCS12_REVISION ||
12523             shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12))
12524                 r = -EINVAL;
12525         kunmap(page);
12526         kvm_release_page_clean(page);
12527         return r;
12528 }
12529
12530 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12531                                   u32 *exit_qual)
12532 {
12533         bool ia32e;
12534
12535         *exit_qual = ENTRY_FAIL_DEFAULT;
12536
12537         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
12538             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
12539                 return 1;
12540
12541         if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
12542                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
12543                 return 1;
12544         }
12545
12546         /*
12547          * If the load IA32_EFER VM-entry control is 1, the following checks
12548          * are performed on the field for the IA32_EFER MSR:
12549          * - Bits reserved in the IA32_EFER MSR must be 0.
12550          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
12551          *   the IA-32e mode guest VM-exit control. It must also be identical
12552          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
12553          *   CR0.PG) is 1.
12554          */
12555         if (to_vmx(vcpu)->nested.nested_run_pending &&
12556             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
12557                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
12558                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
12559                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
12560                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
12561                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
12562                         return 1;
12563         }
12564
12565         /*
12566          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
12567          * IA32_EFER MSR must be 0 in the field for that register. In addition,
12568          * the values of the LMA and LME bits in the field must each be that of
12569          * the host address-space size VM-exit control.
12570          */
12571         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
12572                 ia32e = (vmcs12->vm_exit_controls &
12573                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
12574                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
12575                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
12576                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
12577                         return 1;
12578         }
12579
12580         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
12581                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
12582                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
12583                         return 1;
12584
12585         return 0;
12586 }
12587
12588 /*
12589  * If exit_qual is NULL, this is being called from state restore (either RSM
12590  * or KVM_SET_NESTED_STATE).  Otherwise it's called from vmlaunch/vmresume.
12591  */
12592 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, u32 *exit_qual)
12593 {
12594         struct vcpu_vmx *vmx = to_vmx(vcpu);
12595         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12596         bool from_vmentry = !!exit_qual;
12597         u32 dummy_exit_qual;
12598         u32 vmcs01_cpu_exec_ctrl;
12599         int r = 0;
12600
12601         vmcs01_cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
12602
12603         enter_guest_mode(vcpu);
12604
12605         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
12606                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12607
12608         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
12609         vmx_segment_cache_clear(vmx);
12610
12611         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12612                 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
12613
12614         r = EXIT_REASON_INVALID_STATE;
12615         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry ? exit_qual : &dummy_exit_qual))
12616                 goto fail;
12617
12618         if (from_vmentry) {
12619                 nested_get_vmcs12_pages(vcpu);
12620
12621                 r = EXIT_REASON_MSR_LOAD_FAIL;
12622                 *exit_qual = nested_vmx_load_msr(vcpu,
12623                                                  vmcs12->vm_entry_msr_load_addr,
12624                                                  vmcs12->vm_entry_msr_load_count);
12625                 if (*exit_qual)
12626                         goto fail;
12627         } else {
12628                 /*
12629                  * The MMU is not initialized to point at the right entities yet and
12630                  * "get pages" would need to read data from the guest (i.e. we will
12631                  * need to perform gpa to hpa translation). Request a call
12632                  * to nested_get_vmcs12_pages before the next VM-entry.  The MSRs
12633                  * have already been set at vmentry time and should not be reset.
12634                  */
12635                 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
12636         }
12637
12638         /*
12639          * If L1 had a pending IRQ/NMI until it executed
12640          * VMLAUNCH/VMRESUME which wasn't delivered because it was
12641          * disallowed (e.g. interrupts disabled), L0 needs to
12642          * evaluate if this pending event should cause an exit from L2
12643          * to L1 or delivered directly to L2 (e.g. In case L1 don't
12644          * intercept EXTERNAL_INTERRUPT).
12645          *
12646          * Usually this would be handled by L0 requesting a
12647          * IRQ/NMI window by setting VMCS accordingly. However,
12648          * this setting was done on VMCS01 and now VMCS02 is active
12649          * instead. Thus, we force L0 to perform pending event
12650          * evaluation by requesting a KVM_REQ_EVENT.
12651          */
12652         if (vmcs01_cpu_exec_ctrl &
12653                 (CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_VIRTUAL_NMI_PENDING)) {
12654                 kvm_make_request(KVM_REQ_EVENT, vcpu);
12655         }
12656
12657         /*
12658          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
12659          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
12660          * returned as far as L1 is concerned. It will only return (and set
12661          * the success flag) when L2 exits (see nested_vmx_vmexit()).
12662          */
12663         return 0;
12664
12665 fail:
12666         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12667                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12668         leave_guest_mode(vcpu);
12669         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12670         return r;
12671 }
12672
12673 /*
12674  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
12675  * for running an L2 nested guest.
12676  */
12677 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
12678 {
12679         struct vmcs12 *vmcs12;
12680         struct vcpu_vmx *vmx = to_vmx(vcpu);
12681         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
12682         u32 exit_qual;
12683         int ret;
12684
12685         if (!nested_vmx_check_permission(vcpu))
12686                 return 1;
12687
12688         if (!nested_vmx_check_vmcs12(vcpu))
12689                 goto out;
12690
12691         vmcs12 = get_vmcs12(vcpu);
12692
12693         /*
12694          * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
12695          * that there *is* a valid VMCS pointer, RFLAGS.CF is set
12696          * rather than RFLAGS.ZF, and no error number is stored to the
12697          * VM-instruction error field.
12698          */
12699         if (vmcs12->hdr.shadow_vmcs) {
12700                 nested_vmx_failInvalid(vcpu);
12701                 goto out;
12702         }
12703
12704         if (enable_shadow_vmcs)
12705                 copy_shadow_to_vmcs12(vmx);
12706
12707         /*
12708          * The nested entry process starts with enforcing various prerequisites
12709          * on vmcs12 as required by the Intel SDM, and act appropriately when
12710          * they fail: As the SDM explains, some conditions should cause the
12711          * instruction to fail, while others will cause the instruction to seem
12712          * to succeed, but return an EXIT_REASON_INVALID_STATE.
12713          * To speed up the normal (success) code path, we should avoid checking
12714          * for misconfigurations which will anyway be caught by the processor
12715          * when using the merged vmcs02.
12716          */
12717         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
12718                 nested_vmx_failValid(vcpu,
12719                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
12720                 goto out;
12721         }
12722
12723         if (vmcs12->launch_state == launch) {
12724                 nested_vmx_failValid(vcpu,
12725                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
12726                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
12727                 goto out;
12728         }
12729
12730         ret = check_vmentry_prereqs(vcpu, vmcs12);
12731         if (ret) {
12732                 nested_vmx_failValid(vcpu, ret);
12733                 goto out;
12734         }
12735
12736         /*
12737          * After this point, the trap flag no longer triggers a singlestep trap
12738          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
12739          * This is not 100% correct; for performance reasons, we delegate most
12740          * of the checks on host state to the processor.  If those fail,
12741          * the singlestep trap is missed.
12742          */
12743         skip_emulated_instruction(vcpu);
12744
12745         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
12746         if (ret) {
12747                 nested_vmx_entry_failure(vcpu, vmcs12,
12748                                          EXIT_REASON_INVALID_STATE, exit_qual);
12749                 return 1;
12750         }
12751
12752         /*
12753          * We're finally done with prerequisite checking, and can start with
12754          * the nested entry.
12755          */
12756
12757         vmx->nested.nested_run_pending = 1;
12758         ret = enter_vmx_non_root_mode(vcpu, &exit_qual);
12759         if (ret) {
12760                 nested_vmx_entry_failure(vcpu, vmcs12, ret, exit_qual);
12761                 vmx->nested.nested_run_pending = 0;
12762                 return 1;
12763         }
12764
12765         /* Hide L1D cache contents from the nested guest.  */
12766         vmx->vcpu.arch.l1tf_flush_l1d = true;
12767
12768         /*
12769          * Must happen outside of enter_vmx_non_root_mode() as it will
12770          * also be used as part of restoring nVMX state for
12771          * snapshot restore (migration).
12772          *
12773          * In this flow, it is assumed that vmcs12 cache was
12774          * trasferred as part of captured nVMX state and should
12775          * therefore not be read from guest memory (which may not
12776          * exist on destination host yet).
12777          */
12778         nested_cache_shadow_vmcs12(vcpu, vmcs12);
12779
12780         /*
12781          * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
12782          * by event injection, halt vcpu.
12783          */
12784         if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
12785             !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
12786                 vmx->nested.nested_run_pending = 0;
12787                 return kvm_vcpu_halt(vcpu);
12788         }
12789         return 1;
12790
12791 out:
12792         return kvm_skip_emulated_instruction(vcpu);
12793 }
12794
12795 /*
12796  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
12797  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
12798  * This function returns the new value we should put in vmcs12.guest_cr0.
12799  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
12800  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
12801  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
12802  *     didn't trap the bit, because if L1 did, so would L0).
12803  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
12804  *     been modified by L2, and L1 knows it. So just leave the old value of
12805  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
12806  *     isn't relevant, because if L0 traps this bit it can set it to anything.
12807  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
12808  *     changed these bits, and therefore they need to be updated, but L0
12809  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
12810  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
12811  */
12812 static inline unsigned long
12813 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12814 {
12815         return
12816         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
12817         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
12818         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
12819                         vcpu->arch.cr0_guest_owned_bits));
12820 }
12821
12822 static inline unsigned long
12823 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12824 {
12825         return
12826         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
12827         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
12828         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
12829                         vcpu->arch.cr4_guest_owned_bits));
12830 }
12831
12832 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
12833                                        struct vmcs12 *vmcs12)
12834 {
12835         u32 idt_vectoring;
12836         unsigned int nr;
12837
12838         if (vcpu->arch.exception.injected) {
12839                 nr = vcpu->arch.exception.nr;
12840                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12841
12842                 if (kvm_exception_is_soft(nr)) {
12843                         vmcs12->vm_exit_instruction_len =
12844                                 vcpu->arch.event_exit_inst_len;
12845                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
12846                 } else
12847                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
12848
12849                 if (vcpu->arch.exception.has_error_code) {
12850                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
12851                         vmcs12->idt_vectoring_error_code =
12852                                 vcpu->arch.exception.error_code;
12853                 }
12854
12855                 vmcs12->idt_vectoring_info_field = idt_vectoring;
12856         } else if (vcpu->arch.nmi_injected) {
12857                 vmcs12->idt_vectoring_info_field =
12858                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
12859         } else if (vcpu->arch.interrupt.injected) {
12860                 nr = vcpu->arch.interrupt.nr;
12861                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12862
12863                 if (vcpu->arch.interrupt.soft) {
12864                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
12865                         vmcs12->vm_entry_instruction_len =
12866                                 vcpu->arch.event_exit_inst_len;
12867                 } else
12868                         idt_vectoring |= INTR_TYPE_EXT_INTR;
12869
12870                 vmcs12->idt_vectoring_info_field = idt_vectoring;
12871         }
12872 }
12873
12874 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
12875 {
12876         struct vcpu_vmx *vmx = to_vmx(vcpu);
12877         unsigned long exit_qual;
12878         bool block_nested_events =
12879             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
12880
12881         if (vcpu->arch.exception.pending &&
12882                 nested_vmx_check_exception(vcpu, &exit_qual)) {
12883                 if (block_nested_events)
12884                         return -EBUSY;
12885                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
12886                 return 0;
12887         }
12888
12889         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
12890             vmx->nested.preemption_timer_expired) {
12891                 if (block_nested_events)
12892                         return -EBUSY;
12893                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
12894                 return 0;
12895         }
12896
12897         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
12898                 if (block_nested_events)
12899                         return -EBUSY;
12900                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
12901                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
12902                                   INTR_INFO_VALID_MASK, 0);
12903                 /*
12904                  * The NMI-triggered VM exit counts as injection:
12905                  * clear this one and block further NMIs.
12906                  */
12907                 vcpu->arch.nmi_pending = 0;
12908                 vmx_set_nmi_mask(vcpu, true);
12909                 return 0;
12910         }
12911
12912         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
12913             nested_exit_on_intr(vcpu)) {
12914                 if (block_nested_events)
12915                         return -EBUSY;
12916                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
12917                 return 0;
12918         }
12919
12920         vmx_complete_nested_posted_interrupt(vcpu);
12921         return 0;
12922 }
12923
12924 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
12925 {
12926         to_vmx(vcpu)->req_immediate_exit = true;
12927 }
12928
12929 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
12930 {
12931         ktime_t remaining =
12932                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
12933         u64 value;
12934
12935         if (ktime_to_ns(remaining) <= 0)
12936                 return 0;
12937
12938         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
12939         do_div(value, 1000000);
12940         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
12941 }
12942
12943 /*
12944  * Update the guest state fields of vmcs12 to reflect changes that
12945  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
12946  * VM-entry controls is also updated, since this is really a guest
12947  * state bit.)
12948  */
12949 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12950 {
12951         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
12952         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
12953
12954         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
12955         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
12956         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
12957
12958         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
12959         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
12960         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
12961         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
12962         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
12963         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
12964         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
12965         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
12966         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
12967         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
12968         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
12969         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
12970         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
12971         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
12972         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
12973         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
12974         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
12975         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
12976         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
12977         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
12978         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
12979         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
12980         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
12981         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
12982         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
12983         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
12984         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
12985         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
12986         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
12987         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
12988         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
12989         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
12990         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
12991         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
12992         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
12993         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
12994
12995         vmcs12->guest_interruptibility_info =
12996                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
12997         vmcs12->guest_pending_dbg_exceptions =
12998                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
12999         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
13000                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
13001         else
13002                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
13003
13004         if (nested_cpu_has_preemption_timer(vmcs12)) {
13005                 if (vmcs12->vm_exit_controls &
13006                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
13007                         vmcs12->vmx_preemption_timer_value =
13008                                 vmx_get_preemption_timer_value(vcpu);
13009                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
13010         }
13011
13012         /*
13013          * In some cases (usually, nested EPT), L2 is allowed to change its
13014          * own CR3 without exiting. If it has changed it, we must keep it.
13015          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
13016          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
13017          *
13018          * Additionally, restore L2's PDPTR to vmcs12.
13019          */
13020         if (enable_ept) {
13021                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
13022                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
13023                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
13024                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
13025                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
13026         }
13027
13028         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
13029
13030         if (nested_cpu_has_vid(vmcs12))
13031                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
13032
13033         vmcs12->vm_entry_controls =
13034                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
13035                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
13036
13037         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
13038                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
13039                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
13040         }
13041
13042         /* TODO: These cannot have changed unless we have MSR bitmaps and
13043          * the relevant bit asks not to trap the change */
13044         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
13045                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
13046         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
13047                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
13048         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
13049         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
13050         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
13051         if (kvm_mpx_supported())
13052                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
13053 }
13054
13055 /*
13056  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
13057  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
13058  * and this function updates it to reflect the changes to the guest state while
13059  * L2 was running (and perhaps made some exits which were handled directly by L0
13060  * without going back to L1), and to reflect the exit reason.
13061  * Note that we do not have to copy here all VMCS fields, just those that
13062  * could have changed by the L2 guest or the exit - i.e., the guest-state and
13063  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
13064  * which already writes to vmcs12 directly.
13065  */
13066 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
13067                            u32 exit_reason, u32 exit_intr_info,
13068                            unsigned long exit_qualification)
13069 {
13070         /* update guest state fields: */
13071         sync_vmcs12(vcpu, vmcs12);
13072
13073         /* update exit information fields: */
13074
13075         vmcs12->vm_exit_reason = exit_reason;
13076         vmcs12->exit_qualification = exit_qualification;
13077         vmcs12->vm_exit_intr_info = exit_intr_info;
13078
13079         vmcs12->idt_vectoring_info_field = 0;
13080         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
13081         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
13082
13083         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
13084                 vmcs12->launch_state = 1;
13085
13086                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
13087                  * instead of reading the real value. */
13088                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
13089
13090                 /*
13091                  * Transfer the event that L0 or L1 may wanted to inject into
13092                  * L2 to IDT_VECTORING_INFO_FIELD.
13093                  */
13094                 vmcs12_save_pending_event(vcpu, vmcs12);
13095         }
13096
13097         /*
13098          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
13099          * preserved above and would only end up incorrectly in L1.
13100          */
13101         vcpu->arch.nmi_injected = false;
13102         kvm_clear_exception_queue(vcpu);
13103         kvm_clear_interrupt_queue(vcpu);
13104 }
13105
13106 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
13107                         struct vmcs12 *vmcs12)
13108 {
13109         u32 entry_failure_code;
13110
13111         nested_ept_uninit_mmu_context(vcpu);
13112
13113         /*
13114          * Only PDPTE load can fail as the value of cr3 was checked on entry and
13115          * couldn't have changed.
13116          */
13117         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
13118                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
13119
13120         if (!enable_ept)
13121                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
13122 }
13123
13124 /*
13125  * A part of what we need to when the nested L2 guest exits and we want to
13126  * run its L1 parent, is to reset L1's guest state to the host state specified
13127  * in vmcs12.
13128  * This function is to be called not only on normal nested exit, but also on
13129  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
13130  * Failures During or After Loading Guest State").
13131  * This function should be called when the active VMCS is L1's (vmcs01).
13132  */
13133 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
13134                                    struct vmcs12 *vmcs12)
13135 {
13136         struct kvm_segment seg;
13137
13138         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
13139                 vcpu->arch.efer = vmcs12->host_ia32_efer;
13140         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13141                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
13142         else
13143                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
13144         vmx_set_efer(vcpu, vcpu->arch.efer);
13145
13146         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
13147         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
13148         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
13149         /*
13150          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
13151          * actually changed, because vmx_set_cr0 refers to efer set above.
13152          *
13153          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
13154          * (KVM doesn't change it);
13155          */
13156         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
13157         vmx_set_cr0(vcpu, vmcs12->host_cr0);
13158
13159         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
13160         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
13161         vmx_set_cr4(vcpu, vmcs12->host_cr4);
13162
13163         load_vmcs12_mmu_host_state(vcpu, vmcs12);
13164
13165         /*
13166          * If vmcs01 don't use VPID, CPU flushes TLB on every
13167          * VMEntry/VMExit. Thus, no need to flush TLB.
13168          *
13169          * If vmcs12 uses VPID, TLB entries populated by L2 are
13170          * tagged with vmx->nested.vpid02 while L1 entries are tagged
13171          * with vmx->vpid. Thus, no need to flush TLB.
13172          *
13173          * Therefore, flush TLB only in case vmcs01 uses VPID and
13174          * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
13175          * are both tagged with vmx->vpid.
13176          */
13177         if (enable_vpid &&
13178             !(nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02)) {
13179                 vmx_flush_tlb(vcpu, true);
13180         }
13181
13182         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
13183         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
13184         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
13185         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
13186         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
13187         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
13188         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
13189
13190         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
13191         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
13192                 vmcs_write64(GUEST_BNDCFGS, 0);
13193
13194         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
13195                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
13196                 vcpu->arch.pat = vmcs12->host_ia32_pat;
13197         }
13198         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
13199                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
13200                         vmcs12->host_ia32_perf_global_ctrl);
13201
13202         /* Set L1 segment info according to Intel SDM
13203             27.5.2 Loading Host Segment and Descriptor-Table Registers */
13204         seg = (struct kvm_segment) {
13205                 .base = 0,
13206                 .limit = 0xFFFFFFFF,
13207                 .selector = vmcs12->host_cs_selector,
13208                 .type = 11,
13209                 .present = 1,
13210                 .s = 1,
13211                 .g = 1
13212         };
13213         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13214                 seg.l = 1;
13215         else
13216                 seg.db = 1;
13217         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
13218         seg = (struct kvm_segment) {
13219                 .base = 0,
13220                 .limit = 0xFFFFFFFF,
13221                 .type = 3,
13222                 .present = 1,
13223                 .s = 1,
13224                 .db = 1,
13225                 .g = 1
13226         };
13227         seg.selector = vmcs12->host_ds_selector;
13228         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
13229         seg.selector = vmcs12->host_es_selector;
13230         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
13231         seg.selector = vmcs12->host_ss_selector;
13232         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
13233         seg.selector = vmcs12->host_fs_selector;
13234         seg.base = vmcs12->host_fs_base;
13235         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
13236         seg.selector = vmcs12->host_gs_selector;
13237         seg.base = vmcs12->host_gs_base;
13238         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
13239         seg = (struct kvm_segment) {
13240                 .base = vmcs12->host_tr_base,
13241                 .limit = 0x67,
13242                 .selector = vmcs12->host_tr_selector,
13243                 .type = 11,
13244                 .present = 1
13245         };
13246         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
13247
13248         kvm_set_dr(vcpu, 7, 0x400);
13249         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
13250
13251         if (cpu_has_vmx_msr_bitmap())
13252                 vmx_update_msr_bitmap(vcpu);
13253
13254         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
13255                                 vmcs12->vm_exit_msr_load_count))
13256                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
13257 }
13258
13259 /*
13260  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
13261  * and modify vmcs12 to make it see what it would expect to see there if
13262  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
13263  */
13264 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
13265                               u32 exit_intr_info,
13266                               unsigned long exit_qualification)
13267 {
13268         struct vcpu_vmx *vmx = to_vmx(vcpu);
13269         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13270
13271         /* trying to cancel vmlaunch/vmresume is a bug */
13272         WARN_ON_ONCE(vmx->nested.nested_run_pending);
13273
13274         /*
13275          * The only expected VM-instruction error is "VM entry with
13276          * invalid control field(s)." Anything else indicates a
13277          * problem with L0.
13278          */
13279         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
13280                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
13281
13282         leave_guest_mode(vcpu);
13283
13284         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
13285                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
13286
13287         if (likely(!vmx->fail)) {
13288                 if (exit_reason == -1)
13289                         sync_vmcs12(vcpu, vmcs12);
13290                 else
13291                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
13292                                        exit_qualification);
13293
13294                 /*
13295                  * Must happen outside of sync_vmcs12() as it will
13296                  * also be used to capture vmcs12 cache as part of
13297                  * capturing nVMX state for snapshot (migration).
13298                  *
13299                  * Otherwise, this flush will dirty guest memory at a
13300                  * point it is already assumed by user-space to be
13301                  * immutable.
13302                  */
13303                 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
13304
13305                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
13306                                          vmcs12->vm_exit_msr_store_count))
13307                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
13308         }
13309
13310         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
13311         vm_entry_controls_reset_shadow(vmx);
13312         vm_exit_controls_reset_shadow(vmx);
13313         vmx_segment_cache_clear(vmx);
13314
13315         /* Update any VMCS fields that might have changed while L2 ran */
13316         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
13317         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
13318         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
13319
13320         if (kvm_has_tsc_control)
13321                 decache_tsc_multiplier(vmx);
13322
13323         if (vmx->nested.change_vmcs01_virtual_apic_mode) {
13324                 vmx->nested.change_vmcs01_virtual_apic_mode = false;
13325                 vmx_set_virtual_apic_mode(vcpu);
13326         } else if (!nested_cpu_has_ept(vmcs12) &&
13327                    nested_cpu_has2(vmcs12,
13328                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
13329                 vmx_flush_tlb(vcpu, true);
13330         }
13331
13332         /* This is needed for same reason as it was needed in prepare_vmcs02 */
13333         vmx->host_rsp = 0;
13334
13335         /* Unpin physical memory we referred to in vmcs02 */
13336         if (vmx->nested.apic_access_page) {
13337                 kvm_release_page_dirty(vmx->nested.apic_access_page);
13338                 vmx->nested.apic_access_page = NULL;
13339         }
13340         if (vmx->nested.virtual_apic_page) {
13341                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
13342                 vmx->nested.virtual_apic_page = NULL;
13343         }
13344         if (vmx->nested.pi_desc_page) {
13345                 kunmap(vmx->nested.pi_desc_page);
13346                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
13347                 vmx->nested.pi_desc_page = NULL;
13348                 vmx->nested.pi_desc = NULL;
13349         }
13350
13351         /*
13352          * We are now running in L2, mmu_notifier will force to reload the
13353          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
13354          */
13355         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
13356
13357         if (enable_shadow_vmcs && exit_reason != -1)
13358                 vmx->nested.sync_shadow_vmcs = true;
13359
13360         /* in case we halted in L2 */
13361         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13362
13363         if (likely(!vmx->fail)) {
13364                 /*
13365                  * TODO: SDM says that with acknowledge interrupt on
13366                  * exit, bit 31 of the VM-exit interrupt information
13367                  * (valid interrupt) is always set to 1 on
13368                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
13369                  * need kvm_cpu_has_interrupt().  See the commit
13370                  * message for details.
13371                  */
13372                 if (nested_exit_intr_ack_set(vcpu) &&
13373                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
13374                     kvm_cpu_has_interrupt(vcpu)) {
13375                         int irq = kvm_cpu_get_interrupt(vcpu);
13376                         WARN_ON(irq < 0);
13377                         vmcs12->vm_exit_intr_info = irq |
13378                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
13379                 }
13380
13381                 if (exit_reason != -1)
13382                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
13383                                                        vmcs12->exit_qualification,
13384                                                        vmcs12->idt_vectoring_info_field,
13385                                                        vmcs12->vm_exit_intr_info,
13386                                                        vmcs12->vm_exit_intr_error_code,
13387                                                        KVM_ISA_VMX);
13388
13389                 load_vmcs12_host_state(vcpu, vmcs12);
13390
13391                 return;
13392         }
13393
13394         /*
13395          * After an early L2 VM-entry failure, we're now back
13396          * in L1 which thinks it just finished a VMLAUNCH or
13397          * VMRESUME instruction, so we need to set the failure
13398          * flag and the VM-instruction error field of the VMCS
13399          * accordingly.
13400          */
13401         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
13402
13403         load_vmcs12_mmu_host_state(vcpu, vmcs12);
13404
13405         /*
13406          * The emulated instruction was already skipped in
13407          * nested_vmx_run, but the updated RIP was never
13408          * written back to the vmcs01.
13409          */
13410         skip_emulated_instruction(vcpu);
13411         vmx->fail = 0;
13412 }
13413
13414 /*
13415  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
13416  */
13417 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
13418 {
13419         if (is_guest_mode(vcpu)) {
13420                 to_vmx(vcpu)->nested.nested_run_pending = 0;
13421                 nested_vmx_vmexit(vcpu, -1, 0, 0);
13422         }
13423         free_nested(to_vmx(vcpu));
13424 }
13425
13426 /*
13427  * L1's failure to enter L2 is a subset of a normal exit, as explained in
13428  * 23.7 "VM-entry failures during or after loading guest state" (this also
13429  * lists the acceptable exit-reason and exit-qualification parameters).
13430  * It should only be called before L2 actually succeeded to run, and when
13431  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
13432  */
13433 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
13434                         struct vmcs12 *vmcs12,
13435                         u32 reason, unsigned long qualification)
13436 {
13437         load_vmcs12_host_state(vcpu, vmcs12);
13438         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
13439         vmcs12->exit_qualification = qualification;
13440         nested_vmx_succeed(vcpu);
13441         if (enable_shadow_vmcs)
13442                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
13443 }
13444
13445 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
13446                                struct x86_instruction_info *info,
13447                                enum x86_intercept_stage stage)
13448 {
13449         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13450         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
13451
13452         /*
13453          * RDPID causes #UD if disabled through secondary execution controls.
13454          * Because it is marked as EmulateOnUD, we need to intercept it here.
13455          */
13456         if (info->intercept == x86_intercept_rdtscp &&
13457             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
13458                 ctxt->exception.vector = UD_VECTOR;
13459                 ctxt->exception.error_code_valid = false;
13460                 return X86EMUL_PROPAGATE_FAULT;
13461         }
13462
13463         /* TODO: check more intercepts... */
13464         return X86EMUL_CONTINUE;
13465 }
13466
13467 #ifdef CONFIG_X86_64
13468 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
13469 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
13470                                   u64 divisor, u64 *result)
13471 {
13472         u64 low = a << shift, high = a >> (64 - shift);
13473
13474         /* To avoid the overflow on divq */
13475         if (high >= divisor)
13476                 return 1;
13477
13478         /* Low hold the result, high hold rem which is discarded */
13479         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
13480             "rm" (divisor), "0" (low), "1" (high));
13481         *result = low;
13482
13483         return 0;
13484 }
13485
13486 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
13487 {
13488         struct vcpu_vmx *vmx;
13489         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
13490
13491         if (kvm_mwait_in_guest(vcpu->kvm))
13492                 return -EOPNOTSUPP;
13493
13494         vmx = to_vmx(vcpu);
13495         tscl = rdtsc();
13496         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
13497         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
13498         lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
13499
13500         if (delta_tsc > lapic_timer_advance_cycles)
13501                 delta_tsc -= lapic_timer_advance_cycles;
13502         else
13503                 delta_tsc = 0;
13504
13505         /* Convert to host delta tsc if tsc scaling is enabled */
13506         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
13507                         u64_shl_div_u64(delta_tsc,
13508                                 kvm_tsc_scaling_ratio_frac_bits,
13509                                 vcpu->arch.tsc_scaling_ratio,
13510                                 &delta_tsc))
13511                 return -ERANGE;
13512
13513         /*
13514          * If the delta tsc can't fit in the 32 bit after the multi shift,
13515          * we can't use the preemption timer.
13516          * It's possible that it fits on later vmentries, but checking
13517          * on every vmentry is costly so we just use an hrtimer.
13518          */
13519         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
13520                 return -ERANGE;
13521
13522         vmx->hv_deadline_tsc = tscl + delta_tsc;
13523         return delta_tsc == 0;
13524 }
13525
13526 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
13527 {
13528         to_vmx(vcpu)->hv_deadline_tsc = -1;
13529 }
13530 #endif
13531
13532 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
13533 {
13534         if (!kvm_pause_in_guest(vcpu->kvm))
13535                 shrink_ple_window(vcpu);
13536 }
13537
13538 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
13539                                      struct kvm_memory_slot *slot)
13540 {
13541         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
13542         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
13543 }
13544
13545 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
13546                                        struct kvm_memory_slot *slot)
13547 {
13548         kvm_mmu_slot_set_dirty(kvm, slot);
13549 }
13550
13551 static void vmx_flush_log_dirty(struct kvm *kvm)
13552 {
13553         kvm_flush_pml_buffers(kvm);
13554 }
13555
13556 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
13557 {
13558         struct vmcs12 *vmcs12;
13559         struct vcpu_vmx *vmx = to_vmx(vcpu);
13560         gpa_t gpa;
13561         struct page *page = NULL;
13562         u64 *pml_address;
13563
13564         if (is_guest_mode(vcpu)) {
13565                 WARN_ON_ONCE(vmx->nested.pml_full);
13566
13567                 /*
13568                  * Check if PML is enabled for the nested guest.
13569                  * Whether eptp bit 6 is set is already checked
13570                  * as part of A/D emulation.
13571                  */
13572                 vmcs12 = get_vmcs12(vcpu);
13573                 if (!nested_cpu_has_pml(vmcs12))
13574                         return 0;
13575
13576                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
13577                         vmx->nested.pml_full = true;
13578                         return 1;
13579                 }
13580
13581                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
13582
13583                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
13584                 if (is_error_page(page))
13585                         return 0;
13586
13587                 pml_address = kmap(page);
13588                 pml_address[vmcs12->guest_pml_index--] = gpa;
13589                 kunmap(page);
13590                 kvm_release_page_clean(page);
13591         }
13592
13593         return 0;
13594 }
13595
13596 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
13597                                            struct kvm_memory_slot *memslot,
13598                                            gfn_t offset, unsigned long mask)
13599 {
13600         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
13601 }
13602
13603 static void __pi_post_block(struct kvm_vcpu *vcpu)
13604 {
13605         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13606         struct pi_desc old, new;
13607         unsigned int dest;
13608
13609         do {
13610                 old.control = new.control = pi_desc->control;
13611                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
13612                      "Wakeup handler not enabled while the VCPU is blocked\n");
13613
13614                 dest = cpu_physical_id(vcpu->cpu);
13615
13616                 if (x2apic_enabled())
13617                         new.ndst = dest;
13618                 else
13619                         new.ndst = (dest << 8) & 0xFF00;
13620
13621                 /* set 'NV' to 'notification vector' */
13622                 new.nv = POSTED_INTR_VECTOR;
13623         } while (cmpxchg64(&pi_desc->control, old.control,
13624                            new.control) != old.control);
13625
13626         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
13627                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13628                 list_del(&vcpu->blocked_vcpu_list);
13629                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13630                 vcpu->pre_pcpu = -1;
13631         }
13632 }
13633
13634 /*
13635  * This routine does the following things for vCPU which is going
13636  * to be blocked if VT-d PI is enabled.
13637  * - Store the vCPU to the wakeup list, so when interrupts happen
13638  *   we can find the right vCPU to wake up.
13639  * - Change the Posted-interrupt descriptor as below:
13640  *      'NDST' <-- vcpu->pre_pcpu
13641  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
13642  * - If 'ON' is set during this process, which means at least one
13643  *   interrupt is posted for this vCPU, we cannot block it, in
13644  *   this case, return 1, otherwise, return 0.
13645  *
13646  */
13647 static int pi_pre_block(struct kvm_vcpu *vcpu)
13648 {
13649         unsigned int dest;
13650         struct pi_desc old, new;
13651         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13652
13653         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
13654                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
13655                 !kvm_vcpu_apicv_active(vcpu))
13656                 return 0;
13657
13658         WARN_ON(irqs_disabled());
13659         local_irq_disable();
13660         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
13661                 vcpu->pre_pcpu = vcpu->cpu;
13662                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13663                 list_add_tail(&vcpu->blocked_vcpu_list,
13664                               &per_cpu(blocked_vcpu_on_cpu,
13665                                        vcpu->pre_pcpu));
13666                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13667         }
13668
13669         do {
13670                 old.control = new.control = pi_desc->control;
13671
13672                 WARN((pi_desc->sn == 1),
13673                      "Warning: SN field of posted-interrupts "
13674                      "is set before blocking\n");
13675
13676                 /*
13677                  * Since vCPU can be preempted during this process,
13678                  * vcpu->cpu could be different with pre_pcpu, we
13679                  * need to set pre_pcpu as the destination of wakeup
13680                  * notification event, then we can find the right vCPU
13681                  * to wakeup in wakeup handler if interrupts happen
13682                  * when the vCPU is in blocked state.
13683                  */
13684                 dest = cpu_physical_id(vcpu->pre_pcpu);
13685
13686                 if (x2apic_enabled())
13687                         new.ndst = dest;
13688                 else
13689                         new.ndst = (dest << 8) & 0xFF00;
13690
13691                 /* set 'NV' to 'wakeup vector' */
13692                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
13693         } while (cmpxchg64(&pi_desc->control, old.control,
13694                            new.control) != old.control);
13695
13696         /* We should not block the vCPU if an interrupt is posted for it.  */
13697         if (pi_test_on(pi_desc) == 1)
13698                 __pi_post_block(vcpu);
13699
13700         local_irq_enable();
13701         return (vcpu->pre_pcpu == -1);
13702 }
13703
13704 static int vmx_pre_block(struct kvm_vcpu *vcpu)
13705 {
13706         if (pi_pre_block(vcpu))
13707                 return 1;
13708
13709         if (kvm_lapic_hv_timer_in_use(vcpu))
13710                 kvm_lapic_switch_to_sw_timer(vcpu);
13711
13712         return 0;
13713 }
13714
13715 static void pi_post_block(struct kvm_vcpu *vcpu)
13716 {
13717         if (vcpu->pre_pcpu == -1)
13718                 return;
13719
13720         WARN_ON(irqs_disabled());
13721         local_irq_disable();
13722         __pi_post_block(vcpu);
13723         local_irq_enable();
13724 }
13725
13726 static void vmx_post_block(struct kvm_vcpu *vcpu)
13727 {
13728         if (kvm_x86_ops->set_hv_timer)
13729                 kvm_lapic_switch_to_hv_timer(vcpu);
13730
13731         pi_post_block(vcpu);
13732 }
13733
13734 /*
13735  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
13736  *
13737  * @kvm: kvm
13738  * @host_irq: host irq of the interrupt
13739  * @guest_irq: gsi of the interrupt
13740  * @set: set or unset PI
13741  * returns 0 on success, < 0 on failure
13742  */
13743 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
13744                               uint32_t guest_irq, bool set)
13745 {
13746         struct kvm_kernel_irq_routing_entry *e;
13747         struct kvm_irq_routing_table *irq_rt;
13748         struct kvm_lapic_irq irq;
13749         struct kvm_vcpu *vcpu;
13750         struct vcpu_data vcpu_info;
13751         int idx, ret = 0;
13752
13753         if (!kvm_arch_has_assigned_device(kvm) ||
13754                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
13755                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
13756                 return 0;
13757
13758         idx = srcu_read_lock(&kvm->irq_srcu);
13759         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
13760         if (guest_irq >= irq_rt->nr_rt_entries ||
13761             hlist_empty(&irq_rt->map[guest_irq])) {
13762                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
13763                              guest_irq, irq_rt->nr_rt_entries);
13764                 goto out;
13765         }
13766
13767         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
13768                 if (e->type != KVM_IRQ_ROUTING_MSI)
13769                         continue;
13770                 /*
13771                  * VT-d PI cannot support posting multicast/broadcast
13772                  * interrupts to a vCPU, we still use interrupt remapping
13773                  * for these kind of interrupts.
13774                  *
13775                  * For lowest-priority interrupts, we only support
13776                  * those with single CPU as the destination, e.g. user
13777                  * configures the interrupts via /proc/irq or uses
13778                  * irqbalance to make the interrupts single-CPU.
13779                  *
13780                  * We will support full lowest-priority interrupt later.
13781                  */
13782
13783                 kvm_set_msi_irq(kvm, e, &irq);
13784                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
13785                         /*
13786                          * Make sure the IRTE is in remapped mode if
13787                          * we don't handle it in posted mode.
13788                          */
13789                         ret = irq_set_vcpu_affinity(host_irq, NULL);
13790                         if (ret < 0) {
13791                                 printk(KERN_INFO
13792                                    "failed to back to remapped mode, irq: %u\n",
13793                                    host_irq);
13794                                 goto out;
13795                         }
13796
13797                         continue;
13798                 }
13799
13800                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
13801                 vcpu_info.vector = irq.vector;
13802
13803                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
13804                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
13805
13806                 if (set)
13807                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
13808                 else
13809                         ret = irq_set_vcpu_affinity(host_irq, NULL);
13810
13811                 if (ret < 0) {
13812                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
13813                                         __func__);
13814                         goto out;
13815                 }
13816         }
13817
13818         ret = 0;
13819 out:
13820         srcu_read_unlock(&kvm->irq_srcu, idx);
13821         return ret;
13822 }
13823
13824 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
13825 {
13826         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
13827                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
13828                         FEATURE_CONTROL_LMCE;
13829         else
13830                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
13831                         ~FEATURE_CONTROL_LMCE;
13832 }
13833
13834 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
13835 {
13836         /* we need a nested vmexit to enter SMM, postpone if run is pending */
13837         if (to_vmx(vcpu)->nested.nested_run_pending)
13838                 return 0;
13839         return 1;
13840 }
13841
13842 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
13843 {
13844         struct vcpu_vmx *vmx = to_vmx(vcpu);
13845
13846         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
13847         if (vmx->nested.smm.guest_mode)
13848                 nested_vmx_vmexit(vcpu, -1, 0, 0);
13849
13850         vmx->nested.smm.vmxon = vmx->nested.vmxon;
13851         vmx->nested.vmxon = false;
13852         vmx_clear_hlt(vcpu);
13853         return 0;
13854 }
13855
13856 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
13857 {
13858         struct vcpu_vmx *vmx = to_vmx(vcpu);
13859         int ret;
13860
13861         if (vmx->nested.smm.vmxon) {
13862                 vmx->nested.vmxon = true;
13863                 vmx->nested.smm.vmxon = false;
13864         }
13865
13866         if (vmx->nested.smm.guest_mode) {
13867                 vcpu->arch.hflags &= ~HF_SMM_MASK;
13868                 ret = enter_vmx_non_root_mode(vcpu, NULL);
13869                 vcpu->arch.hflags |= HF_SMM_MASK;
13870                 if (ret)
13871                         return ret;
13872
13873                 vmx->nested.smm.guest_mode = false;
13874         }
13875         return 0;
13876 }
13877
13878 static int enable_smi_window(struct kvm_vcpu *vcpu)
13879 {
13880         return 0;
13881 }
13882
13883 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
13884                                 struct kvm_nested_state __user *user_kvm_nested_state,
13885                                 u32 user_data_size)
13886 {
13887         struct vcpu_vmx *vmx;
13888         struct vmcs12 *vmcs12;
13889         struct kvm_nested_state kvm_state = {
13890                 .flags = 0,
13891                 .format = 0,
13892                 .size = sizeof(kvm_state),
13893                 .vmx.vmxon_pa = -1ull,
13894                 .vmx.vmcs_pa = -1ull,
13895         };
13896
13897         if (!vcpu)
13898                 return kvm_state.size + 2 * VMCS12_SIZE;
13899
13900         vmx = to_vmx(vcpu);
13901         vmcs12 = get_vmcs12(vcpu);
13902         if (nested_vmx_allowed(vcpu) &&
13903             (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
13904                 kvm_state.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
13905                 kvm_state.vmx.vmcs_pa = vmx->nested.current_vmptr;
13906
13907                 if (vmx->nested.current_vmptr != -1ull) {
13908                         kvm_state.size += VMCS12_SIZE;
13909
13910                         if (is_guest_mode(vcpu) &&
13911                             nested_cpu_has_shadow_vmcs(vmcs12) &&
13912                             vmcs12->vmcs_link_pointer != -1ull)
13913                                 kvm_state.size += VMCS12_SIZE;
13914                 }
13915
13916                 if (vmx->nested.smm.vmxon)
13917                         kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
13918
13919                 if (vmx->nested.smm.guest_mode)
13920                         kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
13921
13922                 if (is_guest_mode(vcpu)) {
13923                         kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
13924
13925                         if (vmx->nested.nested_run_pending)
13926                                 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
13927                 }
13928         }
13929
13930         if (user_data_size < kvm_state.size)
13931                 goto out;
13932
13933         if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
13934                 return -EFAULT;
13935
13936         if (vmx->nested.current_vmptr == -1ull)
13937                 goto out;
13938
13939         /*
13940          * When running L2, the authoritative vmcs12 state is in the
13941          * vmcs02. When running L1, the authoritative vmcs12 state is
13942          * in the shadow vmcs linked to vmcs01, unless
13943          * sync_shadow_vmcs is set, in which case, the authoritative
13944          * vmcs12 state is in the vmcs12 already.
13945          */
13946         if (is_guest_mode(vcpu))
13947                 sync_vmcs12(vcpu, vmcs12);
13948         else if (enable_shadow_vmcs && !vmx->nested.sync_shadow_vmcs)
13949                 copy_shadow_to_vmcs12(vmx);
13950
13951         if (copy_to_user(user_kvm_nested_state->data, vmcs12, sizeof(*vmcs12)))
13952                 return -EFAULT;
13953
13954         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
13955             vmcs12->vmcs_link_pointer != -1ull) {
13956                 if (copy_to_user(user_kvm_nested_state->data + VMCS12_SIZE,
13957                                  get_shadow_vmcs12(vcpu), sizeof(*vmcs12)))
13958                         return -EFAULT;
13959         }
13960
13961 out:
13962         return kvm_state.size;
13963 }
13964
13965 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
13966                                 struct kvm_nested_state __user *user_kvm_nested_state,
13967                                 struct kvm_nested_state *kvm_state)
13968 {
13969         struct vcpu_vmx *vmx = to_vmx(vcpu);
13970         struct vmcs12 *vmcs12;
13971         u32 exit_qual;
13972         int ret;
13973
13974         if (kvm_state->format != 0)
13975                 return -EINVAL;
13976
13977         if (!nested_vmx_allowed(vcpu))
13978                 return kvm_state->vmx.vmxon_pa == -1ull ? 0 : -EINVAL;
13979
13980         if (kvm_state->vmx.vmxon_pa == -1ull) {
13981                 if (kvm_state->vmx.smm.flags)
13982                         return -EINVAL;
13983
13984                 if (kvm_state->vmx.vmcs_pa != -1ull)
13985                         return -EINVAL;
13986
13987                 vmx_leave_nested(vcpu);
13988                 return 0;
13989         }
13990
13991         if (!page_address_valid(vcpu, kvm_state->vmx.vmxon_pa))
13992                 return -EINVAL;
13993
13994         if (kvm_state->size < sizeof(kvm_state) + sizeof(*vmcs12))
13995                 return -EINVAL;
13996
13997         if (kvm_state->vmx.vmcs_pa == kvm_state->vmx.vmxon_pa ||
13998             !page_address_valid(vcpu, kvm_state->vmx.vmcs_pa))
13999                 return -EINVAL;
14000
14001         if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
14002             (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
14003                 return -EINVAL;
14004
14005         if (kvm_state->vmx.smm.flags &
14006             ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
14007                 return -EINVAL;
14008
14009         /*
14010          * SMM temporarily disables VMX, so we cannot be in guest mode,
14011          * nor can VMLAUNCH/VMRESUME be pending.  Outside SMM, SMM flags
14012          * must be zero.
14013          */
14014         if (is_smm(vcpu) ? kvm_state->flags : kvm_state->vmx.smm.flags)
14015                 return -EINVAL;
14016
14017         if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
14018             !(kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
14019                 return -EINVAL;
14020
14021         vmx_leave_nested(vcpu);
14022         if (kvm_state->vmx.vmxon_pa == -1ull)
14023                 return 0;
14024
14025         vmx->nested.vmxon_ptr = kvm_state->vmx.vmxon_pa;
14026         ret = enter_vmx_operation(vcpu);
14027         if (ret)
14028                 return ret;
14029
14030         set_current_vmptr(vmx, kvm_state->vmx.vmcs_pa);
14031
14032         if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
14033                 vmx->nested.smm.vmxon = true;
14034                 vmx->nested.vmxon = false;
14035
14036                 if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
14037                         vmx->nested.smm.guest_mode = true;
14038         }
14039
14040         vmcs12 = get_vmcs12(vcpu);
14041         if (copy_from_user(vmcs12, user_kvm_nested_state->data, sizeof(*vmcs12)))
14042                 return -EFAULT;
14043
14044         if (vmcs12->hdr.revision_id != VMCS12_REVISION)
14045                 return -EINVAL;
14046
14047         if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
14048                 return 0;
14049
14050         vmx->nested.nested_run_pending =
14051                 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
14052
14053         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
14054             vmcs12->vmcs_link_pointer != -1ull) {
14055                 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
14056                 if (kvm_state->size < sizeof(kvm_state) + 2 * sizeof(*vmcs12))
14057                         return -EINVAL;
14058
14059                 if (copy_from_user(shadow_vmcs12,
14060                                    user_kvm_nested_state->data + VMCS12_SIZE,
14061                                    sizeof(*vmcs12)))
14062                         return -EFAULT;
14063
14064                 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
14065                     !shadow_vmcs12->hdr.shadow_vmcs)
14066                         return -EINVAL;
14067         }
14068
14069         if (check_vmentry_prereqs(vcpu, vmcs12) ||
14070             check_vmentry_postreqs(vcpu, vmcs12, &exit_qual))
14071                 return -EINVAL;
14072
14073         vmx->nested.dirty_vmcs12 = true;
14074         ret = enter_vmx_non_root_mode(vcpu, NULL);
14075         if (ret)
14076                 return -EINVAL;
14077
14078         return 0;
14079 }
14080
14081 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
14082         .cpu_has_kvm_support = cpu_has_kvm_support,
14083         .disabled_by_bios = vmx_disabled_by_bios,
14084         .hardware_setup = hardware_setup,
14085         .hardware_unsetup = hardware_unsetup,
14086         .check_processor_compatibility = vmx_check_processor_compat,
14087         .hardware_enable = hardware_enable,
14088         .hardware_disable = hardware_disable,
14089         .cpu_has_accelerated_tpr = report_flexpriority,
14090         .has_emulated_msr = vmx_has_emulated_msr,
14091
14092         .vm_init = vmx_vm_init,
14093         .vm_alloc = vmx_vm_alloc,
14094         .vm_free = vmx_vm_free,
14095
14096         .vcpu_create = vmx_create_vcpu,
14097         .vcpu_free = vmx_free_vcpu,
14098         .vcpu_reset = vmx_vcpu_reset,
14099
14100         .prepare_guest_switch = vmx_prepare_switch_to_guest,
14101         .vcpu_load = vmx_vcpu_load,
14102         .vcpu_put = vmx_vcpu_put,
14103
14104         .update_bp_intercept = update_exception_bitmap,
14105         .get_msr_feature = vmx_get_msr_feature,
14106         .get_msr = vmx_get_msr,
14107         .set_msr = vmx_set_msr,
14108         .get_segment_base = vmx_get_segment_base,
14109         .get_segment = vmx_get_segment,
14110         .set_segment = vmx_set_segment,
14111         .get_cpl = vmx_get_cpl,
14112         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
14113         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
14114         .decache_cr3 = vmx_decache_cr3,
14115         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
14116         .set_cr0 = vmx_set_cr0,
14117         .set_cr3 = vmx_set_cr3,
14118         .set_cr4 = vmx_set_cr4,
14119         .set_efer = vmx_set_efer,
14120         .get_idt = vmx_get_idt,
14121         .set_idt = vmx_set_idt,
14122         .get_gdt = vmx_get_gdt,
14123         .set_gdt = vmx_set_gdt,
14124         .get_dr6 = vmx_get_dr6,
14125         .set_dr6 = vmx_set_dr6,
14126         .set_dr7 = vmx_set_dr7,
14127         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
14128         .cache_reg = vmx_cache_reg,
14129         .get_rflags = vmx_get_rflags,
14130         .set_rflags = vmx_set_rflags,
14131
14132         .tlb_flush = vmx_flush_tlb,
14133         .tlb_flush_gva = vmx_flush_tlb_gva,
14134
14135         .run = vmx_vcpu_run,
14136         .handle_exit = vmx_handle_exit,
14137         .skip_emulated_instruction = skip_emulated_instruction,
14138         .set_interrupt_shadow = vmx_set_interrupt_shadow,
14139         .get_interrupt_shadow = vmx_get_interrupt_shadow,
14140         .patch_hypercall = vmx_patch_hypercall,
14141         .set_irq = vmx_inject_irq,
14142         .set_nmi = vmx_inject_nmi,
14143         .queue_exception = vmx_queue_exception,
14144         .cancel_injection = vmx_cancel_injection,
14145         .interrupt_allowed = vmx_interrupt_allowed,
14146         .nmi_allowed = vmx_nmi_allowed,
14147         .get_nmi_mask = vmx_get_nmi_mask,
14148         .set_nmi_mask = vmx_set_nmi_mask,
14149         .enable_nmi_window = enable_nmi_window,
14150         .enable_irq_window = enable_irq_window,
14151         .update_cr8_intercept = update_cr8_intercept,
14152         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
14153         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
14154         .get_enable_apicv = vmx_get_enable_apicv,
14155         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
14156         .load_eoi_exitmap = vmx_load_eoi_exitmap,
14157         .apicv_post_state_restore = vmx_apicv_post_state_restore,
14158         .hwapic_irr_update = vmx_hwapic_irr_update,
14159         .hwapic_isr_update = vmx_hwapic_isr_update,
14160         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
14161         .sync_pir_to_irr = vmx_sync_pir_to_irr,
14162         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
14163
14164         .set_tss_addr = vmx_set_tss_addr,
14165         .set_identity_map_addr = vmx_set_identity_map_addr,
14166         .get_tdp_level = get_ept_level,
14167         .get_mt_mask = vmx_get_mt_mask,
14168
14169         .get_exit_info = vmx_get_exit_info,
14170
14171         .get_lpage_level = vmx_get_lpage_level,
14172
14173         .cpuid_update = vmx_cpuid_update,
14174
14175         .rdtscp_supported = vmx_rdtscp_supported,
14176         .invpcid_supported = vmx_invpcid_supported,
14177
14178         .set_supported_cpuid = vmx_set_supported_cpuid,
14179
14180         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
14181
14182         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
14183         .write_tsc_offset = vmx_write_tsc_offset,
14184
14185         .set_tdp_cr3 = vmx_set_cr3,
14186
14187         .check_intercept = vmx_check_intercept,
14188         .handle_external_intr = vmx_handle_external_intr,
14189         .mpx_supported = vmx_mpx_supported,
14190         .xsaves_supported = vmx_xsaves_supported,
14191         .umip_emulated = vmx_umip_emulated,
14192
14193         .check_nested_events = vmx_check_nested_events,
14194         .request_immediate_exit = vmx_request_immediate_exit,
14195
14196         .sched_in = vmx_sched_in,
14197
14198         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
14199         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
14200         .flush_log_dirty = vmx_flush_log_dirty,
14201         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
14202         .write_log_dirty = vmx_write_pml_buffer,
14203
14204         .pre_block = vmx_pre_block,
14205         .post_block = vmx_post_block,
14206
14207         .pmu_ops = &intel_pmu_ops,
14208
14209         .update_pi_irte = vmx_update_pi_irte,
14210
14211 #ifdef CONFIG_X86_64
14212         .set_hv_timer = vmx_set_hv_timer,
14213         .cancel_hv_timer = vmx_cancel_hv_timer,
14214 #endif
14215
14216         .setup_mce = vmx_setup_mce,
14217
14218         .get_nested_state = vmx_get_nested_state,
14219         .set_nested_state = vmx_set_nested_state,
14220         .get_vmcs12_pages = nested_get_vmcs12_pages,
14221
14222         .smi_allowed = vmx_smi_allowed,
14223         .pre_enter_smm = vmx_pre_enter_smm,
14224         .pre_leave_smm = vmx_pre_leave_smm,
14225         .enable_smi_window = enable_smi_window,
14226 };
14227
14228 static void vmx_cleanup_l1d_flush(void)
14229 {
14230         if (vmx_l1d_flush_pages) {
14231                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
14232                 vmx_l1d_flush_pages = NULL;
14233         }
14234         /* Restore state so sysfs ignores VMX */
14235         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
14236 }
14237
14238 static void vmx_exit(void)
14239 {
14240 #ifdef CONFIG_KEXEC_CORE
14241         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
14242         synchronize_rcu();
14243 #endif
14244
14245         kvm_exit();
14246
14247 #if IS_ENABLED(CONFIG_HYPERV)
14248         if (static_branch_unlikely(&enable_evmcs)) {
14249                 int cpu;
14250                 struct hv_vp_assist_page *vp_ap;
14251                 /*
14252                  * Reset everything to support using non-enlightened VMCS
14253                  * access later (e.g. when we reload the module with
14254                  * enlightened_vmcs=0)
14255                  */
14256                 for_each_online_cpu(cpu) {
14257                         vp_ap = hv_get_vp_assist_page(cpu);
14258
14259                         if (!vp_ap)
14260                                 continue;
14261
14262                         vp_ap->current_nested_vmcs = 0;
14263                         vp_ap->enlighten_vmentry = 0;
14264                 }
14265
14266                 static_branch_disable(&enable_evmcs);
14267         }
14268 #endif
14269         vmx_cleanup_l1d_flush();
14270 }
14271 module_exit(vmx_exit);
14272
14273 static int __init vmx_init(void)
14274 {
14275         int r;
14276
14277 #if IS_ENABLED(CONFIG_HYPERV)
14278         /*
14279          * Enlightened VMCS usage should be recommended and the host needs
14280          * to support eVMCS v1 or above. We can also disable eVMCS support
14281          * with module parameter.
14282          */
14283         if (enlightened_vmcs &&
14284             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
14285             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
14286             KVM_EVMCS_VERSION) {
14287                 int cpu;
14288
14289                 /* Check that we have assist pages on all online CPUs */
14290                 for_each_online_cpu(cpu) {
14291                         if (!hv_get_vp_assist_page(cpu)) {
14292                                 enlightened_vmcs = false;
14293                                 break;
14294                         }
14295                 }
14296
14297                 if (enlightened_vmcs) {
14298                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
14299                         static_branch_enable(&enable_evmcs);
14300                 }
14301         } else {
14302                 enlightened_vmcs = false;
14303         }
14304 #endif
14305
14306         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
14307                      __alignof__(struct vcpu_vmx), THIS_MODULE);
14308         if (r)
14309                 return r;
14310
14311         /*
14312          * Must be called after kvm_init() so enable_ept is properly set
14313          * up. Hand the parameter mitigation value in which was stored in
14314          * the pre module init parser. If no parameter was given, it will
14315          * contain 'auto' which will be turned into the default 'cond'
14316          * mitigation mode.
14317          */
14318         if (boot_cpu_has(X86_BUG_L1TF)) {
14319                 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
14320                 if (r) {
14321                         vmx_exit();
14322                         return r;
14323                 }
14324         }
14325
14326 #ifdef CONFIG_KEXEC_CORE
14327         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
14328                            crash_vmclear_local_loaded_vmcss);
14329 #endif
14330         vmx_check_vmcs12_offsets();
14331
14332         return 0;
14333 }
14334 module_init(vmx_init);