arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         u32 ldr_mode;
 149         struct page *avic_logical_id_table_page;
 150         struct page *avic_physical_id_table_page;
 151         struct hlist_node hnode;
 152
 153         struct kvm_sev_info sev_info;
 154 };
 155
 156 struct kvm_vcpu;
 157
 158 struct nested_state {
 159         struct vmcb *hsave;
 160         u64 hsave_msr;
 161         u64 vm_cr_msr;
 162         u64 vmcb;
 163
 164         /* These are the merged vectors */
 165         u32 *msrpm;
 166
 167         /* gpa pointers to the real vectors */
 168         u64 vmcb_msrpm;
 169         u64 vmcb_iopm;
 170
 171         /* A VMEXIT is required but not yet emulated */
 172         bool exit_required;
 173
 174         /* cache for intercepts of the guest */
 175         u32 intercept_cr;
 176         u32 intercept_dr;
 177         u32 intercept_exceptions;
 178         u64 intercept;
 179
 180         /* Nested Paging related state */
 181         u64 nested_cr3;
 182 };
 183
 184 #define MSRPM_OFFSETS   16
 185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 186
 187 /*
 188  * Set osvw_len to higher value when updated Revision Guides
 189  * are published and we know what the new status bits are
 190  */
 191 static uint64_t osvw_len = 4, osvw_status;
 192
 193 struct vcpu_svm {
 194         struct kvm_vcpu vcpu;
 195         struct vmcb *vmcb;
 196         unsigned long vmcb_pa;
 197         struct svm_cpu_data *svm_data;
 198         uint64_t asid_generation;
 199         uint64_t sysenter_esp;
 200         uint64_t sysenter_eip;
 201         uint64_t tsc_aux;
 202
 203         u64 msr_decfg;
 204
 205         u64 next_rip;
 206
 207         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 208         struct {
 209                 u16 fs;
 210                 u16 gs;
 211                 u16 ldt;
 212                 u64 gs_base;
 213         } host;
 214
 215         u64 spec_ctrl;
 216         /*
 217          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 218          * translated into the appropriate L2_CFG bits on the host to
 219          * perform speculative control.
 220          */
 221         u64 virt_spec_ctrl;
 222
 223         u32 *msrpm;
 224
 225         ulong nmi_iret_rip;
 226
 227         struct nested_state nested;
 228
 229         bool nmi_singlestep;
 230         u64 nmi_singlestep_guest_rflags;
 231
 232         unsigned int3_injected;
 233         unsigned long int3_rip;
 234
 235         /* cached guest cpuid flags for faster access */
 236         bool nrips_enabled      : 1;
 237
 238         u32 ldr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 266
 267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 271
 272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 273 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 274
 275 #define MSR_INVALID                     0xffffffffU
 276
 277 static const struct svm_direct_access_msrs {
 278         u32 index;   /* Index of the MSR */
 279         bool always; /* True if intercept is always on */
 280 } direct_access_msrs[] = {
 281         { .index = MSR_STAR,                            .always = true  },
 282         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 283 #ifdef CONFIG_X86_64
 284         { .index = MSR_GS_BASE,                         .always = true  },
 285         { .index = MSR_FS_BASE,                         .always = true  },
 286         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 287         { .index = MSR_LSTAR,                           .always = true  },
 288         { .index = MSR_CSTAR,                           .always = true  },
 289         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 290 #endif
 291         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 292         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 293         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 294         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 295         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 296         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 297         { .index = MSR_INVALID,                         .always = false },
 298 };
 299
 300 /* enable NPT for AMD64 and X86 with PAE */
 301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 302 static bool npt_enabled = true;
 303 #else
 304 static bool npt_enabled;
 305 #endif
 306
 307 /*
 308  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 309  * pause_filter_count: On processors that support Pause filtering(indicated
 310  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 311  *      count value. On VMRUN this value is loaded into an internal counter.
 312  *      Each time a pause instruction is executed, this counter is decremented
 313  *      until it reaches zero at which time a #VMEXIT is generated if pause
 314  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 315  *      Intercept Filtering for more details.
 316  *      This also indicate if ple logic enabled.
 317  *
 318  * pause_filter_thresh: In addition, some processor families support advanced
 319  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 320  *      the amount of time a guest is allowed to execute in a pause loop.
 321  *      In this mode, a 16-bit pause filter threshold field is added in the
 322  *      VMCB. The threshold value is a cycle count that is used to reset the
 323  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 324  *      count value from VMCB into an internal counter. Then, on each pause
 325  *      instruction the hardware checks the elapsed number of cycles since
 326  *      the most recent pause instruction against the pause filter threshold.
 327  *      If the elapsed cycle count is greater than the pause filter threshold,
 328  *      then the internal pause count is reloaded from the VMCB and execution
 329  *      continues. If the elapsed cycle count is less than the pause filter
 330  *      threshold, then the internal pause count is decremented. If the count
 331  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 332  *      triggered. If advanced pause filtering is supported and pause filter
 333  *      threshold field is set to zero, the filter will operate in the simpler,
 334  *      count only mode.
 335  */
 336
 337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 338 module_param(pause_filter_thresh, ushort, 0444);
 339
 340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 341 module_param(pause_filter_count, ushort, 0444);
 342
 343 /* Default doubles per-vcpu window every exit. */
 344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 345 module_param(pause_filter_count_grow, ushort, 0444);
 346
 347 /* Default resets per-vcpu window every exit to pause_filter_count. */
 348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 349 module_param(pause_filter_count_shrink, ushort, 0444);
 350
 351 /* Default is to compute the maximum so we can never overflow. */
 352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 353 module_param(pause_filter_count_max, ushort, 0444);
 354
 355 /* allow nested paging (virtualized MMU) for all guests */
 356 static int npt = true;
 357 module_param(npt, int, S_IRUGO);
 358
 359 /* allow nested virtualization in KVM/SVM */
 360 static int nested = true;
 361 module_param(nested, int, S_IRUGO);
 362
 363 /* enable / disable AVIC */
 364 static int avic;
 365 #ifdef CONFIG_X86_LOCAL_APIC
 366 module_param(avic, int, S_IRUGO);
 367 #endif
 368
 369 /* enable/disable Virtual VMLOAD VMSAVE */
 370 static int vls = true;
 371 module_param(vls, int, 0444);
 372
 373 /* enable/disable Virtual GIF */
 374 static int vgif = true;
 375 module_param(vgif, int, 0444);
 376
 377 /* enable/disable SEV support */
 378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 379 module_param(sev, int, 0444);
 380
 381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 382
 383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 385 static void svm_complete_interrupts(struct vcpu_svm *svm);
 386
 387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 388 static int nested_svm_intercept(struct vcpu_svm *svm);
 389 static int nested_svm_vmexit(struct vcpu_svm *svm);
 390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 391                                       bool has_error_code, u32 error_code);
 392
 393 enum {
 394         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 395                             pause filter count */
 396         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 397         VMCB_ASID,       /* ASID */
 398         VMCB_INTR,       /* int_ctl, int_vector */
 399         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 400         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 401         VMCB_DR,         /* DR6, DR7 */
 402         VMCB_DT,         /* GDT, IDT */
 403         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 404         VMCB_CR2,        /* CR2 only */
 405         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 406         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 407                           * AVIC PHYSICAL_TABLE pointer,
 408                           * AVIC LOGICAL_TABLE pointer
 409                           */
 410         VMCB_DIRTY_MAX,
 411 };
 412
 413 /* TPR and CR2 are always written before VMRUN */
 414 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 415
 416 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 417
 418 static unsigned int max_sev_asid;
 419 static unsigned int min_sev_asid;
 420 static unsigned long *sev_asid_bitmap;
 421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 422
 423 struct enc_region {
 424         struct list_head list;
 425         unsigned long npages;
 426         struct page **pages;
 427         unsigned long uaddr;
 428         unsigned long size;
 429 };
 430
 431
 432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 433 {
 434         return container_of(kvm, struct kvm_svm, kvm);
 435 }
 436
 437 static inline bool svm_sev_enabled(void)
 438 {
 439         return max_sev_asid;
 440 }
 441
 442 static inline bool sev_guest(struct kvm *kvm)
 443 {
 444         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 445
 446         return sev->active;
 447 }
 448
 449 static inline int sev_get_asid(struct kvm *kvm)
 450 {
 451         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 452
 453         return sev->asid;
 454 }
 455
 456 static inline void mark_all_dirty(struct vmcb *vmcb)
 457 {
 458         vmcb->control.clean = 0;
 459 }
 460
 461 static inline void mark_all_clean(struct vmcb *vmcb)
 462 {
 463         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 464                                & ~VMCB_ALWAYS_DIRTY_MASK;
 465 }
 466
 467 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 468 {
 469         vmcb->control.clean &= ~(1 << bit);
 470 }
 471
 472 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 473 {
 474         return container_of(vcpu, struct vcpu_svm, vcpu);
 475 }
 476
 477 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 478 {
 479         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 480         mark_dirty(svm->vmcb, VMCB_AVIC);
 481 }
 482
 483 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 484 {
 485         struct vcpu_svm *svm = to_svm(vcpu);
 486         u64 *entry = svm->avic_physical_id_cache;
 487
 488         if (!entry)
 489                 return false;
 490
 491         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 492 }
 493
 494 static void recalc_intercepts(struct vcpu_svm *svm)
 495 {
 496         struct vmcb_control_area *c, *h;
 497         struct nested_state *g;
 498
 499         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 500
 501         if (!is_guest_mode(&svm->vcpu))
 502                 return;
 503
 504         c = &svm->vmcb->control;
 505         h = &svm->nested.hsave->control;
 506         g = &svm->nested;
 507
 508         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 509         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 510         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 511         c->intercept = h->intercept | g->intercept;
 512 }
 513
 514 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 515 {
 516         if (is_guest_mode(&svm->vcpu))
 517                 return svm->nested.hsave;
 518         else
 519                 return svm->vmcb;
 520 }
 521
 522 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 523 {
 524         struct vmcb *vmcb = get_host_vmcb(svm);
 525
 526         vmcb->control.intercept_cr |= (1U << bit);
 527
 528         recalc_intercepts(svm);
 529 }
 530
 531 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 532 {
 533         struct vmcb *vmcb = get_host_vmcb(svm);
 534
 535         vmcb->control.intercept_cr &= ~(1U << bit);
 536
 537         recalc_intercepts(svm);
 538 }
 539
 540 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 541 {
 542         struct vmcb *vmcb = get_host_vmcb(svm);
 543
 544         return vmcb->control.intercept_cr & (1U << bit);
 545 }
 546
 547 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 548 {
 549         struct vmcb *vmcb = get_host_vmcb(svm);
 550
 551         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 552                 | (1 << INTERCEPT_DR1_READ)
 553                 | (1 << INTERCEPT_DR2_READ)
 554                 | (1 << INTERCEPT_DR3_READ)
 555                 | (1 << INTERCEPT_DR4_READ)
 556                 | (1 << INTERCEPT_DR5_READ)
 557                 | (1 << INTERCEPT_DR6_READ)
 558                 | (1 << INTERCEPT_DR7_READ)
 559                 | (1 << INTERCEPT_DR0_WRITE)
 560                 | (1 << INTERCEPT_DR1_WRITE)
 561                 | (1 << INTERCEPT_DR2_WRITE)
 562                 | (1 << INTERCEPT_DR3_WRITE)
 563                 | (1 << INTERCEPT_DR4_WRITE)
 564                 | (1 << INTERCEPT_DR5_WRITE)
 565                 | (1 << INTERCEPT_DR6_WRITE)
 566                 | (1 << INTERCEPT_DR7_WRITE);
 567
 568         recalc_intercepts(svm);
 569 }
 570
 571 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 572 {
 573         struct vmcb *vmcb = get_host_vmcb(svm);
 574
 575         vmcb->control.intercept_dr = 0;
 576
 577         recalc_intercepts(svm);
 578 }
 579
 580 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 581 {
 582         struct vmcb *vmcb = get_host_vmcb(svm);
 583
 584         vmcb->control.intercept_exceptions |= (1U << bit);
 585
 586         recalc_intercepts(svm);
 587 }
 588
 589 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 590 {
 591         struct vmcb *vmcb = get_host_vmcb(svm);
 592
 593         vmcb->control.intercept_exceptions &= ~(1U << bit);
 594
 595         recalc_intercepts(svm);
 596 }
 597
 598 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 599 {
 600         struct vmcb *vmcb = get_host_vmcb(svm);
 601
 602         vmcb->control.intercept |= (1ULL << bit);
 603
 604         recalc_intercepts(svm);
 605 }
 606
 607 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 608 {
 609         struct vmcb *vmcb = get_host_vmcb(svm);
 610
 611         vmcb->control.intercept &= ~(1ULL << bit);
 612
 613         recalc_intercepts(svm);
 614 }
 615
 616 static inline bool vgif_enabled(struct vcpu_svm *svm)
 617 {
 618         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 619 }
 620
 621 static inline void enable_gif(struct vcpu_svm *svm)
 622 {
 623         if (vgif_enabled(svm))
 624                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 625         else
 626                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 627 }
 628
 629 static inline void disable_gif(struct vcpu_svm *svm)
 630 {
 631         if (vgif_enabled(svm))
 632                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 633         else
 634                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 635 }
 636
 637 static inline bool gif_set(struct vcpu_svm *svm)
 638 {
 639         if (vgif_enabled(svm))
 640                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 641         else
 642                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 643 }
 644
 645 static unsigned long iopm_base;
 646
 647 struct kvm_ldttss_desc {
 648         u16 limit0;
 649         u16 base0;
 650         unsigned base1:8, type:5, dpl:2, p:1;
 651         unsigned limit1:4, zero0:3, g:1, base2:8;
 652         u32 base3;
 653         u32 zero1;
 654 } __attribute__((packed));
 655
 656 struct svm_cpu_data {
 657         int cpu;
 658
 659         u64 asid_generation;
 660         u32 max_asid;
 661         u32 next_asid;
 662         u32 min_asid;
 663         struct kvm_ldttss_desc *tss_desc;
 664
 665         struct page *save_area;
 666         struct vmcb *current_vmcb;
 667
 668         /* index = sev_asid, value = vmcb pointer */
 669         struct vmcb **sev_vmcbs;
 670 };
 671
 672 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 673
 674 struct svm_init_data {
 675         int cpu;
 676         int r;
 677 };
 678
 679 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 680
 681 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 682 #define MSRS_RANGE_SIZE 2048
 683 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 684
 685 static u32 svm_msrpm_offset(u32 msr)
 686 {
 687         u32 offset;
 688         int i;
 689
 690         for (i = 0; i < NUM_MSR_MAPS; i++) {
 691                 if (msr < msrpm_ranges[i] ||
 692                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 693                         continue;
 694
 695                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 696                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 697
 698                 /* Now we have the u8 offset - but need the u32 offset */
 699                 return offset / 4;
 700         }
 701
 702         /* MSR not in any range */
 703         return MSR_INVALID;
 704 }
 705
 706 #define MAX_INST_SIZE 15
 707
 708 static inline void clgi(void)
 709 {
 710         asm volatile (__ex(SVM_CLGI));
 711 }
 712
 713 static inline void stgi(void)
 714 {
 715         asm volatile (__ex(SVM_STGI));
 716 }
 717
 718 static inline void invlpga(unsigned long addr, u32 asid)
 719 {
 720         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 721 }
 722
 723 static int get_npt_level(struct kvm_vcpu *vcpu)
 724 {
 725 #ifdef CONFIG_X86_64
 726         return PT64_ROOT_4LEVEL;
 727 #else
 728         return PT32E_ROOT_LEVEL;
 729 #endif
 730 }
 731
 732 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 733 {
 734         vcpu->arch.efer = efer;
 735         if (!npt_enabled && !(efer & EFER_LMA))
 736                 efer &= ~EFER_LME;
 737
 738         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 739         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 740 }
 741
 742 static int is_external_interrupt(u32 info)
 743 {
 744         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 745         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 746 }
 747
 748 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 749 {
 750         struct vcpu_svm *svm = to_svm(vcpu);
 751         u32 ret = 0;
 752
 753         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 754                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 755         return ret;
 756 }
 757
 758 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 759 {
 760         struct vcpu_svm *svm = to_svm(vcpu);
 761
 762         if (mask == 0)
 763                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 764         else
 765                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 766
 767 }
 768
 769 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 770 {
 771         struct vcpu_svm *svm = to_svm(vcpu);
 772
 773         if (svm->vmcb->control.next_rip != 0) {
 774                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 775                 svm->next_rip = svm->vmcb->control.next_rip;
 776         }
 777
 778         if (!svm->next_rip) {
 779                 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 780                                 EMULATE_DONE)
 781                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 782                 return;
 783         }
 784         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 785                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 786                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 787
 788         kvm_rip_write(vcpu, svm->next_rip);
 789         svm_set_interrupt_shadow(vcpu, 0);
 790 }
 791
 792 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 793 {
 794         struct vcpu_svm *svm = to_svm(vcpu);
 795         unsigned nr = vcpu->arch.exception.nr;
 796         bool has_error_code = vcpu->arch.exception.has_error_code;
 797         bool reinject = vcpu->arch.exception.injected;
 798         u32 error_code = vcpu->arch.exception.error_code;
 799
 800         /*
 801          * If we are within a nested VM we'd better #VMEXIT and let the guest
 802          * handle the exception
 803          */
 804         if (!reinject &&
 805             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 806                 return;
 807
 808         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 809                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 810
 811                 /*
 812                  * For guest debugging where we have to reinject #BP if some
 813                  * INT3 is guest-owned:
 814                  * Emulate nRIP by moving RIP forward. Will fail if injection
 815                  * raises a fault that is not intercepted. Still better than
 816                  * failing in all cases.
 817                  */
 818                 skip_emulated_instruction(&svm->vcpu);
 819                 rip = kvm_rip_read(&svm->vcpu);
 820                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 821                 svm->int3_injected = rip - old_rip;
 822         }
 823
 824         svm->vmcb->control.event_inj = nr
 825                 | SVM_EVTINJ_VALID
 826                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 827                 | SVM_EVTINJ_TYPE_EXEPT;
 828         svm->vmcb->control.event_inj_err = error_code;
 829 }
 830
 831 static void svm_init_erratum_383(void)
 832 {
 833         u32 low, high;
 834         int err;
 835         u64 val;
 836
 837         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 838                 return;
 839
 840         /* Use _safe variants to not break nested virtualization */
 841         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 842         if (err)
 843                 return;
 844
 845         val |= (1ULL << 47);
 846
 847         low  = lower_32_bits(val);
 848         high = upper_32_bits(val);
 849
 850         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 851
 852         erratum_383_found = true;
 853 }
 854
 855 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 856 {
 857         /*
 858          * Guests should see errata 400 and 415 as fixed (assuming that
 859          * HLT and IO instructions are intercepted).
 860          */
 861         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 862         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 863
 864         /*
 865          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 866          * all osvw.status bits inside that length, including bit 0 (which is
 867          * reserved for erratum 298), are valid. However, if host processor's
 868          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 869          * be conservative here and therefore we tell the guest that erratum 298
 870          * is present (because we really don't know).
 871          */
 872         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 873                 vcpu->arch.osvw.status |= 1;
 874 }
 875
 876 static int has_svm(void)
 877 {
 878         const char *msg;
 879
 880         if (!cpu_has_svm(&msg)) {
 881                 printk(KERN_INFO "has_svm: %s\n", msg);
 882                 return 0;
 883         }
 884
 885         return 1;
 886 }
 887
 888 static void svm_hardware_disable(void)
 889 {
 890         /* Make sure we clean up behind us */
 891         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 892                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 893
 894         cpu_svm_disable();
 895
 896         amd_pmu_disable_virt();
 897 }
 898
 899 static int svm_hardware_enable(void)
 900 {
 901
 902         struct svm_cpu_data *sd;
 903         uint64_t efer;
 904         struct desc_struct *gdt;
 905         int me = raw_smp_processor_id();
 906
 907         rdmsrl(MSR_EFER, efer);
 908         if (efer & EFER_SVME)
 909                 return -EBUSY;
 910
 911         if (!has_svm()) {
 912                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 913                 return -EINVAL;
 914         }
 915         sd = per_cpu(svm_data, me);
 916         if (!sd) {
 917                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 918                 return -EINVAL;
 919         }
 920
 921         sd->asid_generation = 1;
 922         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 923         sd->next_asid = sd->max_asid + 1;
 924         sd->min_asid = max_sev_asid + 1;
 925
 926         gdt = get_current_gdt_rw();
 927         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 928
 929         wrmsrl(MSR_EFER, efer | EFER_SVME);
 930
 931         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 932
 933         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 934                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 935                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 936         }
 937
 938
 939         /*
 940          * Get OSVW bits.
 941          *
 942          * Note that it is possible to have a system with mixed processor
 943          * revisions and therefore different OSVW bits. If bits are not the same
 944          * on different processors then choose the worst case (i.e. if erratum
 945          * is present on one processor and not on another then assume that the
 946          * erratum is present everywhere).
 947          */
 948         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 949                 uint64_t len, status = 0;
 950                 int err;
 951
 952                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 953                 if (!err)
 954                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 955                                                       &err);
 956
 957                 if (err)
 958                         osvw_status = osvw_len = 0;
 959                 else {
 960                         if (len < osvw_len)
 961                                 osvw_len = len;
 962                         osvw_status |= status;
 963                         osvw_status &= (1ULL << osvw_len) - 1;
 964                 }
 965         } else
 966                 osvw_status = osvw_len = 0;
 967
 968         svm_init_erratum_383();
 969
 970         amd_pmu_enable_virt();
 971
 972         return 0;
 973 }
 974
 975 static void svm_cpu_uninit(int cpu)
 976 {
 977         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 978
 979         if (!sd)
 980                 return;
 981
 982         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 983         kfree(sd->sev_vmcbs);
 984         __free_page(sd->save_area);
 985         kfree(sd);
 986 }
 987
 988 static int svm_cpu_init(int cpu)
 989 {
 990         struct svm_cpu_data *sd;
 991         int r;
 992
 993         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 994         if (!sd)
 995                 return -ENOMEM;
 996         sd->cpu = cpu;
 997         r = -ENOMEM;
 998         sd->save_area = alloc_page(GFP_KERNEL);
 999         if (!sd->save_area)
1000                 goto err_1;
1001
1002         if (svm_sev_enabled()) {
1003                 r = -ENOMEM;
1004                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1005                                               sizeof(void *),
1006                                               GFP_KERNEL);
1007                 if (!sd->sev_vmcbs)
1008                         goto err_1;
1009         }
1010
1011         per_cpu(svm_data, cpu) = sd;
1012
1013         return 0;
1014
1015 err_1:
1016         kfree(sd);
1017         return r;
1018
1019 }
1020
1021 static bool valid_msr_intercept(u32 index)
1022 {
1023         int i;
1024
1025         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1026                 if (direct_access_msrs[i].index == index)
1027                         return true;
1028
1029         return false;
1030 }
1031
1032 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1033 {
1034         u8 bit_write;
1035         unsigned long tmp;
1036         u32 offset;
1037         u32 *msrpm;
1038
1039         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1040                                       to_svm(vcpu)->msrpm;
1041
1042         offset    = svm_msrpm_offset(msr);
1043         bit_write = 2 * (msr & 0x0f) + 1;
1044         tmp       = msrpm[offset];
1045
1046         BUG_ON(offset == MSR_INVALID);
1047
1048         return !!test_bit(bit_write,  &tmp);
1049 }
1050
1051 static void set_msr_interception(u32 *msrpm, unsigned msr,
1052                                  int read, int write)
1053 {
1054         u8 bit_read, bit_write;
1055         unsigned long tmp;
1056         u32 offset;
1057
1058         /*
1059          * If this warning triggers extend the direct_access_msrs list at the
1060          * beginning of the file
1061          */
1062         WARN_ON(!valid_msr_intercept(msr));
1063
1064         offset    = svm_msrpm_offset(msr);
1065         bit_read  = 2 * (msr & 0x0f);
1066         bit_write = 2 * (msr & 0x0f) + 1;
1067         tmp       = msrpm[offset];
1068
1069         BUG_ON(offset == MSR_INVALID);
1070
1071         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1072         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1073
1074         msrpm[offset] = tmp;
1075 }
1076
1077 static void svm_vcpu_init_msrpm(u32 *msrpm)
1078 {
1079         int i;
1080
1081         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1082
1083         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1084                 if (!direct_access_msrs[i].always)
1085                         continue;
1086
1087                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1088         }
1089 }
1090
1091 static void add_msr_offset(u32 offset)
1092 {
1093         int i;
1094
1095         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1096
1097                 /* Offset already in list? */
1098                 if (msrpm_offsets[i] == offset)
1099                         return;
1100
1101                 /* Slot used by another offset? */
1102                 if (msrpm_offsets[i] != MSR_INVALID)
1103                         continue;
1104
1105                 /* Add offset to list */
1106                 msrpm_offsets[i] = offset;
1107
1108                 return;
1109         }
1110
1111         /*
1112          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1113          * increase MSRPM_OFFSETS in this case.
1114          */
1115         BUG();
1116 }
1117
1118 static void init_msrpm_offsets(void)
1119 {
1120         int i;
1121
1122         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1123
1124         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1125                 u32 offset;
1126
1127                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1128                 BUG_ON(offset == MSR_INVALID);
1129
1130                 add_msr_offset(offset);
1131         }
1132 }
1133
1134 static void svm_enable_lbrv(struct vcpu_svm *svm)
1135 {
1136         u32 *msrpm = svm->msrpm;
1137
1138         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1139         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1140         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1141         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1142         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1143 }
1144
1145 static void svm_disable_lbrv(struct vcpu_svm *svm)
1146 {
1147         u32 *msrpm = svm->msrpm;
1148
1149         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1150         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1151         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1152         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1153         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1154 }
1155
1156 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1157 {
1158         svm->nmi_singlestep = false;
1159
1160         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1161                 /* Clear our flags if they were not set by the guest */
1162                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1163                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1164                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1165                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1166         }
1167 }
1168
1169 /* Note:
1170  * This hash table is used to map VM_ID to a struct kvm_svm,
1171  * when handling AMD IOMMU GALOG notification to schedule in
1172  * a particular vCPU.
1173  */
1174 #define SVM_VM_DATA_HASH_BITS   8
1175 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1176 static u32 next_vm_id = 0;
1177 static bool next_vm_id_wrapped = 0;
1178 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1179
1180 /* Note:
1181  * This function is called from IOMMU driver to notify
1182  * SVM to schedule in a particular vCPU of a particular VM.
1183  */
1184 static int avic_ga_log_notifier(u32 ga_tag)
1185 {
1186         unsigned long flags;
1187         struct kvm_svm *kvm_svm;
1188         struct kvm_vcpu *vcpu = NULL;
1189         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1190         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1191
1192         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1193
1194         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1195         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1196                 if (kvm_svm->avic_vm_id != vm_id)
1197                         continue;
1198                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1199                 break;
1200         }
1201         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1202
1203         /* Note:
1204          * At this point, the IOMMU should have already set the pending
1205          * bit in the vAPIC backing page. So, we just need to schedule
1206          * in the vcpu.
1207          */
1208         if (vcpu)
1209                 kvm_vcpu_wake_up(vcpu);
1210
1211         return 0;
1212 }
1213
1214 static __init int sev_hardware_setup(void)
1215 {
1216         struct sev_user_data_status *status;
1217         int rc;
1218
1219         /* Maximum number of encrypted guests supported simultaneously */
1220         max_sev_asid = cpuid_ecx(0x8000001F);
1221
1222         if (!max_sev_asid)
1223                 return 1;
1224
1225         /* Minimum ASID value that should be used for SEV guest */
1226         min_sev_asid = cpuid_edx(0x8000001F);
1227
1228         /* Initialize SEV ASID bitmap */
1229         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1230         if (!sev_asid_bitmap)
1231                 return 1;
1232
1233         status = kmalloc(sizeof(*status), GFP_KERNEL);
1234         if (!status)
1235                 return 1;
1236
1237         /*
1238          * Check SEV platform status.
1239          *
1240          * PLATFORM_STATUS can be called in any state, if we failed to query
1241          * the PLATFORM status then either PSP firmware does not support SEV
1242          * feature or SEV firmware is dead.
1243          */
1244         rc = sev_platform_status(status, NULL);
1245         if (rc)
1246                 goto err;
1247
1248         pr_info("SEV supported\n");
1249
1250 err:
1251         kfree(status);
1252         return rc;
1253 }
1254
1255 static void grow_ple_window(struct kvm_vcpu *vcpu)
1256 {
1257         struct vcpu_svm *svm = to_svm(vcpu);
1258         struct vmcb_control_area *control = &svm->vmcb->control;
1259         int old = control->pause_filter_count;
1260
1261         control->pause_filter_count = __grow_ple_window(old,
1262                                                         pause_filter_count,
1263                                                         pause_filter_count_grow,
1264                                                         pause_filter_count_max);
1265
1266         if (control->pause_filter_count != old)
1267                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1268
1269         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1270                                   control->pause_filter_count, old);
1271 }
1272
1273 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1274 {
1275         struct vcpu_svm *svm = to_svm(vcpu);
1276         struct vmcb_control_area *control = &svm->vmcb->control;
1277         int old = control->pause_filter_count;
1278
1279         control->pause_filter_count =
1280                                 __shrink_ple_window(old,
1281                                                     pause_filter_count,
1282                                                     pause_filter_count_shrink,
1283                                                     pause_filter_count);
1284         if (control->pause_filter_count != old)
1285                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1286
1287         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1288                                     control->pause_filter_count, old);
1289 }
1290
1291 static __init int svm_hardware_setup(void)
1292 {
1293         int cpu;
1294         struct page *iopm_pages;
1295         void *iopm_va;
1296         int r;
1297
1298         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1299
1300         if (!iopm_pages)
1301                 return -ENOMEM;
1302
1303         iopm_va = page_address(iopm_pages);
1304         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1305         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1306
1307         init_msrpm_offsets();
1308
1309         if (boot_cpu_has(X86_FEATURE_NX))
1310                 kvm_enable_efer_bits(EFER_NX);
1311
1312         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1313                 kvm_enable_efer_bits(EFER_FFXSR);
1314
1315         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1316                 kvm_has_tsc_control = true;
1317                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1318                 kvm_tsc_scaling_ratio_frac_bits = 32;
1319         }
1320
1321         /* Check for pause filtering support */
1322         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1323                 pause_filter_count = 0;
1324                 pause_filter_thresh = 0;
1325         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1326                 pause_filter_thresh = 0;
1327         }
1328
1329         if (nested) {
1330                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1331                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1332         }
1333
1334         if (sev) {
1335                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1336                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1337                         r = sev_hardware_setup();
1338                         if (r)
1339                                 sev = false;
1340                 } else {
1341                         sev = false;
1342                 }
1343         }
1344
1345         for_each_possible_cpu(cpu) {
1346                 r = svm_cpu_init(cpu);
1347                 if (r)
1348                         goto err;
1349         }
1350
1351         if (!boot_cpu_has(X86_FEATURE_NPT))
1352                 npt_enabled = false;
1353
1354         if (npt_enabled && !npt) {
1355                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1356                 npt_enabled = false;
1357         }
1358
1359         if (npt_enabled) {
1360                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1361                 kvm_enable_tdp();
1362         } else
1363                 kvm_disable_tdp();
1364
1365         if (avic) {
1366                 if (!npt_enabled ||
1367                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1368                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1369                         avic = false;
1370                 } else {
1371                         pr_info("AVIC enabled\n");
1372
1373                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1374                 }
1375         }
1376
1377         if (vls) {
1378                 if (!npt_enabled ||
1379                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1380                     !IS_ENABLED(CONFIG_X86_64)) {
1381                         vls = false;
1382                 } else {
1383                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1384                 }
1385         }
1386
1387         if (vgif) {
1388                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1389                         vgif = false;
1390                 else
1391                         pr_info("Virtual GIF supported\n");
1392         }
1393
1394         return 0;
1395
1396 err:
1397         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1398         iopm_base = 0;
1399         return r;
1400 }
1401
1402 static __exit void svm_hardware_unsetup(void)
1403 {
1404         int cpu;
1405
1406         if (svm_sev_enabled())
1407                 bitmap_free(sev_asid_bitmap);
1408
1409         for_each_possible_cpu(cpu)
1410                 svm_cpu_uninit(cpu);
1411
1412         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1413         iopm_base = 0;
1414 }
1415
1416 static void init_seg(struct vmcb_seg *seg)
1417 {
1418         seg->selector = 0;
1419         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1420                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1421         seg->limit = 0xffff;
1422         seg->base = 0;
1423 }
1424
1425 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1426 {
1427         seg->selector = 0;
1428         seg->attrib = SVM_SELECTOR_P_MASK | type;
1429         seg->limit = 0xffff;
1430         seg->base = 0;
1431 }
1432
1433 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1434 {
1435         struct vcpu_svm *svm = to_svm(vcpu);
1436
1437         if (is_guest_mode(vcpu))
1438                 return svm->nested.hsave->control.tsc_offset;
1439
1440         return vcpu->arch.tsc_offset;
1441 }
1442
1443 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1444 {
1445         struct vcpu_svm *svm = to_svm(vcpu);
1446         u64 g_tsc_offset = 0;
1447
1448         if (is_guest_mode(vcpu)) {
1449                 /* Write L1's TSC offset.  */
1450                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1451                                svm->nested.hsave->control.tsc_offset;
1452                 svm->nested.hsave->control.tsc_offset = offset;
1453         } else
1454                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1455                                            svm->vmcb->control.tsc_offset,
1456                                            offset);
1457
1458         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1459
1460         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1461 }
1462
1463 static void avic_init_vmcb(struct vcpu_svm *svm)
1464 {
1465         struct vmcb *vmcb = svm->vmcb;
1466         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1467         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1468         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1469         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1470
1471         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1472         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1473         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1474         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1475         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1476 }
1477
1478 static void init_vmcb(struct vcpu_svm *svm)
1479 {
1480         struct vmcb_control_area *control = &svm->vmcb->control;
1481         struct vmcb_save_area *save = &svm->vmcb->save;
1482
1483         svm->vcpu.arch.hflags = 0;
1484
1485         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1486         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1487         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1488         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1489         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1490         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1491         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1492                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1493
1494         set_dr_intercepts(svm);
1495
1496         set_exception_intercept(svm, PF_VECTOR);
1497         set_exception_intercept(svm, UD_VECTOR);
1498         set_exception_intercept(svm, MC_VECTOR);
1499         set_exception_intercept(svm, AC_VECTOR);
1500         set_exception_intercept(svm, DB_VECTOR);
1501         /*
1502          * Guest access to VMware backdoor ports could legitimately
1503          * trigger #GP because of TSS I/O permission bitmap.
1504          * We intercept those #GP and allow access to them anyway
1505          * as VMware does.
1506          */
1507         if (enable_vmware_backdoor)
1508                 set_exception_intercept(svm, GP_VECTOR);
1509
1510         set_intercept(svm, INTERCEPT_INTR);
1511         set_intercept(svm, INTERCEPT_NMI);
1512         set_intercept(svm, INTERCEPT_SMI);
1513         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1514         set_intercept(svm, INTERCEPT_RDPMC);
1515         set_intercept(svm, INTERCEPT_CPUID);
1516         set_intercept(svm, INTERCEPT_INVD);
1517         set_intercept(svm, INTERCEPT_INVLPG);
1518         set_intercept(svm, INTERCEPT_INVLPGA);
1519         set_intercept(svm, INTERCEPT_IOIO_PROT);
1520         set_intercept(svm, INTERCEPT_MSR_PROT);
1521         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1522         set_intercept(svm, INTERCEPT_SHUTDOWN);
1523         set_intercept(svm, INTERCEPT_VMRUN);
1524         set_intercept(svm, INTERCEPT_VMMCALL);
1525         set_intercept(svm, INTERCEPT_VMLOAD);
1526         set_intercept(svm, INTERCEPT_VMSAVE);
1527         set_intercept(svm, INTERCEPT_STGI);
1528         set_intercept(svm, INTERCEPT_CLGI);
1529         set_intercept(svm, INTERCEPT_SKINIT);
1530         set_intercept(svm, INTERCEPT_WBINVD);
1531         set_intercept(svm, INTERCEPT_XSETBV);
1532         set_intercept(svm, INTERCEPT_RSM);
1533
1534         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1535                 set_intercept(svm, INTERCEPT_MONITOR);
1536                 set_intercept(svm, INTERCEPT_MWAIT);
1537         }
1538
1539         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1540                 set_intercept(svm, INTERCEPT_HLT);
1541
1542         control->iopm_base_pa = __sme_set(iopm_base);
1543         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1544         control->int_ctl = V_INTR_MASKING_MASK;
1545
1546         init_seg(&save->es);
1547         init_seg(&save->ss);
1548         init_seg(&save->ds);
1549         init_seg(&save->fs);
1550         init_seg(&save->gs);
1551
1552         save->cs.selector = 0xf000;
1553         save->cs.base = 0xffff0000;
1554         /* Executable/Readable Code Segment */
1555         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1556                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1557         save->cs.limit = 0xffff;
1558
1559         save->gdtr.limit = 0xffff;
1560         save->idtr.limit = 0xffff;
1561
1562         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1563         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1564
1565         svm_set_efer(&svm->vcpu, 0);
1566         save->dr6 = 0xffff0ff0;
1567         kvm_set_rflags(&svm->vcpu, 2);
1568         save->rip = 0x0000fff0;
1569         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1570
1571         /*
1572          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1573          * It also updates the guest-visible cr0 value.
1574          */
1575         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1576         kvm_mmu_reset_context(&svm->vcpu);
1577
1578         save->cr4 = X86_CR4_PAE;
1579         /* rdx = ?? */
1580
1581         if (npt_enabled) {
1582                 /* Setup VMCB for Nested Paging */
1583                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1584                 clr_intercept(svm, INTERCEPT_INVLPG);
1585                 clr_exception_intercept(svm, PF_VECTOR);
1586                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1587                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1588                 save->g_pat = svm->vcpu.arch.pat;
1589                 save->cr3 = 0;
1590                 save->cr4 = 0;
1591         }
1592         svm->asid_generation = 0;
1593
1594         svm->nested.vmcb = 0;
1595         svm->vcpu.arch.hflags = 0;
1596
1597         if (pause_filter_count) {
1598                 control->pause_filter_count = pause_filter_count;
1599                 if (pause_filter_thresh)
1600                         control->pause_filter_thresh = pause_filter_thresh;
1601                 set_intercept(svm, INTERCEPT_PAUSE);
1602         } else {
1603                 clr_intercept(svm, INTERCEPT_PAUSE);
1604         }
1605
1606         if (kvm_vcpu_apicv_active(&svm->vcpu))
1607                 avic_init_vmcb(svm);
1608
1609         /*
1610          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1611          * in VMCB and clear intercepts to avoid #VMEXIT.
1612          */
1613         if (vls) {
1614                 clr_intercept(svm, INTERCEPT_VMLOAD);
1615                 clr_intercept(svm, INTERCEPT_VMSAVE);
1616                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1617         }
1618
1619         if (vgif) {
1620                 clr_intercept(svm, INTERCEPT_STGI);
1621                 clr_intercept(svm, INTERCEPT_CLGI);
1622                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1623         }
1624
1625         if (sev_guest(svm->vcpu.kvm)) {
1626                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1627                 clr_exception_intercept(svm, UD_VECTOR);
1628         }
1629
1630         mark_all_dirty(svm->vmcb);
1631
1632         enable_gif(svm);
1633
1634 }
1635
1636 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1637                                        unsigned int index)
1638 {
1639         u64 *avic_physical_id_table;
1640         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1641
1642         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1643                 return NULL;
1644
1645         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1646
1647         return &avic_physical_id_table[index];
1648 }
1649
1650 /**
1651  * Note:
1652  * AVIC hardware walks the nested page table to check permissions,
1653  * but does not use the SPA address specified in the leaf page
1654  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1655  * field of the VMCB. Therefore, we set up the
1656  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1657  */
1658 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1659 {
1660         struct kvm *kvm = vcpu->kvm;
1661         int ret;
1662
1663         if (kvm->arch.apic_access_page_done)
1664                 return 0;
1665
1666         ret = x86_set_memory_region(kvm,
1667                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1668                                     APIC_DEFAULT_PHYS_BASE,
1669                                     PAGE_SIZE);
1670         if (ret)
1671                 return ret;
1672
1673         kvm->arch.apic_access_page_done = true;
1674         return 0;
1675 }
1676
1677 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1678 {
1679         int ret;
1680         u64 *entry, new_entry;
1681         int id = vcpu->vcpu_id;
1682         struct vcpu_svm *svm = to_svm(vcpu);
1683
1684         ret = avic_init_access_page(vcpu);
1685         if (ret)
1686                 return ret;
1687
1688         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1689                 return -EINVAL;
1690
1691         if (!svm->vcpu.arch.apic->regs)
1692                 return -EINVAL;
1693
1694         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1695
1696         /* Setting AVIC backing page address in the phy APIC ID table */
1697         entry = avic_get_physical_id_entry(vcpu, id);
1698         if (!entry)
1699                 return -EINVAL;
1700
1701         new_entry = READ_ONCE(*entry);
1702         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1703                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1704                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1705         WRITE_ONCE(*entry, new_entry);
1706
1707         svm->avic_physical_id_cache = entry;
1708
1709         return 0;
1710 }
1711
1712 static void __sev_asid_free(int asid)
1713 {
1714         struct svm_cpu_data *sd;
1715         int cpu, pos;
1716
1717         pos = asid - 1;
1718         clear_bit(pos, sev_asid_bitmap);
1719
1720         for_each_possible_cpu(cpu) {
1721                 sd = per_cpu(svm_data, cpu);
1722                 sd->sev_vmcbs[pos] = NULL;
1723         }
1724 }
1725
1726 static void sev_asid_free(struct kvm *kvm)
1727 {
1728         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1729
1730         __sev_asid_free(sev->asid);
1731 }
1732
1733 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1734 {
1735         struct sev_data_decommission *decommission;
1736         struct sev_data_deactivate *data;
1737
1738         if (!handle)
1739                 return;
1740
1741         data = kzalloc(sizeof(*data), GFP_KERNEL);
1742         if (!data)
1743                 return;
1744
1745         /* deactivate handle */
1746         data->handle = handle;
1747         sev_guest_deactivate(data, NULL);
1748
1749         wbinvd_on_all_cpus();
1750         sev_guest_df_flush(NULL);
1751         kfree(data);
1752
1753         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1754         if (!decommission)
1755                 return;
1756
1757         /* decommission handle */
1758         decommission->handle = handle;
1759         sev_guest_decommission(decommission, NULL);
1760
1761         kfree(decommission);
1762 }
1763
1764 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1765                                     unsigned long ulen, unsigned long *n,
1766                                     int write)
1767 {
1768         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1769         unsigned long npages, npinned, size;
1770         unsigned long locked, lock_limit;
1771         struct page **pages;
1772         unsigned long first, last;
1773
1774         if (ulen == 0 || uaddr + ulen < uaddr)
1775                 return NULL;
1776
1777         /* Calculate number of pages. */
1778         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1779         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1780         npages = (last - first + 1);
1781
1782         locked = sev->pages_locked + npages;
1783         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1784         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1785                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1786                 return NULL;
1787         }
1788
1789         /* Avoid using vmalloc for smaller buffers. */
1790         size = npages * sizeof(struct page *);
1791         if (size > PAGE_SIZE)
1792                 pages = vmalloc(size);
1793         else
1794                 pages = kmalloc(size, GFP_KERNEL);
1795
1796         if (!pages)
1797                 return NULL;
1798
1799         /* Pin the user virtual address. */
1800         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1801         if (npinned != npages) {
1802                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1803                 goto err;
1804         }
1805
1806         *n = npages;
1807         sev->pages_locked = locked;
1808
1809         return pages;
1810
1811 err:
1812         if (npinned > 0)
1813                 release_pages(pages, npinned);
1814
1815         kvfree(pages);
1816         return NULL;
1817 }
1818
1819 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1820                              unsigned long npages)
1821 {
1822         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1823
1824         release_pages(pages, npages);
1825         kvfree(pages);
1826         sev->pages_locked -= npages;
1827 }
1828
1829 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1830 {
1831         uint8_t *page_virtual;
1832         unsigned long i;
1833
1834         if (npages == 0 || pages == NULL)
1835                 return;
1836
1837         for (i = 0; i < npages; i++) {
1838                 page_virtual = kmap_atomic(pages[i]);
1839                 clflush_cache_range(page_virtual, PAGE_SIZE);
1840                 kunmap_atomic(page_virtual);
1841         }
1842 }
1843
1844 static void __unregister_enc_region_locked(struct kvm *kvm,
1845                                            struct enc_region *region)
1846 {
1847         /*
1848          * The guest may change the memory encryption attribute from C=0 -> C=1
1849          * or vice versa for this memory range. Lets make sure caches are
1850          * flushed to ensure that guest data gets written into memory with
1851          * correct C-bit.
1852          */
1853         sev_clflush_pages(region->pages, region->npages);
1854
1855         sev_unpin_memory(kvm, region->pages, region->npages);
1856         list_del(&region->list);
1857         kfree(region);
1858 }
1859
1860 static struct kvm *svm_vm_alloc(void)
1861 {
1862         struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1863         return &kvm_svm->kvm;
1864 }
1865
1866 static void svm_vm_free(struct kvm *kvm)
1867 {
1868         vfree(to_kvm_svm(kvm));
1869 }
1870
1871 static void sev_vm_destroy(struct kvm *kvm)
1872 {
1873         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1874         struct list_head *head = &sev->regions_list;
1875         struct list_head *pos, *q;
1876
1877         if (!sev_guest(kvm))
1878                 return;
1879
1880         mutex_lock(&kvm->lock);
1881
1882         /*
1883          * if userspace was terminated before unregistering the memory regions
1884          * then lets unpin all the registered memory.
1885          */
1886         if (!list_empty(head)) {
1887                 list_for_each_safe(pos, q, head) {
1888                         __unregister_enc_region_locked(kvm,
1889                                 list_entry(pos, struct enc_region, list));
1890                 }
1891         }
1892
1893         mutex_unlock(&kvm->lock);
1894
1895         sev_unbind_asid(kvm, sev->handle);
1896         sev_asid_free(kvm);
1897 }
1898
1899 static void avic_vm_destroy(struct kvm *kvm)
1900 {
1901         unsigned long flags;
1902         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1903
1904         if (!avic)
1905                 return;
1906
1907         if (kvm_svm->avic_logical_id_table_page)
1908                 __free_page(kvm_svm->avic_logical_id_table_page);
1909         if (kvm_svm->avic_physical_id_table_page)
1910                 __free_page(kvm_svm->avic_physical_id_table_page);
1911
1912         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1913         hash_del(&kvm_svm->hnode);
1914         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1915 }
1916
1917 static void svm_vm_destroy(struct kvm *kvm)
1918 {
1919         avic_vm_destroy(kvm);
1920         sev_vm_destroy(kvm);
1921 }
1922
1923 static int avic_vm_init(struct kvm *kvm)
1924 {
1925         unsigned long flags;
1926         int err = -ENOMEM;
1927         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1928         struct kvm_svm *k2;
1929         struct page *p_page;
1930         struct page *l_page;
1931         u32 vm_id;
1932
1933         if (!avic)
1934                 return 0;
1935
1936         /* Allocating physical APIC ID table (4KB) */
1937         p_page = alloc_page(GFP_KERNEL);
1938         if (!p_page)
1939                 goto free_avic;
1940
1941         kvm_svm->avic_physical_id_table_page = p_page;
1942         clear_page(page_address(p_page));
1943
1944         /* Allocating logical APIC ID table (4KB) */
1945         l_page = alloc_page(GFP_KERNEL);
1946         if (!l_page)
1947                 goto free_avic;
1948
1949         kvm_svm->avic_logical_id_table_page = l_page;
1950         clear_page(page_address(l_page));
1951
1952         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1953  again:
1954         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1955         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1956                 next_vm_id_wrapped = 1;
1957                 goto again;
1958         }
1959         /* Is it still in use? Only possible if wrapped at least once */
1960         if (next_vm_id_wrapped) {
1961                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1962                         if (k2->avic_vm_id == vm_id)
1963                                 goto again;
1964                 }
1965         }
1966         kvm_svm->avic_vm_id = vm_id;
1967         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1968         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1969
1970         return 0;
1971
1972 free_avic:
1973         avic_vm_destroy(kvm);
1974         return err;
1975 }
1976
1977 static inline int
1978 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1979 {
1980         int ret = 0;
1981         unsigned long flags;
1982         struct amd_svm_iommu_ir *ir;
1983         struct vcpu_svm *svm = to_svm(vcpu);
1984
1985         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1986                 return 0;
1987
1988         /*
1989          * Here, we go through the per-vcpu ir_list to update all existing
1990          * interrupt remapping table entry targeting this vcpu.
1991          */
1992         spin_lock_irqsave(&svm->ir_list_lock, flags);
1993
1994         if (list_empty(&svm->ir_list))
1995                 goto out;
1996
1997         list_for_each_entry(ir, &svm->ir_list, node) {
1998                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1999                 if (ret)
2000                         break;
2001         }
2002 out:
2003         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2004         return ret;
2005 }
2006
2007 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2008 {
2009         u64 entry;
2010         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2011         int h_physical_id = kvm_cpu_get_apicid(cpu);
2012         struct vcpu_svm *svm = to_svm(vcpu);
2013
2014         if (!kvm_vcpu_apicv_active(vcpu))
2015                 return;
2016
2017         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2018                 return;
2019
2020         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2021         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2022
2023         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2024         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2025
2026         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2027         if (svm->avic_is_running)
2028                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2029
2030         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2031         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2032                                         svm->avic_is_running);
2033 }
2034
2035 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2036 {
2037         u64 entry;
2038         struct vcpu_svm *svm = to_svm(vcpu);
2039
2040         if (!kvm_vcpu_apicv_active(vcpu))
2041                 return;
2042
2043         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2044         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2045                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2046
2047         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2048         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2049 }
2050
2051 /**
2052  * This function is called during VCPU halt/unhalt.
2053  */
2054 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2055 {
2056         struct vcpu_svm *svm = to_svm(vcpu);
2057
2058         svm->avic_is_running = is_run;
2059         if (is_run)
2060                 avic_vcpu_load(vcpu, vcpu->cpu);
2061         else
2062                 avic_vcpu_put(vcpu);
2063 }
2064
2065 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2066 {
2067         struct vcpu_svm *svm = to_svm(vcpu);
2068         u32 dummy;
2069         u32 eax = 1;
2070
2071         vcpu->arch.microcode_version = 0x01000065;
2072         svm->spec_ctrl = 0;
2073         svm->virt_spec_ctrl = 0;
2074
2075         if (!init_event) {
2076                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2077                                            MSR_IA32_APICBASE_ENABLE;
2078                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2079                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2080         }
2081         init_vmcb(svm);
2082
2083         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2084         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2085
2086         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2087                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2088 }
2089
2090 static int avic_init_vcpu(struct vcpu_svm *svm)
2091 {
2092         int ret;
2093
2094         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2095                 return 0;
2096
2097         ret = avic_init_backing_page(&svm->vcpu);
2098         if (ret)
2099                 return ret;
2100
2101         INIT_LIST_HEAD(&svm->ir_list);
2102         spin_lock_init(&svm->ir_list_lock);
2103
2104         return ret;
2105 }
2106
2107 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2108 {
2109         struct vcpu_svm *svm;
2110         struct page *page;
2111         struct page *msrpm_pages;
2112         struct page *hsave_page;
2113         struct page *nested_msrpm_pages;
2114         int err;
2115
2116         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2117         if (!svm) {
2118                 err = -ENOMEM;
2119                 goto out;
2120         }
2121
2122         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2123         if (err)
2124                 goto free_svm;
2125
2126         err = -ENOMEM;
2127         page = alloc_page(GFP_KERNEL);
2128         if (!page)
2129                 goto uninit;
2130
2131         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2132         if (!msrpm_pages)
2133                 goto free_page1;
2134
2135         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2136         if (!nested_msrpm_pages)
2137                 goto free_page2;
2138
2139         hsave_page = alloc_page(GFP_KERNEL);
2140         if (!hsave_page)
2141                 goto free_page3;
2142
2143         err = avic_init_vcpu(svm);
2144         if (err)
2145                 goto free_page4;
2146
2147         /* We initialize this flag to true to make sure that the is_running
2148          * bit would be set the first time the vcpu is loaded.
2149          */
2150         svm->avic_is_running = true;
2151
2152         svm->nested.hsave = page_address(hsave_page);
2153
2154         svm->msrpm = page_address(msrpm_pages);
2155         svm_vcpu_init_msrpm(svm->msrpm);
2156
2157         svm->nested.msrpm = page_address(nested_msrpm_pages);
2158         svm_vcpu_init_msrpm(svm->nested.msrpm);
2159
2160         svm->vmcb = page_address(page);
2161         clear_page(svm->vmcb);
2162         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2163         svm->asid_generation = 0;
2164         init_vmcb(svm);
2165
2166         svm_init_osvw(&svm->vcpu);
2167
2168         return &svm->vcpu;
2169
2170 free_page4:
2171         __free_page(hsave_page);
2172 free_page3:
2173         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2174 free_page2:
2175         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2176 free_page1:
2177         __free_page(page);
2178 uninit:
2179         kvm_vcpu_uninit(&svm->vcpu);
2180 free_svm:
2181         kmem_cache_free(kvm_vcpu_cache, svm);
2182 out:
2183         return ERR_PTR(err);
2184 }
2185
2186 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2187 {
2188         struct vcpu_svm *svm = to_svm(vcpu);
2189
2190         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2191         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2192         __free_page(virt_to_page(svm->nested.hsave));
2193         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2194         kvm_vcpu_uninit(vcpu);
2195         kmem_cache_free(kvm_vcpu_cache, svm);
2196         /*
2197          * The vmcb page can be recycled, causing a false negative in
2198          * svm_vcpu_load(). So do a full IBPB now.
2199          */
2200         indirect_branch_prediction_barrier();
2201 }
2202
2203 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2204 {
2205         struct vcpu_svm *svm = to_svm(vcpu);
2206         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2207         int i;
2208
2209         if (unlikely(cpu != vcpu->cpu)) {
2210                 svm->asid_generation = 0;
2211                 mark_all_dirty(svm->vmcb);
2212         }
2213
2214 #ifdef CONFIG_X86_64
2215         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2216 #endif
2217         savesegment(fs, svm->host.fs);
2218         savesegment(gs, svm->host.gs);
2219         svm->host.ldt = kvm_read_ldt();
2220
2221         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2222                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2223
2224         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2225                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2226                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2227                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2228                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2229                 }
2230         }
2231         /* This assumes that the kernel never uses MSR_TSC_AUX */
2232         if (static_cpu_has(X86_FEATURE_RDTSCP))
2233                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2234
2235         if (sd->current_vmcb != svm->vmcb) {
2236                 sd->current_vmcb = svm->vmcb;
2237                 indirect_branch_prediction_barrier();
2238         }
2239         avic_vcpu_load(vcpu, cpu);
2240 }
2241
2242 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2243 {
2244         struct vcpu_svm *svm = to_svm(vcpu);
2245         int i;
2246
2247         avic_vcpu_put(vcpu);
2248
2249         ++vcpu->stat.host_state_reload;
2250         kvm_load_ldt(svm->host.ldt);
2251 #ifdef CONFIG_X86_64
2252         loadsegment(fs, svm->host.fs);
2253         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2254         load_gs_index(svm->host.gs);
2255 #else
2256 #ifdef CONFIG_X86_32_LAZY_GS
2257         loadsegment(gs, svm->host.gs);
2258 #endif
2259 #endif
2260         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2261                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2262 }
2263
2264 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2265 {
2266         avic_set_running(vcpu, false);
2267 }
2268
2269 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2270 {
2271         avic_set_running(vcpu, true);
2272 }
2273
2274 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2275 {
2276         struct vcpu_svm *svm = to_svm(vcpu);
2277         unsigned long rflags = svm->vmcb->save.rflags;
2278
2279         if (svm->nmi_singlestep) {
2280                 /* Hide our flags if they were not set by the guest */
2281                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2282                         rflags &= ~X86_EFLAGS_TF;
2283                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2284                         rflags &= ~X86_EFLAGS_RF;
2285         }
2286         return rflags;
2287 }
2288
2289 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2290 {
2291         if (to_svm(vcpu)->nmi_singlestep)
2292                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2293
2294        /*
2295         * Any change of EFLAGS.VM is accompanied by a reload of SS
2296         * (caused by either a task switch or an inter-privilege IRET),
2297         * so we do not need to update the CPL here.
2298         */
2299         to_svm(vcpu)->vmcb->save.rflags = rflags;
2300 }
2301
2302 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2303 {
2304         switch (reg) {
2305         case VCPU_EXREG_PDPTR:
2306                 BUG_ON(!npt_enabled);
2307                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2308                 break;
2309         default:
2310                 BUG();
2311         }
2312 }
2313
2314 static void svm_set_vintr(struct vcpu_svm *svm)
2315 {
2316         set_intercept(svm, INTERCEPT_VINTR);
2317 }
2318
2319 static void svm_clear_vintr(struct vcpu_svm *svm)
2320 {
2321         clr_intercept(svm, INTERCEPT_VINTR);
2322 }
2323
2324 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2325 {
2326         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2327
2328         switch (seg) {
2329         case VCPU_SREG_CS: return &save->cs;
2330         case VCPU_SREG_DS: return &save->ds;
2331         case VCPU_SREG_ES: return &save->es;
2332         case VCPU_SREG_FS: return &save->fs;
2333         case VCPU_SREG_GS: return &save->gs;
2334         case VCPU_SREG_SS: return &save->ss;
2335         case VCPU_SREG_TR: return &save->tr;
2336         case VCPU_SREG_LDTR: return &save->ldtr;
2337         }
2338         BUG();
2339         return NULL;
2340 }
2341
2342 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2343 {
2344         struct vmcb_seg *s = svm_seg(vcpu, seg);
2345
2346         return s->base;
2347 }
2348
2349 static void svm_get_segment(struct kvm_vcpu *vcpu,
2350                             struct kvm_segment *var, int seg)
2351 {
2352         struct vmcb_seg *s = svm_seg(vcpu, seg);
2353
2354         var->base = s->base;
2355         var->limit = s->limit;
2356         var->selector = s->selector;
2357         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2358         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2359         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2360         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2361         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2362         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2363         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2364
2365         /*
2366          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2367          * However, the SVM spec states that the G bit is not observed by the
2368          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2369          * So let's synthesize a legal G bit for all segments, this helps
2370          * running KVM nested. It also helps cross-vendor migration, because
2371          * Intel's vmentry has a check on the 'G' bit.
2372          */
2373         var->g = s->limit > 0xfffff;
2374
2375         /*
2376          * AMD's VMCB does not have an explicit unusable field, so emulate it
2377          * for cross vendor migration purposes by "not present"
2378          */
2379         var->unusable = !var->present;
2380
2381         switch (seg) {
2382         case VCPU_SREG_TR:
2383                 /*
2384                  * Work around a bug where the busy flag in the tr selector
2385                  * isn't exposed
2386                  */
2387                 var->type |= 0x2;
2388                 break;
2389         case VCPU_SREG_DS:
2390         case VCPU_SREG_ES:
2391         case VCPU_SREG_FS:
2392         case VCPU_SREG_GS:
2393                 /*
2394                  * The accessed bit must always be set in the segment
2395                  * descriptor cache, although it can be cleared in the
2396                  * descriptor, the cached bit always remains at 1. Since
2397                  * Intel has a check on this, set it here to support
2398                  * cross-vendor migration.
2399                  */
2400                 if (!var->unusable)
2401                         var->type |= 0x1;
2402                 break;
2403         case VCPU_SREG_SS:
2404                 /*
2405                  * On AMD CPUs sometimes the DB bit in the segment
2406                  * descriptor is left as 1, although the whole segment has
2407                  * been made unusable. Clear it here to pass an Intel VMX
2408                  * entry check when cross vendor migrating.
2409                  */
2410                 if (var->unusable)
2411                         var->db = 0;
2412                 /* This is symmetric with svm_set_segment() */
2413                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2414                 break;
2415         }
2416 }
2417
2418 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2419 {
2420         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2421
2422         return save->cpl;
2423 }
2424
2425 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2426 {
2427         struct vcpu_svm *svm = to_svm(vcpu);
2428
2429         dt->size = svm->vmcb->save.idtr.limit;
2430         dt->address = svm->vmcb->save.idtr.base;
2431 }
2432
2433 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2434 {
2435         struct vcpu_svm *svm = to_svm(vcpu);
2436
2437         svm->vmcb->save.idtr.limit = dt->size;
2438         svm->vmcb->save.idtr.base = dt->address ;
2439         mark_dirty(svm->vmcb, VMCB_DT);
2440 }
2441
2442 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2443 {
2444         struct vcpu_svm *svm = to_svm(vcpu);
2445
2446         dt->size = svm->vmcb->save.gdtr.limit;
2447         dt->address = svm->vmcb->save.gdtr.base;
2448 }
2449
2450 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2451 {
2452         struct vcpu_svm *svm = to_svm(vcpu);
2453
2454         svm->vmcb->save.gdtr.limit = dt->size;
2455         svm->vmcb->save.gdtr.base = dt->address ;
2456         mark_dirty(svm->vmcb, VMCB_DT);
2457 }
2458
2459 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2460 {
2461 }
2462
2463 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2464 {
2465 }
2466
2467 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2468 {
2469 }
2470
2471 static void update_cr0_intercept(struct vcpu_svm *svm)
2472 {
2473         ulong gcr0 = svm->vcpu.arch.cr0;
2474         u64 *hcr0 = &svm->vmcb->save.cr0;
2475
2476         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2477                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2478
2479         mark_dirty(svm->vmcb, VMCB_CR);
2480
2481         if (gcr0 == *hcr0) {
2482                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2483                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2484         } else {
2485                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2486                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2487         }
2488 }
2489
2490 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2491 {
2492         struct vcpu_svm *svm = to_svm(vcpu);
2493
2494 #ifdef CONFIG_X86_64
2495         if (vcpu->arch.efer & EFER_LME) {
2496                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2497                         vcpu->arch.efer |= EFER_LMA;
2498                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2499                 }
2500
2501                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2502                         vcpu->arch.efer &= ~EFER_LMA;
2503                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2504                 }
2505         }
2506 #endif
2507         vcpu->arch.cr0 = cr0;
2508
2509         if (!npt_enabled)
2510                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2511
2512         /*
2513          * re-enable caching here because the QEMU bios
2514          * does not do it - this results in some delay at
2515          * reboot
2516          */
2517         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2518                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2519         svm->vmcb->save.cr0 = cr0;
2520         mark_dirty(svm->vmcb, VMCB_CR);
2521         update_cr0_intercept(svm);
2522 }
2523
2524 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2525 {
2526         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2527         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2528
2529         if (cr4 & X86_CR4_VMXE)
2530                 return 1;
2531
2532         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2533                 svm_flush_tlb(vcpu, true);
2534
2535         vcpu->arch.cr4 = cr4;
2536         if (!npt_enabled)
2537                 cr4 |= X86_CR4_PAE;
2538         cr4 |= host_cr4_mce;
2539         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2540         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2541         return 0;
2542 }
2543
2544 static void svm_set_segment(struct kvm_vcpu *vcpu,
2545                             struct kvm_segment *var, int seg)
2546 {
2547         struct vcpu_svm *svm = to_svm(vcpu);
2548         struct vmcb_seg *s = svm_seg(vcpu, seg);
2549
2550         s->base = var->base;
2551         s->limit = var->limit;
2552         s->selector = var->selector;
2553         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2554         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2555         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2556         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2557         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2558         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2559         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2560         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2561
2562         /*
2563          * This is always accurate, except if SYSRET returned to a segment
2564          * with SS.DPL != 3.  Intel does not have this quirk, and always
2565          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2566          * would entail passing the CPL to userspace and back.
2567          */
2568         if (seg == VCPU_SREG_SS)
2569                 /* This is symmetric with svm_get_segment() */
2570                 svm->vmcb->save.cpl = (var->dpl & 3);
2571
2572         mark_dirty(svm->vmcb, VMCB_SEG);
2573 }
2574
2575 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2576 {
2577         struct vcpu_svm *svm = to_svm(vcpu);
2578
2579         clr_exception_intercept(svm, BP_VECTOR);
2580
2581         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2582                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2583                         set_exception_intercept(svm, BP_VECTOR);
2584         } else
2585                 vcpu->guest_debug = 0;
2586 }
2587
2588 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2589 {
2590         if (sd->next_asid > sd->max_asid) {
2591                 ++sd->asid_generation;
2592                 sd->next_asid = sd->min_asid;
2593                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2594         }
2595
2596         svm->asid_generation = sd->asid_generation;
2597         svm->vmcb->control.asid = sd->next_asid++;
2598
2599         mark_dirty(svm->vmcb, VMCB_ASID);
2600 }
2601
2602 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2603 {
2604         return to_svm(vcpu)->vmcb->save.dr6;
2605 }
2606
2607 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2608 {
2609         struct vcpu_svm *svm = to_svm(vcpu);
2610
2611         svm->vmcb->save.dr6 = value;
2612         mark_dirty(svm->vmcb, VMCB_DR);
2613 }
2614
2615 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2616 {
2617         struct vcpu_svm *svm = to_svm(vcpu);
2618
2619         get_debugreg(vcpu->arch.db[0], 0);
2620         get_debugreg(vcpu->arch.db[1], 1);
2621         get_debugreg(vcpu->arch.db[2], 2);
2622         get_debugreg(vcpu->arch.db[3], 3);
2623         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2624         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2625
2626         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2627         set_dr_intercepts(svm);
2628 }
2629
2630 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2631 {
2632         struct vcpu_svm *svm = to_svm(vcpu);
2633
2634         svm->vmcb->save.dr7 = value;
2635         mark_dirty(svm->vmcb, VMCB_DR);
2636 }
2637
2638 static int pf_interception(struct vcpu_svm *svm)
2639 {
2640         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2641         u64 error_code = svm->vmcb->control.exit_info_1;
2642
2643         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2644                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2645                         svm->vmcb->control.insn_bytes : NULL,
2646                         svm->vmcb->control.insn_len);
2647 }
2648
2649 static int npf_interception(struct vcpu_svm *svm)
2650 {
2651         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2652         u64 error_code = svm->vmcb->control.exit_info_1;
2653
2654         trace_kvm_page_fault(fault_address, error_code);
2655         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2656                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2657                         svm->vmcb->control.insn_bytes : NULL,
2658                         svm->vmcb->control.insn_len);
2659 }
2660
2661 static int db_interception(struct vcpu_svm *svm)
2662 {
2663         struct kvm_run *kvm_run = svm->vcpu.run;
2664
2665         if (!(svm->vcpu.guest_debug &
2666               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2667                 !svm->nmi_singlestep) {
2668                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2669                 return 1;
2670         }
2671
2672         if (svm->nmi_singlestep) {
2673                 disable_nmi_singlestep(svm);
2674         }
2675
2676         if (svm->vcpu.guest_debug &
2677             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2678                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2679                 kvm_run->debug.arch.pc =
2680                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2681                 kvm_run->debug.arch.exception = DB_VECTOR;
2682                 return 0;
2683         }
2684
2685         return 1;
2686 }
2687
2688 static int bp_interception(struct vcpu_svm *svm)
2689 {
2690         struct kvm_run *kvm_run = svm->vcpu.run;
2691
2692         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2693         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2694         kvm_run->debug.arch.exception = BP_VECTOR;
2695         return 0;
2696 }
2697
2698 static int ud_interception(struct vcpu_svm *svm)
2699 {
2700         return handle_ud(&svm->vcpu);
2701 }
2702
2703 static int ac_interception(struct vcpu_svm *svm)
2704 {
2705         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2706         return 1;
2707 }
2708
2709 static int gp_interception(struct vcpu_svm *svm)
2710 {
2711         struct kvm_vcpu *vcpu = &svm->vcpu;
2712         u32 error_code = svm->vmcb->control.exit_info_1;
2713         int er;
2714
2715         WARN_ON_ONCE(!enable_vmware_backdoor);
2716
2717         er = kvm_emulate_instruction(vcpu,
2718                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2719         if (er == EMULATE_USER_EXIT)
2720                 return 0;
2721         else if (er != EMULATE_DONE)
2722                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2723         return 1;
2724 }
2725
2726 static bool is_erratum_383(void)
2727 {
2728         int err, i;
2729         u64 value;
2730
2731         if (!erratum_383_found)
2732                 return false;
2733
2734         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2735         if (err)
2736                 return false;
2737
2738         /* Bit 62 may or may not be set for this mce */
2739         value &= ~(1ULL << 62);
2740
2741         if (value != 0xb600000000010015ULL)
2742                 return false;
2743
2744         /* Clear MCi_STATUS registers */
2745         for (i = 0; i < 6; ++i)
2746                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2747
2748         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2749         if (!err) {
2750                 u32 low, high;
2751
2752                 value &= ~(1ULL << 2);
2753                 low    = lower_32_bits(value);
2754                 high   = upper_32_bits(value);
2755
2756                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2757         }
2758
2759         /* Flush tlb to evict multi-match entries */
2760         __flush_tlb_all();
2761
2762         return true;
2763 }
2764
2765 static void svm_handle_mce(struct vcpu_svm *svm)
2766 {
2767         if (is_erratum_383()) {
2768                 /*
2769                  * Erratum 383 triggered. Guest state is corrupt so kill the
2770                  * guest.
2771                  */
2772                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2773
2774                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2775
2776                 return;
2777         }
2778
2779         /*
2780          * On an #MC intercept the MCE handler is not called automatically in
2781          * the host. So do it by hand here.
2782          */
2783         asm volatile (
2784                 "int $0x12\n");
2785         /* not sure if we ever come back to this point */
2786
2787         return;
2788 }
2789
2790 static int mc_interception(struct vcpu_svm *svm)
2791 {
2792         return 1;
2793 }
2794
2795 static int shutdown_interception(struct vcpu_svm *svm)
2796 {
2797         struct kvm_run *kvm_run = svm->vcpu.run;
2798
2799         /*
2800          * VMCB is undefined after a SHUTDOWN intercept
2801          * so reinitialize it.
2802          */
2803         clear_page(svm->vmcb);
2804         init_vmcb(svm);
2805
2806         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2807         return 0;
2808 }
2809
2810 static int io_interception(struct vcpu_svm *svm)
2811 {
2812         struct kvm_vcpu *vcpu = &svm->vcpu;
2813         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2814         int size, in, string;
2815         unsigned port;
2816
2817         ++svm->vcpu.stat.io_exits;
2818         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2819         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2820         if (string)
2821                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2822
2823         port = io_info >> 16;
2824         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2825         svm->next_rip = svm->vmcb->control.exit_info_2;
2826
2827         return kvm_fast_pio(&svm->vcpu, size, port, in);
2828 }
2829
2830 static int nmi_interception(struct vcpu_svm *svm)
2831 {
2832         return 1;
2833 }
2834
2835 static int intr_interception(struct vcpu_svm *svm)
2836 {
2837         ++svm->vcpu.stat.irq_exits;
2838         return 1;
2839 }
2840
2841 static int nop_on_interception(struct vcpu_svm *svm)
2842 {
2843         return 1;
2844 }
2845
2846 static int halt_interception(struct vcpu_svm *svm)
2847 {
2848         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2849         return kvm_emulate_halt(&svm->vcpu);
2850 }
2851
2852 static int vmmcall_interception(struct vcpu_svm *svm)
2853 {
2854         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2855         return kvm_emulate_hypercall(&svm->vcpu);
2856 }
2857
2858 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2859 {
2860         struct vcpu_svm *svm = to_svm(vcpu);
2861
2862         return svm->nested.nested_cr3;
2863 }
2864
2865 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2866 {
2867         struct vcpu_svm *svm = to_svm(vcpu);
2868         u64 cr3 = svm->nested.nested_cr3;
2869         u64 pdpte;
2870         int ret;
2871
2872         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2873                                        offset_in_page(cr3) + index * 8, 8);
2874         if (ret)
2875                 return 0;
2876         return pdpte;
2877 }
2878
2879 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2880                                    unsigned long root)
2881 {
2882         struct vcpu_svm *svm = to_svm(vcpu);
2883
2884         svm->vmcb->control.nested_cr3 = __sme_set(root);
2885         mark_dirty(svm->vmcb, VMCB_NPT);
2886 }
2887
2888 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2889                                        struct x86_exception *fault)
2890 {
2891         struct vcpu_svm *svm = to_svm(vcpu);
2892
2893         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2894                 /*
2895                  * TODO: track the cause of the nested page fault, and
2896                  * correctly fill in the high bits of exit_info_1.
2897                  */
2898                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2899                 svm->vmcb->control.exit_code_hi = 0;
2900                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2901                 svm->vmcb->control.exit_info_2 = fault->address;
2902         }
2903
2904         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2905         svm->vmcb->control.exit_info_1 |= fault->error_code;
2906
2907         /*
2908          * The present bit is always zero for page structure faults on real
2909          * hardware.
2910          */
2911         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2912                 svm->vmcb->control.exit_info_1 &= ~1;
2913
2914         nested_svm_vmexit(svm);
2915 }
2916
2917 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2918 {
2919         WARN_ON(mmu_is_nested(vcpu));
2920         kvm_init_shadow_mmu(vcpu);
2921         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2922         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2923         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2924         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2925         vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2926         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2927         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2928 }
2929
2930 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2931 {
2932         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2933 }
2934
2935 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2936 {
2937         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2938             !is_paging(&svm->vcpu)) {
2939                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2940                 return 1;
2941         }
2942
2943         if (svm->vmcb->save.cpl) {
2944                 kvm_inject_gp(&svm->vcpu, 0);
2945                 return 1;
2946         }
2947
2948         return 0;
2949 }
2950
2951 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2952                                       bool has_error_code, u32 error_code)
2953 {
2954         int vmexit;
2955
2956         if (!is_guest_mode(&svm->vcpu))
2957                 return 0;
2958
2959         vmexit = nested_svm_intercept(svm);
2960         if (vmexit != NESTED_EXIT_DONE)
2961                 return 0;
2962
2963         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2964         svm->vmcb->control.exit_code_hi = 0;
2965         svm->vmcb->control.exit_info_1 = error_code;
2966
2967         /*
2968          * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2969          * The fix is to add the ancillary datum (CR2 or DR6) to structs
2970          * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2971          * written only when inject_pending_event runs (DR6 would written here
2972          * too).  This should be conditional on a new capability---if the
2973          * capability is disabled, kvm_multiple_exception would write the
2974          * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2975          */
2976         if (svm->vcpu.arch.exception.nested_apf)
2977                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2978         else
2979                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2980
2981         svm->nested.exit_required = true;
2982         return vmexit;
2983 }
2984
2985 /* This function returns true if it is save to enable the irq window */
2986 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2987 {
2988         if (!is_guest_mode(&svm->vcpu))
2989                 return true;
2990
2991         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2992                 return true;
2993
2994         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2995                 return false;
2996
2997         /*
2998          * if vmexit was already requested (by intercepted exception
2999          * for instance) do not overwrite it with "external interrupt"
3000          * vmexit.
3001          */
3002         if (svm->nested.exit_required)
3003                 return false;
3004
3005         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3006         svm->vmcb->control.exit_info_1 = 0;
3007         svm->vmcb->control.exit_info_2 = 0;
3008
3009         if (svm->nested.intercept & 1ULL) {
3010                 /*
3011                  * The #vmexit can't be emulated here directly because this
3012                  * code path runs with irqs and preemption disabled. A
3013                  * #vmexit emulation might sleep. Only signal request for
3014                  * the #vmexit here.
3015                  */
3016                 svm->nested.exit_required = true;
3017                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3018                 return false;
3019         }
3020
3021         return true;
3022 }
3023
3024 /* This function returns true if it is save to enable the nmi window */
3025 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3026 {
3027         if (!is_guest_mode(&svm->vcpu))
3028                 return true;
3029
3030         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3031                 return true;
3032
3033         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3034         svm->nested.exit_required = true;
3035
3036         return false;
3037 }
3038
3039 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3040 {
3041         struct page *page;
3042
3043         might_sleep();
3044
3045         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3046         if (is_error_page(page))
3047                 goto error;
3048
3049         *_page = page;
3050
3051         return kmap(page);
3052
3053 error:
3054         kvm_inject_gp(&svm->vcpu, 0);
3055
3056         return NULL;
3057 }
3058
3059 static void nested_svm_unmap(struct page *page)
3060 {
3061         kunmap(page);
3062         kvm_release_page_dirty(page);
3063 }
3064
3065 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3066 {
3067         unsigned port, size, iopm_len;
3068         u16 val, mask;
3069         u8 start_bit;
3070         u64 gpa;
3071
3072         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3073                 return NESTED_EXIT_HOST;
3074
3075         port = svm->vmcb->control.exit_info_1 >> 16;
3076         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3077                 SVM_IOIO_SIZE_SHIFT;
3078         gpa  = svm->nested.vmcb_iopm + (port / 8);
3079         start_bit = port % 8;
3080         iopm_len = (start_bit + size > 8) ? 2 : 1;
3081         mask = (0xf >> (4 - size)) << start_bit;
3082         val = 0;
3083
3084         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3085                 return NESTED_EXIT_DONE;
3086
3087         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3088 }
3089
3090 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3091 {
3092         u32 offset, msr, value;
3093         int write, mask;
3094
3095         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3096                 return NESTED_EXIT_HOST;
3097
3098         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3099         offset = svm_msrpm_offset(msr);
3100         write  = svm->vmcb->control.exit_info_1 & 1;
3101         mask   = 1 << ((2 * (msr & 0xf)) + write);
3102
3103         if (offset == MSR_INVALID)
3104                 return NESTED_EXIT_DONE;
3105
3106         /* Offset is in 32 bit units but need in 8 bit units */
3107         offset *= 4;
3108
3109         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3110                 return NESTED_EXIT_DONE;
3111
3112         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3113 }
3114
3115 /* DB exceptions for our internal use must not cause vmexit */
3116 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3117 {
3118         unsigned long dr6;
3119
3120         /* if we're not singlestepping, it's not ours */
3121         if (!svm->nmi_singlestep)
3122                 return NESTED_EXIT_DONE;
3123
3124         /* if it's not a singlestep exception, it's not ours */
3125         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3126                 return NESTED_EXIT_DONE;
3127         if (!(dr6 & DR6_BS))
3128                 return NESTED_EXIT_DONE;
3129
3130         /* if the guest is singlestepping, it should get the vmexit */
3131         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3132                 disable_nmi_singlestep(svm);
3133                 return NESTED_EXIT_DONE;
3134         }
3135
3136         /* it's ours, the nested hypervisor must not see this one */
3137         return NESTED_EXIT_HOST;
3138 }
3139
3140 static int nested_svm_exit_special(struct vcpu_svm *svm)
3141 {
3142         u32 exit_code = svm->vmcb->control.exit_code;
3143
3144         switch (exit_code) {
3145         case SVM_EXIT_INTR:
3146         case SVM_EXIT_NMI:
3147         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3148                 return NESTED_EXIT_HOST;
3149         case SVM_EXIT_NPF:
3150                 /* For now we are always handling NPFs when using them */
3151                 if (npt_enabled)
3152                         return NESTED_EXIT_HOST;
3153                 break;
3154         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3155                 /* When we're shadowing, trap PFs, but not async PF */
3156                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3157                         return NESTED_EXIT_HOST;
3158                 break;
3159         default:
3160                 break;
3161         }
3162
3163         return NESTED_EXIT_CONTINUE;
3164 }
3165
3166 /*
3167  * If this function returns true, this #vmexit was already handled
3168  */
3169 static int nested_svm_intercept(struct vcpu_svm *svm)
3170 {
3171         u32 exit_code = svm->vmcb->control.exit_code;
3172         int vmexit = NESTED_EXIT_HOST;
3173
3174         switch (exit_code) {
3175         case SVM_EXIT_MSR:
3176                 vmexit = nested_svm_exit_handled_msr(svm);
3177                 break;
3178         case SVM_EXIT_IOIO:
3179                 vmexit = nested_svm_intercept_ioio(svm);
3180                 break;
3181         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3182                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3183                 if (svm->nested.intercept_cr & bit)
3184                         vmexit = NESTED_EXIT_DONE;
3185                 break;
3186         }
3187         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3188                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3189                 if (svm->nested.intercept_dr & bit)
3190                         vmexit = NESTED_EXIT_DONE;
3191                 break;
3192         }
3193         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3194                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3195                 if (svm->nested.intercept_exceptions & excp_bits) {
3196                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3197                                 vmexit = nested_svm_intercept_db(svm);
3198                         else
3199                                 vmexit = NESTED_EXIT_DONE;
3200                 }
3201                 /* async page fault always cause vmexit */
3202                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3203                          svm->vcpu.arch.exception.nested_apf != 0)
3204                         vmexit = NESTED_EXIT_DONE;
3205                 break;
3206         }
3207         case SVM_EXIT_ERR: {
3208                 vmexit = NESTED_EXIT_DONE;
3209                 break;
3210         }
3211         default: {
3212                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3213                 if (svm->nested.intercept & exit_bits)
3214                         vmexit = NESTED_EXIT_DONE;
3215         }
3216         }
3217
3218         return vmexit;
3219 }
3220
3221 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3222 {
3223         int vmexit;
3224
3225         vmexit = nested_svm_intercept(svm);
3226
3227         if (vmexit == NESTED_EXIT_DONE)
3228                 nested_svm_vmexit(svm);
3229
3230         return vmexit;
3231 }
3232
3233 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3234 {
3235         struct vmcb_control_area *dst  = &dst_vmcb->control;
3236         struct vmcb_control_area *from = &from_vmcb->control;
3237
3238         dst->intercept_cr         = from->intercept_cr;
3239         dst->intercept_dr         = from->intercept_dr;
3240         dst->intercept_exceptions = from->intercept_exceptions;
3241         dst->intercept            = from->intercept;
3242         dst->iopm_base_pa         = from->iopm_base_pa;
3243         dst->msrpm_base_pa        = from->msrpm_base_pa;
3244         dst->tsc_offset           = from->tsc_offset;
3245         dst->asid                 = from->asid;
3246         dst->tlb_ctl              = from->tlb_ctl;
3247         dst->int_ctl              = from->int_ctl;
3248         dst->int_vector           = from->int_vector;
3249         dst->int_state            = from->int_state;
3250         dst->exit_code            = from->exit_code;
3251         dst->exit_code_hi         = from->exit_code_hi;
3252         dst->exit_info_1          = from->exit_info_1;
3253         dst->exit_info_2          = from->exit_info_2;
3254         dst->exit_int_info        = from->exit_int_info;
3255         dst->exit_int_info_err    = from->exit_int_info_err;
3256         dst->nested_ctl           = from->nested_ctl;
3257         dst->event_inj            = from->event_inj;
3258         dst->event_inj_err        = from->event_inj_err;
3259         dst->nested_cr3           = from->nested_cr3;
3260         dst->virt_ext              = from->virt_ext;
3261 }
3262
3263 static int nested_svm_vmexit(struct vcpu_svm *svm)
3264 {
3265         struct vmcb *nested_vmcb;
3266         struct vmcb *hsave = svm->nested.hsave;
3267         struct vmcb *vmcb = svm->vmcb;
3268         struct page *page;
3269
3270         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3271                                        vmcb->control.exit_info_1,
3272                                        vmcb->control.exit_info_2,
3273                                        vmcb->control.exit_int_info,
3274                                        vmcb->control.exit_int_info_err,
3275                                        KVM_ISA_SVM);
3276
3277         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3278         if (!nested_vmcb)
3279                 return 1;
3280
3281         /* Exit Guest-Mode */
3282         leave_guest_mode(&svm->vcpu);
3283         svm->nested.vmcb = 0;
3284
3285         /* Give the current vmcb to the guest */
3286         disable_gif(svm);
3287
3288         nested_vmcb->save.es     = vmcb->save.es;
3289         nested_vmcb->save.cs     = vmcb->save.cs;
3290         nested_vmcb->save.ss     = vmcb->save.ss;
3291         nested_vmcb->save.ds     = vmcb->save.ds;
3292         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3293         nested_vmcb->save.idtr   = vmcb->save.idtr;
3294         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3295         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3296         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3297         nested_vmcb->save.cr2    = vmcb->save.cr2;
3298         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3299         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3300         nested_vmcb->save.rip    = vmcb->save.rip;
3301         nested_vmcb->save.rsp    = vmcb->save.rsp;
3302         nested_vmcb->save.rax    = vmcb->save.rax;
3303         nested_vmcb->save.dr7    = vmcb->save.dr7;
3304         nested_vmcb->save.dr6    = vmcb->save.dr6;
3305         nested_vmcb->save.cpl    = vmcb->save.cpl;
3306
3307         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3308         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3309         nested_vmcb->control.int_state         = vmcb->control.int_state;
3310         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3311         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3312         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3313         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3314         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3315         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3316
3317         if (svm->nrips_enabled)
3318                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3319
3320         /*
3321          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3322          * to make sure that we do not lose injected events. So check event_inj
3323          * here and copy it to exit_int_info if it is valid.
3324          * Exit_int_info and event_inj can't be both valid because the case
3325          * below only happens on a VMRUN instruction intercept which has
3326          * no valid exit_int_info set.
3327          */
3328         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3329                 struct vmcb_control_area *nc = &nested_vmcb->control;
3330
3331                 nc->exit_int_info     = vmcb->control.event_inj;
3332                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3333         }
3334
3335         nested_vmcb->control.tlb_ctl           = 0;
3336         nested_vmcb->control.event_inj         = 0;
3337         nested_vmcb->control.event_inj_err     = 0;
3338
3339         /* We always set V_INTR_MASKING and remember the old value in hflags */
3340         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3341                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3342
3343         /* Restore the original control entries */
3344         copy_vmcb_control_area(vmcb, hsave);
3345
3346         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3347         kvm_clear_exception_queue(&svm->vcpu);
3348         kvm_clear_interrupt_queue(&svm->vcpu);
3349
3350         svm->nested.nested_cr3 = 0;
3351
3352         /* Restore selected save entries */
3353         svm->vmcb->save.es = hsave->save.es;
3354         svm->vmcb->save.cs = hsave->save.cs;
3355         svm->vmcb->save.ss = hsave->save.ss;
3356         svm->vmcb->save.ds = hsave->save.ds;
3357         svm->vmcb->save.gdtr = hsave->save.gdtr;
3358         svm->vmcb->save.idtr = hsave->save.idtr;
3359         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3360         svm_set_efer(&svm->vcpu, hsave->save.efer);
3361         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3362         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3363         if (npt_enabled) {
3364                 svm->vmcb->save.cr3 = hsave->save.cr3;
3365                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3366         } else {
3367                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3368         }
3369         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3370         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3371         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3372         svm->vmcb->save.dr7 = 0;
3373         svm->vmcb->save.cpl = 0;
3374         svm->vmcb->control.exit_int_info = 0;
3375
3376         mark_all_dirty(svm->vmcb);
3377
3378         nested_svm_unmap(page);
3379
3380         nested_svm_uninit_mmu_context(&svm->vcpu);
3381         kvm_mmu_reset_context(&svm->vcpu);
3382         kvm_mmu_load(&svm->vcpu);
3383
3384         return 0;
3385 }
3386
3387 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3388 {
3389         /*
3390          * This function merges the msr permission bitmaps of kvm and the
3391          * nested vmcb. It is optimized in that it only merges the parts where
3392          * the kvm msr permission bitmap may contain zero bits
3393          */
3394         int i;
3395
3396         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3397                 return true;
3398
3399         for (i = 0; i < MSRPM_OFFSETS; i++) {
3400                 u32 value, p;
3401                 u64 offset;
3402
3403                 if (msrpm_offsets[i] == 0xffffffff)
3404                         break;
3405
3406                 p      = msrpm_offsets[i];
3407                 offset = svm->nested.vmcb_msrpm + (p * 4);
3408
3409                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3410                         return false;
3411
3412                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3413         }
3414
3415         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3416
3417         return true;
3418 }
3419
3420 static bool nested_vmcb_checks(struct vmcb *vmcb)
3421 {
3422         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3423                 return false;
3424
3425         if (vmcb->control.asid == 0)
3426                 return false;
3427
3428         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3429             !npt_enabled)
3430                 return false;
3431
3432         return true;
3433 }
3434
3435 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3436                                  struct vmcb *nested_vmcb, struct page *page)
3437 {
3438         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3439                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3440         else
3441                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3442
3443         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3444                 kvm_mmu_unload(&svm->vcpu);
3445                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3446                 nested_svm_init_mmu_context(&svm->vcpu);
3447         }
3448
3449         /* Load the nested guest state */
3450         svm->vmcb->save.es = nested_vmcb->save.es;
3451         svm->vmcb->save.cs = nested_vmcb->save.cs;
3452         svm->vmcb->save.ss = nested_vmcb->save.ss;
3453         svm->vmcb->save.ds = nested_vmcb->save.ds;
3454         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3455         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3456         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3457         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3458         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3459         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3460         if (npt_enabled) {
3461                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3462                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3463         } else
3464                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3465
3466         /* Guest paging mode is active - reset mmu */
3467         kvm_mmu_reset_context(&svm->vcpu);
3468
3469         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3470         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3471         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3472         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3473
3474         /* In case we don't even reach vcpu_run, the fields are not updated */
3475         svm->vmcb->save.rax = nested_vmcb->save.rax;
3476         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3477         svm->vmcb->save.rip = nested_vmcb->save.rip;
3478         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3479         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3480         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3481
3482         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3483         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3484
3485         /* cache intercepts */
3486         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3487         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3488         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3489         svm->nested.intercept            = nested_vmcb->control.intercept;
3490
3491         svm_flush_tlb(&svm->vcpu, true);
3492         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3493         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3494                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3495         else
3496                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3497
3498         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3499                 /* We only want the cr8 intercept bits of the guest */
3500                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3501                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3502         }
3503
3504         /* We don't want to see VMMCALLs from a nested guest */
3505         clr_intercept(svm, INTERCEPT_VMMCALL);
3506
3507         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3508         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3509
3510         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3511         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3512         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3513         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3514         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3515
3516         nested_svm_unmap(page);
3517
3518         /* Enter Guest-Mode */
3519         enter_guest_mode(&svm->vcpu);
3520
3521         /*
3522          * Merge guest and host intercepts - must be called  with vcpu in
3523          * guest-mode to take affect here
3524          */
3525         recalc_intercepts(svm);
3526
3527         svm->nested.vmcb = vmcb_gpa;
3528
3529         enable_gif(svm);
3530
3531         mark_all_dirty(svm->vmcb);
3532 }
3533
3534 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3535 {
3536         struct vmcb *nested_vmcb;
3537         struct vmcb *hsave = svm->nested.hsave;
3538         struct vmcb *vmcb = svm->vmcb;
3539         struct page *page;
3540         u64 vmcb_gpa;
3541
3542         vmcb_gpa = svm->vmcb->save.rax;
3543
3544         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3545         if (!nested_vmcb)
3546                 return false;
3547
3548         if (!nested_vmcb_checks(nested_vmcb)) {
3549                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3550                 nested_vmcb->control.exit_code_hi = 0;
3551                 nested_vmcb->control.exit_info_1  = 0;
3552                 nested_vmcb->control.exit_info_2  = 0;
3553
3554                 nested_svm_unmap(page);
3555
3556                 return false;
3557         }
3558
3559         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3560                                nested_vmcb->save.rip,
3561                                nested_vmcb->control.int_ctl,
3562                                nested_vmcb->control.event_inj,
3563                                nested_vmcb->control.nested_ctl);
3564
3565         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3566                                     nested_vmcb->control.intercept_cr >> 16,
3567                                     nested_vmcb->control.intercept_exceptions,
3568                                     nested_vmcb->control.intercept);
3569
3570         /* Clear internal status */
3571         kvm_clear_exception_queue(&svm->vcpu);
3572         kvm_clear_interrupt_queue(&svm->vcpu);
3573
3574         /*
3575          * Save the old vmcb, so we don't need to pick what we save, but can
3576          * restore everything when a VMEXIT occurs
3577          */
3578         hsave->save.es     = vmcb->save.es;
3579         hsave->save.cs     = vmcb->save.cs;
3580         hsave->save.ss     = vmcb->save.ss;
3581         hsave->save.ds     = vmcb->save.ds;
3582         hsave->save.gdtr   = vmcb->save.gdtr;
3583         hsave->save.idtr   = vmcb->save.idtr;
3584         hsave->save.efer   = svm->vcpu.arch.efer;
3585         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3586         hsave->save.cr4    = svm->vcpu.arch.cr4;
3587         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3588         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3589         hsave->save.rsp    = vmcb->save.rsp;
3590         hsave->save.rax    = vmcb->save.rax;
3591         if (npt_enabled)
3592                 hsave->save.cr3    = vmcb->save.cr3;
3593         else
3594                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3595
3596         copy_vmcb_control_area(hsave, vmcb);
3597
3598         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3599
3600         return true;
3601 }
3602
3603 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3604 {
3605         to_vmcb->save.fs = from_vmcb->save.fs;
3606         to_vmcb->save.gs = from_vmcb->save.gs;
3607         to_vmcb->save.tr = from_vmcb->save.tr;
3608         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3609         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3610         to_vmcb->save.star = from_vmcb->save.star;
3611         to_vmcb->save.lstar = from_vmcb->save.lstar;
3612         to_vmcb->save.cstar = from_vmcb->save.cstar;
3613         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3614         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3615         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3616         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3617 }
3618
3619 static int vmload_interception(struct vcpu_svm *svm)
3620 {
3621         struct vmcb *nested_vmcb;
3622         struct page *page;
3623         int ret;
3624
3625         if (nested_svm_check_permissions(svm))
3626                 return 1;
3627
3628         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3629         if (!nested_vmcb)
3630                 return 1;
3631
3632         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3633         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3634
3635         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3636         nested_svm_unmap(page);
3637
3638         return ret;
3639 }
3640
3641 static int vmsave_interception(struct vcpu_svm *svm)
3642 {
3643         struct vmcb *nested_vmcb;
3644         struct page *page;
3645         int ret;
3646
3647         if (nested_svm_check_permissions(svm))
3648                 return 1;
3649
3650         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3651         if (!nested_vmcb)
3652                 return 1;
3653
3654         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3655         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3656
3657         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3658         nested_svm_unmap(page);
3659
3660         return ret;
3661 }
3662
3663 static int vmrun_interception(struct vcpu_svm *svm)
3664 {
3665         if (nested_svm_check_permissions(svm))
3666                 return 1;
3667
3668         /* Save rip after vmrun instruction */
3669         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3670
3671         if (!nested_svm_vmrun(svm))
3672                 return 1;
3673
3674         if (!nested_svm_vmrun_msrpm(svm))
3675                 goto failed;
3676
3677         return 1;
3678
3679 failed:
3680
3681         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3682         svm->vmcb->control.exit_code_hi = 0;
3683         svm->vmcb->control.exit_info_1  = 0;
3684         svm->vmcb->control.exit_info_2  = 0;
3685
3686         nested_svm_vmexit(svm);
3687
3688         return 1;
3689 }
3690
3691 static int stgi_interception(struct vcpu_svm *svm)
3692 {
3693         int ret;
3694
3695         if (nested_svm_check_permissions(svm))
3696                 return 1;
3697
3698         /*
3699          * If VGIF is enabled, the STGI intercept is only added to
3700          * detect the opening of the SMI/NMI window; remove it now.
3701          */
3702         if (vgif_enabled(svm))
3703                 clr_intercept(svm, INTERCEPT_STGI);
3704
3705         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3706         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3707         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3708
3709         enable_gif(svm);
3710
3711         return ret;
3712 }
3713
3714 static int clgi_interception(struct vcpu_svm *svm)
3715 {
3716         int ret;
3717
3718         if (nested_svm_check_permissions(svm))
3719                 return 1;
3720
3721         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3722         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3723
3724         disable_gif(svm);
3725
3726         /* After a CLGI no interrupts should come */
3727         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3728                 svm_clear_vintr(svm);
3729                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3730                 mark_dirty(svm->vmcb, VMCB_INTR);
3731         }
3732
3733         return ret;
3734 }
3735
3736 static int invlpga_interception(struct vcpu_svm *svm)
3737 {
3738         struct kvm_vcpu *vcpu = &svm->vcpu;
3739
3740         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3741                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3742
3743         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3744         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3745
3746         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3747         return kvm_skip_emulated_instruction(&svm->vcpu);
3748 }
3749
3750 static int skinit_interception(struct vcpu_svm *svm)
3751 {
3752         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3753
3754         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3755         return 1;
3756 }
3757
3758 static int wbinvd_interception(struct vcpu_svm *svm)
3759 {
3760         return kvm_emulate_wbinvd(&svm->vcpu);
3761 }
3762
3763 static int xsetbv_interception(struct vcpu_svm *svm)
3764 {
3765         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3766         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3767
3768         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3769                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3770                 return kvm_skip_emulated_instruction(&svm->vcpu);
3771         }
3772
3773         return 1;
3774 }
3775
3776 static int task_switch_interception(struct vcpu_svm *svm)
3777 {
3778         u16 tss_selector;
3779         int reason;
3780         int int_type = svm->vmcb->control.exit_int_info &
3781                 SVM_EXITINTINFO_TYPE_MASK;
3782         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3783         uint32_t type =
3784                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3785         uint32_t idt_v =
3786                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3787         bool has_error_code = false;
3788         u32 error_code = 0;
3789
3790         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3791
3792         if (svm->vmcb->control.exit_info_2 &
3793             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3794                 reason = TASK_SWITCH_IRET;
3795         else if (svm->vmcb->control.exit_info_2 &
3796                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3797                 reason = TASK_SWITCH_JMP;
3798         else if (idt_v)
3799                 reason = TASK_SWITCH_GATE;
3800         else
3801                 reason = TASK_SWITCH_CALL;
3802
3803         if (reason == TASK_SWITCH_GATE) {
3804                 switch (type) {
3805                 case SVM_EXITINTINFO_TYPE_NMI:
3806                         svm->vcpu.arch.nmi_injected = false;
3807                         break;
3808                 case SVM_EXITINTINFO_TYPE_EXEPT:
3809                         if (svm->vmcb->control.exit_info_2 &
3810                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3811                                 has_error_code = true;
3812                                 error_code =
3813                                         (u32)svm->vmcb->control.exit_info_2;
3814                         }
3815                         kvm_clear_exception_queue(&svm->vcpu);
3816                         break;
3817                 case SVM_EXITINTINFO_TYPE_INTR:
3818                         kvm_clear_interrupt_queue(&svm->vcpu);
3819                         break;
3820                 default:
3821                         break;
3822                 }
3823         }
3824
3825         if (reason != TASK_SWITCH_GATE ||
3826             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3827             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3828              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3829                 skip_emulated_instruction(&svm->vcpu);
3830
3831         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3832                 int_vec = -1;
3833
3834         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3835                                 has_error_code, error_code) == EMULATE_FAIL) {
3836                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3837                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3838                 svm->vcpu.run->internal.ndata = 0;
3839                 return 0;
3840         }
3841         return 1;
3842 }
3843
3844 static int cpuid_interception(struct vcpu_svm *svm)
3845 {
3846         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3847         return kvm_emulate_cpuid(&svm->vcpu);
3848 }
3849
3850 static int iret_interception(struct vcpu_svm *svm)
3851 {
3852         ++svm->vcpu.stat.nmi_window_exits;
3853         clr_intercept(svm, INTERCEPT_IRET);
3854         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3855         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3856         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3857         return 1;
3858 }
3859
3860 static int invlpg_interception(struct vcpu_svm *svm)
3861 {
3862         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3863                 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3864
3865         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3866         return kvm_skip_emulated_instruction(&svm->vcpu);
3867 }
3868
3869 static int emulate_on_interception(struct vcpu_svm *svm)
3870 {
3871         return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3872 }
3873
3874 static int rsm_interception(struct vcpu_svm *svm)
3875 {
3876         return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3877                                         rsm_ins_bytes, 2) == EMULATE_DONE;
3878 }
3879
3880 static int rdpmc_interception(struct vcpu_svm *svm)
3881 {
3882         int err;
3883
3884         if (!static_cpu_has(X86_FEATURE_NRIPS))
3885                 return emulate_on_interception(svm);
3886
3887         err = kvm_rdpmc(&svm->vcpu);
3888         return kvm_complete_insn_gp(&svm->vcpu, err);
3889 }
3890
3891 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3892                                             unsigned long val)
3893 {
3894         unsigned long cr0 = svm->vcpu.arch.cr0;
3895         bool ret = false;
3896         u64 intercept;
3897
3898         intercept = svm->nested.intercept;
3899
3900         if (!is_guest_mode(&svm->vcpu) ||
3901             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3902                 return false;
3903
3904         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3905         val &= ~SVM_CR0_SELECTIVE_MASK;
3906
3907         if (cr0 ^ val) {
3908                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3909                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3910         }
3911
3912         return ret;
3913 }
3914
3915 #define CR_VALID (1ULL << 63)
3916
3917 static int cr_interception(struct vcpu_svm *svm)
3918 {
3919         int reg, cr;
3920         unsigned long val;
3921         int err;
3922
3923         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3924                 return emulate_on_interception(svm);
3925
3926         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3927                 return emulate_on_interception(svm);
3928
3929         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3930         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3931                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3932         else
3933                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3934
3935         err = 0;
3936         if (cr >= 16) { /* mov to cr */
3937                 cr -= 16;
3938                 val = kvm_register_read(&svm->vcpu, reg);
3939                 switch (cr) {
3940                 case 0:
3941                         if (!check_selective_cr0_intercepted(svm, val))
3942                                 err = kvm_set_cr0(&svm->vcpu, val);
3943                         else
3944                                 return 1;
3945
3946                         break;
3947                 case 3:
3948                         err = kvm_set_cr3(&svm->vcpu, val);
3949                         break;
3950                 case 4:
3951                         err = kvm_set_cr4(&svm->vcpu, val);
3952                         break;
3953                 case 8:
3954                         err = kvm_set_cr8(&svm->vcpu, val);
3955                         break;
3956                 default:
3957                         WARN(1, "unhandled write to CR%d", cr);
3958                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3959                         return 1;
3960                 }
3961         } else { /* mov from cr */
3962                 switch (cr) {
3963                 case 0:
3964                         val = kvm_read_cr0(&svm->vcpu);
3965                         break;
3966                 case 2:
3967                         val = svm->vcpu.arch.cr2;
3968                         break;
3969                 case 3:
3970                         val = kvm_read_cr3(&svm->vcpu);
3971                         break;
3972                 case 4:
3973                         val = kvm_read_cr4(&svm->vcpu);
3974                         break;
3975                 case 8:
3976                         val = kvm_get_cr8(&svm->vcpu);
3977                         break;
3978                 default:
3979                         WARN(1, "unhandled read from CR%d", cr);
3980                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3981                         return 1;
3982                 }
3983                 kvm_register_write(&svm->vcpu, reg, val);
3984         }
3985         return kvm_complete_insn_gp(&svm->vcpu, err);
3986 }
3987
3988 static int dr_interception(struct vcpu_svm *svm)
3989 {
3990         int reg, dr;
3991         unsigned long val;
3992
3993         if (svm->vcpu.guest_debug == 0) {
3994                 /*
3995                  * No more DR vmexits; force a reload of the debug registers
3996                  * and reenter on this instruction.  The next vmexit will
3997                  * retrieve the full state of the debug registers.
3998                  */
3999                 clr_dr_intercepts(svm);
4000                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4001                 return 1;
4002         }
4003
4004         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4005                 return emulate_on_interception(svm);
4006
4007         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4008         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4009
4010         if (dr >= 16) { /* mov to DRn */
4011                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4012                         return 1;
4013                 val = kvm_register_read(&svm->vcpu, reg);
4014                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4015         } else {
4016                 if (!kvm_require_dr(&svm->vcpu, dr))
4017                         return 1;
4018                 kvm_get_dr(&svm->vcpu, dr, &val);
4019                 kvm_register_write(&svm->vcpu, reg, val);
4020         }
4021
4022         return kvm_skip_emulated_instruction(&svm->vcpu);
4023 }
4024
4025 static int cr8_write_interception(struct vcpu_svm *svm)
4026 {
4027         struct kvm_run *kvm_run = svm->vcpu.run;
4028         int r;
4029
4030         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4031         /* instruction emulation calls kvm_set_cr8() */
4032         r = cr_interception(svm);
4033         if (lapic_in_kernel(&svm->vcpu))
4034                 return r;
4035         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4036                 return r;
4037         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4038         return 0;
4039 }
4040
4041 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4042 {
4043         msr->data = 0;
4044
4045         switch (msr->index) {
4046         case MSR_F10H_DECFG:
4047                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4048                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4049                 break;
4050         default:
4051                 return 1;
4052         }
4053
4054         return 0;
4055 }
4056
4057 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4058 {
4059         struct vcpu_svm *svm = to_svm(vcpu);
4060
4061         switch (msr_info->index) {
4062         case MSR_STAR:
4063                 msr_info->data = svm->vmcb->save.star;
4064                 break;
4065 #ifdef CONFIG_X86_64
4066         case MSR_LSTAR:
4067                 msr_info->data = svm->vmcb->save.lstar;
4068                 break;
4069         case MSR_CSTAR:
4070                 msr_info->data = svm->vmcb->save.cstar;
4071                 break;
4072         case MSR_KERNEL_GS_BASE:
4073                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4074                 break;
4075         case MSR_SYSCALL_MASK:
4076                 msr_info->data = svm->vmcb->save.sfmask;
4077                 break;
4078 #endif
4079         case MSR_IA32_SYSENTER_CS:
4080                 msr_info->data = svm->vmcb->save.sysenter_cs;
4081                 break;
4082         case MSR_IA32_SYSENTER_EIP:
4083                 msr_info->data = svm->sysenter_eip;
4084                 break;
4085         case MSR_IA32_SYSENTER_ESP:
4086                 msr_info->data = svm->sysenter_esp;
4087                 break;
4088         case MSR_TSC_AUX:
4089                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4090                         return 1;
4091                 msr_info->data = svm->tsc_aux;
4092                 break;
4093         /*
4094          * Nobody will change the following 5 values in the VMCB so we can
4095          * safely return them on rdmsr. They will always be 0 until LBRV is
4096          * implemented.
4097          */
4098         case MSR_IA32_DEBUGCTLMSR:
4099                 msr_info->data = svm->vmcb->save.dbgctl;
4100                 break;
4101         case MSR_IA32_LASTBRANCHFROMIP:
4102                 msr_info->data = svm->vmcb->save.br_from;
4103                 break;
4104         case MSR_IA32_LASTBRANCHTOIP:
4105                 msr_info->data = svm->vmcb->save.br_to;
4106                 break;
4107         case MSR_IA32_LASTINTFROMIP:
4108                 msr_info->data = svm->vmcb->save.last_excp_from;
4109                 break;
4110         case MSR_IA32_LASTINTTOIP:
4111                 msr_info->data = svm->vmcb->save.last_excp_to;
4112                 break;
4113         case MSR_VM_HSAVE_PA:
4114                 msr_info->data = svm->nested.hsave_msr;
4115                 break;
4116         case MSR_VM_CR:
4117                 msr_info->data = svm->nested.vm_cr_msr;
4118                 break;
4119         case MSR_IA32_SPEC_CTRL:
4120                 if (!msr_info->host_initiated &&
4121                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4122                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4123                         return 1;
4124
4125                 msr_info->data = svm->spec_ctrl;
4126                 break;
4127         case MSR_AMD64_VIRT_SPEC_CTRL:
4128                 if (!msr_info->host_initiated &&
4129                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4130                         return 1;
4131
4132                 msr_info->data = svm->virt_spec_ctrl;
4133                 break;
4134         case MSR_F15H_IC_CFG: {
4135
4136                 int family, model;
4137
4138                 family = guest_cpuid_family(vcpu);
4139                 model  = guest_cpuid_model(vcpu);
4140
4141                 if (family < 0 || model < 0)
4142                         return kvm_get_msr_common(vcpu, msr_info);
4143
4144                 msr_info->data = 0;
4145
4146                 if (family == 0x15 &&
4147                     (model >= 0x2 && model < 0x20))
4148                         msr_info->data = 0x1E;
4149                 }
4150                 break;
4151         case MSR_F10H_DECFG:
4152                 msr_info->data = svm->msr_decfg;
4153                 break;
4154         default:
4155                 return kvm_get_msr_common(vcpu, msr_info);
4156         }
4157         return 0;
4158 }
4159
4160 static int rdmsr_interception(struct vcpu_svm *svm)
4161 {
4162         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4163         struct msr_data msr_info;
4164
4165         msr_info.index = ecx;
4166         msr_info.host_initiated = false;
4167         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4168                 trace_kvm_msr_read_ex(ecx);
4169                 kvm_inject_gp(&svm->vcpu, 0);
4170                 return 1;
4171         } else {
4172                 trace_kvm_msr_read(ecx, msr_info.data);
4173
4174                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4175                                    msr_info.data & 0xffffffff);
4176                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4177                                    msr_info.data >> 32);
4178                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4179                 return kvm_skip_emulated_instruction(&svm->vcpu);
4180         }
4181 }
4182
4183 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4184 {
4185         struct vcpu_svm *svm = to_svm(vcpu);
4186         int svm_dis, chg_mask;
4187
4188         if (data & ~SVM_VM_CR_VALID_MASK)
4189                 return 1;
4190
4191         chg_mask = SVM_VM_CR_VALID_MASK;
4192
4193         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4194                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4195
4196         svm->nested.vm_cr_msr &= ~chg_mask;
4197         svm->nested.vm_cr_msr |= (data & chg_mask);
4198
4199         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4200
4201         /* check for svm_disable while efer.svme is set */
4202         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4203                 return 1;
4204
4205         return 0;
4206 }
4207
4208 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4209 {
4210         struct vcpu_svm *svm = to_svm(vcpu);
4211
4212         u32 ecx = msr->index;
4213         u64 data = msr->data;
4214         switch (ecx) {
4215         case MSR_IA32_CR_PAT:
4216                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4217                         return 1;
4218                 vcpu->arch.pat = data;
4219                 svm->vmcb->save.g_pat = data;
4220                 mark_dirty(svm->vmcb, VMCB_NPT);
4221                 break;
4222         case MSR_IA32_SPEC_CTRL:
4223                 if (!msr->host_initiated &&
4224                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4225                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4226                         return 1;
4227
4228                 /* The STIBP bit doesn't fault even if it's not advertised */
4229                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4230                         return 1;
4231
4232                 svm->spec_ctrl = data;
4233
4234                 if (!data)
4235                         break;
4236
4237                 /*
4238                  * For non-nested:
4239                  * When it's written (to non-zero) for the first time, pass
4240                  * it through.
4241                  *
4242                  * For nested:
4243                  * The handling of the MSR bitmap for L2 guests is done in
4244                  * nested_svm_vmrun_msrpm.
4245                  * We update the L1 MSR bit as well since it will end up
4246                  * touching the MSR anyway now.
4247                  */
4248                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4249                 break;
4250         case MSR_IA32_PRED_CMD:
4251                 if (!msr->host_initiated &&
4252                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4253                         return 1;
4254
4255                 if (data & ~PRED_CMD_IBPB)
4256                         return 1;
4257
4258                 if (!data)
4259                         break;
4260
4261                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4262                 if (is_guest_mode(vcpu))
4263                         break;
4264                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4265                 break;
4266         case MSR_AMD64_VIRT_SPEC_CTRL:
4267                 if (!msr->host_initiated &&
4268                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4269                         return 1;
4270
4271                 if (data & ~SPEC_CTRL_SSBD)
4272                         return 1;
4273
4274                 svm->virt_spec_ctrl = data;
4275                 break;
4276         case MSR_STAR:
4277                 svm->vmcb->save.star = data;
4278                 break;
4279 #ifdef CONFIG_X86_64
4280         case MSR_LSTAR:
4281                 svm->vmcb->save.lstar = data;
4282                 break;
4283         case MSR_CSTAR:
4284                 svm->vmcb->save.cstar = data;
4285                 break;
4286         case MSR_KERNEL_GS_BASE:
4287                 svm->vmcb->save.kernel_gs_base = data;
4288                 break;
4289         case MSR_SYSCALL_MASK:
4290                 svm->vmcb->save.sfmask = data;
4291                 break;
4292 #endif
4293         case MSR_IA32_SYSENTER_CS:
4294                 svm->vmcb->save.sysenter_cs = data;
4295                 break;
4296         case MSR_IA32_SYSENTER_EIP:
4297                 svm->sysenter_eip = data;
4298                 svm->vmcb->save.sysenter_eip = data;
4299                 break;
4300         case MSR_IA32_SYSENTER_ESP:
4301                 svm->sysenter_esp = data;
4302                 svm->vmcb->save.sysenter_esp = data;
4303                 break;
4304         case MSR_TSC_AUX:
4305                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4306                         return 1;
4307
4308                 /*
4309                  * This is rare, so we update the MSR here instead of using
4310                  * direct_access_msrs.  Doing that would require a rdmsr in
4311                  * svm_vcpu_put.
4312                  */
4313                 svm->tsc_aux = data;
4314                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4315                 break;
4316         case MSR_IA32_DEBUGCTLMSR:
4317                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4318                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4319                                     __func__, data);
4320                         break;
4321                 }
4322                 if (data & DEBUGCTL_RESERVED_BITS)
4323                         return 1;
4324
4325                 svm->vmcb->save.dbgctl = data;
4326                 mark_dirty(svm->vmcb, VMCB_LBR);
4327                 if (data & (1ULL<<0))
4328                         svm_enable_lbrv(svm);
4329                 else
4330                         svm_disable_lbrv(svm);
4331                 break;
4332         case MSR_VM_HSAVE_PA:
4333                 svm->nested.hsave_msr = data;
4334                 break;
4335         case MSR_VM_CR:
4336                 return svm_set_vm_cr(vcpu, data);
4337         case MSR_VM_IGNNE:
4338                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4339                 break;
4340         case MSR_F10H_DECFG: {
4341                 struct kvm_msr_entry msr_entry;
4342
4343                 msr_entry.index = msr->index;
4344                 if (svm_get_msr_feature(&msr_entry))
4345                         return 1;
4346
4347                 /* Check the supported bits */
4348                 if (data & ~msr_entry.data)
4349                         return 1;
4350
4351                 /* Don't allow the guest to change a bit, #GP */
4352                 if (!msr->host_initiated && (data ^ msr_entry.data))
4353                         return 1;
4354
4355                 svm->msr_decfg = data;
4356                 break;
4357         }
4358         case MSR_IA32_APICBASE:
4359                 if (kvm_vcpu_apicv_active(vcpu))
4360                         avic_update_vapic_bar(to_svm(vcpu), data);
4361                 /* Follow through */
4362         default:
4363                 return kvm_set_msr_common(vcpu, msr);
4364         }
4365         return 0;
4366 }
4367
4368 static int wrmsr_interception(struct vcpu_svm *svm)
4369 {
4370         struct msr_data msr;
4371         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4372         u64 data = kvm_read_edx_eax(&svm->vcpu);
4373
4374         msr.data = data;
4375         msr.index = ecx;
4376         msr.host_initiated = false;
4377
4378         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4379         if (kvm_set_msr(&svm->vcpu, &msr)) {
4380                 trace_kvm_msr_write_ex(ecx, data);
4381                 kvm_inject_gp(&svm->vcpu, 0);
4382                 return 1;
4383         } else {
4384                 trace_kvm_msr_write(ecx, data);
4385                 return kvm_skip_emulated_instruction(&svm->vcpu);
4386         }
4387 }
4388
4389 static int msr_interception(struct vcpu_svm *svm)
4390 {
4391         if (svm->vmcb->control.exit_info_1)
4392                 return wrmsr_interception(svm);
4393         else
4394                 return rdmsr_interception(svm);
4395 }
4396
4397 static int interrupt_window_interception(struct vcpu_svm *svm)
4398 {
4399         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4400         svm_clear_vintr(svm);
4401         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4402         mark_dirty(svm->vmcb, VMCB_INTR);
4403         ++svm->vcpu.stat.irq_window_exits;
4404         return 1;
4405 }
4406
4407 static int pause_interception(struct vcpu_svm *svm)
4408 {
4409         struct kvm_vcpu *vcpu = &svm->vcpu;
4410         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4411
4412         if (pause_filter_thresh)
4413                 grow_ple_window(vcpu);
4414
4415         kvm_vcpu_on_spin(vcpu, in_kernel);
4416         return 1;
4417 }
4418
4419 static int nop_interception(struct vcpu_svm *svm)
4420 {
4421         return kvm_skip_emulated_instruction(&(svm->vcpu));
4422 }
4423
4424 static int monitor_interception(struct vcpu_svm *svm)
4425 {
4426         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4427         return nop_interception(svm);
4428 }
4429
4430 static int mwait_interception(struct vcpu_svm *svm)
4431 {
4432         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4433         return nop_interception(svm);
4434 }
4435
4436 enum avic_ipi_failure_cause {
4437         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4438         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4439         AVIC_IPI_FAILURE_INVALID_TARGET,
4440         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4441 };
4442
4443 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4444 {
4445         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4446         u32 icrl = svm->vmcb->control.exit_info_1;
4447         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4448         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4449         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4450
4451         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4452
4453         switch (id) {
4454         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4455                 /*
4456                  * AVIC hardware handles the generation of
4457                  * IPIs when the specified Message Type is Fixed
4458                  * (also known as fixed delivery mode) and
4459                  * the Trigger Mode is edge-triggered. The hardware
4460                  * also supports self and broadcast delivery modes
4461                  * specified via the Destination Shorthand(DSH)
4462                  * field of the ICRL. Logical and physical APIC ID
4463                  * formats are supported. All other IPI types cause
4464                  * a #VMEXIT, which needs to emulated.
4465                  */
4466                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4467                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4468                 break;
4469         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4470                 int i;
4471                 struct kvm_vcpu *vcpu;
4472                 struct kvm *kvm = svm->vcpu.kvm;
4473                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4474
4475                 /*
4476                  * At this point, we expect that the AVIC HW has already
4477                  * set the appropriate IRR bits on the valid target
4478                  * vcpus. So, we just need to kick the appropriate vcpu.
4479                  */
4480                 kvm_for_each_vcpu(i, vcpu, kvm) {
4481                         bool m = kvm_apic_match_dest(vcpu, apic,
4482                                                      icrl & KVM_APIC_SHORT_MASK,
4483                                                      GET_APIC_DEST_FIELD(icrh),
4484                                                      icrl & KVM_APIC_DEST_MASK);
4485
4486                         if (m && !avic_vcpu_is_running(vcpu))
4487                                 kvm_vcpu_wake_up(vcpu);
4488                 }
4489                 break;
4490         }
4491         case AVIC_IPI_FAILURE_INVALID_TARGET:
4492                 break;
4493         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4494                 WARN_ONCE(1, "Invalid backing page\n");
4495                 break;
4496         default:
4497                 pr_err("Unknown IPI interception\n");
4498         }
4499
4500         return 1;
4501 }
4502
4503 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4504 {
4505         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4506         int index;
4507         u32 *logical_apic_id_table;
4508         int dlid = GET_APIC_LOGICAL_ID(ldr);
4509
4510         if (!dlid)
4511                 return NULL;
4512
4513         if (flat) { /* flat */
4514                 index = ffs(dlid) - 1;
4515                 if (index > 7)
4516                         return NULL;
4517         } else { /* cluster */
4518                 int cluster = (dlid & 0xf0) >> 4;
4519                 int apic = ffs(dlid & 0x0f) - 1;
4520
4521                 if ((apic < 0) || (apic > 7) ||
4522                     (cluster >= 0xf))
4523                         return NULL;
4524                 index = (cluster << 2) + apic;
4525         }
4526
4527         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4528
4529         return &logical_apic_id_table[index];
4530 }
4531
4532 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4533                           bool valid)
4534 {
4535         bool flat;
4536         u32 *entry, new_entry;
4537
4538         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4539         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4540         if (!entry)
4541                 return -EINVAL;
4542
4543         new_entry = READ_ONCE(*entry);
4544         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4545         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4546         if (valid)
4547                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4548         else
4549                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4550         WRITE_ONCE(*entry, new_entry);
4551
4552         return 0;
4553 }
4554
4555 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4556 {
4557         int ret;
4558         struct vcpu_svm *svm = to_svm(vcpu);
4559         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4560
4561         if (!ldr)
4562                 return 1;
4563
4564         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4565         if (ret && svm->ldr_reg) {
4566                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4567                 svm->ldr_reg = 0;
4568         } else {
4569                 svm->ldr_reg = ldr;
4570         }
4571         return ret;
4572 }
4573
4574 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4575 {
4576         u64 *old, *new;
4577         struct vcpu_svm *svm = to_svm(vcpu);
4578         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4579         u32 id = (apic_id_reg >> 24) & 0xff;
4580
4581         if (vcpu->vcpu_id == id)
4582                 return 0;
4583
4584         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4585         new = avic_get_physical_id_entry(vcpu, id);
4586         if (!new || !old)
4587                 return 1;
4588
4589         /* We need to move physical_id_entry to new offset */
4590         *new = *old;
4591         *old = 0ULL;
4592         to_svm(vcpu)->avic_physical_id_cache = new;
4593
4594         /*
4595          * Also update the guest physical APIC ID in the logical
4596          * APIC ID table entry if already setup the LDR.
4597          */
4598         if (svm->ldr_reg)
4599                 avic_handle_ldr_update(vcpu);
4600
4601         return 0;
4602 }
4603
4604 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4605 {
4606         struct vcpu_svm *svm = to_svm(vcpu);
4607         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4608         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4609         u32 mod = (dfr >> 28) & 0xf;
4610
4611         /*
4612          * We assume that all local APICs are using the same type.
4613          * If this changes, we need to flush the AVIC logical
4614          * APID id table.
4615          */
4616         if (kvm_svm->ldr_mode == mod)
4617                 return 0;
4618
4619         clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4620         kvm_svm->ldr_mode = mod;
4621
4622         if (svm->ldr_reg)
4623                 avic_handle_ldr_update(vcpu);
4624         return 0;
4625 }
4626
4627 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4628 {
4629         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4630         u32 offset = svm->vmcb->control.exit_info_1 &
4631                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4632
4633         switch (offset) {
4634         case APIC_ID:
4635                 if (avic_handle_apic_id_update(&svm->vcpu))
4636                         return 0;
4637                 break;
4638         case APIC_LDR:
4639                 if (avic_handle_ldr_update(&svm->vcpu))
4640                         return 0;
4641                 break;
4642         case APIC_DFR:
4643                 avic_handle_dfr_update(&svm->vcpu);
4644                 break;
4645         default:
4646                 break;
4647         }
4648
4649         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4650
4651         return 1;
4652 }
4653
4654 static bool is_avic_unaccelerated_access_trap(u32 offset)
4655 {
4656         bool ret = false;
4657
4658         switch (offset) {
4659         case APIC_ID:
4660         case APIC_EOI:
4661         case APIC_RRR:
4662         case APIC_LDR:
4663         case APIC_DFR:
4664         case APIC_SPIV:
4665         case APIC_ESR:
4666         case APIC_ICR:
4667         case APIC_LVTT:
4668         case APIC_LVTTHMR:
4669         case APIC_LVTPC:
4670         case APIC_LVT0:
4671         case APIC_LVT1:
4672         case APIC_LVTERR:
4673         case APIC_TMICT:
4674         case APIC_TDCR:
4675                 ret = true;
4676                 break;
4677         default:
4678                 break;
4679         }
4680         return ret;
4681 }
4682
4683 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4684 {
4685         int ret = 0;
4686         u32 offset = svm->vmcb->control.exit_info_1 &
4687                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4688         u32 vector = svm->vmcb->control.exit_info_2 &
4689                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4690         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4691                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4692         bool trap = is_avic_unaccelerated_access_trap(offset);
4693
4694         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4695                                             trap, write, vector);
4696         if (trap) {
4697                 /* Handling Trap */
4698                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4699                 ret = avic_unaccel_trap_write(svm);
4700         } else {
4701                 /* Handling Fault */
4702                 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4703         }
4704
4705         return ret;
4706 }
4707
4708 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4709         [SVM_EXIT_READ_CR0]                     = cr_interception,
4710         [SVM_EXIT_READ_CR3]                     = cr_interception,
4711         [SVM_EXIT_READ_CR4]                     = cr_interception,
4712         [SVM_EXIT_READ_CR8]                     = cr_interception,
4713         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4714         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4715         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4716         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4717         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4718         [SVM_EXIT_READ_DR0]                     = dr_interception,
4719         [SVM_EXIT_READ_DR1]                     = dr_interception,
4720         [SVM_EXIT_READ_DR2]                     = dr_interception,
4721         [SVM_EXIT_READ_DR3]                     = dr_interception,
4722         [SVM_EXIT_READ_DR4]                     = dr_interception,
4723         [SVM_EXIT_READ_DR5]                     = dr_interception,
4724         [SVM_EXIT_READ_DR6]                     = dr_interception,
4725         [SVM_EXIT_READ_DR7]                     = dr_interception,
4726         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4727         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4728         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4729         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4730         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4731         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4732         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4733         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4734         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4735         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4736         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4737         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4738         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4739         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4740         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4741         [SVM_EXIT_INTR]                         = intr_interception,
4742         [SVM_EXIT_NMI]                          = nmi_interception,
4743         [SVM_EXIT_SMI]                          = nop_on_interception,
4744         [SVM_EXIT_INIT]                         = nop_on_interception,
4745         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4746         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4747         [SVM_EXIT_CPUID]                        = cpuid_interception,
4748         [SVM_EXIT_IRET]                         = iret_interception,
4749         [SVM_EXIT_INVD]                         = emulate_on_interception,
4750         [SVM_EXIT_PAUSE]                        = pause_interception,
4751         [SVM_EXIT_HLT]                          = halt_interception,
4752         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4753         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4754         [SVM_EXIT_IOIO]                         = io_interception,
4755         [SVM_EXIT_MSR]                          = msr_interception,
4756         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4757         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4758         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4759         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4760         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4761         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4762         [SVM_EXIT_STGI]                         = stgi_interception,
4763         [SVM_EXIT_CLGI]                         = clgi_interception,
4764         [SVM_EXIT_SKINIT]                       = skinit_interception,
4765         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4766         [SVM_EXIT_MONITOR]                      = monitor_interception,
4767         [SVM_EXIT_MWAIT]                        = mwait_interception,
4768         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4769         [SVM_EXIT_NPF]                          = npf_interception,
4770         [SVM_EXIT_RSM]                          = rsm_interception,
4771         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4772         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4773 };
4774
4775 static void dump_vmcb(struct kvm_vcpu *vcpu)
4776 {
4777         struct vcpu_svm *svm = to_svm(vcpu);
4778         struct vmcb_control_area *control = &svm->vmcb->control;
4779         struct vmcb_save_area *save = &svm->vmcb->save;
4780
4781         pr_err("VMCB Control Area:\n");
4782         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4783         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4784         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4785         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4786         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4787         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4788         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4789         pr_err("%-20s%d\n", "pause filter threshold:",
4790                control->pause_filter_thresh);
4791         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4792         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4793         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4794         pr_err("%-20s%d\n", "asid:", control->asid);
4795         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4796         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4797         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4798         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4799         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4800         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4801         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4802         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4803         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4804         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4805         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4806         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4807         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4808         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4809         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4810         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4811         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4812         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4813         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4814         pr_err("VMCB State Save Area:\n");
4815         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4816                "es:",
4817                save->es.selector, save->es.attrib,
4818                save->es.limit, save->es.base);
4819         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4820                "cs:",
4821                save->cs.selector, save->cs.attrib,
4822                save->cs.limit, save->cs.base);
4823         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4824                "ss:",
4825                save->ss.selector, save->ss.attrib,
4826                save->ss.limit, save->ss.base);
4827         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4828                "ds:",
4829                save->ds.selector, save->ds.attrib,
4830                save->ds.limit, save->ds.base);
4831         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4832                "fs:",
4833                save->fs.selector, save->fs.attrib,
4834                save->fs.limit, save->fs.base);
4835         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4836                "gs:",
4837                save->gs.selector, save->gs.attrib,
4838                save->gs.limit, save->gs.base);
4839         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4840                "gdtr:",
4841                save->gdtr.selector, save->gdtr.attrib,
4842                save->gdtr.limit, save->gdtr.base);
4843         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4844                "ldtr:",
4845                save->ldtr.selector, save->ldtr.attrib,
4846                save->ldtr.limit, save->ldtr.base);
4847         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4848                "idtr:",
4849                save->idtr.selector, save->idtr.attrib,
4850                save->idtr.limit, save->idtr.base);
4851         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4852                "tr:",
4853                save->tr.selector, save->tr.attrib,
4854                save->tr.limit, save->tr.base);
4855         pr_err("cpl:            %d                efer:         %016llx\n",
4856                 save->cpl, save->efer);
4857         pr_err("%-15s %016llx %-13s %016llx\n",
4858                "cr0:", save->cr0, "cr2:", save->cr2);
4859         pr_err("%-15s %016llx %-13s %016llx\n",
4860                "cr3:", save->cr3, "cr4:", save->cr4);
4861         pr_err("%-15s %016llx %-13s %016llx\n",
4862                "dr6:", save->dr6, "dr7:", save->dr7);
4863         pr_err("%-15s %016llx %-13s %016llx\n",
4864                "rip:", save->rip, "rflags:", save->rflags);
4865         pr_err("%-15s %016llx %-13s %016llx\n",
4866                "rsp:", save->rsp, "rax:", save->rax);
4867         pr_err("%-15s %016llx %-13s %016llx\n",
4868                "star:", save->star, "lstar:", save->lstar);
4869         pr_err("%-15s %016llx %-13s %016llx\n",
4870                "cstar:", save->cstar, "sfmask:", save->sfmask);
4871         pr_err("%-15s %016llx %-13s %016llx\n",
4872                "kernel_gs_base:", save->kernel_gs_base,
4873                "sysenter_cs:", save->sysenter_cs);
4874         pr_err("%-15s %016llx %-13s %016llx\n",
4875                "sysenter_esp:", save->sysenter_esp,
4876                "sysenter_eip:", save->sysenter_eip);
4877         pr_err("%-15s %016llx %-13s %016llx\n",
4878                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4879         pr_err("%-15s %016llx %-13s %016llx\n",
4880                "br_from:", save->br_from, "br_to:", save->br_to);
4881         pr_err("%-15s %016llx %-13s %016llx\n",
4882                "excp_from:", save->last_excp_from,
4883                "excp_to:", save->last_excp_to);
4884 }
4885
4886 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4887 {
4888         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4889
4890         *info1 = control->exit_info_1;
4891         *info2 = control->exit_info_2;
4892 }
4893
4894 static int handle_exit(struct kvm_vcpu *vcpu)
4895 {
4896         struct vcpu_svm *svm = to_svm(vcpu);
4897         struct kvm_run *kvm_run = vcpu->run;
4898         u32 exit_code = svm->vmcb->control.exit_code;
4899
4900         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4901
4902         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4903                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4904         if (npt_enabled)
4905                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4906
4907         if (unlikely(svm->nested.exit_required)) {
4908                 nested_svm_vmexit(svm);
4909                 svm->nested.exit_required = false;
4910
4911                 return 1;
4912         }
4913
4914         if (is_guest_mode(vcpu)) {
4915                 int vmexit;
4916
4917                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4918                                         svm->vmcb->control.exit_info_1,
4919                                         svm->vmcb->control.exit_info_2,
4920                                         svm->vmcb->control.exit_int_info,
4921                                         svm->vmcb->control.exit_int_info_err,
4922                                         KVM_ISA_SVM);
4923
4924                 vmexit = nested_svm_exit_special(svm);
4925
4926                 if (vmexit == NESTED_EXIT_CONTINUE)
4927                         vmexit = nested_svm_exit_handled(svm);
4928
4929                 if (vmexit == NESTED_EXIT_DONE)
4930                         return 1;
4931         }
4932
4933         svm_complete_interrupts(svm);
4934
4935         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4936                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4937                 kvm_run->fail_entry.hardware_entry_failure_reason
4938                         = svm->vmcb->control.exit_code;
4939                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4940                 dump_vmcb(vcpu);
4941                 return 0;
4942         }
4943
4944         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4945             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4946             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4947             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4948                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4949                        "exit_code 0x%x\n",
4950                        __func__, svm->vmcb->control.exit_int_info,
4951                        exit_code);
4952
4953         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4954             || !svm_exit_handlers[exit_code]) {
4955                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4956                 kvm_queue_exception(vcpu, UD_VECTOR);
4957                 return 1;
4958         }
4959
4960         return svm_exit_handlers[exit_code](svm);
4961 }
4962
4963 static void reload_tss(struct kvm_vcpu *vcpu)
4964 {
4965         int cpu = raw_smp_processor_id();
4966
4967         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4968         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4969         load_TR_desc();
4970 }
4971
4972 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4973 {
4974         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4975         int asid = sev_get_asid(svm->vcpu.kvm);
4976
4977         /* Assign the asid allocated with this SEV guest */
4978         svm->vmcb->control.asid = asid;
4979
4980         /*
4981          * Flush guest TLB:
4982          *
4983          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4984          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4985          */
4986         if (sd->sev_vmcbs[asid] == svm->vmcb &&
4987             svm->last_cpu == cpu)
4988                 return;
4989
4990         svm->last_cpu = cpu;
4991         sd->sev_vmcbs[asid] = svm->vmcb;
4992         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4993         mark_dirty(svm->vmcb, VMCB_ASID);
4994 }
4995
4996 static void pre_svm_run(struct vcpu_svm *svm)
4997 {
4998         int cpu = raw_smp_processor_id();
4999
5000         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5001
5002         if (sev_guest(svm->vcpu.kvm))
5003                 return pre_sev_run(svm, cpu);
5004
5005         /* FIXME: handle wraparound of asid_generation */
5006         if (svm->asid_generation != sd->asid_generation)
5007                 new_asid(svm, sd);
5008 }
5009
5010 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5011 {
5012         struct vcpu_svm *svm = to_svm(vcpu);
5013
5014         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5015         vcpu->arch.hflags |= HF_NMI_MASK;
5016         set_intercept(svm, INTERCEPT_IRET);
5017         ++vcpu->stat.nmi_injections;
5018 }
5019
5020 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5021 {
5022         struct vmcb_control_area *control;
5023
5024         /* The following fields are ignored when AVIC is enabled */
5025         control = &svm->vmcb->control;
5026         control->int_vector = irq;
5027         control->int_ctl &= ~V_INTR_PRIO_MASK;
5028         control->int_ctl |= V_IRQ_MASK |
5029                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5030         mark_dirty(svm->vmcb, VMCB_INTR);
5031 }
5032
5033 static void svm_set_irq(struct kvm_vcpu *vcpu)
5034 {
5035         struct vcpu_svm *svm = to_svm(vcpu);
5036
5037         BUG_ON(!(gif_set(svm)));
5038
5039         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5040         ++vcpu->stat.irq_injections;
5041
5042         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5043                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5044 }
5045
5046 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5047 {
5048         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5049 }
5050
5051 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5052 {
5053         struct vcpu_svm *svm = to_svm(vcpu);
5054
5055         if (svm_nested_virtualize_tpr(vcpu) ||
5056             kvm_vcpu_apicv_active(vcpu))
5057                 return;
5058
5059         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5060
5061         if (irr == -1)
5062                 return;
5063
5064         if (tpr >= irr)
5065                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5066 }
5067
5068 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5069 {
5070         return;
5071 }
5072
5073 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5074 {
5075         return avic && irqchip_split(vcpu->kvm);
5076 }
5077
5078 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5079 {
5080 }
5081
5082 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5083 {
5084 }
5085
5086 /* Note: Currently only used by Hyper-V. */
5087 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5088 {
5089         struct vcpu_svm *svm = to_svm(vcpu);
5090         struct vmcb *vmcb = svm->vmcb;
5091
5092         if (!kvm_vcpu_apicv_active(&svm->vcpu))
5093                 return;
5094
5095         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5096         mark_dirty(vmcb, VMCB_INTR);
5097 }
5098
5099 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5100 {
5101         return;
5102 }
5103
5104 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5105 {
5106         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5107         smp_mb__after_atomic();
5108
5109         if (avic_vcpu_is_running(vcpu))
5110                 wrmsrl(SVM_AVIC_DOORBELL,
5111                        kvm_cpu_get_apicid(vcpu->cpu));
5112         else
5113                 kvm_vcpu_wake_up(vcpu);
5114 }
5115
5116 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5117 {
5118         unsigned long flags;
5119         struct amd_svm_iommu_ir *cur;
5120
5121         spin_lock_irqsave(&svm->ir_list_lock, flags);
5122         list_for_each_entry(cur, &svm->ir_list, node) {
5123                 if (cur->data != pi->ir_data)
5124                         continue;
5125                 list_del(&cur->node);
5126                 kfree(cur);
5127                 break;
5128         }
5129         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5130 }
5131
5132 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5133 {
5134         int ret = 0;
5135         unsigned long flags;
5136         struct amd_svm_iommu_ir *ir;
5137
5138         /**
5139          * In some cases, the existing irte is updaed and re-set,
5140          * so we need to check here if it's already been * added
5141          * to the ir_list.
5142          */
5143         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5144                 struct kvm *kvm = svm->vcpu.kvm;
5145                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5146                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5147                 struct vcpu_svm *prev_svm;
5148
5149                 if (!prev_vcpu) {
5150                         ret = -EINVAL;
5151                         goto out;
5152                 }
5153
5154                 prev_svm = to_svm(prev_vcpu);
5155                 svm_ir_list_del(prev_svm, pi);
5156         }
5157
5158         /**
5159          * Allocating new amd_iommu_pi_data, which will get
5160          * add to the per-vcpu ir_list.
5161          */
5162         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5163         if (!ir) {
5164                 ret = -ENOMEM;
5165                 goto out;
5166         }
5167         ir->data = pi->ir_data;
5168
5169         spin_lock_irqsave(&svm->ir_list_lock, flags);
5170         list_add(&ir->node, &svm->ir_list);
5171         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5172 out:
5173         return ret;
5174 }
5175
5176 /**
5177  * Note:
5178  * The HW cannot support posting multicast/broadcast
5179  * interrupts to a vCPU. So, we still use legacy interrupt
5180  * remapping for these kind of interrupts.
5181  *
5182  * For lowest-priority interrupts, we only support
5183  * those with single CPU as the destination, e.g. user
5184  * configures the interrupts via /proc/irq or uses
5185  * irqbalance to make the interrupts single-CPU.
5186  */
5187 static int
5188 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5189                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5190 {
5191         struct kvm_lapic_irq irq;
5192         struct kvm_vcpu *vcpu = NULL;
5193
5194         kvm_set_msi_irq(kvm, e, &irq);
5195
5196         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5197                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5198                          __func__, irq.vector);
5199                 return -1;
5200         }
5201
5202         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5203                  irq.vector);
5204         *svm = to_svm(vcpu);
5205         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5206         vcpu_info->vector = irq.vector;
5207
5208         return 0;
5209 }
5210
5211 /*
5212  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5213  *
5214  * @kvm: kvm
5215  * @host_irq: host irq of the interrupt
5216  * @guest_irq: gsi of the interrupt
5217  * @set: set or unset PI
5218  * returns 0 on success, < 0 on failure
5219  */
5220 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5221                               uint32_t guest_irq, bool set)
5222 {
5223         struct kvm_kernel_irq_routing_entry *e;
5224         struct kvm_irq_routing_table *irq_rt;
5225         int idx, ret = -EINVAL;
5226
5227         if (!kvm_arch_has_assigned_device(kvm) ||
5228             !irq_remapping_cap(IRQ_POSTING_CAP))
5229                 return 0;
5230
5231         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5232                  __func__, host_irq, guest_irq, set);
5233
5234         idx = srcu_read_lock(&kvm->irq_srcu);
5235         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5236         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5237
5238         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5239                 struct vcpu_data vcpu_info;
5240                 struct vcpu_svm *svm = NULL;
5241
5242                 if (e->type != KVM_IRQ_ROUTING_MSI)
5243                         continue;
5244
5245                 /**
5246                  * Here, we setup with legacy mode in the following cases:
5247                  * 1. When cannot target interrupt to a specific vcpu.
5248                  * 2. Unsetting posted interrupt.
5249                  * 3. APIC virtialization is disabled for the vcpu.
5250                  */
5251                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5252                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5253                         struct amd_iommu_pi_data pi;
5254
5255                         /* Try to enable guest_mode in IRTE */
5256                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5257                                             AVIC_HPA_MASK);
5258                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5259                                                      svm->vcpu.vcpu_id);
5260                         pi.is_guest_mode = true;
5261                         pi.vcpu_data = &vcpu_info;
5262                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5263
5264                         /**
5265                          * Here, we successfully setting up vcpu affinity in
5266                          * IOMMU guest mode. Now, we need to store the posted
5267                          * interrupt information in a per-vcpu ir_list so that
5268                          * we can reference to them directly when we update vcpu
5269                          * scheduling information in IOMMU irte.
5270                          */
5271                         if (!ret && pi.is_guest_mode)
5272                                 svm_ir_list_add(svm, &pi);
5273                 } else {
5274                         /* Use legacy mode in IRTE */
5275                         struct amd_iommu_pi_data pi;
5276
5277                         /**
5278                          * Here, pi is used to:
5279                          * - Tell IOMMU to use legacy mode for this interrupt.
5280                          * - Retrieve ga_tag of prior interrupt remapping data.
5281                          */
5282                         pi.is_guest_mode = false;
5283                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5284
5285                         /**
5286                          * Check if the posted interrupt was previously
5287                          * setup with the guest_mode by checking if the ga_tag
5288                          * was cached. If so, we need to clean up the per-vcpu
5289                          * ir_list.
5290                          */
5291                         if (!ret && pi.prev_ga_tag) {
5292                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5293                                 struct kvm_vcpu *vcpu;
5294
5295                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5296                                 if (vcpu)
5297                                         svm_ir_list_del(to_svm(vcpu), &pi);
5298                         }
5299                 }
5300
5301                 if (!ret && svm) {
5302                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5303                                                  e->gsi, vcpu_info.vector,
5304                                                  vcpu_info.pi_desc_addr, set);
5305                 }
5306
5307                 if (ret < 0) {
5308                         pr_err("%s: failed to update PI IRTE\n", __func__);
5309                         goto out;
5310                 }
5311         }
5312
5313         ret = 0;
5314 out:
5315         srcu_read_unlock(&kvm->irq_srcu, idx);
5316         return ret;
5317 }
5318
5319 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5320 {
5321         struct vcpu_svm *svm = to_svm(vcpu);
5322         struct vmcb *vmcb = svm->vmcb;
5323         int ret;
5324         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5325               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5326         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5327
5328         return ret;
5329 }
5330
5331 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5332 {
5333         struct vcpu_svm *svm = to_svm(vcpu);
5334
5335         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5336 }
5337
5338 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5339 {
5340         struct vcpu_svm *svm = to_svm(vcpu);
5341
5342         if (masked) {
5343                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5344                 set_intercept(svm, INTERCEPT_IRET);
5345         } else {
5346                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5347                 clr_intercept(svm, INTERCEPT_IRET);
5348         }
5349 }
5350
5351 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5352 {
5353         struct vcpu_svm *svm = to_svm(vcpu);
5354         struct vmcb *vmcb = svm->vmcb;
5355         int ret;
5356
5357         if (!gif_set(svm) ||
5358              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5359                 return 0;
5360
5361         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5362
5363         if (is_guest_mode(vcpu))
5364                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5365
5366         return ret;
5367 }
5368
5369 static void enable_irq_window(struct kvm_vcpu *vcpu)
5370 {
5371         struct vcpu_svm *svm = to_svm(vcpu);
5372
5373         if (kvm_vcpu_apicv_active(vcpu))
5374                 return;
5375
5376         /*
5377          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5378          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5379          * get that intercept, this function will be called again though and
5380          * we'll get the vintr intercept. However, if the vGIF feature is
5381          * enabled, the STGI interception will not occur. Enable the irq
5382          * window under the assumption that the hardware will set the GIF.
5383          */
5384         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5385                 svm_set_vintr(svm);
5386                 svm_inject_irq(svm, 0x0);
5387         }
5388 }
5389
5390 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5391 {
5392         struct vcpu_svm *svm = to_svm(vcpu);
5393
5394         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5395             == HF_NMI_MASK)
5396                 return; /* IRET will cause a vm exit */
5397
5398         if (!gif_set(svm)) {
5399                 if (vgif_enabled(svm))
5400                         set_intercept(svm, INTERCEPT_STGI);
5401                 return; /* STGI will cause a vm exit */
5402         }
5403
5404         if (svm->nested.exit_required)
5405                 return; /* we're not going to run the guest yet */
5406
5407         /*
5408          * Something prevents NMI from been injected. Single step over possible
5409          * problem (IRET or exception injection or interrupt shadow)
5410          */
5411         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5412         svm->nmi_singlestep = true;
5413         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5414 }
5415
5416 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5417 {
5418         return 0;
5419 }
5420
5421 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5422 {
5423         return 0;
5424 }
5425
5426 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5427 {
5428         struct vcpu_svm *svm = to_svm(vcpu);
5429
5430         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5431                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5432         else
5433                 svm->asid_generation--;
5434 }
5435
5436 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5437 {
5438         struct vcpu_svm *svm = to_svm(vcpu);
5439
5440         invlpga(gva, svm->vmcb->control.asid);
5441 }
5442
5443 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5444 {
5445 }
5446
5447 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5448 {
5449         struct vcpu_svm *svm = to_svm(vcpu);
5450
5451         if (svm_nested_virtualize_tpr(vcpu))
5452                 return;
5453
5454         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5455                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5456                 kvm_set_cr8(vcpu, cr8);
5457         }
5458 }
5459
5460 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5461 {
5462         struct vcpu_svm *svm = to_svm(vcpu);
5463         u64 cr8;
5464
5465         if (svm_nested_virtualize_tpr(vcpu) ||
5466             kvm_vcpu_apicv_active(vcpu))
5467                 return;
5468
5469         cr8 = kvm_get_cr8(vcpu);
5470         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5471         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5472 }
5473
5474 static void svm_complete_interrupts(struct vcpu_svm *svm)
5475 {
5476         u8 vector;
5477         int type;
5478         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5479         unsigned int3_injected = svm->int3_injected;
5480
5481         svm->int3_injected = 0;
5482
5483         /*
5484          * If we've made progress since setting HF_IRET_MASK, we've
5485          * executed an IRET and can allow NMI injection.
5486          */
5487         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5488             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5489                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5490                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5491         }
5492
5493         svm->vcpu.arch.nmi_injected = false;
5494         kvm_clear_exception_queue(&svm->vcpu);
5495         kvm_clear_interrupt_queue(&svm->vcpu);
5496
5497         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5498                 return;
5499
5500         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5501
5502         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5503         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5504
5505         switch (type) {
5506         case SVM_EXITINTINFO_TYPE_NMI:
5507                 svm->vcpu.arch.nmi_injected = true;
5508                 break;
5509         case SVM_EXITINTINFO_TYPE_EXEPT:
5510                 /*
5511                  * In case of software exceptions, do not reinject the vector,
5512                  * but re-execute the instruction instead. Rewind RIP first
5513                  * if we emulated INT3 before.
5514                  */
5515                 if (kvm_exception_is_soft(vector)) {
5516                         if (vector == BP_VECTOR && int3_injected &&
5517                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5518                                 kvm_rip_write(&svm->vcpu,
5519                                               kvm_rip_read(&svm->vcpu) -
5520                                               int3_injected);
5521                         break;
5522                 }
5523                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5524                         u32 err = svm->vmcb->control.exit_int_info_err;
5525                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5526
5527                 } else
5528                         kvm_requeue_exception(&svm->vcpu, vector);
5529                 break;
5530         case SVM_EXITINTINFO_TYPE_INTR:
5531                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5532                 break;
5533         default:
5534                 break;
5535         }
5536 }
5537
5538 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5539 {
5540         struct vcpu_svm *svm = to_svm(vcpu);
5541         struct vmcb_control_area *control = &svm->vmcb->control;
5542
5543         control->exit_int_info = control->event_inj;
5544         control->exit_int_info_err = control->event_inj_err;
5545         control->event_inj = 0;
5546         svm_complete_interrupts(svm);
5547 }
5548
5549 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5550 {
5551         struct vcpu_svm *svm = to_svm(vcpu);
5552
5553         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5554         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5555         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5556
5557         /*
5558          * A vmexit emulation is required before the vcpu can be executed
5559          * again.
5560          */
5561         if (unlikely(svm->nested.exit_required))
5562                 return;
5563
5564         /*
5565          * Disable singlestep if we're injecting an interrupt/exception.
5566          * We don't want our modified rflags to be pushed on the stack where
5567          * we might not be able to easily reset them if we disabled NMI
5568          * singlestep later.
5569          */
5570         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5571                 /*
5572                  * Event injection happens before external interrupts cause a
5573                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5574                  * is enough to force an immediate vmexit.
5575                  */
5576                 disable_nmi_singlestep(svm);
5577                 smp_send_reschedule(vcpu->cpu);
5578         }
5579
5580         pre_svm_run(svm);
5581
5582         sync_lapic_to_cr8(vcpu);
5583
5584         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5585
5586         clgi();
5587
5588         /*
5589          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5590          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5591          * is no need to worry about the conditional branch over the wrmsr
5592          * being speculatively taken.
5593          */
5594         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5595
5596         local_irq_enable();
5597
5598         asm volatile (
5599                 "push %%" _ASM_BP "; \n\t"
5600                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5601                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5602                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5603                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5604                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5605                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5606 #ifdef CONFIG_X86_64
5607                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5608                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5609                 "mov %c[r10](%[svm]), %%r10 \n\t"
5610                 "mov %c[r11](%[svm]), %%r11 \n\t"
5611                 "mov %c[r12](%[svm]), %%r12 \n\t"
5612                 "mov %c[r13](%[svm]), %%r13 \n\t"
5613                 "mov %c[r14](%[svm]), %%r14 \n\t"
5614                 "mov %c[r15](%[svm]), %%r15 \n\t"
5615 #endif
5616
5617                 /* Enter guest mode */
5618                 "push %%" _ASM_AX " \n\t"
5619                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5620                 __ex(SVM_VMLOAD) "\n\t"
5621                 __ex(SVM_VMRUN) "\n\t"
5622                 __ex(SVM_VMSAVE) "\n\t"
5623                 "pop %%" _ASM_AX " \n\t"
5624
5625                 /* Save guest registers, load host registers */
5626                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5627                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5628                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5629                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5630                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5631                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5632 #ifdef CONFIG_X86_64
5633                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5634                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5635                 "mov %%r10, %c[r10](%[svm]) \n\t"
5636                 "mov %%r11, %c[r11](%[svm]) \n\t"
5637                 "mov %%r12, %c[r12](%[svm]) \n\t"
5638                 "mov %%r13, %c[r13](%[svm]) \n\t"
5639                 "mov %%r14, %c[r14](%[svm]) \n\t"
5640                 "mov %%r15, %c[r15](%[svm]) \n\t"
5641 #endif
5642                 /*
5643                 * Clear host registers marked as clobbered to prevent
5644                 * speculative use.
5645                 */
5646                 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
5647                 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
5648                 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
5649                 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
5650                 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
5651 #ifdef CONFIG_X86_64
5652                 "xor %%r8, %%r8 \n\t"
5653                 "xor %%r9, %%r9 \n\t"
5654                 "xor %%r10, %%r10 \n\t"
5655                 "xor %%r11, %%r11 \n\t"
5656                 "xor %%r12, %%r12 \n\t"
5657                 "xor %%r13, %%r13 \n\t"
5658                 "xor %%r14, %%r14 \n\t"
5659                 "xor %%r15, %%r15 \n\t"
5660 #endif
5661                 "pop %%" _ASM_BP
5662                 :
5663                 : [svm]"a"(svm),
5664                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5665                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5666                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5667                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5668                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5669                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5670                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5671 #ifdef CONFIG_X86_64
5672                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5673                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5674                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5675                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5676                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5677                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5678                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5679                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5680 #endif
5681                 : "cc", "memory"
5682 #ifdef CONFIG_X86_64
5683                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5684                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5685 #else
5686                 , "ebx", "ecx", "edx", "esi", "edi"
5687 #endif
5688                 );
5689
5690         /* Eliminate branch target predictions from guest mode */
5691         vmexit_fill_RSB();
5692
5693 #ifdef CONFIG_X86_64
5694         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5695 #else
5696         loadsegment(fs, svm->host.fs);
5697 #ifndef CONFIG_X86_32_LAZY_GS
5698         loadsegment(gs, svm->host.gs);
5699 #endif
5700 #endif
5701
5702         /*
5703          * We do not use IBRS in the kernel. If this vCPU has used the
5704          * SPEC_CTRL MSR it may have left it on; save the value and
5705          * turn it off. This is much more efficient than blindly adding
5706          * it to the atomic save/restore list. Especially as the former
5707          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5708          *
5709          * For non-nested case:
5710          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5711          * save it.
5712          *
5713          * For nested case:
5714          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5715          * save it.
5716          */
5717         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5718                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5719
5720         reload_tss(vcpu);
5721
5722         local_irq_disable();
5723
5724         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5725
5726         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5727         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5728         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5729         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5730
5731         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5732                 kvm_before_interrupt(&svm->vcpu);
5733
5734         stgi();
5735
5736         /* Any pending NMI will happen here */
5737
5738         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5739                 kvm_after_interrupt(&svm->vcpu);
5740
5741         sync_cr8_to_lapic(vcpu);
5742
5743         svm->next_rip = 0;
5744
5745         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5746
5747         /* if exit due to PF check for async PF */
5748         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5749                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5750
5751         if (npt_enabled) {
5752                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5753                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5754         }
5755
5756         /*
5757          * We need to handle MC intercepts here before the vcpu has a chance to
5758          * change the physical cpu
5759          */
5760         if (unlikely(svm->vmcb->control.exit_code ==
5761                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5762                 svm_handle_mce(svm);
5763
5764         mark_all_clean(svm->vmcb);
5765 }
5766 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5767
5768 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5769 {
5770         struct vcpu_svm *svm = to_svm(vcpu);
5771
5772         svm->vmcb->save.cr3 = __sme_set(root);
5773         mark_dirty(svm->vmcb, VMCB_CR);
5774 }
5775
5776 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5777 {
5778         struct vcpu_svm *svm = to_svm(vcpu);
5779
5780         svm->vmcb->control.nested_cr3 = __sme_set(root);
5781         mark_dirty(svm->vmcb, VMCB_NPT);
5782
5783         /* Also sync guest cr3 here in case we live migrate */
5784         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5785         mark_dirty(svm->vmcb, VMCB_CR);
5786 }
5787
5788 static int is_disabled(void)
5789 {
5790         u64 vm_cr;
5791
5792         rdmsrl(MSR_VM_CR, vm_cr);
5793         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5794                 return 1;
5795
5796         return 0;
5797 }
5798
5799 static void
5800 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5801 {
5802         /*
5803          * Patch in the VMMCALL instruction:
5804          */
5805         hypercall[0] = 0x0f;
5806         hypercall[1] = 0x01;
5807         hypercall[2] = 0xd9;
5808 }
5809
5810 static void svm_check_processor_compat(void *rtn)
5811 {
5812         *(int *)rtn = 0;
5813 }
5814
5815 static bool svm_cpu_has_accelerated_tpr(void)
5816 {
5817         return false;
5818 }
5819
5820 static bool svm_has_emulated_msr(int index)
5821 {
5822         return true;
5823 }
5824
5825 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5826 {
5827         return 0;
5828 }
5829
5830 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5831 {
5832         struct vcpu_svm *svm = to_svm(vcpu);
5833
5834         /* Update nrips enabled cache */
5835         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5836
5837         if (!kvm_vcpu_apicv_active(vcpu))
5838                 return;
5839
5840         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5841 }
5842
5843 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5844 {
5845         switch (func) {
5846         case 0x1:
5847                 if (avic)
5848                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5849                 break;
5850         case 0x80000001:
5851                 if (nested)
5852                         entry->ecx |= (1 << 2); /* Set SVM bit */
5853                 break;
5854         case 0x8000000A:
5855                 entry->eax = 1; /* SVM revision 1 */
5856                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5857                                    ASID emulation to nested SVM */
5858                 entry->ecx = 0; /* Reserved */
5859                 entry->edx = 0; /* Per default do not support any
5860                                    additional features */
5861
5862                 /* Support next_rip if host supports it */
5863                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5864                         entry->edx |= SVM_FEATURE_NRIP;
5865
5866                 /* Support NPT for the guest if enabled */
5867                 if (npt_enabled)
5868                         entry->edx |= SVM_FEATURE_NPT;
5869
5870                 break;
5871         case 0x8000001F:
5872                 /* Support memory encryption cpuid if host supports it */
5873                 if (boot_cpu_has(X86_FEATURE_SEV))
5874                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5875                                 &entry->ecx, &entry->edx);
5876
5877         }
5878 }
5879
5880 static int svm_get_lpage_level(void)
5881 {
5882         return PT_PDPE_LEVEL;
5883 }
5884
5885 static bool svm_rdtscp_supported(void)
5886 {
5887         return boot_cpu_has(X86_FEATURE_RDTSCP);
5888 }
5889
5890 static bool svm_invpcid_supported(void)
5891 {
5892         return false;
5893 }
5894
5895 static bool svm_mpx_supported(void)
5896 {
5897         return false;
5898 }
5899
5900 static bool svm_xsaves_supported(void)
5901 {
5902         return false;
5903 }
5904
5905 static bool svm_umip_emulated(void)
5906 {
5907         return false;
5908 }
5909
5910 static bool svm_has_wbinvd_exit(void)
5911 {
5912         return true;
5913 }
5914
5915 #define PRE_EX(exit)  { .exit_code = (exit), \
5916                         .stage = X86_ICPT_PRE_EXCEPT, }
5917 #define POST_EX(exit) { .exit_code = (exit), \
5918                         .stage = X86_ICPT_POST_EXCEPT, }
5919 #define POST_MEM(exit) { .exit_code = (exit), \
5920                         .stage = X86_ICPT_POST_MEMACCESS, }
5921
5922 static const struct __x86_intercept {
5923         u32 exit_code;
5924         enum x86_intercept_stage stage;
5925 } x86_intercept_map[] = {
5926         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5927         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5928         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5929         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5930         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5931         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5932         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5933         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5934         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5935         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5936         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5937         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5938         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5939         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5940         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5941         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5942         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5943         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5944         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5945         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5946         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5947         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5948         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5949         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5950         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5951         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5952         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5953         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5954         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5955         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5956         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5957         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5958         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5959         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5960         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5961         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5962         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5963         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5964         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5965         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5966         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5967         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5968         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5969         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5970         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5971         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5972 };
5973
5974 #undef PRE_EX
5975 #undef POST_EX
5976 #undef POST_MEM
5977
5978 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5979                                struct x86_instruction_info *info,
5980                                enum x86_intercept_stage stage)
5981 {
5982         struct vcpu_svm *svm = to_svm(vcpu);
5983         int vmexit, ret = X86EMUL_CONTINUE;
5984         struct __x86_intercept icpt_info;
5985         struct vmcb *vmcb = svm->vmcb;
5986
5987         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5988                 goto out;
5989
5990         icpt_info = x86_intercept_map[info->intercept];
5991
5992         if (stage != icpt_info.stage)
5993                 goto out;
5994
5995         switch (icpt_info.exit_code) {
5996         case SVM_EXIT_READ_CR0:
5997                 if (info->intercept == x86_intercept_cr_read)
5998                         icpt_info.exit_code += info->modrm_reg;
5999                 break;
6000         case SVM_EXIT_WRITE_CR0: {
6001                 unsigned long cr0, val;
6002                 u64 intercept;
6003
6004                 if (info->intercept == x86_intercept_cr_write)
6005                         icpt_info.exit_code += info->modrm_reg;
6006
6007                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6008                     info->intercept == x86_intercept_clts)
6009                         break;
6010
6011                 intercept = svm->nested.intercept;
6012
6013                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6014                         break;
6015
6016                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6017                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6018
6019                 if (info->intercept == x86_intercept_lmsw) {
6020                         cr0 &= 0xfUL;
6021                         val &= 0xfUL;
6022                         /* lmsw can't clear PE - catch this here */
6023                         if (cr0 & X86_CR0_PE)
6024                                 val |= X86_CR0_PE;
6025                 }
6026
6027                 if (cr0 ^ val)
6028                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6029
6030                 break;
6031         }
6032         case SVM_EXIT_READ_DR0:
6033         case SVM_EXIT_WRITE_DR0:
6034                 icpt_info.exit_code += info->modrm_reg;
6035                 break;
6036         case SVM_EXIT_MSR:
6037                 if (info->intercept == x86_intercept_wrmsr)
6038                         vmcb->control.exit_info_1 = 1;
6039                 else
6040                         vmcb->control.exit_info_1 = 0;
6041                 break;
6042         case SVM_EXIT_PAUSE:
6043                 /*
6044                  * We get this for NOP only, but pause
6045                  * is rep not, check this here
6046                  */
6047                 if (info->rep_prefix != REPE_PREFIX)
6048                         goto out;
6049                 break;
6050         case SVM_EXIT_IOIO: {
6051                 u64 exit_info;
6052                 u32 bytes;
6053
6054                 if (info->intercept == x86_intercept_in ||
6055                     info->intercept == x86_intercept_ins) {
6056                         exit_info = ((info->src_val & 0xffff) << 16) |
6057                                 SVM_IOIO_TYPE_MASK;
6058                         bytes = info->dst_bytes;
6059                 } else {
6060                         exit_info = (info->dst_val & 0xffff) << 16;
6061                         bytes = info->src_bytes;
6062                 }
6063
6064                 if (info->intercept == x86_intercept_outs ||
6065                     info->intercept == x86_intercept_ins)
6066                         exit_info |= SVM_IOIO_STR_MASK;
6067
6068                 if (info->rep_prefix)
6069                         exit_info |= SVM_IOIO_REP_MASK;
6070
6071                 bytes = min(bytes, 4u);
6072
6073                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6074
6075                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6076
6077                 vmcb->control.exit_info_1 = exit_info;
6078                 vmcb->control.exit_info_2 = info->next_rip;
6079
6080                 break;
6081         }
6082         default:
6083                 break;
6084         }
6085
6086         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6087         if (static_cpu_has(X86_FEATURE_NRIPS))
6088                 vmcb->control.next_rip  = info->next_rip;
6089         vmcb->control.exit_code = icpt_info.exit_code;
6090         vmexit = nested_svm_exit_handled(svm);
6091
6092         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6093                                            : X86EMUL_CONTINUE;
6094
6095 out:
6096         return ret;
6097 }
6098
6099 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6100 {
6101         local_irq_enable();
6102         /*
6103          * We must have an instruction with interrupts enabled, so
6104          * the timer interrupt isn't delayed by the interrupt shadow.
6105          */
6106         asm("nop");
6107         local_irq_disable();
6108 }
6109
6110 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6111 {
6112         if (pause_filter_thresh)
6113                 shrink_ple_window(vcpu);
6114 }
6115
6116 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6117 {
6118         if (avic_handle_apic_id_update(vcpu) != 0)
6119                 return;
6120         if (avic_handle_dfr_update(vcpu) != 0)
6121                 return;
6122         avic_handle_ldr_update(vcpu);
6123 }
6124
6125 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6126 {
6127         /* [63:9] are reserved. */
6128         vcpu->arch.mcg_cap &= 0x1ff;
6129 }
6130
6131 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6132 {
6133         struct vcpu_svm *svm = to_svm(vcpu);
6134
6135         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6136         if (!gif_set(svm))
6137                 return 0;
6138
6139         if (is_guest_mode(&svm->vcpu) &&
6140             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6141                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6142                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6143                 svm->nested.exit_required = true;
6144                 return 0;
6145         }
6146
6147         return 1;
6148 }
6149
6150 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6151 {
6152         struct vcpu_svm *svm = to_svm(vcpu);
6153         int ret;
6154
6155         if (is_guest_mode(vcpu)) {
6156                 /* FED8h - SVM Guest */
6157                 put_smstate(u64, smstate, 0x7ed8, 1);
6158                 /* FEE0h - SVM Guest VMCB Physical Address */
6159                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6160
6161                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6162                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6163                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6164
6165                 ret = nested_svm_vmexit(svm);
6166                 if (ret)
6167                         return ret;
6168         }
6169         return 0;
6170 }
6171
6172 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6173 {
6174         struct vcpu_svm *svm = to_svm(vcpu);
6175         struct vmcb *nested_vmcb;
6176         struct page *page;
6177         struct {
6178                 u64 guest;
6179                 u64 vmcb;
6180         } svm_state_save;
6181         int ret;
6182
6183         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6184                                   sizeof(svm_state_save));
6185         if (ret)
6186                 return ret;
6187
6188         if (svm_state_save.guest) {
6189                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6190                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6191                 if (nested_vmcb)
6192                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6193                 else
6194                         ret = 1;
6195                 vcpu->arch.hflags |= HF_SMM_MASK;
6196         }
6197         return ret;
6198 }
6199
6200 static int enable_smi_window(struct kvm_vcpu *vcpu)
6201 {
6202         struct vcpu_svm *svm = to_svm(vcpu);
6203
6204         if (!gif_set(svm)) {
6205                 if (vgif_enabled(svm))
6206                         set_intercept(svm, INTERCEPT_STGI);
6207                 /* STGI will cause a vm exit */
6208                 return 1;
6209         }
6210         return 0;
6211 }
6212
6213 static int sev_asid_new(void)
6214 {
6215         int pos;
6216
6217         /*
6218          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6219          */
6220         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6221         if (pos >= max_sev_asid)
6222                 return -EBUSY;
6223
6224         set_bit(pos, sev_asid_bitmap);
6225         return pos + 1;
6226 }
6227
6228 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6229 {
6230         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6231         int asid, ret;
6232
6233         ret = -EBUSY;
6234         asid = sev_asid_new();
6235         if (asid < 0)
6236                 return ret;
6237
6238         ret = sev_platform_init(&argp->error);
6239         if (ret)
6240                 goto e_free;
6241
6242         sev->active = true;
6243         sev->asid = asid;
6244         INIT_LIST_HEAD(&sev->regions_list);
6245
6246         return 0;
6247
6248 e_free:
6249         __sev_asid_free(asid);
6250         return ret;
6251 }
6252
6253 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6254 {
6255         struct sev_data_activate *data;
6256         int asid = sev_get_asid(kvm);
6257         int ret;
6258
6259         wbinvd_on_all_cpus();
6260
6261         ret = sev_guest_df_flush(error);
6262         if (ret)
6263                 return ret;
6264
6265         data = kzalloc(sizeof(*data), GFP_KERNEL);
6266         if (!data)
6267                 return -ENOMEM;
6268
6269         /* activate ASID on the given handle */
6270         data->handle = handle;
6271         data->asid   = asid;
6272         ret = sev_guest_activate(data, error);
6273         kfree(data);
6274
6275         return ret;
6276 }
6277
6278 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6279 {
6280         struct fd f;
6281         int ret;
6282
6283         f = fdget(fd);
6284         if (!f.file)
6285                 return -EBADF;
6286
6287         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6288
6289         fdput(f);
6290         return ret;
6291 }
6292
6293 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6294 {
6295         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6296
6297         return __sev_issue_cmd(sev->fd, id, data, error);
6298 }
6299
6300 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6301 {
6302         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6303         struct sev_data_launch_start *start;
6304         struct kvm_sev_launch_start params;
6305         void *dh_blob, *session_blob;
6306         int *error = &argp->error;
6307         int ret;
6308
6309         if (!sev_guest(kvm))
6310                 return -ENOTTY;
6311
6312         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6313                 return -EFAULT;
6314
6315         start = kzalloc(sizeof(*start), GFP_KERNEL);
6316         if (!start)
6317                 return -ENOMEM;
6318
6319         dh_blob = NULL;
6320         if (params.dh_uaddr) {
6321                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6322                 if (IS_ERR(dh_blob)) {
6323                         ret = PTR_ERR(dh_blob);
6324                         goto e_free;
6325                 }
6326
6327                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6328                 start->dh_cert_len = params.dh_len;
6329         }
6330
6331         session_blob = NULL;
6332         if (params.session_uaddr) {
6333                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6334                 if (IS_ERR(session_blob)) {
6335                         ret = PTR_ERR(session_blob);
6336                         goto e_free_dh;
6337                 }
6338
6339                 start->session_address = __sme_set(__pa(session_blob));
6340                 start->session_len = params.session_len;
6341         }
6342
6343         start->handle = params.handle;
6344         start->policy = params.policy;
6345
6346         /* create memory encryption context */
6347         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6348         if (ret)
6349                 goto e_free_session;
6350
6351         /* Bind ASID to this guest */
6352         ret = sev_bind_asid(kvm, start->handle, error);
6353         if (ret)
6354                 goto e_free_session;
6355
6356         /* return handle to userspace */
6357         params.handle = start->handle;
6358         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6359                 sev_unbind_asid(kvm, start->handle);
6360                 ret = -EFAULT;
6361                 goto e_free_session;
6362         }
6363
6364         sev->handle = start->handle;
6365         sev->fd = argp->sev_fd;
6366
6367 e_free_session:
6368         kfree(session_blob);
6369 e_free_dh:
6370         kfree(dh_blob);
6371 e_free:
6372         kfree(start);
6373         return ret;
6374 }
6375
6376 static int get_num_contig_pages(int idx, struct page **inpages,
6377                                 unsigned long npages)
6378 {
6379         unsigned long paddr, next_paddr;
6380         int i = idx + 1, pages = 1;
6381
6382         /* find the number of contiguous pages starting from idx */
6383         paddr = __sme_page_pa(inpages[idx]);
6384         while (i < npages) {
6385                 next_paddr = __sme_page_pa(inpages[i++]);
6386                 if ((paddr + PAGE_SIZE) == next_paddr) {
6387                         pages++;
6388                         paddr = next_paddr;
6389                         continue;
6390                 }
6391                 break;
6392         }
6393
6394         return pages;
6395 }
6396
6397 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6398 {
6399         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6400         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6401         struct kvm_sev_launch_update_data params;
6402         struct sev_data_launch_update_data *data;
6403         struct page **inpages;
6404         int i, ret, pages;
6405
6406         if (!sev_guest(kvm))
6407                 return -ENOTTY;
6408
6409         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6410                 return -EFAULT;
6411
6412         data = kzalloc(sizeof(*data), GFP_KERNEL);
6413         if (!data)
6414                 return -ENOMEM;
6415
6416         vaddr = params.uaddr;
6417         size = params.len;
6418         vaddr_end = vaddr + size;
6419
6420         /* Lock the user memory. */
6421         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6422         if (!inpages) {
6423                 ret = -ENOMEM;
6424                 goto e_free;
6425         }
6426
6427         /*
6428          * The LAUNCH_UPDATE command will perform in-place encryption of the
6429          * memory content (i.e it will write the same memory region with C=1).
6430          * It's possible that the cache may contain the data with C=0, i.e.,
6431          * unencrypted so invalidate it first.
6432          */
6433         sev_clflush_pages(inpages, npages);
6434
6435         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6436                 int offset, len;
6437
6438                 /*
6439                  * If the user buffer is not page-aligned, calculate the offset
6440                  * within the page.
6441                  */
6442                 offset = vaddr & (PAGE_SIZE - 1);
6443
6444                 /* Calculate the number of pages that can be encrypted in one go. */
6445                 pages = get_num_contig_pages(i, inpages, npages);
6446
6447                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6448
6449                 data->handle = sev->handle;
6450                 data->len = len;
6451                 data->address = __sme_page_pa(inpages[i]) + offset;
6452                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6453                 if (ret)
6454                         goto e_unpin;
6455
6456                 size -= len;
6457                 next_vaddr = vaddr + len;
6458         }
6459
6460 e_unpin:
6461         /* content of memory is updated, mark pages dirty */
6462         for (i = 0; i < npages; i++) {
6463                 set_page_dirty_lock(inpages[i]);
6464                 mark_page_accessed(inpages[i]);
6465         }
6466         /* unlock the user pages */
6467         sev_unpin_memory(kvm, inpages, npages);
6468 e_free:
6469         kfree(data);
6470         return ret;
6471 }
6472
6473 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6474 {
6475         void __user *measure = (void __user *)(uintptr_t)argp->data;
6476         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6477         struct sev_data_launch_measure *data;
6478         struct kvm_sev_launch_measure params;
6479         void __user *p = NULL;
6480         void *blob = NULL;
6481         int ret;
6482
6483         if (!sev_guest(kvm))
6484                 return -ENOTTY;
6485
6486         if (copy_from_user(&params, measure, sizeof(params)))
6487                 return -EFAULT;
6488
6489         data = kzalloc(sizeof(*data), GFP_KERNEL);
6490         if (!data)
6491                 return -ENOMEM;
6492
6493         /* User wants to query the blob length */
6494         if (!params.len)
6495                 goto cmd;
6496
6497         p = (void __user *)(uintptr_t)params.uaddr;
6498         if (p) {
6499                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6500                         ret = -EINVAL;
6501                         goto e_free;
6502                 }
6503
6504                 ret = -ENOMEM;
6505                 blob = kmalloc(params.len, GFP_KERNEL);
6506                 if (!blob)
6507                         goto e_free;
6508
6509                 data->address = __psp_pa(blob);
6510                 data->len = params.len;
6511         }
6512
6513 cmd:
6514         data->handle = sev->handle;
6515         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6516
6517         /*
6518          * If we query the session length, FW responded with expected data.
6519          */
6520         if (!params.len)
6521                 goto done;
6522
6523         if (ret)
6524                 goto e_free_blob;
6525
6526         if (blob) {
6527                 if (copy_to_user(p, blob, params.len))
6528                         ret = -EFAULT;
6529         }
6530
6531 done:
6532         params.len = data->len;
6533         if (copy_to_user(measure, &params, sizeof(params)))
6534                 ret = -EFAULT;
6535 e_free_blob:
6536         kfree(blob);
6537 e_free:
6538         kfree(data);
6539         return ret;
6540 }
6541
6542 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6543 {
6544         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6545         struct sev_data_launch_finish *data;
6546         int ret;
6547
6548         if (!sev_guest(kvm))
6549                 return -ENOTTY;
6550
6551         data = kzalloc(sizeof(*data), GFP_KERNEL);
6552         if (!data)
6553                 return -ENOMEM;
6554
6555         data->handle = sev->handle;
6556         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6557
6558         kfree(data);
6559         return ret;
6560 }
6561
6562 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6563 {
6564         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6565         struct kvm_sev_guest_status params;
6566         struct sev_data_guest_status *data;
6567         int ret;
6568
6569         if (!sev_guest(kvm))
6570                 return -ENOTTY;
6571
6572         data = kzalloc(sizeof(*data), GFP_KERNEL);
6573         if (!data)
6574                 return -ENOMEM;
6575
6576         data->handle = sev->handle;
6577         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6578         if (ret)
6579                 goto e_free;
6580
6581         params.policy = data->policy;
6582         params.state = data->state;
6583         params.handle = data->handle;
6584
6585         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6586                 ret = -EFAULT;
6587 e_free:
6588         kfree(data);
6589         return ret;
6590 }
6591
6592 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6593                                unsigned long dst, int size,
6594                                int *error, bool enc)
6595 {
6596         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6597         struct sev_data_dbg *data;
6598         int ret;
6599
6600         data = kzalloc(sizeof(*data), GFP_KERNEL);
6601         if (!data)
6602                 return -ENOMEM;
6603
6604         data->handle = sev->handle;
6605         data->dst_addr = dst;
6606         data->src_addr = src;
6607         data->len = size;
6608
6609         ret = sev_issue_cmd(kvm,
6610                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6611                             data, error);
6612         kfree(data);
6613         return ret;
6614 }
6615
6616 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6617                              unsigned long dst_paddr, int sz, int *err)
6618 {
6619         int offset;
6620
6621         /*
6622          * Its safe to read more than we are asked, caller should ensure that
6623          * destination has enough space.
6624          */
6625         src_paddr = round_down(src_paddr, 16);
6626         offset = src_paddr & 15;
6627         sz = round_up(sz + offset, 16);
6628
6629         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6630 }
6631
6632 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6633                                   unsigned long __user dst_uaddr,
6634                                   unsigned long dst_paddr,
6635                                   int size, int *err)
6636 {
6637         struct page *tpage = NULL;
6638         int ret, offset;
6639
6640         /* if inputs are not 16-byte then use intermediate buffer */
6641         if (!IS_ALIGNED(dst_paddr, 16) ||
6642             !IS_ALIGNED(paddr,     16) ||
6643             !IS_ALIGNED(size,      16)) {
6644                 tpage = (void *)alloc_page(GFP_KERNEL);
6645                 if (!tpage)
6646                         return -ENOMEM;
6647
6648                 dst_paddr = __sme_page_pa(tpage);
6649         }
6650
6651         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6652         if (ret)
6653                 goto e_free;
6654
6655         if (tpage) {
6656                 offset = paddr & 15;
6657                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6658                                  page_address(tpage) + offset, size))
6659                         ret = -EFAULT;
6660         }
6661
6662 e_free:
6663         if (tpage)
6664                 __free_page(tpage);
6665
6666         return ret;
6667 }
6668
6669 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6670                                   unsigned long __user vaddr,
6671                                   unsigned long dst_paddr,
6672                                   unsigned long __user dst_vaddr,
6673                                   int size, int *error)
6674 {
6675         struct page *src_tpage = NULL;
6676         struct page *dst_tpage = NULL;
6677         int ret, len = size;
6678
6679         /* If source buffer is not aligned then use an intermediate buffer */
6680         if (!IS_ALIGNED(vaddr, 16)) {
6681                 src_tpage = alloc_page(GFP_KERNEL);
6682                 if (!src_tpage)
6683                         return -ENOMEM;
6684
6685                 if (copy_from_user(page_address(src_tpage),
6686                                 (void __user *)(uintptr_t)vaddr, size)) {
6687                         __free_page(src_tpage);
6688                         return -EFAULT;
6689                 }
6690
6691                 paddr = __sme_page_pa(src_tpage);
6692         }
6693
6694         /*
6695          *  If destination buffer or length is not aligned then do read-modify-write:
6696          *   - decrypt destination in an intermediate buffer
6697          *   - copy the source buffer in an intermediate buffer
6698          *   - use the intermediate buffer as source buffer
6699          */
6700         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6701                 int dst_offset;
6702
6703                 dst_tpage = alloc_page(GFP_KERNEL);
6704                 if (!dst_tpage) {
6705                         ret = -ENOMEM;
6706                         goto e_free;
6707                 }
6708
6709                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6710                                         __sme_page_pa(dst_tpage), size, error);
6711                 if (ret)
6712                         goto e_free;
6713
6714                 /*
6715                  *  If source is kernel buffer then use memcpy() otherwise
6716                  *  copy_from_user().
6717                  */
6718                 dst_offset = dst_paddr & 15;
6719
6720                 if (src_tpage)
6721                         memcpy(page_address(dst_tpage) + dst_offset,
6722                                page_address(src_tpage), size);
6723                 else {
6724                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6725                                            (void __user *)(uintptr_t)vaddr, size)) {
6726                                 ret = -EFAULT;
6727                                 goto e_free;
6728                         }
6729                 }
6730
6731                 paddr = __sme_page_pa(dst_tpage);
6732                 dst_paddr = round_down(dst_paddr, 16);
6733                 len = round_up(size, 16);
6734         }
6735
6736         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6737
6738 e_free:
6739         if (src_tpage)
6740                 __free_page(src_tpage);
6741         if (dst_tpage)
6742                 __free_page(dst_tpage);
6743         return ret;
6744 }
6745
6746 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6747 {
6748         unsigned long vaddr, vaddr_end, next_vaddr;
6749         unsigned long dst_vaddr;
6750         struct page **src_p, **dst_p;
6751         struct kvm_sev_dbg debug;
6752         unsigned long n;
6753         int ret, size;
6754
6755         if (!sev_guest(kvm))
6756                 return -ENOTTY;
6757
6758         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6759                 return -EFAULT;
6760
6761         vaddr = debug.src_uaddr;
6762         size = debug.len;
6763         vaddr_end = vaddr + size;
6764         dst_vaddr = debug.dst_uaddr;
6765
6766         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6767                 int len, s_off, d_off;
6768
6769                 /* lock userspace source and destination page */
6770                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6771                 if (!src_p)
6772                         return -EFAULT;
6773
6774                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6775                 if (!dst_p) {
6776                         sev_unpin_memory(kvm, src_p, n);
6777                         return -EFAULT;
6778                 }
6779
6780                 /*
6781                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6782                  * memory content (i.e it will write the same memory region with C=1).
6783                  * It's possible that the cache may contain the data with C=0, i.e.,
6784                  * unencrypted so invalidate it first.
6785                  */
6786                 sev_clflush_pages(src_p, 1);
6787                 sev_clflush_pages(dst_p, 1);
6788
6789                 /*
6790                  * Since user buffer may not be page aligned, calculate the
6791                  * offset within the page.
6792                  */
6793                 s_off = vaddr & ~PAGE_MASK;
6794                 d_off = dst_vaddr & ~PAGE_MASK;
6795                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6796
6797                 if (dec)
6798                         ret = __sev_dbg_decrypt_user(kvm,
6799                                                      __sme_page_pa(src_p[0]) + s_off,
6800                                                      dst_vaddr,
6801                                                      __sme_page_pa(dst_p[0]) + d_off,
6802                                                      len, &argp->error);
6803                 else
6804                         ret = __sev_dbg_encrypt_user(kvm,
6805                                                      __sme_page_pa(src_p[0]) + s_off,
6806                                                      vaddr,
6807                                                      __sme_page_pa(dst_p[0]) + d_off,
6808                                                      dst_vaddr,
6809                                                      len, &argp->error);
6810
6811                 sev_unpin_memory(kvm, src_p, 1);
6812                 sev_unpin_memory(kvm, dst_p, 1);
6813
6814                 if (ret)
6815                         goto err;
6816
6817                 next_vaddr = vaddr + len;
6818                 dst_vaddr = dst_vaddr + len;
6819                 size -= len;
6820         }
6821 err:
6822         return ret;
6823 }
6824
6825 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6826 {
6827         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6828         struct sev_data_launch_secret *data;
6829         struct kvm_sev_launch_secret params;
6830         struct page **pages;
6831         void *blob, *hdr;
6832         unsigned long n;
6833         int ret, offset;
6834
6835         if (!sev_guest(kvm))
6836                 return -ENOTTY;
6837
6838         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6839                 return -EFAULT;
6840
6841         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6842         if (!pages)
6843                 return -ENOMEM;
6844
6845         /*
6846          * The secret must be copied into contiguous memory region, lets verify
6847          * that userspace memory pages are contiguous before we issue command.
6848          */
6849         if (get_num_contig_pages(0, pages, n) != n) {
6850                 ret = -EINVAL;
6851                 goto e_unpin_memory;
6852         }
6853
6854         ret = -ENOMEM;
6855         data = kzalloc(sizeof(*data), GFP_KERNEL);
6856         if (!data)
6857                 goto e_unpin_memory;
6858
6859         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6860         data->guest_address = __sme_page_pa(pages[0]) + offset;
6861         data->guest_len = params.guest_len;
6862
6863         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6864         if (IS_ERR(blob)) {
6865                 ret = PTR_ERR(blob);
6866                 goto e_free;
6867         }
6868
6869         data->trans_address = __psp_pa(blob);
6870         data->trans_len = params.trans_len;
6871
6872         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6873         if (IS_ERR(hdr)) {
6874                 ret = PTR_ERR(hdr);
6875                 goto e_free_blob;
6876         }
6877         data->hdr_address = __psp_pa(hdr);
6878         data->hdr_len = params.hdr_len;
6879
6880         data->handle = sev->handle;
6881         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6882
6883         kfree(hdr);
6884
6885 e_free_blob:
6886         kfree(blob);
6887 e_free:
6888         kfree(data);
6889 e_unpin_memory:
6890         sev_unpin_memory(kvm, pages, n);
6891         return ret;
6892 }
6893
6894 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6895 {
6896         struct kvm_sev_cmd sev_cmd;
6897         int r;
6898
6899         if (!svm_sev_enabled())
6900                 return -ENOTTY;
6901
6902         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6903                 return -EFAULT;
6904
6905         mutex_lock(&kvm->lock);
6906
6907         switch (sev_cmd.id) {
6908         case KVM_SEV_INIT:
6909                 r = sev_guest_init(kvm, &sev_cmd);
6910                 break;
6911         case KVM_SEV_LAUNCH_START:
6912                 r = sev_launch_start(kvm, &sev_cmd);
6913                 break;
6914         case KVM_SEV_LAUNCH_UPDATE_DATA:
6915                 r = sev_launch_update_data(kvm, &sev_cmd);
6916                 break;
6917         case KVM_SEV_LAUNCH_MEASURE:
6918                 r = sev_launch_measure(kvm, &sev_cmd);
6919                 break;
6920         case KVM_SEV_LAUNCH_FINISH:
6921                 r = sev_launch_finish(kvm, &sev_cmd);
6922                 break;
6923         case KVM_SEV_GUEST_STATUS:
6924                 r = sev_guest_status(kvm, &sev_cmd);
6925                 break;
6926         case KVM_SEV_DBG_DECRYPT:
6927                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6928                 break;
6929         case KVM_SEV_DBG_ENCRYPT:
6930                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6931                 break;
6932         case KVM_SEV_LAUNCH_SECRET:
6933                 r = sev_launch_secret(kvm, &sev_cmd);
6934                 break;
6935         default:
6936                 r = -EINVAL;
6937                 goto out;
6938         }
6939
6940         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6941                 r = -EFAULT;
6942
6943 out:
6944         mutex_unlock(&kvm->lock);
6945         return r;
6946 }
6947
6948 static int svm_register_enc_region(struct kvm *kvm,
6949                                    struct kvm_enc_region *range)
6950 {
6951         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6952         struct enc_region *region;
6953         int ret = 0;
6954
6955         if (!sev_guest(kvm))
6956                 return -ENOTTY;
6957
6958         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
6959                 return -EINVAL;
6960
6961         region = kzalloc(sizeof(*region), GFP_KERNEL);
6962         if (!region)
6963                 return -ENOMEM;
6964
6965         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
6966         if (!region->pages) {
6967                 ret = -ENOMEM;
6968                 goto e_free;
6969         }
6970
6971         /*
6972          * The guest may change the memory encryption attribute from C=0 -> C=1
6973          * or vice versa for this memory range. Lets make sure caches are
6974          * flushed to ensure that guest data gets written into memory with
6975          * correct C-bit.
6976          */
6977         sev_clflush_pages(region->pages, region->npages);
6978
6979         region->uaddr = range->addr;
6980         region->size = range->size;
6981
6982         mutex_lock(&kvm->lock);
6983         list_add_tail(&region->list, &sev->regions_list);
6984         mutex_unlock(&kvm->lock);
6985
6986         return ret;
6987
6988 e_free:
6989         kfree(region);
6990         return ret;
6991 }
6992
6993 static struct enc_region *
6994 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
6995 {
6996         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6997         struct list_head *head = &sev->regions_list;
6998         struct enc_region *i;
6999
7000         list_for_each_entry(i, head, list) {
7001                 if (i->uaddr == range->addr &&
7002                     i->size == range->size)
7003                         return i;
7004         }
7005
7006         return NULL;
7007 }
7008
7009
7010 static int svm_unregister_enc_region(struct kvm *kvm,
7011                                      struct kvm_enc_region *range)
7012 {
7013         struct enc_region *region;
7014         int ret;
7015
7016         mutex_lock(&kvm->lock);
7017
7018         if (!sev_guest(kvm)) {
7019                 ret = -ENOTTY;
7020                 goto failed;
7021         }
7022
7023         region = find_enc_region(kvm, range);
7024         if (!region) {
7025                 ret = -EINVAL;
7026                 goto failed;
7027         }
7028
7029         __unregister_enc_region_locked(kvm, region);
7030
7031         mutex_unlock(&kvm->lock);
7032         return 0;
7033
7034 failed:
7035         mutex_unlock(&kvm->lock);
7036         return ret;
7037 }
7038
7039 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7040         .cpu_has_kvm_support = has_svm,
7041         .disabled_by_bios = is_disabled,
7042         .hardware_setup = svm_hardware_setup,
7043         .hardware_unsetup = svm_hardware_unsetup,
7044         .check_processor_compatibility = svm_check_processor_compat,
7045         .hardware_enable = svm_hardware_enable,
7046         .hardware_disable = svm_hardware_disable,
7047         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7048         .has_emulated_msr = svm_has_emulated_msr,
7049
7050         .vcpu_create = svm_create_vcpu,
7051         .vcpu_free = svm_free_vcpu,
7052         .vcpu_reset = svm_vcpu_reset,
7053
7054         .vm_alloc = svm_vm_alloc,
7055         .vm_free = svm_vm_free,
7056         .vm_init = avic_vm_init,
7057         .vm_destroy = svm_vm_destroy,
7058
7059         .prepare_guest_switch = svm_prepare_guest_switch,
7060         .vcpu_load = svm_vcpu_load,
7061         .vcpu_put = svm_vcpu_put,
7062         .vcpu_blocking = svm_vcpu_blocking,
7063         .vcpu_unblocking = svm_vcpu_unblocking,
7064
7065         .update_bp_intercept = update_bp_intercept,
7066         .get_msr_feature = svm_get_msr_feature,
7067         .get_msr = svm_get_msr,
7068         .set_msr = svm_set_msr,
7069         .get_segment_base = svm_get_segment_base,
7070         .get_segment = svm_get_segment,
7071         .set_segment = svm_set_segment,
7072         .get_cpl = svm_get_cpl,
7073         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7074         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7075         .decache_cr3 = svm_decache_cr3,
7076         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7077         .set_cr0 = svm_set_cr0,
7078         .set_cr3 = svm_set_cr3,
7079         .set_cr4 = svm_set_cr4,
7080         .set_efer = svm_set_efer,
7081         .get_idt = svm_get_idt,
7082         .set_idt = svm_set_idt,
7083         .get_gdt = svm_get_gdt,
7084         .set_gdt = svm_set_gdt,
7085         .get_dr6 = svm_get_dr6,
7086         .set_dr6 = svm_set_dr6,
7087         .set_dr7 = svm_set_dr7,
7088         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7089         .cache_reg = svm_cache_reg,
7090         .get_rflags = svm_get_rflags,
7091         .set_rflags = svm_set_rflags,
7092
7093         .tlb_flush = svm_flush_tlb,
7094         .tlb_flush_gva = svm_flush_tlb_gva,
7095
7096         .run = svm_vcpu_run,
7097         .handle_exit = handle_exit,
7098         .skip_emulated_instruction = skip_emulated_instruction,
7099         .set_interrupt_shadow = svm_set_interrupt_shadow,
7100         .get_interrupt_shadow = svm_get_interrupt_shadow,
7101         .patch_hypercall = svm_patch_hypercall,
7102         .set_irq = svm_set_irq,
7103         .set_nmi = svm_inject_nmi,
7104         .queue_exception = svm_queue_exception,
7105         .cancel_injection = svm_cancel_injection,
7106         .interrupt_allowed = svm_interrupt_allowed,
7107         .nmi_allowed = svm_nmi_allowed,
7108         .get_nmi_mask = svm_get_nmi_mask,
7109         .set_nmi_mask = svm_set_nmi_mask,
7110         .enable_nmi_window = enable_nmi_window,
7111         .enable_irq_window = enable_irq_window,
7112         .update_cr8_intercept = update_cr8_intercept,
7113         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7114         .get_enable_apicv = svm_get_enable_apicv,
7115         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7116         .load_eoi_exitmap = svm_load_eoi_exitmap,
7117         .hwapic_irr_update = svm_hwapic_irr_update,
7118         .hwapic_isr_update = svm_hwapic_isr_update,
7119         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7120         .apicv_post_state_restore = avic_post_state_restore,
7121
7122         .set_tss_addr = svm_set_tss_addr,
7123         .set_identity_map_addr = svm_set_identity_map_addr,
7124         .get_tdp_level = get_npt_level,
7125         .get_mt_mask = svm_get_mt_mask,
7126
7127         .get_exit_info = svm_get_exit_info,
7128
7129         .get_lpage_level = svm_get_lpage_level,
7130
7131         .cpuid_update = svm_cpuid_update,
7132
7133         .rdtscp_supported = svm_rdtscp_supported,
7134         .invpcid_supported = svm_invpcid_supported,
7135         .mpx_supported = svm_mpx_supported,
7136         .xsaves_supported = svm_xsaves_supported,
7137         .umip_emulated = svm_umip_emulated,
7138
7139         .set_supported_cpuid = svm_set_supported_cpuid,
7140
7141         .has_wbinvd_exit = svm_has_wbinvd_exit,
7142
7143         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7144         .write_tsc_offset = svm_write_tsc_offset,
7145
7146         .set_tdp_cr3 = set_tdp_cr3,
7147
7148         .check_intercept = svm_check_intercept,
7149         .handle_external_intr = svm_handle_external_intr,
7150
7151         .request_immediate_exit = __kvm_request_immediate_exit,
7152
7153         .sched_in = svm_sched_in,
7154
7155         .pmu_ops = &amd_pmu_ops,
7156         .deliver_posted_interrupt = svm_deliver_avic_intr,
7157         .update_pi_irte = svm_update_pi_irte,
7158         .setup_mce = svm_setup_mce,
7159
7160         .smi_allowed = svm_smi_allowed,
7161         .pre_enter_smm = svm_pre_enter_smm,
7162         .pre_leave_smm = svm_pre_leave_smm,
7163         .enable_smi_window = enable_smi_window,
7164
7165         .mem_enc_op = svm_mem_enc_op,
7166         .mem_enc_reg_region = svm_register_enc_region,
7167         .mem_enc_unreg_region = svm_unregister_enc_region,
7168 };
7169
7170 static int __init svm_init(void)
7171 {
7172         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7173                         __alignof__(struct vcpu_svm), THIS_MODULE);
7174 }
7175
7176 static void __exit svm_exit(void)
7177 {
7178         kvm_exit();
7179 }
7180
7181 module_init(svm_init)
7182 module_exit(svm_exit)