arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39
  40 #include <asm/apic.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/tlbflush.h>
  43 #include <asm/desc.h>
  44 #include <asm/debugreg.h>
  45 #include <asm/kvm_para.h>
  46 #include <asm/irq_remapping.h>
  47
  48 #include <asm/virtext.h>
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id svm_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  61
  62 #define IOPM_ALLOC_ORDER 2
  63 #define MSRPM_ALLOC_ORDER 1
  64
  65 #define SEG_TYPE_LDT 2
  66 #define SEG_TYPE_BUSY_TSS16 3
  67
  68 #define SVM_FEATURE_NPT            (1 <<  0)
  69 #define SVM_FEATURE_LBRV           (1 <<  1)
  70 #define SVM_FEATURE_SVML           (1 <<  2)
  71 #define SVM_FEATURE_NRIP           (1 <<  3)
  72 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  73 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  74 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  75 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  76 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  77
  78 #define SVM_AVIC_DOORBELL       0xc001011b
  79
  80 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  81 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  82 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  83
  84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  85
  86 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  87 #define TSC_RATIO_MIN           0x0000000000000001ULL
  88 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  89
  90 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  91
  92 /*
  93  * 0xff is broadcast, so the max index allowed for physical APIC ID
  94  * table is 0xfe.  APIC IDs above 0xff are reserved.
  95  */
  96 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  97
  98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
  99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 101
 102 /* AVIC GATAG is encoded using VM and VCPU IDs */
 103 #define AVIC_VCPU_ID_BITS               8
 104 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 105
 106 #define AVIC_VM_ID_BITS                 24
 107 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 108 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 109
 110 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 111                                                 (y & AVIC_VCPU_ID_MASK))
 112 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 113 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 114
 115 static bool erratum_383_found __read_mostly;
 116
 117 static const u32 host_save_user_msrs[] = {
 118 #ifdef CONFIG_X86_64
 119         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 120         MSR_FS_BASE,
 121 #endif
 122         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 123         MSR_TSC_AUX,
 124 };
 125
 126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 127
 128 struct kvm_vcpu;
 129
 130 struct nested_state {
 131         struct vmcb *hsave;
 132         u64 hsave_msr;
 133         u64 vm_cr_msr;
 134         u64 vmcb;
 135
 136         /* These are the merged vectors */
 137         u32 *msrpm;
 138
 139         /* gpa pointers to the real vectors */
 140         u64 vmcb_msrpm;
 141         u64 vmcb_iopm;
 142
 143         /* A VMEXIT is required but not yet emulated */
 144         bool exit_required;
 145
 146         /* cache for intercepts of the guest */
 147         u32 intercept_cr;
 148         u32 intercept_dr;
 149         u32 intercept_exceptions;
 150         u64 intercept;
 151
 152         /* Nested Paging related state */
 153         u64 nested_cr3;
 154 };
 155
 156 #define MSRPM_OFFSETS   16
 157 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 158
 159 /*
 160  * Set osvw_len to higher value when updated Revision Guides
 161  * are published and we know what the new status bits are
 162  */
 163 static uint64_t osvw_len = 4, osvw_status;
 164
 165 struct vcpu_svm {
 166         struct kvm_vcpu vcpu;
 167         struct vmcb *vmcb;
 168         unsigned long vmcb_pa;
 169         struct svm_cpu_data *svm_data;
 170         uint64_t asid_generation;
 171         uint64_t sysenter_esp;
 172         uint64_t sysenter_eip;
 173         uint64_t tsc_aux;
 174
 175         u64 next_rip;
 176
 177         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 178         struct {
 179                 u16 fs;
 180                 u16 gs;
 181                 u16 ldt;
 182                 u64 gs_base;
 183         } host;
 184
 185         u32 *msrpm;
 186
 187         ulong nmi_iret_rip;
 188
 189         struct nested_state nested;
 190
 191         bool nmi_singlestep;
 192
 193         unsigned int3_injected;
 194         unsigned long int3_rip;
 195         u32 apf_reason;
 196
 197         /* cached guest cpuid flags for faster access */
 198         bool nrips_enabled      : 1;
 199
 200         u32 ldr_reg;
 201         struct page *avic_backing_page;
 202         u64 *avic_physical_id_cache;
 203         bool avic_is_running;
 204
 205         /*
 206          * Per-vcpu list of struct amd_svm_iommu_ir:
 207          * This is used mainly to store interrupt remapping information used
 208          * when update the vcpu affinity. This avoids the need to scan for
 209          * IRTE and try to match ga_tag in the IOMMU driver.
 210          */
 211         struct list_head ir_list;
 212         spinlock_t ir_list_lock;
 213 };
 214
 215 /*
 216  * This is a wrapper of struct amd_iommu_ir_data.
 217  */
 218 struct amd_svm_iommu_ir {
 219         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 220         void *data;             /* Storing pointer to struct amd_ir_data */
 221 };
 222
 223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 225
 226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 230
 231 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 232 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 233
 234 #define MSR_INVALID                     0xffffffffU
 235
 236 static const struct svm_direct_access_msrs {
 237         u32 index;   /* Index of the MSR */
 238         bool always; /* True if intercept is always on */
 239 } direct_access_msrs[] = {
 240         { .index = MSR_STAR,                            .always = true  },
 241         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 242 #ifdef CONFIG_X86_64
 243         { .index = MSR_GS_BASE,                         .always = true  },
 244         { .index = MSR_FS_BASE,                         .always = true  },
 245         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 246         { .index = MSR_LSTAR,                           .always = true  },
 247         { .index = MSR_CSTAR,                           .always = true  },
 248         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 249 #endif
 250         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 251         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 252         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 253         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 254         { .index = MSR_INVALID,                         .always = false },
 255 };
 256
 257 /* enable NPT for AMD64 and X86 with PAE */
 258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 259 static bool npt_enabled = true;
 260 #else
 261 static bool npt_enabled;
 262 #endif
 263
 264 /* allow nested paging (virtualized MMU) for all guests */
 265 static int npt = true;
 266 module_param(npt, int, S_IRUGO);
 267
 268 /* allow nested virtualization in KVM/SVM */
 269 static int nested = true;
 270 module_param(nested, int, S_IRUGO);
 271
 272 /* enable / disable AVIC */
 273 static int avic;
 274 #ifdef CONFIG_X86_LOCAL_APIC
 275 module_param(avic, int, S_IRUGO);
 276 #endif
 277
 278 /* AVIC VM ID bit masks and lock */
 279 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
 280 static DEFINE_SPINLOCK(avic_vm_id_lock);
 281
 282 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 283 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 284 static void svm_complete_interrupts(struct vcpu_svm *svm);
 285
 286 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 287 static int nested_svm_intercept(struct vcpu_svm *svm);
 288 static int nested_svm_vmexit(struct vcpu_svm *svm);
 289 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 290                                       bool has_error_code, u32 error_code);
 291
 292 enum {
 293         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 294                             pause filter count */
 295         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 296         VMCB_ASID,       /* ASID */
 297         VMCB_INTR,       /* int_ctl, int_vector */
 298         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 299         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 300         VMCB_DR,         /* DR6, DR7 */
 301         VMCB_DT,         /* GDT, IDT */
 302         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 303         VMCB_CR2,        /* CR2 only */
 304         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 305         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 306                           * AVIC PHYSICAL_TABLE pointer,
 307                           * AVIC LOGICAL_TABLE pointer
 308                           */
 309         VMCB_DIRTY_MAX,
 310 };
 311
 312 /* TPR and CR2 are always written before VMRUN */
 313 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 314
 315 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 316
 317 static inline void mark_all_dirty(struct vmcb *vmcb)
 318 {
 319         vmcb->control.clean = 0;
 320 }
 321
 322 static inline void mark_all_clean(struct vmcb *vmcb)
 323 {
 324         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 325                                & ~VMCB_ALWAYS_DIRTY_MASK;
 326 }
 327
 328 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 329 {
 330         vmcb->control.clean &= ~(1 << bit);
 331 }
 332
 333 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 334 {
 335         return container_of(vcpu, struct vcpu_svm, vcpu);
 336 }
 337
 338 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 339 {
 340         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 341         mark_dirty(svm->vmcb, VMCB_AVIC);
 342 }
 343
 344 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 345 {
 346         struct vcpu_svm *svm = to_svm(vcpu);
 347         u64 *entry = svm->avic_physical_id_cache;
 348
 349         if (!entry)
 350                 return false;
 351
 352         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 353 }
 354
 355 static void recalc_intercepts(struct vcpu_svm *svm)
 356 {
 357         struct vmcb_control_area *c, *h;
 358         struct nested_state *g;
 359
 360         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 361
 362         if (!is_guest_mode(&svm->vcpu))
 363                 return;
 364
 365         c = &svm->vmcb->control;
 366         h = &svm->nested.hsave->control;
 367         g = &svm->nested;
 368
 369         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 370         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 371         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 372         c->intercept = h->intercept | g->intercept;
 373 }
 374
 375 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 376 {
 377         if (is_guest_mode(&svm->vcpu))
 378                 return svm->nested.hsave;
 379         else
 380                 return svm->vmcb;
 381 }
 382
 383 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 384 {
 385         struct vmcb *vmcb = get_host_vmcb(svm);
 386
 387         vmcb->control.intercept_cr |= (1U << bit);
 388
 389         recalc_intercepts(svm);
 390 }
 391
 392 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 393 {
 394         struct vmcb *vmcb = get_host_vmcb(svm);
 395
 396         vmcb->control.intercept_cr &= ~(1U << bit);
 397
 398         recalc_intercepts(svm);
 399 }
 400
 401 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 402 {
 403         struct vmcb *vmcb = get_host_vmcb(svm);
 404
 405         return vmcb->control.intercept_cr & (1U << bit);
 406 }
 407
 408 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 409 {
 410         struct vmcb *vmcb = get_host_vmcb(svm);
 411
 412         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 413                 | (1 << INTERCEPT_DR1_READ)
 414                 | (1 << INTERCEPT_DR2_READ)
 415                 | (1 << INTERCEPT_DR3_READ)
 416                 | (1 << INTERCEPT_DR4_READ)
 417                 | (1 << INTERCEPT_DR5_READ)
 418                 | (1 << INTERCEPT_DR6_READ)
 419                 | (1 << INTERCEPT_DR7_READ)
 420                 | (1 << INTERCEPT_DR0_WRITE)
 421                 | (1 << INTERCEPT_DR1_WRITE)
 422                 | (1 << INTERCEPT_DR2_WRITE)
 423                 | (1 << INTERCEPT_DR3_WRITE)
 424                 | (1 << INTERCEPT_DR4_WRITE)
 425                 | (1 << INTERCEPT_DR5_WRITE)
 426                 | (1 << INTERCEPT_DR6_WRITE)
 427                 | (1 << INTERCEPT_DR7_WRITE);
 428
 429         recalc_intercepts(svm);
 430 }
 431
 432 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 433 {
 434         struct vmcb *vmcb = get_host_vmcb(svm);
 435
 436         vmcb->control.intercept_dr = 0;
 437
 438         recalc_intercepts(svm);
 439 }
 440
 441 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 442 {
 443         struct vmcb *vmcb = get_host_vmcb(svm);
 444
 445         vmcb->control.intercept_exceptions |= (1U << bit);
 446
 447         recalc_intercepts(svm);
 448 }
 449
 450 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 451 {
 452         struct vmcb *vmcb = get_host_vmcb(svm);
 453
 454         vmcb->control.intercept_exceptions &= ~(1U << bit);
 455
 456         recalc_intercepts(svm);
 457 }
 458
 459 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 460 {
 461         struct vmcb *vmcb = get_host_vmcb(svm);
 462
 463         vmcb->control.intercept |= (1ULL << bit);
 464
 465         recalc_intercepts(svm);
 466 }
 467
 468 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 469 {
 470         struct vmcb *vmcb = get_host_vmcb(svm);
 471
 472         vmcb->control.intercept &= ~(1ULL << bit);
 473
 474         recalc_intercepts(svm);
 475 }
 476
 477 static inline void enable_gif(struct vcpu_svm *svm)
 478 {
 479         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 480 }
 481
 482 static inline void disable_gif(struct vcpu_svm *svm)
 483 {
 484         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 485 }
 486
 487 static inline bool gif_set(struct vcpu_svm *svm)
 488 {
 489         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 490 }
 491
 492 static unsigned long iopm_base;
 493
 494 struct kvm_ldttss_desc {
 495         u16 limit0;
 496         u16 base0;
 497         unsigned base1:8, type:5, dpl:2, p:1;
 498         unsigned limit1:4, zero0:3, g:1, base2:8;
 499         u32 base3;
 500         u32 zero1;
 501 } __attribute__((packed));
 502
 503 struct svm_cpu_data {
 504         int cpu;
 505
 506         u64 asid_generation;
 507         u32 max_asid;
 508         u32 next_asid;
 509         struct kvm_ldttss_desc *tss_desc;
 510
 511         struct page *save_area;
 512 };
 513
 514 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 515
 516 struct svm_init_data {
 517         int cpu;
 518         int r;
 519 };
 520
 521 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 522
 523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 524 #define MSRS_RANGE_SIZE 2048
 525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 526
 527 static u32 svm_msrpm_offset(u32 msr)
 528 {
 529         u32 offset;
 530         int i;
 531
 532         for (i = 0; i < NUM_MSR_MAPS; i++) {
 533                 if (msr < msrpm_ranges[i] ||
 534                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 535                         continue;
 536
 537                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 538                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 539
 540                 /* Now we have the u8 offset - but need the u32 offset */
 541                 return offset / 4;
 542         }
 543
 544         /* MSR not in any range */
 545         return MSR_INVALID;
 546 }
 547
 548 #define MAX_INST_SIZE 15
 549
 550 static inline void clgi(void)
 551 {
 552         asm volatile (__ex(SVM_CLGI));
 553 }
 554
 555 static inline void stgi(void)
 556 {
 557         asm volatile (__ex(SVM_STGI));
 558 }
 559
 560 static inline void invlpga(unsigned long addr, u32 asid)
 561 {
 562         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 563 }
 564
 565 static int get_npt_level(void)
 566 {
 567 #ifdef CONFIG_X86_64
 568         return PT64_ROOT_LEVEL;
 569 #else
 570         return PT32E_ROOT_LEVEL;
 571 #endif
 572 }
 573
 574 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 575 {
 576         vcpu->arch.efer = efer;
 577         if (!npt_enabled && !(efer & EFER_LMA))
 578                 efer &= ~EFER_LME;
 579
 580         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 581         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 582 }
 583
 584 static int is_external_interrupt(u32 info)
 585 {
 586         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 587         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 588 }
 589
 590 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 591 {
 592         struct vcpu_svm *svm = to_svm(vcpu);
 593         u32 ret = 0;
 594
 595         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 596                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 597         return ret;
 598 }
 599
 600 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         if (mask == 0)
 605                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 606         else
 607                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 608
 609 }
 610
 611 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         if (svm->vmcb->control.next_rip != 0) {
 616                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 617                 svm->next_rip = svm->vmcb->control.next_rip;
 618         }
 619
 620         if (!svm->next_rip) {
 621                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 622                                 EMULATE_DONE)
 623                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 624                 return;
 625         }
 626         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 627                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 628                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 629
 630         kvm_rip_write(vcpu, svm->next_rip);
 631         svm_set_interrupt_shadow(vcpu, 0);
 632 }
 633
 634 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 635                                 bool has_error_code, u32 error_code,
 636                                 bool reinject)
 637 {
 638         struct vcpu_svm *svm = to_svm(vcpu);
 639
 640         /*
 641          * If we are within a nested VM we'd better #VMEXIT and let the guest
 642          * handle the exception
 643          */
 644         if (!reinject &&
 645             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 646                 return;
 647
 648         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 649                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 650
 651                 /*
 652                  * For guest debugging where we have to reinject #BP if some
 653                  * INT3 is guest-owned:
 654                  * Emulate nRIP by moving RIP forward. Will fail if injection
 655                  * raises a fault that is not intercepted. Still better than
 656                  * failing in all cases.
 657                  */
 658                 skip_emulated_instruction(&svm->vcpu);
 659                 rip = kvm_rip_read(&svm->vcpu);
 660                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 661                 svm->int3_injected = rip - old_rip;
 662         }
 663
 664         svm->vmcb->control.event_inj = nr
 665                 | SVM_EVTINJ_VALID
 666                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 667                 | SVM_EVTINJ_TYPE_EXEPT;
 668         svm->vmcb->control.event_inj_err = error_code;
 669 }
 670
 671 static void svm_init_erratum_383(void)
 672 {
 673         u32 low, high;
 674         int err;
 675         u64 val;
 676
 677         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 678                 return;
 679
 680         /* Use _safe variants to not break nested virtualization */
 681         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 682         if (err)
 683                 return;
 684
 685         val |= (1ULL << 47);
 686
 687         low  = lower_32_bits(val);
 688         high = upper_32_bits(val);
 689
 690         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 691
 692         erratum_383_found = true;
 693 }
 694
 695 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 696 {
 697         /*
 698          * Guests should see errata 400 and 415 as fixed (assuming that
 699          * HLT and IO instructions are intercepted).
 700          */
 701         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 702         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 703
 704         /*
 705          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 706          * all osvw.status bits inside that length, including bit 0 (which is
 707          * reserved for erratum 298), are valid. However, if host processor's
 708          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 709          * be conservative here and therefore we tell the guest that erratum 298
 710          * is present (because we really don't know).
 711          */
 712         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 713                 vcpu->arch.osvw.status |= 1;
 714 }
 715
 716 static int has_svm(void)
 717 {
 718         const char *msg;
 719
 720         if (!cpu_has_svm(&msg)) {
 721                 printk(KERN_INFO "has_svm: %s\n", msg);
 722                 return 0;
 723         }
 724
 725         return 1;
 726 }
 727
 728 static void svm_hardware_disable(void)
 729 {
 730         /* Make sure we clean up behind us */
 731         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 732                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 733
 734         cpu_svm_disable();
 735
 736         amd_pmu_disable_virt();
 737 }
 738
 739 static int svm_hardware_enable(void)
 740 {
 741
 742         struct svm_cpu_data *sd;
 743         uint64_t efer;
 744         struct desc_struct *gdt;
 745         int me = raw_smp_processor_id();
 746
 747         rdmsrl(MSR_EFER, efer);
 748         if (efer & EFER_SVME)
 749                 return -EBUSY;
 750
 751         if (!has_svm()) {
 752                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 753                 return -EINVAL;
 754         }
 755         sd = per_cpu(svm_data, me);
 756         if (!sd) {
 757                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 758                 return -EINVAL;
 759         }
 760
 761         sd->asid_generation = 1;
 762         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 763         sd->next_asid = sd->max_asid + 1;
 764
 765         gdt = get_current_gdt_rw();
 766         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 767
 768         wrmsrl(MSR_EFER, efer | EFER_SVME);
 769
 770         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 771
 772         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 773                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 774                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 775         }
 776
 777
 778         /*
 779          * Get OSVW bits.
 780          *
 781          * Note that it is possible to have a system with mixed processor
 782          * revisions and therefore different OSVW bits. If bits are not the same
 783          * on different processors then choose the worst case (i.e. if erratum
 784          * is present on one processor and not on another then assume that the
 785          * erratum is present everywhere).
 786          */
 787         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 788                 uint64_t len, status = 0;
 789                 int err;
 790
 791                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 792                 if (!err)
 793                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 794                                                       &err);
 795
 796                 if (err)
 797                         osvw_status = osvw_len = 0;
 798                 else {
 799                         if (len < osvw_len)
 800                                 osvw_len = len;
 801                         osvw_status |= status;
 802                         osvw_status &= (1ULL << osvw_len) - 1;
 803                 }
 804         } else
 805                 osvw_status = osvw_len = 0;
 806
 807         svm_init_erratum_383();
 808
 809         amd_pmu_enable_virt();
 810
 811         return 0;
 812 }
 813
 814 static void svm_cpu_uninit(int cpu)
 815 {
 816         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 817
 818         if (!sd)
 819                 return;
 820
 821         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 822         __free_page(sd->save_area);
 823         kfree(sd);
 824 }
 825
 826 static int svm_cpu_init(int cpu)
 827 {
 828         struct svm_cpu_data *sd;
 829         int r;
 830
 831         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 832         if (!sd)
 833                 return -ENOMEM;
 834         sd->cpu = cpu;
 835         sd->save_area = alloc_page(GFP_KERNEL);
 836         r = -ENOMEM;
 837         if (!sd->save_area)
 838                 goto err_1;
 839
 840         per_cpu(svm_data, cpu) = sd;
 841
 842         return 0;
 843
 844 err_1:
 845         kfree(sd);
 846         return r;
 847
 848 }
 849
 850 static bool valid_msr_intercept(u32 index)
 851 {
 852         int i;
 853
 854         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 855                 if (direct_access_msrs[i].index == index)
 856                         return true;
 857
 858         return false;
 859 }
 860
 861 static void set_msr_interception(u32 *msrpm, unsigned msr,
 862                                  int read, int write)
 863 {
 864         u8 bit_read, bit_write;
 865         unsigned long tmp;
 866         u32 offset;
 867
 868         /*
 869          * If this warning triggers extend the direct_access_msrs list at the
 870          * beginning of the file
 871          */
 872         WARN_ON(!valid_msr_intercept(msr));
 873
 874         offset    = svm_msrpm_offset(msr);
 875         bit_read  = 2 * (msr & 0x0f);
 876         bit_write = 2 * (msr & 0x0f) + 1;
 877         tmp       = msrpm[offset];
 878
 879         BUG_ON(offset == MSR_INVALID);
 880
 881         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 882         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 883
 884         msrpm[offset] = tmp;
 885 }
 886
 887 static void svm_vcpu_init_msrpm(u32 *msrpm)
 888 {
 889         int i;
 890
 891         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 892
 893         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 894                 if (!direct_access_msrs[i].always)
 895                         continue;
 896
 897                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 898         }
 899 }
 900
 901 static void add_msr_offset(u32 offset)
 902 {
 903         int i;
 904
 905         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 906
 907                 /* Offset already in list? */
 908                 if (msrpm_offsets[i] == offset)
 909                         return;
 910
 911                 /* Slot used by another offset? */
 912                 if (msrpm_offsets[i] != MSR_INVALID)
 913                         continue;
 914
 915                 /* Add offset to list */
 916                 msrpm_offsets[i] = offset;
 917
 918                 return;
 919         }
 920
 921         /*
 922          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 923          * increase MSRPM_OFFSETS in this case.
 924          */
 925         BUG();
 926 }
 927
 928 static void init_msrpm_offsets(void)
 929 {
 930         int i;
 931
 932         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 933
 934         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 935                 u32 offset;
 936
 937                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 938                 BUG_ON(offset == MSR_INVALID);
 939
 940                 add_msr_offset(offset);
 941         }
 942 }
 943
 944 static void svm_enable_lbrv(struct vcpu_svm *svm)
 945 {
 946         u32 *msrpm = svm->msrpm;
 947
 948         svm->vmcb->control.lbr_ctl = 1;
 949         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 950         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 951         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 952         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 953 }
 954
 955 static void svm_disable_lbrv(struct vcpu_svm *svm)
 956 {
 957         u32 *msrpm = svm->msrpm;
 958
 959         svm->vmcb->control.lbr_ctl = 0;
 960         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 961         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 962         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 963         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 964 }
 965
 966 /* Note:
 967  * This hash table is used to map VM_ID to a struct kvm_arch,
 968  * when handling AMD IOMMU GALOG notification to schedule in
 969  * a particular vCPU.
 970  */
 971 #define SVM_VM_DATA_HASH_BITS   8
 972 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
 973 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
 974
 975 /* Note:
 976  * This function is called from IOMMU driver to notify
 977  * SVM to schedule in a particular vCPU of a particular VM.
 978  */
 979 static int avic_ga_log_notifier(u32 ga_tag)
 980 {
 981         unsigned long flags;
 982         struct kvm_arch *ka = NULL;
 983         struct kvm_vcpu *vcpu = NULL;
 984         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
 985         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
 986
 987         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
 988
 989         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
 990         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
 991                 struct kvm *kvm = container_of(ka, struct kvm, arch);
 992                 struct kvm_arch *vm_data = &kvm->arch;
 993
 994                 if (vm_data->avic_vm_id != vm_id)
 995                         continue;
 996                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
 997                 break;
 998         }
 999         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1000
1001         if (!vcpu)
1002                 return 0;
1003
1004         /* Note:
1005          * At this point, the IOMMU should have already set the pending
1006          * bit in the vAPIC backing page. So, we just need to schedule
1007          * in the vcpu.
1008          */
1009         if (vcpu->mode == OUTSIDE_GUEST_MODE)
1010                 kvm_vcpu_wake_up(vcpu);
1011
1012         return 0;
1013 }
1014
1015 static __init int svm_hardware_setup(void)
1016 {
1017         int cpu;
1018         struct page *iopm_pages;
1019         void *iopm_va;
1020         int r;
1021
1022         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1023
1024         if (!iopm_pages)
1025                 return -ENOMEM;
1026
1027         iopm_va = page_address(iopm_pages);
1028         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1029         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1030
1031         init_msrpm_offsets();
1032
1033         if (boot_cpu_has(X86_FEATURE_NX))
1034                 kvm_enable_efer_bits(EFER_NX);
1035
1036         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1037                 kvm_enable_efer_bits(EFER_FFXSR);
1038
1039         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1040                 kvm_has_tsc_control = true;
1041                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1042                 kvm_tsc_scaling_ratio_frac_bits = 32;
1043         }
1044
1045         if (nested) {
1046                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1047                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1048         }
1049
1050         for_each_possible_cpu(cpu) {
1051                 r = svm_cpu_init(cpu);
1052                 if (r)
1053                         goto err;
1054         }
1055
1056         if (!boot_cpu_has(X86_FEATURE_NPT))
1057                 npt_enabled = false;
1058
1059         if (npt_enabled && !npt) {
1060                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1061                 npt_enabled = false;
1062         }
1063
1064         if (npt_enabled) {
1065                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1066                 kvm_enable_tdp();
1067         } else
1068                 kvm_disable_tdp();
1069
1070         if (avic) {
1071                 if (!npt_enabled ||
1072                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1073                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1074                         avic = false;
1075                 } else {
1076                         pr_info("AVIC enabled\n");
1077
1078                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1079                 }
1080         }
1081
1082         return 0;
1083
1084 err:
1085         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1086         iopm_base = 0;
1087         return r;
1088 }
1089
1090 static __exit void svm_hardware_unsetup(void)
1091 {
1092         int cpu;
1093
1094         for_each_possible_cpu(cpu)
1095                 svm_cpu_uninit(cpu);
1096
1097         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1098         iopm_base = 0;
1099 }
1100
1101 static void init_seg(struct vmcb_seg *seg)
1102 {
1103         seg->selector = 0;
1104         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1105                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1106         seg->limit = 0xffff;
1107         seg->base = 0;
1108 }
1109
1110 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1111 {
1112         seg->selector = 0;
1113         seg->attrib = SVM_SELECTOR_P_MASK | type;
1114         seg->limit = 0xffff;
1115         seg->base = 0;
1116 }
1117
1118 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1119 {
1120         struct vcpu_svm *svm = to_svm(vcpu);
1121         u64 g_tsc_offset = 0;
1122
1123         if (is_guest_mode(vcpu)) {
1124                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1125                                svm->nested.hsave->control.tsc_offset;
1126                 svm->nested.hsave->control.tsc_offset = offset;
1127         } else
1128                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1129                                            svm->vmcb->control.tsc_offset,
1130                                            offset);
1131
1132         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1133
1134         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1135 }
1136
1137 static void avic_init_vmcb(struct vcpu_svm *svm)
1138 {
1139         struct vmcb *vmcb = svm->vmcb;
1140         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1141         phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1142         phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1143         phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1144
1145         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1146         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1147         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1148         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1149         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1150         svm->vcpu.arch.apicv_active = true;
1151 }
1152
1153 static void init_vmcb(struct vcpu_svm *svm)
1154 {
1155         struct vmcb_control_area *control = &svm->vmcb->control;
1156         struct vmcb_save_area *save = &svm->vmcb->save;
1157
1158         svm->vcpu.arch.hflags = 0;
1159
1160         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1161         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1162         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1163         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1164         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1165         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1166         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1167                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1168
1169         set_dr_intercepts(svm);
1170
1171         set_exception_intercept(svm, PF_VECTOR);
1172         set_exception_intercept(svm, UD_VECTOR);
1173         set_exception_intercept(svm, MC_VECTOR);
1174         set_exception_intercept(svm, AC_VECTOR);
1175         set_exception_intercept(svm, DB_VECTOR);
1176
1177         set_intercept(svm, INTERCEPT_INTR);
1178         set_intercept(svm, INTERCEPT_NMI);
1179         set_intercept(svm, INTERCEPT_SMI);
1180         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1181         set_intercept(svm, INTERCEPT_RDPMC);
1182         set_intercept(svm, INTERCEPT_CPUID);
1183         set_intercept(svm, INTERCEPT_INVD);
1184         set_intercept(svm, INTERCEPT_HLT);
1185         set_intercept(svm, INTERCEPT_INVLPG);
1186         set_intercept(svm, INTERCEPT_INVLPGA);
1187         set_intercept(svm, INTERCEPT_IOIO_PROT);
1188         set_intercept(svm, INTERCEPT_MSR_PROT);
1189         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1190         set_intercept(svm, INTERCEPT_SHUTDOWN);
1191         set_intercept(svm, INTERCEPT_VMRUN);
1192         set_intercept(svm, INTERCEPT_VMMCALL);
1193         set_intercept(svm, INTERCEPT_VMLOAD);
1194         set_intercept(svm, INTERCEPT_VMSAVE);
1195         set_intercept(svm, INTERCEPT_STGI);
1196         set_intercept(svm, INTERCEPT_CLGI);
1197         set_intercept(svm, INTERCEPT_SKINIT);
1198         set_intercept(svm, INTERCEPT_WBINVD);
1199         set_intercept(svm, INTERCEPT_XSETBV);
1200
1201         if (!kvm_mwait_in_guest()) {
1202                 set_intercept(svm, INTERCEPT_MONITOR);
1203                 set_intercept(svm, INTERCEPT_MWAIT);
1204         }
1205
1206         control->iopm_base_pa = iopm_base;
1207         control->msrpm_base_pa = __pa(svm->msrpm);
1208         control->int_ctl = V_INTR_MASKING_MASK;
1209
1210         init_seg(&save->es);
1211         init_seg(&save->ss);
1212         init_seg(&save->ds);
1213         init_seg(&save->fs);
1214         init_seg(&save->gs);
1215
1216         save->cs.selector = 0xf000;
1217         save->cs.base = 0xffff0000;
1218         /* Executable/Readable Code Segment */
1219         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1220                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1221         save->cs.limit = 0xffff;
1222
1223         save->gdtr.limit = 0xffff;
1224         save->idtr.limit = 0xffff;
1225
1226         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1227         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1228
1229         svm_set_efer(&svm->vcpu, 0);
1230         save->dr6 = 0xffff0ff0;
1231         kvm_set_rflags(&svm->vcpu, 2);
1232         save->rip = 0x0000fff0;
1233         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1234
1235         /*
1236          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1237          * It also updates the guest-visible cr0 value.
1238          */
1239         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1240         kvm_mmu_reset_context(&svm->vcpu);
1241
1242         save->cr4 = X86_CR4_PAE;
1243         /* rdx = ?? */
1244
1245         if (npt_enabled) {
1246                 /* Setup VMCB for Nested Paging */
1247                 control->nested_ctl = 1;
1248                 clr_intercept(svm, INTERCEPT_INVLPG);
1249                 clr_exception_intercept(svm, PF_VECTOR);
1250                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1251                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1252                 save->g_pat = svm->vcpu.arch.pat;
1253                 save->cr3 = 0;
1254                 save->cr4 = 0;
1255         }
1256         svm->asid_generation = 0;
1257
1258         svm->nested.vmcb = 0;
1259         svm->vcpu.arch.hflags = 0;
1260
1261         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1262                 control->pause_filter_count = 3000;
1263                 set_intercept(svm, INTERCEPT_PAUSE);
1264         }
1265
1266         if (avic)
1267                 avic_init_vmcb(svm);
1268
1269         mark_all_dirty(svm->vmcb);
1270
1271         enable_gif(svm);
1272
1273 }
1274
1275 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1276 {
1277         u64 *avic_physical_id_table;
1278         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1279
1280         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1281                 return NULL;
1282
1283         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1284
1285         return &avic_physical_id_table[index];
1286 }
1287
1288 /**
1289  * Note:
1290  * AVIC hardware walks the nested page table to check permissions,
1291  * but does not use the SPA address specified in the leaf page
1292  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1293  * field of the VMCB. Therefore, we set up the
1294  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1295  */
1296 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1297 {
1298         struct kvm *kvm = vcpu->kvm;
1299         int ret;
1300
1301         if (kvm->arch.apic_access_page_done)
1302                 return 0;
1303
1304         ret = x86_set_memory_region(kvm,
1305                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1306                                     APIC_DEFAULT_PHYS_BASE,
1307                                     PAGE_SIZE);
1308         if (ret)
1309                 return ret;
1310
1311         kvm->arch.apic_access_page_done = true;
1312         return 0;
1313 }
1314
1315 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1316 {
1317         int ret;
1318         u64 *entry, new_entry;
1319         int id = vcpu->vcpu_id;
1320         struct vcpu_svm *svm = to_svm(vcpu);
1321
1322         ret = avic_init_access_page(vcpu);
1323         if (ret)
1324                 return ret;
1325
1326         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1327                 return -EINVAL;
1328
1329         if (!svm->vcpu.arch.apic->regs)
1330                 return -EINVAL;
1331
1332         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1333
1334         /* Setting AVIC backing page address in the phy APIC ID table */
1335         entry = avic_get_physical_id_entry(vcpu, id);
1336         if (!entry)
1337                 return -EINVAL;
1338
1339         new_entry = READ_ONCE(*entry);
1340         new_entry = (page_to_phys(svm->avic_backing_page) &
1341                      AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1342                      AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1343         WRITE_ONCE(*entry, new_entry);
1344
1345         svm->avic_physical_id_cache = entry;
1346
1347         return 0;
1348 }
1349
1350 static inline int avic_get_next_vm_id(void)
1351 {
1352         int id;
1353
1354         spin_lock(&avic_vm_id_lock);
1355
1356         /* AVIC VM ID is one-based. */
1357         id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1358         if (id <= AVIC_VM_ID_MASK)
1359                 __set_bit(id, avic_vm_id_bitmap);
1360         else
1361                 id = -EAGAIN;
1362
1363         spin_unlock(&avic_vm_id_lock);
1364         return id;
1365 }
1366
1367 static inline int avic_free_vm_id(int id)
1368 {
1369         if (id <= 0 || id > AVIC_VM_ID_MASK)
1370                 return -EINVAL;
1371
1372         spin_lock(&avic_vm_id_lock);
1373         __clear_bit(id, avic_vm_id_bitmap);
1374         spin_unlock(&avic_vm_id_lock);
1375         return 0;
1376 }
1377
1378 static void avic_vm_destroy(struct kvm *kvm)
1379 {
1380         unsigned long flags;
1381         struct kvm_arch *vm_data = &kvm->arch;
1382
1383         if (!avic)
1384                 return;
1385
1386         avic_free_vm_id(vm_data->avic_vm_id);
1387
1388         if (vm_data->avic_logical_id_table_page)
1389                 __free_page(vm_data->avic_logical_id_table_page);
1390         if (vm_data->avic_physical_id_table_page)
1391                 __free_page(vm_data->avic_physical_id_table_page);
1392
1393         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1394         hash_del(&vm_data->hnode);
1395         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1396 }
1397
1398 static int avic_vm_init(struct kvm *kvm)
1399 {
1400         unsigned long flags;
1401         int vm_id, err = -ENOMEM;
1402         struct kvm_arch *vm_data = &kvm->arch;
1403         struct page *p_page;
1404         struct page *l_page;
1405
1406         if (!avic)
1407                 return 0;
1408
1409         vm_id = avic_get_next_vm_id();
1410         if (vm_id < 0)
1411                 return vm_id;
1412         vm_data->avic_vm_id = (u32)vm_id;
1413
1414         /* Allocating physical APIC ID table (4KB) */
1415         p_page = alloc_page(GFP_KERNEL);
1416         if (!p_page)
1417                 goto free_avic;
1418
1419         vm_data->avic_physical_id_table_page = p_page;
1420         clear_page(page_address(p_page));
1421
1422         /* Allocating logical APIC ID table (4KB) */
1423         l_page = alloc_page(GFP_KERNEL);
1424         if (!l_page)
1425                 goto free_avic;
1426
1427         vm_data->avic_logical_id_table_page = l_page;
1428         clear_page(page_address(l_page));
1429
1430         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1431         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1432         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1433
1434         return 0;
1435
1436 free_avic:
1437         avic_vm_destroy(kvm);
1438         return err;
1439 }
1440
1441 static inline int
1442 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1443 {
1444         int ret = 0;
1445         unsigned long flags;
1446         struct amd_svm_iommu_ir *ir;
1447         struct vcpu_svm *svm = to_svm(vcpu);
1448
1449         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1450                 return 0;
1451
1452         /*
1453          * Here, we go through the per-vcpu ir_list to update all existing
1454          * interrupt remapping table entry targeting this vcpu.
1455          */
1456         spin_lock_irqsave(&svm->ir_list_lock, flags);
1457
1458         if (list_empty(&svm->ir_list))
1459                 goto out;
1460
1461         list_for_each_entry(ir, &svm->ir_list, node) {
1462                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1463                 if (ret)
1464                         break;
1465         }
1466 out:
1467         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1468         return ret;
1469 }
1470
1471 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1472 {
1473         u64 entry;
1474         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1475         int h_physical_id = kvm_cpu_get_apicid(cpu);
1476         struct vcpu_svm *svm = to_svm(vcpu);
1477
1478         if (!kvm_vcpu_apicv_active(vcpu))
1479                 return;
1480
1481         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1482                 return;
1483
1484         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1485         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1486
1487         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1488         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1489
1490         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1491         if (svm->avic_is_running)
1492                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1493
1494         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1495         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1496                                         svm->avic_is_running);
1497 }
1498
1499 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1500 {
1501         u64 entry;
1502         struct vcpu_svm *svm = to_svm(vcpu);
1503
1504         if (!kvm_vcpu_apicv_active(vcpu))
1505                 return;
1506
1507         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1508         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1509                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1510
1511         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1512         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1513 }
1514
1515 /**
1516  * This function is called during VCPU halt/unhalt.
1517  */
1518 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1519 {
1520         struct vcpu_svm *svm = to_svm(vcpu);
1521
1522         svm->avic_is_running = is_run;
1523         if (is_run)
1524                 avic_vcpu_load(vcpu, vcpu->cpu);
1525         else
1526                 avic_vcpu_put(vcpu);
1527 }
1528
1529 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1530 {
1531         struct vcpu_svm *svm = to_svm(vcpu);
1532         u32 dummy;
1533         u32 eax = 1;
1534
1535         if (!init_event) {
1536                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1537                                            MSR_IA32_APICBASE_ENABLE;
1538                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1539                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1540         }
1541         init_vmcb(svm);
1542
1543         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1544         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1545
1546         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1547                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1548 }
1549
1550 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1551 {
1552         struct vcpu_svm *svm;
1553         struct page *page;
1554         struct page *msrpm_pages;
1555         struct page *hsave_page;
1556         struct page *nested_msrpm_pages;
1557         int err;
1558
1559         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1560         if (!svm) {
1561                 err = -ENOMEM;
1562                 goto out;
1563         }
1564
1565         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1566         if (err)
1567                 goto free_svm;
1568
1569         err = -ENOMEM;
1570         page = alloc_page(GFP_KERNEL);
1571         if (!page)
1572                 goto uninit;
1573
1574         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1575         if (!msrpm_pages)
1576                 goto free_page1;
1577
1578         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1579         if (!nested_msrpm_pages)
1580                 goto free_page2;
1581
1582         hsave_page = alloc_page(GFP_KERNEL);
1583         if (!hsave_page)
1584                 goto free_page3;
1585
1586         if (avic) {
1587                 err = avic_init_backing_page(&svm->vcpu);
1588                 if (err)
1589                         goto free_page4;
1590
1591                 INIT_LIST_HEAD(&svm->ir_list);
1592                 spin_lock_init(&svm->ir_list_lock);
1593         }
1594
1595         /* We initialize this flag to true to make sure that the is_running
1596          * bit would be set the first time the vcpu is loaded.
1597          */
1598         svm->avic_is_running = true;
1599
1600         svm->nested.hsave = page_address(hsave_page);
1601
1602         svm->msrpm = page_address(msrpm_pages);
1603         svm_vcpu_init_msrpm(svm->msrpm);
1604
1605         svm->nested.msrpm = page_address(nested_msrpm_pages);
1606         svm_vcpu_init_msrpm(svm->nested.msrpm);
1607
1608         svm->vmcb = page_address(page);
1609         clear_page(svm->vmcb);
1610         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1611         svm->asid_generation = 0;
1612         init_vmcb(svm);
1613
1614         svm_init_osvw(&svm->vcpu);
1615
1616         return &svm->vcpu;
1617
1618 free_page4:
1619         __free_page(hsave_page);
1620 free_page3:
1621         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1622 free_page2:
1623         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1624 free_page1:
1625         __free_page(page);
1626 uninit:
1627         kvm_vcpu_uninit(&svm->vcpu);
1628 free_svm:
1629         kmem_cache_free(kvm_vcpu_cache, svm);
1630 out:
1631         return ERR_PTR(err);
1632 }
1633
1634 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1635 {
1636         struct vcpu_svm *svm = to_svm(vcpu);
1637
1638         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1639         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1640         __free_page(virt_to_page(svm->nested.hsave));
1641         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1642         kvm_vcpu_uninit(vcpu);
1643         kmem_cache_free(kvm_vcpu_cache, svm);
1644 }
1645
1646 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1647 {
1648         struct vcpu_svm *svm = to_svm(vcpu);
1649         int i;
1650
1651         if (unlikely(cpu != vcpu->cpu)) {
1652                 svm->asid_generation = 0;
1653                 mark_all_dirty(svm->vmcb);
1654         }
1655
1656 #ifdef CONFIG_X86_64
1657         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1658 #endif
1659         savesegment(fs, svm->host.fs);
1660         savesegment(gs, svm->host.gs);
1661         svm->host.ldt = kvm_read_ldt();
1662
1663         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1664                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1665
1666         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1667                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1668                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1669                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1670                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1671                 }
1672         }
1673         /* This assumes that the kernel never uses MSR_TSC_AUX */
1674         if (static_cpu_has(X86_FEATURE_RDTSCP))
1675                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1676
1677         avic_vcpu_load(vcpu, cpu);
1678 }
1679
1680 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1681 {
1682         struct vcpu_svm *svm = to_svm(vcpu);
1683         int i;
1684
1685         avic_vcpu_put(vcpu);
1686
1687         ++vcpu->stat.host_state_reload;
1688         kvm_load_ldt(svm->host.ldt);
1689 #ifdef CONFIG_X86_64
1690         loadsegment(fs, svm->host.fs);
1691         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1692         load_gs_index(svm->host.gs);
1693 #else
1694 #ifdef CONFIG_X86_32_LAZY_GS
1695         loadsegment(gs, svm->host.gs);
1696 #endif
1697 #endif
1698         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1699                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1700 }
1701
1702 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1703 {
1704         avic_set_running(vcpu, false);
1705 }
1706
1707 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1708 {
1709         avic_set_running(vcpu, true);
1710 }
1711
1712 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1713 {
1714         return to_svm(vcpu)->vmcb->save.rflags;
1715 }
1716
1717 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1718 {
1719        /*
1720         * Any change of EFLAGS.VM is accompanied by a reload of SS
1721         * (caused by either a task switch or an inter-privilege IRET),
1722         * so we do not need to update the CPL here.
1723         */
1724         to_svm(vcpu)->vmcb->save.rflags = rflags;
1725 }
1726
1727 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1728 {
1729         return 0;
1730 }
1731
1732 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1733 {
1734         switch (reg) {
1735         case VCPU_EXREG_PDPTR:
1736                 BUG_ON(!npt_enabled);
1737                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1738                 break;
1739         default:
1740                 BUG();
1741         }
1742 }
1743
1744 static void svm_set_vintr(struct vcpu_svm *svm)
1745 {
1746         set_intercept(svm, INTERCEPT_VINTR);
1747 }
1748
1749 static void svm_clear_vintr(struct vcpu_svm *svm)
1750 {
1751         clr_intercept(svm, INTERCEPT_VINTR);
1752 }
1753
1754 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1755 {
1756         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1757
1758         switch (seg) {
1759         case VCPU_SREG_CS: return &save->cs;
1760         case VCPU_SREG_DS: return &save->ds;
1761         case VCPU_SREG_ES: return &save->es;
1762         case VCPU_SREG_FS: return &save->fs;
1763         case VCPU_SREG_GS: return &save->gs;
1764         case VCPU_SREG_SS: return &save->ss;
1765         case VCPU_SREG_TR: return &save->tr;
1766         case VCPU_SREG_LDTR: return &save->ldtr;
1767         }
1768         BUG();
1769         return NULL;
1770 }
1771
1772 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1773 {
1774         struct vmcb_seg *s = svm_seg(vcpu, seg);
1775
1776         return s->base;
1777 }
1778
1779 static void svm_get_segment(struct kvm_vcpu *vcpu,
1780                             struct kvm_segment *var, int seg)
1781 {
1782         struct vmcb_seg *s = svm_seg(vcpu, seg);
1783
1784         var->base = s->base;
1785         var->limit = s->limit;
1786         var->selector = s->selector;
1787         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1788         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1789         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1790         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1791         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1792         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1793         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1794
1795         /*
1796          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1797          * However, the SVM spec states that the G bit is not observed by the
1798          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1799          * So let's synthesize a legal G bit for all segments, this helps
1800          * running KVM nested. It also helps cross-vendor migration, because
1801          * Intel's vmentry has a check on the 'G' bit.
1802          */
1803         var->g = s->limit > 0xfffff;
1804
1805         /*
1806          * AMD's VMCB does not have an explicit unusable field, so emulate it
1807          * for cross vendor migration purposes by "not present"
1808          */
1809         var->unusable = !var->present || (var->type == 0);
1810
1811         switch (seg) {
1812         case VCPU_SREG_TR:
1813                 /*
1814                  * Work around a bug where the busy flag in the tr selector
1815                  * isn't exposed
1816                  */
1817                 var->type |= 0x2;
1818                 break;
1819         case VCPU_SREG_DS:
1820         case VCPU_SREG_ES:
1821         case VCPU_SREG_FS:
1822         case VCPU_SREG_GS:
1823                 /*
1824                  * The accessed bit must always be set in the segment
1825                  * descriptor cache, although it can be cleared in the
1826                  * descriptor, the cached bit always remains at 1. Since
1827                  * Intel has a check on this, set it here to support
1828                  * cross-vendor migration.
1829                  */
1830                 if (!var->unusable)
1831                         var->type |= 0x1;
1832                 break;
1833         case VCPU_SREG_SS:
1834                 /*
1835                  * On AMD CPUs sometimes the DB bit in the segment
1836                  * descriptor is left as 1, although the whole segment has
1837                  * been made unusable. Clear it here to pass an Intel VMX
1838                  * entry check when cross vendor migrating.
1839                  */
1840                 if (var->unusable)
1841                         var->db = 0;
1842                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1843                 break;
1844         }
1845 }
1846
1847 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1848 {
1849         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1850
1851         return save->cpl;
1852 }
1853
1854 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1855 {
1856         struct vcpu_svm *svm = to_svm(vcpu);
1857
1858         dt->size = svm->vmcb->save.idtr.limit;
1859         dt->address = svm->vmcb->save.idtr.base;
1860 }
1861
1862 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1863 {
1864         struct vcpu_svm *svm = to_svm(vcpu);
1865
1866         svm->vmcb->save.idtr.limit = dt->size;
1867         svm->vmcb->save.idtr.base = dt->address ;
1868         mark_dirty(svm->vmcb, VMCB_DT);
1869 }
1870
1871 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1872 {
1873         struct vcpu_svm *svm = to_svm(vcpu);
1874
1875         dt->size = svm->vmcb->save.gdtr.limit;
1876         dt->address = svm->vmcb->save.gdtr.base;
1877 }
1878
1879 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1880 {
1881         struct vcpu_svm *svm = to_svm(vcpu);
1882
1883         svm->vmcb->save.gdtr.limit = dt->size;
1884         svm->vmcb->save.gdtr.base = dt->address ;
1885         mark_dirty(svm->vmcb, VMCB_DT);
1886 }
1887
1888 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1889 {
1890 }
1891
1892 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1893 {
1894 }
1895
1896 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1897 {
1898 }
1899
1900 static void update_cr0_intercept(struct vcpu_svm *svm)
1901 {
1902         ulong gcr0 = svm->vcpu.arch.cr0;
1903         u64 *hcr0 = &svm->vmcb->save.cr0;
1904
1905         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1906                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1907
1908         mark_dirty(svm->vmcb, VMCB_CR);
1909
1910         if (gcr0 == *hcr0) {
1911                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1912                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1913         } else {
1914                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1915                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1916         }
1917 }
1918
1919 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1920 {
1921         struct vcpu_svm *svm = to_svm(vcpu);
1922
1923 #ifdef CONFIG_X86_64
1924         if (vcpu->arch.efer & EFER_LME) {
1925                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1926                         vcpu->arch.efer |= EFER_LMA;
1927                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1928                 }
1929
1930                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1931                         vcpu->arch.efer &= ~EFER_LMA;
1932                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1933                 }
1934         }
1935 #endif
1936         vcpu->arch.cr0 = cr0;
1937
1938         if (!npt_enabled)
1939                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1940
1941         /*
1942          * re-enable caching here because the QEMU bios
1943          * does not do it - this results in some delay at
1944          * reboot
1945          */
1946         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1947                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1948         svm->vmcb->save.cr0 = cr0;
1949         mark_dirty(svm->vmcb, VMCB_CR);
1950         update_cr0_intercept(svm);
1951 }
1952
1953 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1954 {
1955         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1956         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1957
1958         if (cr4 & X86_CR4_VMXE)
1959                 return 1;
1960
1961         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1962                 svm_flush_tlb(vcpu);
1963
1964         vcpu->arch.cr4 = cr4;
1965         if (!npt_enabled)
1966                 cr4 |= X86_CR4_PAE;
1967         cr4 |= host_cr4_mce;
1968         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1969         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1970         return 0;
1971 }
1972
1973 static void svm_set_segment(struct kvm_vcpu *vcpu,
1974                             struct kvm_segment *var, int seg)
1975 {
1976         struct vcpu_svm *svm = to_svm(vcpu);
1977         struct vmcb_seg *s = svm_seg(vcpu, seg);
1978
1979         s->base = var->base;
1980         s->limit = var->limit;
1981         s->selector = var->selector;
1982         if (var->unusable)
1983                 s->attrib = 0;
1984         else {
1985                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1986                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1987                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1988                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1989                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1990                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1991                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1992                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1993         }
1994
1995         /*
1996          * This is always accurate, except if SYSRET returned to a segment
1997          * with SS.DPL != 3.  Intel does not have this quirk, and always
1998          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1999          * would entail passing the CPL to userspace and back.
2000          */
2001         if (seg == VCPU_SREG_SS)
2002                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2003
2004         mark_dirty(svm->vmcb, VMCB_SEG);
2005 }
2006
2007 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2008 {
2009         struct vcpu_svm *svm = to_svm(vcpu);
2010
2011         clr_exception_intercept(svm, BP_VECTOR);
2012
2013         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2014                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2015                         set_exception_intercept(svm, BP_VECTOR);
2016         } else
2017                 vcpu->guest_debug = 0;
2018 }
2019
2020 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2021 {
2022         if (sd->next_asid > sd->max_asid) {
2023                 ++sd->asid_generation;
2024                 sd->next_asid = 1;
2025                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2026         }
2027
2028         svm->asid_generation = sd->asid_generation;
2029         svm->vmcb->control.asid = sd->next_asid++;
2030
2031         mark_dirty(svm->vmcb, VMCB_ASID);
2032 }
2033
2034 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2035 {
2036         return to_svm(vcpu)->vmcb->save.dr6;
2037 }
2038
2039 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2040 {
2041         struct vcpu_svm *svm = to_svm(vcpu);
2042
2043         svm->vmcb->save.dr6 = value;
2044         mark_dirty(svm->vmcb, VMCB_DR);
2045 }
2046
2047 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2048 {
2049         struct vcpu_svm *svm = to_svm(vcpu);
2050
2051         get_debugreg(vcpu->arch.db[0], 0);
2052         get_debugreg(vcpu->arch.db[1], 1);
2053         get_debugreg(vcpu->arch.db[2], 2);
2054         get_debugreg(vcpu->arch.db[3], 3);
2055         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2056         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2057
2058         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2059         set_dr_intercepts(svm);
2060 }
2061
2062 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2063 {
2064         struct vcpu_svm *svm = to_svm(vcpu);
2065
2066         svm->vmcb->save.dr7 = value;
2067         mark_dirty(svm->vmcb, VMCB_DR);
2068 }
2069
2070 static int pf_interception(struct vcpu_svm *svm)
2071 {
2072         u64 fault_address = svm->vmcb->control.exit_info_2;
2073         u64 error_code;
2074         int r = 1;
2075
2076         switch (svm->apf_reason) {
2077         default:
2078                 error_code = svm->vmcb->control.exit_info_1;
2079
2080                 trace_kvm_page_fault(fault_address, error_code);
2081                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2082                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2083                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2084                         svm->vmcb->control.insn_bytes,
2085                         svm->vmcb->control.insn_len);
2086                 break;
2087         case KVM_PV_REASON_PAGE_NOT_PRESENT:
2088                 svm->apf_reason = 0;
2089                 local_irq_disable();
2090                 kvm_async_pf_task_wait(fault_address);
2091                 local_irq_enable();
2092                 break;
2093         case KVM_PV_REASON_PAGE_READY:
2094                 svm->apf_reason = 0;
2095                 local_irq_disable();
2096                 kvm_async_pf_task_wake(fault_address);
2097                 local_irq_enable();
2098                 break;
2099         }
2100         return r;
2101 }
2102
2103 static int db_interception(struct vcpu_svm *svm)
2104 {
2105         struct kvm_run *kvm_run = svm->vcpu.run;
2106
2107         if (!(svm->vcpu.guest_debug &
2108               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2109                 !svm->nmi_singlestep) {
2110                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2111                 return 1;
2112         }
2113
2114         if (svm->nmi_singlestep) {
2115                 svm->nmi_singlestep = false;
2116                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2117                         svm->vmcb->save.rflags &=
2118                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2119         }
2120
2121         if (svm->vcpu.guest_debug &
2122             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2123                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2124                 kvm_run->debug.arch.pc =
2125                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2126                 kvm_run->debug.arch.exception = DB_VECTOR;
2127                 return 0;
2128         }
2129
2130         return 1;
2131 }
2132
2133 static int bp_interception(struct vcpu_svm *svm)
2134 {
2135         struct kvm_run *kvm_run = svm->vcpu.run;
2136
2137         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2138         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2139         kvm_run->debug.arch.exception = BP_VECTOR;
2140         return 0;
2141 }
2142
2143 static int ud_interception(struct vcpu_svm *svm)
2144 {
2145         int er;
2146
2147         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2148         if (er != EMULATE_DONE)
2149                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2150         return 1;
2151 }
2152
2153 static int ac_interception(struct vcpu_svm *svm)
2154 {
2155         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2156         return 1;
2157 }
2158
2159 static bool is_erratum_383(void)
2160 {
2161         int err, i;
2162         u64 value;
2163
2164         if (!erratum_383_found)
2165                 return false;
2166
2167         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2168         if (err)
2169                 return false;
2170
2171         /* Bit 62 may or may not be set for this mce */
2172         value &= ~(1ULL << 62);
2173
2174         if (value != 0xb600000000010015ULL)
2175                 return false;
2176
2177         /* Clear MCi_STATUS registers */
2178         for (i = 0; i < 6; ++i)
2179                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2180
2181         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2182         if (!err) {
2183                 u32 low, high;
2184
2185                 value &= ~(1ULL << 2);
2186                 low    = lower_32_bits(value);
2187                 high   = upper_32_bits(value);
2188
2189                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2190         }
2191
2192         /* Flush tlb to evict multi-match entries */
2193         __flush_tlb_all();
2194
2195         return true;
2196 }
2197
2198 static void svm_handle_mce(struct vcpu_svm *svm)
2199 {
2200         if (is_erratum_383()) {
2201                 /*
2202                  * Erratum 383 triggered. Guest state is corrupt so kill the
2203                  * guest.
2204                  */
2205                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2206
2207                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2208
2209                 return;
2210         }
2211
2212         /*
2213          * On an #MC intercept the MCE handler is not called automatically in
2214          * the host. So do it by hand here.
2215          */
2216         asm volatile (
2217                 "int $0x12\n");
2218         /* not sure if we ever come back to this point */
2219
2220         return;
2221 }
2222
2223 static int mc_interception(struct vcpu_svm *svm)
2224 {
2225         return 1;
2226 }
2227
2228 static int shutdown_interception(struct vcpu_svm *svm)
2229 {
2230         struct kvm_run *kvm_run = svm->vcpu.run;
2231
2232         /*
2233          * VMCB is undefined after a SHUTDOWN intercept
2234          * so reinitialize it.
2235          */
2236         clear_page(svm->vmcb);
2237         init_vmcb(svm);
2238
2239         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2240         return 0;
2241 }
2242
2243 static int io_interception(struct vcpu_svm *svm)
2244 {
2245         struct kvm_vcpu *vcpu = &svm->vcpu;
2246         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2247         int size, in, string;
2248         unsigned port;
2249
2250         ++svm->vcpu.stat.io_exits;
2251         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2252         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2253         if (string)
2254                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2255
2256         port = io_info >> 16;
2257         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2258         svm->next_rip = svm->vmcb->control.exit_info_2;
2259         skip_emulated_instruction(&svm->vcpu);
2260
2261         return in ? kvm_fast_pio_in(vcpu, size, port)
2262                   : kvm_fast_pio_out(vcpu, size, port);
2263 }
2264
2265 static int nmi_interception(struct vcpu_svm *svm)
2266 {
2267         return 1;
2268 }
2269
2270 static int intr_interception(struct vcpu_svm *svm)
2271 {
2272         ++svm->vcpu.stat.irq_exits;
2273         return 1;
2274 }
2275
2276 static int nop_on_interception(struct vcpu_svm *svm)
2277 {
2278         return 1;
2279 }
2280
2281 static int halt_interception(struct vcpu_svm *svm)
2282 {
2283         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2284         return kvm_emulate_halt(&svm->vcpu);
2285 }
2286
2287 static int vmmcall_interception(struct vcpu_svm *svm)
2288 {
2289         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2290         return kvm_emulate_hypercall(&svm->vcpu);
2291 }
2292
2293 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2294 {
2295         struct vcpu_svm *svm = to_svm(vcpu);
2296
2297         return svm->nested.nested_cr3;
2298 }
2299
2300 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2301 {
2302         struct vcpu_svm *svm = to_svm(vcpu);
2303         u64 cr3 = svm->nested.nested_cr3;
2304         u64 pdpte;
2305         int ret;
2306
2307         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2308                                        offset_in_page(cr3) + index * 8, 8);
2309         if (ret)
2310                 return 0;
2311         return pdpte;
2312 }
2313
2314 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2315                                    unsigned long root)
2316 {
2317         struct vcpu_svm *svm = to_svm(vcpu);
2318
2319         svm->vmcb->control.nested_cr3 = root;
2320         mark_dirty(svm->vmcb, VMCB_NPT);
2321         svm_flush_tlb(vcpu);
2322 }
2323
2324 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2325                                        struct x86_exception *fault)
2326 {
2327         struct vcpu_svm *svm = to_svm(vcpu);
2328
2329         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2330                 /*
2331                  * TODO: track the cause of the nested page fault, and
2332                  * correctly fill in the high bits of exit_info_1.
2333                  */
2334                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2335                 svm->vmcb->control.exit_code_hi = 0;
2336                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2337                 svm->vmcb->control.exit_info_2 = fault->address;
2338         }
2339
2340         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2341         svm->vmcb->control.exit_info_1 |= fault->error_code;
2342
2343         /*
2344          * The present bit is always zero for page structure faults on real
2345          * hardware.
2346          */
2347         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2348                 svm->vmcb->control.exit_info_1 &= ~1;
2349
2350         nested_svm_vmexit(svm);
2351 }
2352
2353 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2354 {
2355         WARN_ON(mmu_is_nested(vcpu));
2356         kvm_init_shadow_mmu(vcpu);
2357         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2358         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2359         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2360         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2361         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2362         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2363         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2364 }
2365
2366 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2367 {
2368         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2369 }
2370
2371 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2372 {
2373         if (!(svm->vcpu.arch.efer & EFER_SVME)
2374             || !is_paging(&svm->vcpu)) {
2375                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2376                 return 1;
2377         }
2378
2379         if (svm->vmcb->save.cpl) {
2380                 kvm_inject_gp(&svm->vcpu, 0);
2381                 return 1;
2382         }
2383
2384        return 0;
2385 }
2386
2387 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2388                                       bool has_error_code, u32 error_code)
2389 {
2390         int vmexit;
2391
2392         if (!is_guest_mode(&svm->vcpu))
2393                 return 0;
2394
2395         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2396         svm->vmcb->control.exit_code_hi = 0;
2397         svm->vmcb->control.exit_info_1 = error_code;
2398         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2399
2400         vmexit = nested_svm_intercept(svm);
2401         if (vmexit == NESTED_EXIT_DONE)
2402                 svm->nested.exit_required = true;
2403
2404         return vmexit;
2405 }
2406
2407 /* This function returns true if it is save to enable the irq window */
2408 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2409 {
2410         if (!is_guest_mode(&svm->vcpu))
2411                 return true;
2412
2413         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2414                 return true;
2415
2416         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2417                 return false;
2418
2419         /*
2420          * if vmexit was already requested (by intercepted exception
2421          * for instance) do not overwrite it with "external interrupt"
2422          * vmexit.
2423          */
2424         if (svm->nested.exit_required)
2425                 return false;
2426
2427         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2428         svm->vmcb->control.exit_info_1 = 0;
2429         svm->vmcb->control.exit_info_2 = 0;
2430
2431         if (svm->nested.intercept & 1ULL) {
2432                 /*
2433                  * The #vmexit can't be emulated here directly because this
2434                  * code path runs with irqs and preemption disabled. A
2435                  * #vmexit emulation might sleep. Only signal request for
2436                  * the #vmexit here.
2437                  */
2438                 svm->nested.exit_required = true;
2439                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2440                 return false;
2441         }
2442
2443         return true;
2444 }
2445
2446 /* This function returns true if it is save to enable the nmi window */
2447 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2448 {
2449         if (!is_guest_mode(&svm->vcpu))
2450                 return true;
2451
2452         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2453                 return true;
2454
2455         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2456         svm->nested.exit_required = true;
2457
2458         return false;
2459 }
2460
2461 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2462 {
2463         struct page *page;
2464
2465         might_sleep();
2466
2467         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2468         if (is_error_page(page))
2469                 goto error;
2470
2471         *_page = page;
2472
2473         return kmap(page);
2474
2475 error:
2476         kvm_inject_gp(&svm->vcpu, 0);
2477
2478         return NULL;
2479 }
2480
2481 static void nested_svm_unmap(struct page *page)
2482 {
2483         kunmap(page);
2484         kvm_release_page_dirty(page);
2485 }
2486
2487 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2488 {
2489         unsigned port, size, iopm_len;
2490         u16 val, mask;
2491         u8 start_bit;
2492         u64 gpa;
2493
2494         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2495                 return NESTED_EXIT_HOST;
2496
2497         port = svm->vmcb->control.exit_info_1 >> 16;
2498         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2499                 SVM_IOIO_SIZE_SHIFT;
2500         gpa  = svm->nested.vmcb_iopm + (port / 8);
2501         start_bit = port % 8;
2502         iopm_len = (start_bit + size > 8) ? 2 : 1;
2503         mask = (0xf >> (4 - size)) << start_bit;
2504         val = 0;
2505
2506         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2507                 return NESTED_EXIT_DONE;
2508
2509         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2510 }
2511
2512 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2513 {
2514         u32 offset, msr, value;
2515         int write, mask;
2516
2517         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2518                 return NESTED_EXIT_HOST;
2519
2520         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2521         offset = svm_msrpm_offset(msr);
2522         write  = svm->vmcb->control.exit_info_1 & 1;
2523         mask   = 1 << ((2 * (msr & 0xf)) + write);
2524
2525         if (offset == MSR_INVALID)
2526                 return NESTED_EXIT_DONE;
2527
2528         /* Offset is in 32 bit units but need in 8 bit units */
2529         offset *= 4;
2530
2531         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2532                 return NESTED_EXIT_DONE;
2533
2534         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2535 }
2536
2537 static int nested_svm_exit_special(struct vcpu_svm *svm)
2538 {
2539         u32 exit_code = svm->vmcb->control.exit_code;
2540
2541         switch (exit_code) {
2542         case SVM_EXIT_INTR:
2543         case SVM_EXIT_NMI:
2544         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2545                 return NESTED_EXIT_HOST;
2546         case SVM_EXIT_NPF:
2547                 /* For now we are always handling NPFs when using them */
2548                 if (npt_enabled)
2549                         return NESTED_EXIT_HOST;
2550                 break;
2551         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2552                 /* When we're shadowing, trap PFs, but not async PF */
2553                 if (!npt_enabled && svm->apf_reason == 0)
2554                         return NESTED_EXIT_HOST;
2555                 break;
2556         default:
2557                 break;
2558         }
2559
2560         return NESTED_EXIT_CONTINUE;
2561 }
2562
2563 /*
2564  * If this function returns true, this #vmexit was already handled
2565  */
2566 static int nested_svm_intercept(struct vcpu_svm *svm)
2567 {
2568         u32 exit_code = svm->vmcb->control.exit_code;
2569         int vmexit = NESTED_EXIT_HOST;
2570
2571         switch (exit_code) {
2572         case SVM_EXIT_MSR:
2573                 vmexit = nested_svm_exit_handled_msr(svm);
2574                 break;
2575         case SVM_EXIT_IOIO:
2576                 vmexit = nested_svm_intercept_ioio(svm);
2577                 break;
2578         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2579                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2580                 if (svm->nested.intercept_cr & bit)
2581                         vmexit = NESTED_EXIT_DONE;
2582                 break;
2583         }
2584         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2585                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2586                 if (svm->nested.intercept_dr & bit)
2587                         vmexit = NESTED_EXIT_DONE;
2588                 break;
2589         }
2590         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2591                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2592                 if (svm->nested.intercept_exceptions & excp_bits)
2593                         vmexit = NESTED_EXIT_DONE;
2594                 /* async page fault always cause vmexit */
2595                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2596                          svm->apf_reason != 0)
2597                         vmexit = NESTED_EXIT_DONE;
2598                 break;
2599         }
2600         case SVM_EXIT_ERR: {
2601                 vmexit = NESTED_EXIT_DONE;
2602                 break;
2603         }
2604         default: {
2605                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2606                 if (svm->nested.intercept & exit_bits)
2607                         vmexit = NESTED_EXIT_DONE;
2608         }
2609         }
2610
2611         return vmexit;
2612 }
2613
2614 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2615 {
2616         int vmexit;
2617
2618         vmexit = nested_svm_intercept(svm);
2619
2620         if (vmexit == NESTED_EXIT_DONE)
2621                 nested_svm_vmexit(svm);
2622
2623         return vmexit;
2624 }
2625
2626 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2627 {
2628         struct vmcb_control_area *dst  = &dst_vmcb->control;
2629         struct vmcb_control_area *from = &from_vmcb->control;
2630
2631         dst->intercept_cr         = from->intercept_cr;
2632         dst->intercept_dr         = from->intercept_dr;
2633         dst->intercept_exceptions = from->intercept_exceptions;
2634         dst->intercept            = from->intercept;
2635         dst->iopm_base_pa         = from->iopm_base_pa;
2636         dst->msrpm_base_pa        = from->msrpm_base_pa;
2637         dst->tsc_offset           = from->tsc_offset;
2638         dst->asid                 = from->asid;
2639         dst->tlb_ctl              = from->tlb_ctl;
2640         dst->int_ctl              = from->int_ctl;
2641         dst->int_vector           = from->int_vector;
2642         dst->int_state            = from->int_state;
2643         dst->exit_code            = from->exit_code;
2644         dst->exit_code_hi         = from->exit_code_hi;
2645         dst->exit_info_1          = from->exit_info_1;
2646         dst->exit_info_2          = from->exit_info_2;
2647         dst->exit_int_info        = from->exit_int_info;
2648         dst->exit_int_info_err    = from->exit_int_info_err;
2649         dst->nested_ctl           = from->nested_ctl;
2650         dst->event_inj            = from->event_inj;
2651         dst->event_inj_err        = from->event_inj_err;
2652         dst->nested_cr3           = from->nested_cr3;
2653         dst->lbr_ctl              = from->lbr_ctl;
2654 }
2655
2656 static int nested_svm_vmexit(struct vcpu_svm *svm)
2657 {
2658         struct vmcb *nested_vmcb;
2659         struct vmcb *hsave = svm->nested.hsave;
2660         struct vmcb *vmcb = svm->vmcb;
2661         struct page *page;
2662
2663         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2664                                        vmcb->control.exit_info_1,
2665                                        vmcb->control.exit_info_2,
2666                                        vmcb->control.exit_int_info,
2667                                        vmcb->control.exit_int_info_err,
2668                                        KVM_ISA_SVM);
2669
2670         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2671         if (!nested_vmcb)
2672                 return 1;
2673
2674         /* Exit Guest-Mode */
2675         leave_guest_mode(&svm->vcpu);
2676         svm->nested.vmcb = 0;
2677
2678         /* Give the current vmcb to the guest */
2679         disable_gif(svm);
2680
2681         nested_vmcb->save.es     = vmcb->save.es;
2682         nested_vmcb->save.cs     = vmcb->save.cs;
2683         nested_vmcb->save.ss     = vmcb->save.ss;
2684         nested_vmcb->save.ds     = vmcb->save.ds;
2685         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2686         nested_vmcb->save.idtr   = vmcb->save.idtr;
2687         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2688         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2689         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2690         nested_vmcb->save.cr2    = vmcb->save.cr2;
2691         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2692         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2693         nested_vmcb->save.rip    = vmcb->save.rip;
2694         nested_vmcb->save.rsp    = vmcb->save.rsp;
2695         nested_vmcb->save.rax    = vmcb->save.rax;
2696         nested_vmcb->save.dr7    = vmcb->save.dr7;
2697         nested_vmcb->save.dr6    = vmcb->save.dr6;
2698         nested_vmcb->save.cpl    = vmcb->save.cpl;
2699
2700         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2701         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2702         nested_vmcb->control.int_state         = vmcb->control.int_state;
2703         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2704         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2705         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2706         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2707         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2708         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2709
2710         if (svm->nrips_enabled)
2711                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2712
2713         /*
2714          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2715          * to make sure that we do not lose injected events. So check event_inj
2716          * here and copy it to exit_int_info if it is valid.
2717          * Exit_int_info and event_inj can't be both valid because the case
2718          * below only happens on a VMRUN instruction intercept which has
2719          * no valid exit_int_info set.
2720          */
2721         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2722                 struct vmcb_control_area *nc = &nested_vmcb->control;
2723
2724                 nc->exit_int_info     = vmcb->control.event_inj;
2725                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2726         }
2727
2728         nested_vmcb->control.tlb_ctl           = 0;
2729         nested_vmcb->control.event_inj         = 0;
2730         nested_vmcb->control.event_inj_err     = 0;
2731
2732         /* We always set V_INTR_MASKING and remember the old value in hflags */
2733         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2734                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2735
2736         /* Restore the original control entries */
2737         copy_vmcb_control_area(vmcb, hsave);
2738
2739         kvm_clear_exception_queue(&svm->vcpu);
2740         kvm_clear_interrupt_queue(&svm->vcpu);
2741
2742         svm->nested.nested_cr3 = 0;
2743
2744         /* Restore selected save entries */
2745         svm->vmcb->save.es = hsave->save.es;
2746         svm->vmcb->save.cs = hsave->save.cs;
2747         svm->vmcb->save.ss = hsave->save.ss;
2748         svm->vmcb->save.ds = hsave->save.ds;
2749         svm->vmcb->save.gdtr = hsave->save.gdtr;
2750         svm->vmcb->save.idtr = hsave->save.idtr;
2751         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2752         svm_set_efer(&svm->vcpu, hsave->save.efer);
2753         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2754         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2755         if (npt_enabled) {
2756                 svm->vmcb->save.cr3 = hsave->save.cr3;
2757                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2758         } else {
2759                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2760         }
2761         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2762         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2763         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2764         svm->vmcb->save.dr7 = 0;
2765         svm->vmcb->save.cpl = 0;
2766         svm->vmcb->control.exit_int_info = 0;
2767
2768         mark_all_dirty(svm->vmcb);
2769
2770         nested_svm_unmap(page);
2771
2772         nested_svm_uninit_mmu_context(&svm->vcpu);
2773         kvm_mmu_reset_context(&svm->vcpu);
2774         kvm_mmu_load(&svm->vcpu);
2775
2776         return 0;
2777 }
2778
2779 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2780 {
2781         /*
2782          * This function merges the msr permission bitmaps of kvm and the
2783          * nested vmcb. It is optimized in that it only merges the parts where
2784          * the kvm msr permission bitmap may contain zero bits
2785          */
2786         int i;
2787
2788         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2789                 return true;
2790
2791         for (i = 0; i < MSRPM_OFFSETS; i++) {
2792                 u32 value, p;
2793                 u64 offset;
2794
2795                 if (msrpm_offsets[i] == 0xffffffff)
2796                         break;
2797
2798                 p      = msrpm_offsets[i];
2799                 offset = svm->nested.vmcb_msrpm + (p * 4);
2800
2801                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2802                         return false;
2803
2804                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2805         }
2806
2807         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2808
2809         return true;
2810 }
2811
2812 static bool nested_vmcb_checks(struct vmcb *vmcb)
2813 {
2814         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2815                 return false;
2816
2817         if (vmcb->control.asid == 0)
2818                 return false;
2819
2820         if (vmcb->control.nested_ctl && !npt_enabled)
2821                 return false;
2822
2823         return true;
2824 }
2825
2826 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2827 {
2828         struct vmcb *nested_vmcb;
2829         struct vmcb *hsave = svm->nested.hsave;
2830         struct vmcb *vmcb = svm->vmcb;
2831         struct page *page;
2832         u64 vmcb_gpa;
2833
2834         vmcb_gpa = svm->vmcb->save.rax;
2835
2836         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2837         if (!nested_vmcb)
2838                 return false;
2839
2840         if (!nested_vmcb_checks(nested_vmcb)) {
2841                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2842                 nested_vmcb->control.exit_code_hi = 0;
2843                 nested_vmcb->control.exit_info_1  = 0;
2844                 nested_vmcb->control.exit_info_2  = 0;
2845
2846                 nested_svm_unmap(page);
2847
2848                 return false;
2849         }
2850
2851         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2852                                nested_vmcb->save.rip,
2853                                nested_vmcb->control.int_ctl,
2854                                nested_vmcb->control.event_inj,
2855                                nested_vmcb->control.nested_ctl);
2856
2857         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2858                                     nested_vmcb->control.intercept_cr >> 16,
2859                                     nested_vmcb->control.intercept_exceptions,
2860                                     nested_vmcb->control.intercept);
2861
2862         /* Clear internal status */
2863         kvm_clear_exception_queue(&svm->vcpu);
2864         kvm_clear_interrupt_queue(&svm->vcpu);
2865
2866         /*
2867          * Save the old vmcb, so we don't need to pick what we save, but can
2868          * restore everything when a VMEXIT occurs
2869          */
2870         hsave->save.es     = vmcb->save.es;
2871         hsave->save.cs     = vmcb->save.cs;
2872         hsave->save.ss     = vmcb->save.ss;
2873         hsave->save.ds     = vmcb->save.ds;
2874         hsave->save.gdtr   = vmcb->save.gdtr;
2875         hsave->save.idtr   = vmcb->save.idtr;
2876         hsave->save.efer   = svm->vcpu.arch.efer;
2877         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2878         hsave->save.cr4    = svm->vcpu.arch.cr4;
2879         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2880         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2881         hsave->save.rsp    = vmcb->save.rsp;
2882         hsave->save.rax    = vmcb->save.rax;
2883         if (npt_enabled)
2884                 hsave->save.cr3    = vmcb->save.cr3;
2885         else
2886                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2887
2888         copy_vmcb_control_area(hsave, vmcb);
2889
2890         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2891                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2892         else
2893                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2894
2895         if (nested_vmcb->control.nested_ctl) {
2896                 kvm_mmu_unload(&svm->vcpu);
2897                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2898                 nested_svm_init_mmu_context(&svm->vcpu);
2899         }
2900
2901         /* Load the nested guest state */
2902         svm->vmcb->save.es = nested_vmcb->save.es;
2903         svm->vmcb->save.cs = nested_vmcb->save.cs;
2904         svm->vmcb->save.ss = nested_vmcb->save.ss;
2905         svm->vmcb->save.ds = nested_vmcb->save.ds;
2906         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2907         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2908         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2909         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2910         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2911         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2912         if (npt_enabled) {
2913                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2914                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2915         } else
2916                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2917
2918         /* Guest paging mode is active - reset mmu */
2919         kvm_mmu_reset_context(&svm->vcpu);
2920
2921         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2922         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2923         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2924         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2925
2926         /* In case we don't even reach vcpu_run, the fields are not updated */
2927         svm->vmcb->save.rax = nested_vmcb->save.rax;
2928         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2929         svm->vmcb->save.rip = nested_vmcb->save.rip;
2930         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2931         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2932         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2933
2934         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2935         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2936
2937         /* cache intercepts */
2938         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2939         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2940         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2941         svm->nested.intercept            = nested_vmcb->control.intercept;
2942
2943         svm_flush_tlb(&svm->vcpu);
2944         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2945         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2946                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2947         else
2948                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2949
2950         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2951                 /* We only want the cr8 intercept bits of the guest */
2952                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2953                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2954         }
2955
2956         /* We don't want to see VMMCALLs from a nested guest */
2957         clr_intercept(svm, INTERCEPT_VMMCALL);
2958
2959         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2960         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2961         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2962         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2963         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2964         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2965
2966         nested_svm_unmap(page);
2967
2968         /* Enter Guest-Mode */
2969         enter_guest_mode(&svm->vcpu);
2970
2971         /*
2972          * Merge guest and host intercepts - must be called  with vcpu in
2973          * guest-mode to take affect here
2974          */
2975         recalc_intercepts(svm);
2976
2977         svm->nested.vmcb = vmcb_gpa;
2978
2979         enable_gif(svm);
2980
2981         mark_all_dirty(svm->vmcb);
2982
2983         return true;
2984 }
2985
2986 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2987 {
2988         to_vmcb->save.fs = from_vmcb->save.fs;
2989         to_vmcb->save.gs = from_vmcb->save.gs;
2990         to_vmcb->save.tr = from_vmcb->save.tr;
2991         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2992         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2993         to_vmcb->save.star = from_vmcb->save.star;
2994         to_vmcb->save.lstar = from_vmcb->save.lstar;
2995         to_vmcb->save.cstar = from_vmcb->save.cstar;
2996         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2997         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2998         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2999         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3000 }
3001
3002 static int vmload_interception(struct vcpu_svm *svm)
3003 {
3004         struct vmcb *nested_vmcb;
3005         struct page *page;
3006
3007         if (nested_svm_check_permissions(svm))
3008                 return 1;
3009
3010         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3011         if (!nested_vmcb)
3012                 return 1;
3013
3014         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3015         skip_emulated_instruction(&svm->vcpu);
3016
3017         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3018         nested_svm_unmap(page);
3019
3020         return 1;
3021 }
3022
3023 static int vmsave_interception(struct vcpu_svm *svm)
3024 {
3025         struct vmcb *nested_vmcb;
3026         struct page *page;
3027
3028         if (nested_svm_check_permissions(svm))
3029                 return 1;
3030
3031         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3032         if (!nested_vmcb)
3033                 return 1;
3034
3035         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3036         skip_emulated_instruction(&svm->vcpu);
3037
3038         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3039         nested_svm_unmap(page);
3040
3041         return 1;
3042 }
3043
3044 static int vmrun_interception(struct vcpu_svm *svm)
3045 {
3046         if (nested_svm_check_permissions(svm))
3047                 return 1;
3048
3049         /* Save rip after vmrun instruction */
3050         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3051
3052         if (!nested_svm_vmrun(svm))
3053                 return 1;
3054
3055         if (!nested_svm_vmrun_msrpm(svm))
3056                 goto failed;
3057
3058         return 1;
3059
3060 failed:
3061
3062         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3063         svm->vmcb->control.exit_code_hi = 0;
3064         svm->vmcb->control.exit_info_1  = 0;
3065         svm->vmcb->control.exit_info_2  = 0;
3066
3067         nested_svm_vmexit(svm);
3068
3069         return 1;
3070 }
3071
3072 static int stgi_interception(struct vcpu_svm *svm)
3073 {
3074         if (nested_svm_check_permissions(svm))
3075                 return 1;
3076
3077         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3078         skip_emulated_instruction(&svm->vcpu);
3079         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3080
3081         enable_gif(svm);
3082
3083         return 1;
3084 }
3085
3086 static int clgi_interception(struct vcpu_svm *svm)
3087 {
3088         if (nested_svm_check_permissions(svm))
3089                 return 1;
3090
3091         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3092         skip_emulated_instruction(&svm->vcpu);
3093
3094         disable_gif(svm);
3095
3096         /* After a CLGI no interrupts should come */
3097         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3098                 svm_clear_vintr(svm);
3099                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3100                 mark_dirty(svm->vmcb, VMCB_INTR);
3101         }
3102
3103         return 1;
3104 }
3105
3106 static int invlpga_interception(struct vcpu_svm *svm)
3107 {
3108         struct kvm_vcpu *vcpu = &svm->vcpu;
3109
3110         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3111                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3112
3113         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3114         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3115
3116         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3117         skip_emulated_instruction(&svm->vcpu);
3118         return 1;
3119 }
3120
3121 static int skinit_interception(struct vcpu_svm *svm)
3122 {
3123         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3124
3125         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3126         return 1;
3127 }
3128
3129 static int wbinvd_interception(struct vcpu_svm *svm)
3130 {
3131         return kvm_emulate_wbinvd(&svm->vcpu);
3132 }
3133
3134 static int xsetbv_interception(struct vcpu_svm *svm)
3135 {
3136         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3137         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3138
3139         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3140                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3141                 skip_emulated_instruction(&svm->vcpu);
3142         }
3143
3144         return 1;
3145 }
3146
3147 static int task_switch_interception(struct vcpu_svm *svm)
3148 {
3149         u16 tss_selector;
3150         int reason;
3151         int int_type = svm->vmcb->control.exit_int_info &
3152                 SVM_EXITINTINFO_TYPE_MASK;
3153         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3154         uint32_t type =
3155                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3156         uint32_t idt_v =
3157                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3158         bool has_error_code = false;
3159         u32 error_code = 0;
3160
3161         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3162
3163         if (svm->vmcb->control.exit_info_2 &
3164             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3165                 reason = TASK_SWITCH_IRET;
3166         else if (svm->vmcb->control.exit_info_2 &
3167                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3168                 reason = TASK_SWITCH_JMP;
3169         else if (idt_v)
3170                 reason = TASK_SWITCH_GATE;
3171         else
3172                 reason = TASK_SWITCH_CALL;
3173
3174         if (reason == TASK_SWITCH_GATE) {
3175                 switch (type) {
3176                 case SVM_EXITINTINFO_TYPE_NMI:
3177                         svm->vcpu.arch.nmi_injected = false;
3178                         break;
3179                 case SVM_EXITINTINFO_TYPE_EXEPT:
3180                         if (svm->vmcb->control.exit_info_2 &
3181                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3182                                 has_error_code = true;
3183                                 error_code =
3184                                         (u32)svm->vmcb->control.exit_info_2;
3185                         }
3186                         kvm_clear_exception_queue(&svm->vcpu);
3187                         break;
3188                 case SVM_EXITINTINFO_TYPE_INTR:
3189                         kvm_clear_interrupt_queue(&svm->vcpu);
3190                         break;
3191                 default:
3192                         break;
3193                 }
3194         }
3195
3196         if (reason != TASK_SWITCH_GATE ||
3197             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3198             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3199              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3200                 skip_emulated_instruction(&svm->vcpu);
3201
3202         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3203                 int_vec = -1;
3204
3205         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3206                                 has_error_code, error_code) == EMULATE_FAIL) {
3207                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3208                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3209                 svm->vcpu.run->internal.ndata = 0;
3210                 return 0;
3211         }
3212         return 1;
3213 }
3214
3215 static int cpuid_interception(struct vcpu_svm *svm)
3216 {
3217         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3218         return kvm_emulate_cpuid(&svm->vcpu);
3219 }
3220
3221 static int iret_interception(struct vcpu_svm *svm)
3222 {
3223         ++svm->vcpu.stat.nmi_window_exits;
3224         clr_intercept(svm, INTERCEPT_IRET);
3225         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3226         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3227         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3228         return 1;
3229 }
3230
3231 static int invlpg_interception(struct vcpu_svm *svm)
3232 {
3233         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3234                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3235
3236         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3237         skip_emulated_instruction(&svm->vcpu);
3238         return 1;
3239 }
3240
3241 static int emulate_on_interception(struct vcpu_svm *svm)
3242 {
3243         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3244 }
3245
3246 static int rdpmc_interception(struct vcpu_svm *svm)
3247 {
3248         int err;
3249
3250         if (!static_cpu_has(X86_FEATURE_NRIPS))
3251                 return emulate_on_interception(svm);
3252
3253         err = kvm_rdpmc(&svm->vcpu);
3254         return kvm_complete_insn_gp(&svm->vcpu, err);
3255 }
3256
3257 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3258                                             unsigned long val)
3259 {
3260         unsigned long cr0 = svm->vcpu.arch.cr0;
3261         bool ret = false;
3262         u64 intercept;
3263
3264         intercept = svm->nested.intercept;
3265
3266         if (!is_guest_mode(&svm->vcpu) ||
3267             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3268                 return false;
3269
3270         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3271         val &= ~SVM_CR0_SELECTIVE_MASK;
3272
3273         if (cr0 ^ val) {
3274                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3275                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3276         }
3277
3278         return ret;
3279 }
3280
3281 #define CR_VALID (1ULL << 63)
3282
3283 static int cr_interception(struct vcpu_svm *svm)
3284 {
3285         int reg, cr;
3286         unsigned long val;
3287         int err;
3288
3289         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3290                 return emulate_on_interception(svm);
3291
3292         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3293                 return emulate_on_interception(svm);
3294
3295         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3296         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3297                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3298         else
3299                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3300
3301         err = 0;
3302         if (cr >= 16) { /* mov to cr */
3303                 cr -= 16;
3304                 val = kvm_register_read(&svm->vcpu, reg);
3305                 switch (cr) {
3306                 case 0:
3307                         if (!check_selective_cr0_intercepted(svm, val))
3308                                 err = kvm_set_cr0(&svm->vcpu, val);
3309                         else
3310                                 return 1;
3311
3312                         break;
3313                 case 3:
3314                         err = kvm_set_cr3(&svm->vcpu, val);
3315                         break;
3316                 case 4:
3317                         err = kvm_set_cr4(&svm->vcpu, val);
3318                         break;
3319                 case 8:
3320                         err = kvm_set_cr8(&svm->vcpu, val);
3321                         break;
3322                 default:
3323                         WARN(1, "unhandled write to CR%d", cr);
3324                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3325                         return 1;
3326                 }
3327         } else { /* mov from cr */
3328                 switch (cr) {
3329                 case 0:
3330                         val = kvm_read_cr0(&svm->vcpu);
3331                         break;
3332                 case 2:
3333                         val = svm->vcpu.arch.cr2;
3334                         break;
3335                 case 3:
3336                         val = kvm_read_cr3(&svm->vcpu);
3337                         break;
3338                 case 4:
3339                         val = kvm_read_cr4(&svm->vcpu);
3340                         break;
3341                 case 8:
3342                         val = kvm_get_cr8(&svm->vcpu);
3343                         break;
3344                 default:
3345                         WARN(1, "unhandled read from CR%d", cr);
3346                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3347                         return 1;
3348                 }
3349                 kvm_register_write(&svm->vcpu, reg, val);
3350         }
3351         return kvm_complete_insn_gp(&svm->vcpu, err);
3352 }
3353
3354 static int dr_interception(struct vcpu_svm *svm)
3355 {
3356         int reg, dr;
3357         unsigned long val;
3358
3359         if (svm->vcpu.guest_debug == 0) {
3360                 /*
3361                  * No more DR vmexits; force a reload of the debug registers
3362                  * and reenter on this instruction.  The next vmexit will
3363                  * retrieve the full state of the debug registers.
3364                  */
3365                 clr_dr_intercepts(svm);
3366                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3367                 return 1;
3368         }
3369
3370         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3371                 return emulate_on_interception(svm);
3372
3373         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3374         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3375
3376         if (dr >= 16) { /* mov to DRn */
3377                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3378                         return 1;
3379                 val = kvm_register_read(&svm->vcpu, reg);
3380                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3381         } else {
3382                 if (!kvm_require_dr(&svm->vcpu, dr))
3383                         return 1;
3384                 kvm_get_dr(&svm->vcpu, dr, &val);
3385                 kvm_register_write(&svm->vcpu, reg, val);
3386         }
3387
3388         skip_emulated_instruction(&svm->vcpu);
3389
3390         return 1;
3391 }
3392
3393 static int cr8_write_interception(struct vcpu_svm *svm)
3394 {
3395         struct kvm_run *kvm_run = svm->vcpu.run;
3396         int r;
3397
3398         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3399         /* instruction emulation calls kvm_set_cr8() */
3400         r = cr_interception(svm);
3401         if (lapic_in_kernel(&svm->vcpu))
3402                 return r;
3403         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3404                 return r;
3405         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3406         return 0;
3407 }
3408
3409 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3410 {
3411         struct vcpu_svm *svm = to_svm(vcpu);
3412
3413         switch (msr_info->index) {
3414         case MSR_IA32_TSC: {
3415                 msr_info->data = svm->vmcb->control.tsc_offset +
3416                         kvm_scale_tsc(vcpu, rdtsc());
3417
3418                 break;
3419         }
3420         case MSR_STAR:
3421                 msr_info->data = svm->vmcb->save.star;
3422                 break;
3423 #ifdef CONFIG_X86_64
3424         case MSR_LSTAR:
3425                 msr_info->data = svm->vmcb->save.lstar;
3426                 break;
3427         case MSR_CSTAR:
3428                 msr_info->data = svm->vmcb->save.cstar;
3429                 break;
3430         case MSR_KERNEL_GS_BASE:
3431                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3432                 break;
3433         case MSR_SYSCALL_MASK:
3434                 msr_info->data = svm->vmcb->save.sfmask;
3435                 break;
3436 #endif
3437         case MSR_IA32_SYSENTER_CS:
3438                 msr_info->data = svm->vmcb->save.sysenter_cs;
3439                 break;
3440         case MSR_IA32_SYSENTER_EIP:
3441                 msr_info->data = svm->sysenter_eip;
3442                 break;
3443         case MSR_IA32_SYSENTER_ESP:
3444                 msr_info->data = svm->sysenter_esp;
3445                 break;
3446         case MSR_TSC_AUX:
3447                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3448                         return 1;
3449                 msr_info->data = svm->tsc_aux;
3450                 break;
3451         /*
3452          * Nobody will change the following 5 values in the VMCB so we can
3453          * safely return them on rdmsr. They will always be 0 until LBRV is
3454          * implemented.
3455          */
3456         case MSR_IA32_DEBUGCTLMSR:
3457                 msr_info->data = svm->vmcb->save.dbgctl;
3458                 break;
3459         case MSR_IA32_LASTBRANCHFROMIP:
3460                 msr_info->data = svm->vmcb->save.br_from;
3461                 break;
3462         case MSR_IA32_LASTBRANCHTOIP:
3463                 msr_info->data = svm->vmcb->save.br_to;
3464                 break;
3465         case MSR_IA32_LASTINTFROMIP:
3466                 msr_info->data = svm->vmcb->save.last_excp_from;
3467                 break;
3468         case MSR_IA32_LASTINTTOIP:
3469                 msr_info->data = svm->vmcb->save.last_excp_to;
3470                 break;
3471         case MSR_VM_HSAVE_PA:
3472                 msr_info->data = svm->nested.hsave_msr;
3473                 break;
3474         case MSR_VM_CR:
3475                 msr_info->data = svm->nested.vm_cr_msr;
3476                 break;
3477         case MSR_IA32_UCODE_REV:
3478                 msr_info->data = 0x01000065;
3479                 break;
3480         case MSR_F15H_IC_CFG: {
3481
3482                 int family, model;
3483
3484                 family = guest_cpuid_family(vcpu);
3485                 model  = guest_cpuid_model(vcpu);
3486
3487                 if (family < 0 || model < 0)
3488                         return kvm_get_msr_common(vcpu, msr_info);
3489
3490                 msr_info->data = 0;
3491
3492                 if (family == 0x15 &&
3493                     (model >= 0x2 && model < 0x20))
3494                         msr_info->data = 0x1E;
3495                 }
3496                 break;
3497         default:
3498                 return kvm_get_msr_common(vcpu, msr_info);
3499         }
3500         return 0;
3501 }
3502
3503 static int rdmsr_interception(struct vcpu_svm *svm)
3504 {
3505         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3506         struct msr_data msr_info;
3507
3508         msr_info.index = ecx;
3509         msr_info.host_initiated = false;
3510         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3511                 trace_kvm_msr_read_ex(ecx);
3512                 kvm_inject_gp(&svm->vcpu, 0);
3513         } else {
3514                 trace_kvm_msr_read(ecx, msr_info.data);
3515
3516                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3517                                    msr_info.data & 0xffffffff);
3518                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3519                                    msr_info.data >> 32);
3520                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3521                 skip_emulated_instruction(&svm->vcpu);
3522         }
3523         return 1;
3524 }
3525
3526 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3527 {
3528         struct vcpu_svm *svm = to_svm(vcpu);
3529         int svm_dis, chg_mask;
3530
3531         if (data & ~SVM_VM_CR_VALID_MASK)
3532                 return 1;
3533
3534         chg_mask = SVM_VM_CR_VALID_MASK;
3535
3536         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3537                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3538
3539         svm->nested.vm_cr_msr &= ~chg_mask;
3540         svm->nested.vm_cr_msr |= (data & chg_mask);
3541
3542         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3543
3544         /* check for svm_disable while efer.svme is set */
3545         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3546                 return 1;
3547
3548         return 0;
3549 }
3550
3551 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3552 {
3553         struct vcpu_svm *svm = to_svm(vcpu);
3554
3555         u32 ecx = msr->index;
3556         u64 data = msr->data;
3557         switch (ecx) {
3558         case MSR_IA32_TSC:
3559                 kvm_write_tsc(vcpu, msr);
3560                 break;
3561         case MSR_STAR:
3562                 svm->vmcb->save.star = data;
3563                 break;
3564 #ifdef CONFIG_X86_64
3565         case MSR_LSTAR:
3566                 svm->vmcb->save.lstar = data;
3567                 break;
3568         case MSR_CSTAR:
3569                 svm->vmcb->save.cstar = data;
3570                 break;
3571         case MSR_KERNEL_GS_BASE:
3572                 svm->vmcb->save.kernel_gs_base = data;
3573                 break;
3574         case MSR_SYSCALL_MASK:
3575                 svm->vmcb->save.sfmask = data;
3576                 break;
3577 #endif
3578         case MSR_IA32_SYSENTER_CS:
3579                 svm->vmcb->save.sysenter_cs = data;
3580                 break;
3581         case MSR_IA32_SYSENTER_EIP:
3582                 svm->sysenter_eip = data;
3583                 svm->vmcb->save.sysenter_eip = data;
3584                 break;
3585         case MSR_IA32_SYSENTER_ESP:
3586                 svm->sysenter_esp = data;
3587                 svm->vmcb->save.sysenter_esp = data;
3588                 break;
3589         case MSR_TSC_AUX:
3590                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3591                         return 1;
3592
3593                 /*
3594                  * This is rare, so we update the MSR here instead of using
3595                  * direct_access_msrs.  Doing that would require a rdmsr in
3596                  * svm_vcpu_put.
3597                  */
3598                 svm->tsc_aux = data;
3599                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3600                 break;
3601         case MSR_IA32_DEBUGCTLMSR:
3602                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3603                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3604                                     __func__, data);
3605                         break;
3606                 }
3607                 if (data & DEBUGCTL_RESERVED_BITS)
3608                         return 1;
3609
3610                 svm->vmcb->save.dbgctl = data;
3611                 mark_dirty(svm->vmcb, VMCB_LBR);
3612                 if (data & (1ULL<<0))
3613                         svm_enable_lbrv(svm);
3614                 else
3615                         svm_disable_lbrv(svm);
3616                 break;
3617         case MSR_VM_HSAVE_PA:
3618                 svm->nested.hsave_msr = data;
3619                 break;
3620         case MSR_VM_CR:
3621                 return svm_set_vm_cr(vcpu, data);
3622         case MSR_VM_IGNNE:
3623                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3624                 break;
3625         case MSR_IA32_APICBASE:
3626                 if (kvm_vcpu_apicv_active(vcpu))
3627                         avic_update_vapic_bar(to_svm(vcpu), data);
3628                 /* Follow through */
3629         default:
3630                 return kvm_set_msr_common(vcpu, msr);
3631         }
3632         return 0;
3633 }
3634
3635 static int wrmsr_interception(struct vcpu_svm *svm)
3636 {
3637         struct msr_data msr;
3638         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3639         u64 data = kvm_read_edx_eax(&svm->vcpu);
3640
3641         msr.data = data;
3642         msr.index = ecx;
3643         msr.host_initiated = false;
3644
3645         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3646         if (kvm_set_msr(&svm->vcpu, &msr)) {
3647                 trace_kvm_msr_write_ex(ecx, data);
3648                 kvm_inject_gp(&svm->vcpu, 0);
3649         } else {
3650                 trace_kvm_msr_write(ecx, data);
3651                 skip_emulated_instruction(&svm->vcpu);
3652         }
3653         return 1;
3654 }
3655
3656 static int msr_interception(struct vcpu_svm *svm)
3657 {
3658         if (svm->vmcb->control.exit_info_1)
3659                 return wrmsr_interception(svm);
3660         else
3661                 return rdmsr_interception(svm);
3662 }
3663
3664 static int interrupt_window_interception(struct vcpu_svm *svm)
3665 {
3666         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3667         svm_clear_vintr(svm);
3668         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3669         mark_dirty(svm->vmcb, VMCB_INTR);
3670         ++svm->vcpu.stat.irq_window_exits;
3671         return 1;
3672 }
3673
3674 static int pause_interception(struct vcpu_svm *svm)
3675 {
3676         kvm_vcpu_on_spin(&(svm->vcpu));
3677         return 1;
3678 }
3679
3680 static int nop_interception(struct vcpu_svm *svm)
3681 {
3682         skip_emulated_instruction(&(svm->vcpu));
3683         return 1;
3684 }
3685
3686 static int monitor_interception(struct vcpu_svm *svm)
3687 {
3688         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3689         return nop_interception(svm);
3690 }
3691
3692 static int mwait_interception(struct vcpu_svm *svm)
3693 {
3694         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3695         return nop_interception(svm);
3696 }
3697
3698 enum avic_ipi_failure_cause {
3699         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3700         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3701         AVIC_IPI_FAILURE_INVALID_TARGET,
3702         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3703 };
3704
3705 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3706 {
3707         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3708         u32 icrl = svm->vmcb->control.exit_info_1;
3709         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3710         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3711         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3712
3713         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3714
3715         switch (id) {
3716         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3717                 /*
3718                  * AVIC hardware handles the generation of
3719                  * IPIs when the specified Message Type is Fixed
3720                  * (also known as fixed delivery mode) and
3721                  * the Trigger Mode is edge-triggered. The hardware
3722                  * also supports self and broadcast delivery modes
3723                  * specified via the Destination Shorthand(DSH)
3724                  * field of the ICRL. Logical and physical APIC ID
3725                  * formats are supported. All other IPI types cause
3726                  * a #VMEXIT, which needs to emulated.
3727                  */
3728                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3729                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3730                 break;
3731         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3732                 int i;
3733                 struct kvm_vcpu *vcpu;
3734                 struct kvm *kvm = svm->vcpu.kvm;
3735                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3736
3737                 /*
3738                  * At this point, we expect that the AVIC HW has already
3739                  * set the appropriate IRR bits on the valid target
3740                  * vcpus. So, we just need to kick the appropriate vcpu.
3741                  */
3742                 kvm_for_each_vcpu(i, vcpu, kvm) {
3743                         bool m = kvm_apic_match_dest(vcpu, apic,
3744                                                      icrl & KVM_APIC_SHORT_MASK,
3745                                                      GET_APIC_DEST_FIELD(icrh),
3746                                                      icrl & KVM_APIC_DEST_MASK);
3747
3748                         if (m && !avic_vcpu_is_running(vcpu))
3749                                 kvm_vcpu_wake_up(vcpu);
3750                 }
3751                 break;
3752         }
3753         case AVIC_IPI_FAILURE_INVALID_TARGET:
3754                 break;
3755         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3756                 WARN_ONCE(1, "Invalid backing page\n");
3757                 break;
3758         default:
3759                 pr_err("Unknown IPI interception\n");
3760         }
3761
3762         return 1;
3763 }
3764
3765 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3766 {
3767         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3768         int index;
3769         u32 *logical_apic_id_table;
3770         int dlid = GET_APIC_LOGICAL_ID(ldr);
3771
3772         if (!dlid)
3773                 return NULL;
3774
3775         if (flat) { /* flat */
3776                 index = ffs(dlid) - 1;
3777                 if (index > 7)
3778                         return NULL;
3779         } else { /* cluster */
3780                 int cluster = (dlid & 0xf0) >> 4;
3781                 int apic = ffs(dlid & 0x0f) - 1;
3782
3783                 if ((apic < 0) || (apic > 7) ||
3784                     (cluster >= 0xf))
3785                         return NULL;
3786                 index = (cluster << 2) + apic;
3787         }
3788
3789         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3790
3791         return &logical_apic_id_table[index];
3792 }
3793
3794 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3795                           bool valid)
3796 {
3797         bool flat;
3798         u32 *entry, new_entry;
3799
3800         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3801         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3802         if (!entry)
3803                 return -EINVAL;
3804
3805         new_entry = READ_ONCE(*entry);
3806         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3807         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3808         if (valid)
3809                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3810         else
3811                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3812         WRITE_ONCE(*entry, new_entry);
3813
3814         return 0;
3815 }
3816
3817 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3818 {
3819         int ret;
3820         struct vcpu_svm *svm = to_svm(vcpu);
3821         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3822
3823         if (!ldr)
3824                 return 1;
3825
3826         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3827         if (ret && svm->ldr_reg) {
3828                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3829                 svm->ldr_reg = 0;
3830         } else {
3831                 svm->ldr_reg = ldr;
3832         }
3833         return ret;
3834 }
3835
3836 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3837 {
3838         u64 *old, *new;
3839         struct vcpu_svm *svm = to_svm(vcpu);
3840         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3841         u32 id = (apic_id_reg >> 24) & 0xff;
3842
3843         if (vcpu->vcpu_id == id)
3844                 return 0;
3845
3846         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3847         new = avic_get_physical_id_entry(vcpu, id);
3848         if (!new || !old)
3849                 return 1;
3850
3851         /* We need to move physical_id_entry to new offset */
3852         *new = *old;
3853         *old = 0ULL;
3854         to_svm(vcpu)->avic_physical_id_cache = new;
3855
3856         /*
3857          * Also update the guest physical APIC ID in the logical
3858          * APIC ID table entry if already setup the LDR.
3859          */
3860         if (svm->ldr_reg)
3861                 avic_handle_ldr_update(vcpu);
3862
3863         return 0;
3864 }
3865
3866 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3867 {
3868         struct vcpu_svm *svm = to_svm(vcpu);
3869         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3870         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3871         u32 mod = (dfr >> 28) & 0xf;
3872
3873         /*
3874          * We assume that all local APICs are using the same type.
3875          * If this changes, we need to flush the AVIC logical
3876          * APID id table.
3877          */
3878         if (vm_data->ldr_mode == mod)
3879                 return 0;
3880
3881         clear_page(page_address(vm_data->avic_logical_id_table_page));
3882         vm_data->ldr_mode = mod;
3883
3884         if (svm->ldr_reg)
3885                 avic_handle_ldr_update(vcpu);
3886         return 0;
3887 }
3888
3889 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3890 {
3891         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3892         u32 offset = svm->vmcb->control.exit_info_1 &
3893                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3894
3895         switch (offset) {
3896         case APIC_ID:
3897                 if (avic_handle_apic_id_update(&svm->vcpu))
3898                         return 0;
3899                 break;
3900         case APIC_LDR:
3901                 if (avic_handle_ldr_update(&svm->vcpu))
3902                         return 0;
3903                 break;
3904         case APIC_DFR:
3905                 avic_handle_dfr_update(&svm->vcpu);
3906                 break;
3907         default:
3908                 break;
3909         }
3910
3911         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3912
3913         return 1;
3914 }
3915
3916 static bool is_avic_unaccelerated_access_trap(u32 offset)
3917 {
3918         bool ret = false;
3919
3920         switch (offset) {
3921         case APIC_ID:
3922         case APIC_EOI:
3923         case APIC_RRR:
3924         case APIC_LDR:
3925         case APIC_DFR:
3926         case APIC_SPIV:
3927         case APIC_ESR:
3928         case APIC_ICR:
3929         case APIC_LVTT:
3930         case APIC_LVTTHMR:
3931         case APIC_LVTPC:
3932         case APIC_LVT0:
3933         case APIC_LVT1:
3934         case APIC_LVTERR:
3935         case APIC_TMICT:
3936         case APIC_TDCR:
3937                 ret = true;
3938                 break;
3939         default:
3940                 break;
3941         }
3942         return ret;
3943 }
3944
3945 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3946 {
3947         int ret = 0;
3948         u32 offset = svm->vmcb->control.exit_info_1 &
3949                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3950         u32 vector = svm->vmcb->control.exit_info_2 &
3951                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3952         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3953                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
3954         bool trap = is_avic_unaccelerated_access_trap(offset);
3955
3956         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3957                                             trap, write, vector);
3958         if (trap) {
3959                 /* Handling Trap */
3960                 WARN_ONCE(!write, "svm: Handling trap read.\n");
3961                 ret = avic_unaccel_trap_write(svm);
3962         } else {
3963                 /* Handling Fault */
3964                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3965         }
3966
3967         return ret;
3968 }
3969
3970 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3971         [SVM_EXIT_READ_CR0]                     = cr_interception,
3972         [SVM_EXIT_READ_CR3]                     = cr_interception,
3973         [SVM_EXIT_READ_CR4]                     = cr_interception,
3974         [SVM_EXIT_READ_CR8]                     = cr_interception,
3975         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3976         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3977         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3978         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3979         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3980         [SVM_EXIT_READ_DR0]                     = dr_interception,
3981         [SVM_EXIT_READ_DR1]                     = dr_interception,
3982         [SVM_EXIT_READ_DR2]                     = dr_interception,
3983         [SVM_EXIT_READ_DR3]                     = dr_interception,
3984         [SVM_EXIT_READ_DR4]                     = dr_interception,
3985         [SVM_EXIT_READ_DR5]                     = dr_interception,
3986         [SVM_EXIT_READ_DR6]                     = dr_interception,
3987         [SVM_EXIT_READ_DR7]                     = dr_interception,
3988         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3989         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3990         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3991         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3992         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3993         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3994         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3995         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3996         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3997         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3998         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3999         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4000         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4001         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4002         [SVM_EXIT_INTR]                         = intr_interception,
4003         [SVM_EXIT_NMI]                          = nmi_interception,
4004         [SVM_EXIT_SMI]                          = nop_on_interception,
4005         [SVM_EXIT_INIT]                         = nop_on_interception,
4006         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4007         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4008         [SVM_EXIT_CPUID]                        = cpuid_interception,
4009         [SVM_EXIT_IRET]                         = iret_interception,
4010         [SVM_EXIT_INVD]                         = emulate_on_interception,
4011         [SVM_EXIT_PAUSE]                        = pause_interception,
4012         [SVM_EXIT_HLT]                          = halt_interception,
4013         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4014         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4015         [SVM_EXIT_IOIO]                         = io_interception,
4016         [SVM_EXIT_MSR]                          = msr_interception,
4017         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4018         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4019         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4020         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4021         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4022         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4023         [SVM_EXIT_STGI]                         = stgi_interception,
4024         [SVM_EXIT_CLGI]                         = clgi_interception,
4025         [SVM_EXIT_SKINIT]                       = skinit_interception,
4026         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4027         [SVM_EXIT_MONITOR]                      = monitor_interception,
4028         [SVM_EXIT_MWAIT]                        = mwait_interception,
4029         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4030         [SVM_EXIT_NPF]                          = pf_interception,
4031         [SVM_EXIT_RSM]                          = emulate_on_interception,
4032         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4033         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4034 };
4035
4036 static void dump_vmcb(struct kvm_vcpu *vcpu)
4037 {
4038         struct vcpu_svm *svm = to_svm(vcpu);
4039         struct vmcb_control_area *control = &svm->vmcb->control;
4040         struct vmcb_save_area *save = &svm->vmcb->save;
4041
4042         pr_err("VMCB Control Area:\n");
4043         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4044         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4045         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4046         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4047         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4048         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4049         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4050         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4051         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4052         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4053         pr_err("%-20s%d\n", "asid:", control->asid);
4054         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4055         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4056         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4057         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4058         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4059         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4060         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4061         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4062         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4063         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4064         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4065         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4066         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4067         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4068         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4069         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4070         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4071         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4072         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4073         pr_err("VMCB State Save Area:\n");
4074         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4075                "es:",
4076                save->es.selector, save->es.attrib,
4077                save->es.limit, save->es.base);
4078         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4079                "cs:",
4080                save->cs.selector, save->cs.attrib,
4081                save->cs.limit, save->cs.base);
4082         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4083                "ss:",
4084                save->ss.selector, save->ss.attrib,
4085                save->ss.limit, save->ss.base);
4086         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4087                "ds:",
4088                save->ds.selector, save->ds.attrib,
4089                save->ds.limit, save->ds.base);
4090         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4091                "fs:",
4092                save->fs.selector, save->fs.attrib,
4093                save->fs.limit, save->fs.base);
4094         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4095                "gs:",
4096                save->gs.selector, save->gs.attrib,
4097                save->gs.limit, save->gs.base);
4098         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4099                "gdtr:",
4100                save->gdtr.selector, save->gdtr.attrib,
4101                save->gdtr.limit, save->gdtr.base);
4102         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4103                "ldtr:",
4104                save->ldtr.selector, save->ldtr.attrib,
4105                save->ldtr.limit, save->ldtr.base);
4106         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4107                "idtr:",
4108                save->idtr.selector, save->idtr.attrib,
4109                save->idtr.limit, save->idtr.base);
4110         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4111                "tr:",
4112                save->tr.selector, save->tr.attrib,
4113                save->tr.limit, save->tr.base);
4114         pr_err("cpl:            %d                efer:         %016llx\n",
4115                 save->cpl, save->efer);
4116         pr_err("%-15s %016llx %-13s %016llx\n",
4117                "cr0:", save->cr0, "cr2:", save->cr2);
4118         pr_err("%-15s %016llx %-13s %016llx\n",
4119                "cr3:", save->cr3, "cr4:", save->cr4);
4120         pr_err("%-15s %016llx %-13s %016llx\n",
4121                "dr6:", save->dr6, "dr7:", save->dr7);
4122         pr_err("%-15s %016llx %-13s %016llx\n",
4123                "rip:", save->rip, "rflags:", save->rflags);
4124         pr_err("%-15s %016llx %-13s %016llx\n",
4125                "rsp:", save->rsp, "rax:", save->rax);
4126         pr_err("%-15s %016llx %-13s %016llx\n",
4127                "star:", save->star, "lstar:", save->lstar);
4128         pr_err("%-15s %016llx %-13s %016llx\n",
4129                "cstar:", save->cstar, "sfmask:", save->sfmask);
4130         pr_err("%-15s %016llx %-13s %016llx\n",
4131                "kernel_gs_base:", save->kernel_gs_base,
4132                "sysenter_cs:", save->sysenter_cs);
4133         pr_err("%-15s %016llx %-13s %016llx\n",
4134                "sysenter_esp:", save->sysenter_esp,
4135                "sysenter_eip:", save->sysenter_eip);
4136         pr_err("%-15s %016llx %-13s %016llx\n",
4137                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4138         pr_err("%-15s %016llx %-13s %016llx\n",
4139                "br_from:", save->br_from, "br_to:", save->br_to);
4140         pr_err("%-15s %016llx %-13s %016llx\n",
4141                "excp_from:", save->last_excp_from,
4142                "excp_to:", save->last_excp_to);
4143 }
4144
4145 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4146 {
4147         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4148
4149         *info1 = control->exit_info_1;
4150         *info2 = control->exit_info_2;
4151 }
4152
4153 static int handle_exit(struct kvm_vcpu *vcpu)
4154 {
4155         struct vcpu_svm *svm = to_svm(vcpu);
4156         struct kvm_run *kvm_run = vcpu->run;
4157         u32 exit_code = svm->vmcb->control.exit_code;
4158
4159         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4160
4161         vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4162
4163         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4164                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4165         if (npt_enabled)
4166                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4167
4168         if (unlikely(svm->nested.exit_required)) {
4169                 nested_svm_vmexit(svm);
4170                 svm->nested.exit_required = false;
4171
4172                 return 1;
4173         }
4174
4175         if (is_guest_mode(vcpu)) {
4176                 int vmexit;
4177
4178                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4179                                         svm->vmcb->control.exit_info_1,
4180                                         svm->vmcb->control.exit_info_2,
4181                                         svm->vmcb->control.exit_int_info,
4182                                         svm->vmcb->control.exit_int_info_err,
4183                                         KVM_ISA_SVM);
4184
4185                 vmexit = nested_svm_exit_special(svm);
4186
4187                 if (vmexit == NESTED_EXIT_CONTINUE)
4188                         vmexit = nested_svm_exit_handled(svm);
4189
4190                 if (vmexit == NESTED_EXIT_DONE)
4191                         return 1;
4192         }
4193
4194         svm_complete_interrupts(svm);
4195
4196         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4197                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4198                 kvm_run->fail_entry.hardware_entry_failure_reason
4199                         = svm->vmcb->control.exit_code;
4200                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4201                 dump_vmcb(vcpu);
4202                 return 0;
4203         }
4204
4205         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4206             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4207             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4208             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4209                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4210                        "exit_code 0x%x\n",
4211                        __func__, svm->vmcb->control.exit_int_info,
4212                        exit_code);
4213
4214         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4215             || !svm_exit_handlers[exit_code]) {
4216                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4217                 kvm_queue_exception(vcpu, UD_VECTOR);
4218                 return 1;
4219         }
4220
4221         return svm_exit_handlers[exit_code](svm);
4222 }
4223
4224 static void reload_tss(struct kvm_vcpu *vcpu)
4225 {
4226         int cpu = raw_smp_processor_id();
4227
4228         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4229         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4230         load_TR_desc();
4231 }
4232
4233 static void pre_svm_run(struct vcpu_svm *svm)
4234 {
4235         int cpu = raw_smp_processor_id();
4236
4237         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4238
4239         /* FIXME: handle wraparound of asid_generation */
4240         if (svm->asid_generation != sd->asid_generation)
4241                 new_asid(svm, sd);
4242 }
4243
4244 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4245 {
4246         struct vcpu_svm *svm = to_svm(vcpu);
4247
4248         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4249         vcpu->arch.hflags |= HF_NMI_MASK;
4250         set_intercept(svm, INTERCEPT_IRET);
4251         ++vcpu->stat.nmi_injections;
4252 }
4253
4254 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4255 {
4256         struct vmcb_control_area *control;
4257
4258         /* The following fields are ignored when AVIC is enabled */
4259         control = &svm->vmcb->control;
4260         control->int_vector = irq;
4261         control->int_ctl &= ~V_INTR_PRIO_MASK;
4262         control->int_ctl |= V_IRQ_MASK |
4263                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4264         mark_dirty(svm->vmcb, VMCB_INTR);
4265 }
4266
4267 static void svm_set_irq(struct kvm_vcpu *vcpu)
4268 {
4269         struct vcpu_svm *svm = to_svm(vcpu);
4270
4271         BUG_ON(!(gif_set(svm)));
4272
4273         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4274         ++vcpu->stat.irq_injections;
4275
4276         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4277                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4278 }
4279
4280 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4281 {
4282         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4283 }
4284
4285 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4286 {
4287         struct vcpu_svm *svm = to_svm(vcpu);
4288
4289         if (svm_nested_virtualize_tpr(vcpu) ||
4290             kvm_vcpu_apicv_active(vcpu))
4291                 return;
4292
4293         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4294
4295         if (irr == -1)
4296                 return;
4297
4298         if (tpr >= irr)
4299                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4300 }
4301
4302 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4303 {
4304         return;
4305 }
4306
4307 static bool svm_get_enable_apicv(void)
4308 {
4309         return avic;
4310 }
4311
4312 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4313 {
4314 }
4315
4316 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4317 {
4318 }
4319
4320 /* Note: Currently only used by Hyper-V. */
4321 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4322 {
4323         struct vcpu_svm *svm = to_svm(vcpu);
4324         struct vmcb *vmcb = svm->vmcb;
4325
4326         if (!avic)
4327                 return;
4328
4329         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4330         mark_dirty(vmcb, VMCB_INTR);
4331 }
4332
4333 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4334 {
4335         return;
4336 }
4337
4338 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4339 {
4340         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4341         smp_mb__after_atomic();
4342
4343         if (avic_vcpu_is_running(vcpu))
4344                 wrmsrl(SVM_AVIC_DOORBELL,
4345                        kvm_cpu_get_apicid(vcpu->cpu));
4346         else
4347                 kvm_vcpu_wake_up(vcpu);
4348 }
4349
4350 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4351 {
4352         unsigned long flags;
4353         struct amd_svm_iommu_ir *cur;
4354
4355         spin_lock_irqsave(&svm->ir_list_lock, flags);
4356         list_for_each_entry(cur, &svm->ir_list, node) {
4357                 if (cur->data != pi->ir_data)
4358                         continue;
4359                 list_del(&cur->node);
4360                 kfree(cur);
4361                 break;
4362         }
4363         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4364 }
4365
4366 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4367 {
4368         int ret = 0;
4369         unsigned long flags;
4370         struct amd_svm_iommu_ir *ir;
4371
4372         /**
4373          * In some cases, the existing irte is updaed and re-set,
4374          * so we need to check here if it's already been * added
4375          * to the ir_list.
4376          */
4377         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4378                 struct kvm *kvm = svm->vcpu.kvm;
4379                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4380                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4381                 struct vcpu_svm *prev_svm;
4382
4383                 if (!prev_vcpu) {
4384                         ret = -EINVAL;
4385                         goto out;
4386                 }
4387
4388                 prev_svm = to_svm(prev_vcpu);
4389                 svm_ir_list_del(prev_svm, pi);
4390         }
4391
4392         /**
4393          * Allocating new amd_iommu_pi_data, which will get
4394          * add to the per-vcpu ir_list.
4395          */
4396         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4397         if (!ir) {
4398                 ret = -ENOMEM;
4399                 goto out;
4400         }
4401         ir->data = pi->ir_data;
4402
4403         spin_lock_irqsave(&svm->ir_list_lock, flags);
4404         list_add(&ir->node, &svm->ir_list);
4405         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4406 out:
4407         return ret;
4408 }
4409
4410 /**
4411  * Note:
4412  * The HW cannot support posting multicast/broadcast
4413  * interrupts to a vCPU. So, we still use legacy interrupt
4414  * remapping for these kind of interrupts.
4415  *
4416  * For lowest-priority interrupts, we only support
4417  * those with single CPU as the destination, e.g. user
4418  * configures the interrupts via /proc/irq or uses
4419  * irqbalance to make the interrupts single-CPU.
4420  */
4421 static int
4422 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4423                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4424 {
4425         struct kvm_lapic_irq irq;
4426         struct kvm_vcpu *vcpu = NULL;
4427
4428         kvm_set_msi_irq(kvm, e, &irq);
4429
4430         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4431                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4432                          __func__, irq.vector);
4433                 return -1;
4434         }
4435
4436         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4437                  irq.vector);
4438         *svm = to_svm(vcpu);
4439         vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4440         vcpu_info->vector = irq.vector;
4441
4442         return 0;
4443 }
4444
4445 /*
4446  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4447  *
4448  * @kvm: kvm
4449  * @host_irq: host irq of the interrupt
4450  * @guest_irq: gsi of the interrupt
4451  * @set: set or unset PI
4452  * returns 0 on success, < 0 on failure
4453  */
4454 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4455                               uint32_t guest_irq, bool set)
4456 {
4457         struct kvm_kernel_irq_routing_entry *e;
4458         struct kvm_irq_routing_table *irq_rt;
4459         int idx, ret = -EINVAL;
4460
4461         if (!kvm_arch_has_assigned_device(kvm) ||
4462             !irq_remapping_cap(IRQ_POSTING_CAP))
4463                 return 0;
4464
4465         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4466                  __func__, host_irq, guest_irq, set);
4467
4468         idx = srcu_read_lock(&kvm->irq_srcu);
4469         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4470         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4471
4472         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4473                 struct vcpu_data vcpu_info;
4474                 struct vcpu_svm *svm = NULL;
4475
4476                 if (e->type != KVM_IRQ_ROUTING_MSI)
4477                         continue;
4478
4479                 /**
4480                  * Here, we setup with legacy mode in the following cases:
4481                  * 1. When cannot target interrupt to a specific vcpu.
4482                  * 2. Unsetting posted interrupt.
4483                  * 3. APIC virtialization is disabled for the vcpu.
4484                  */
4485                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4486                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4487                         struct amd_iommu_pi_data pi;
4488
4489                         /* Try to enable guest_mode in IRTE */
4490                         pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4491                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4492                                                      svm->vcpu.vcpu_id);
4493                         pi.is_guest_mode = true;
4494                         pi.vcpu_data = &vcpu_info;
4495                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4496
4497                         /**
4498                          * Here, we successfully setting up vcpu affinity in
4499                          * IOMMU guest mode. Now, we need to store the posted
4500                          * interrupt information in a per-vcpu ir_list so that
4501                          * we can reference to them directly when we update vcpu
4502                          * scheduling information in IOMMU irte.
4503                          */
4504                         if (!ret && pi.is_guest_mode)
4505                                 svm_ir_list_add(svm, &pi);
4506                 } else {
4507                         /* Use legacy mode in IRTE */
4508                         struct amd_iommu_pi_data pi;
4509
4510                         /**
4511                          * Here, pi is used to:
4512                          * - Tell IOMMU to use legacy mode for this interrupt.
4513                          * - Retrieve ga_tag of prior interrupt remapping data.
4514                          */
4515                         pi.is_guest_mode = false;
4516                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4517
4518                         /**
4519                          * Check if the posted interrupt was previously
4520                          * setup with the guest_mode by checking if the ga_tag
4521                          * was cached. If so, we need to clean up the per-vcpu
4522                          * ir_list.
4523                          */
4524                         if (!ret && pi.prev_ga_tag) {
4525                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4526                                 struct kvm_vcpu *vcpu;
4527
4528                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4529                                 if (vcpu)
4530                                         svm_ir_list_del(to_svm(vcpu), &pi);
4531                         }
4532                 }
4533
4534                 if (!ret && svm) {
4535                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4536                                                  host_irq, e->gsi,
4537                                                  vcpu_info.vector,
4538                                                  vcpu_info.pi_desc_addr, set);
4539                 }
4540
4541                 if (ret < 0) {
4542                         pr_err("%s: failed to update PI IRTE\n", __func__);
4543                         goto out;
4544                 }
4545         }
4546
4547         ret = 0;
4548 out:
4549         srcu_read_unlock(&kvm->irq_srcu, idx);
4550         return ret;
4551 }
4552
4553 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4554 {
4555         struct vcpu_svm *svm = to_svm(vcpu);
4556         struct vmcb *vmcb = svm->vmcb;
4557         int ret;
4558         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4559               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4560         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4561
4562         return ret;
4563 }
4564
4565 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4566 {
4567         struct vcpu_svm *svm = to_svm(vcpu);
4568
4569         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4570 }
4571
4572 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4573 {
4574         struct vcpu_svm *svm = to_svm(vcpu);
4575
4576         if (masked) {
4577                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4578                 set_intercept(svm, INTERCEPT_IRET);
4579         } else {
4580                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4581                 clr_intercept(svm, INTERCEPT_IRET);
4582         }
4583 }
4584
4585 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4586 {
4587         struct vcpu_svm *svm = to_svm(vcpu);
4588         struct vmcb *vmcb = svm->vmcb;
4589         int ret;
4590
4591         if (!gif_set(svm) ||
4592              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4593                 return 0;
4594
4595         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4596
4597         if (is_guest_mode(vcpu))
4598                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4599
4600         return ret;
4601 }
4602
4603 static void enable_irq_window(struct kvm_vcpu *vcpu)
4604 {
4605         struct vcpu_svm *svm = to_svm(vcpu);
4606
4607         if (kvm_vcpu_apicv_active(vcpu))
4608                 return;
4609
4610         /*
4611          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4612          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4613          * get that intercept, this function will be called again though and
4614          * we'll get the vintr intercept.
4615          */
4616         if (gif_set(svm) && nested_svm_intr(svm)) {
4617                 svm_set_vintr(svm);
4618                 svm_inject_irq(svm, 0x0);
4619         }
4620 }
4621
4622 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4623 {
4624         struct vcpu_svm *svm = to_svm(vcpu);
4625
4626         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4627             == HF_NMI_MASK)
4628                 return; /* IRET will cause a vm exit */
4629
4630         /*
4631          * Something prevents NMI from been injected. Single step over possible
4632          * problem (IRET or exception injection or interrupt shadow)
4633          */
4634         svm->nmi_singlestep = true;
4635         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4636 }
4637
4638 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4639 {
4640         return 0;
4641 }
4642
4643 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4644 {
4645         struct vcpu_svm *svm = to_svm(vcpu);
4646
4647         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4648                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4649         else
4650                 svm->asid_generation--;
4651 }
4652
4653 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4654 {
4655 }
4656
4657 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4658 {
4659         struct vcpu_svm *svm = to_svm(vcpu);
4660
4661         if (svm_nested_virtualize_tpr(vcpu))
4662                 return;
4663
4664         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4665                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4666                 kvm_set_cr8(vcpu, cr8);
4667         }
4668 }
4669
4670 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4671 {
4672         struct vcpu_svm *svm = to_svm(vcpu);
4673         u64 cr8;
4674
4675         if (svm_nested_virtualize_tpr(vcpu) ||
4676             kvm_vcpu_apicv_active(vcpu))
4677                 return;
4678
4679         cr8 = kvm_get_cr8(vcpu);
4680         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4681         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4682 }
4683
4684 static void svm_complete_interrupts(struct vcpu_svm *svm)
4685 {
4686         u8 vector;
4687         int type;
4688         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4689         unsigned int3_injected = svm->int3_injected;
4690
4691         svm->int3_injected = 0;
4692
4693         /*
4694          * If we've made progress since setting HF_IRET_MASK, we've
4695          * executed an IRET and can allow NMI injection.
4696          */
4697         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4698             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4699                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4700                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4701         }
4702
4703         svm->vcpu.arch.nmi_injected = false;
4704         kvm_clear_exception_queue(&svm->vcpu);
4705         kvm_clear_interrupt_queue(&svm->vcpu);
4706
4707         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4708                 return;
4709
4710         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4711
4712         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4713         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4714
4715         switch (type) {
4716         case SVM_EXITINTINFO_TYPE_NMI:
4717                 svm->vcpu.arch.nmi_injected = true;
4718                 break;
4719         case SVM_EXITINTINFO_TYPE_EXEPT:
4720                 /*
4721                  * In case of software exceptions, do not reinject the vector,
4722                  * but re-execute the instruction instead. Rewind RIP first
4723                  * if we emulated INT3 before.
4724                  */
4725                 if (kvm_exception_is_soft(vector)) {
4726                         if (vector == BP_VECTOR && int3_injected &&
4727                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4728                                 kvm_rip_write(&svm->vcpu,
4729                                               kvm_rip_read(&svm->vcpu) -
4730                                               int3_injected);
4731                         break;
4732                 }
4733                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4734                         u32 err = svm->vmcb->control.exit_int_info_err;
4735                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4736
4737                 } else
4738                         kvm_requeue_exception(&svm->vcpu, vector);
4739                 break;
4740         case SVM_EXITINTINFO_TYPE_INTR:
4741                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4742                 break;
4743         default:
4744                 break;
4745         }
4746 }
4747
4748 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4749 {
4750         struct vcpu_svm *svm = to_svm(vcpu);
4751         struct vmcb_control_area *control = &svm->vmcb->control;
4752
4753         control->exit_int_info = control->event_inj;
4754         control->exit_int_info_err = control->event_inj_err;
4755         control->event_inj = 0;
4756         svm_complete_interrupts(svm);
4757 }
4758
4759 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4760 {
4761         struct vcpu_svm *svm = to_svm(vcpu);
4762
4763         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4764         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4765         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4766
4767         /*
4768          * A vmexit emulation is required before the vcpu can be executed
4769          * again.
4770          */
4771         if (unlikely(svm->nested.exit_required))
4772                 return;
4773
4774         pre_svm_run(svm);
4775
4776         sync_lapic_to_cr8(vcpu);
4777
4778         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4779
4780         clgi();
4781
4782         local_irq_enable();
4783
4784         asm volatile (
4785                 "push %%" _ASM_BP "; \n\t"
4786                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4787                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4788                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4789                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4790                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4791                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4792 #ifdef CONFIG_X86_64
4793                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4794                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4795                 "mov %c[r10](%[svm]), %%r10 \n\t"
4796                 "mov %c[r11](%[svm]), %%r11 \n\t"
4797                 "mov %c[r12](%[svm]), %%r12 \n\t"
4798                 "mov %c[r13](%[svm]), %%r13 \n\t"
4799                 "mov %c[r14](%[svm]), %%r14 \n\t"
4800                 "mov %c[r15](%[svm]), %%r15 \n\t"
4801 #endif
4802
4803                 /* Enter guest mode */
4804                 "push %%" _ASM_AX " \n\t"
4805                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4806                 __ex(SVM_VMLOAD) "\n\t"
4807                 __ex(SVM_VMRUN) "\n\t"
4808                 __ex(SVM_VMSAVE) "\n\t"
4809                 "pop %%" _ASM_AX " \n\t"
4810
4811                 /* Save guest registers, load host registers */
4812                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4813                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4814                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4815                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4816                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4817                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4818 #ifdef CONFIG_X86_64
4819                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4820                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4821                 "mov %%r10, %c[r10](%[svm]) \n\t"
4822                 "mov %%r11, %c[r11](%[svm]) \n\t"
4823                 "mov %%r12, %c[r12](%[svm]) \n\t"
4824                 "mov %%r13, %c[r13](%[svm]) \n\t"
4825                 "mov %%r14, %c[r14](%[svm]) \n\t"
4826                 "mov %%r15, %c[r15](%[svm]) \n\t"
4827 #endif
4828                 "pop %%" _ASM_BP
4829                 :
4830                 : [svm]"a"(svm),
4831                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4832                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4833                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4834                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4835                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4836                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4837                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4838 #ifdef CONFIG_X86_64
4839                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4840                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4841                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4842                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4843                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4844                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4845                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4846                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4847 #endif
4848                 : "cc", "memory"
4849 #ifdef CONFIG_X86_64
4850                 , "rbx", "rcx", "rdx", "rsi", "rdi"
4851                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4852 #else
4853                 , "ebx", "ecx", "edx", "esi", "edi"
4854 #endif
4855                 );
4856
4857 #ifdef CONFIG_X86_64
4858         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4859 #else
4860         loadsegment(fs, svm->host.fs);
4861 #ifndef CONFIG_X86_32_LAZY_GS
4862         loadsegment(gs, svm->host.gs);
4863 #endif
4864 #endif
4865
4866         reload_tss(vcpu);
4867
4868         local_irq_disable();
4869
4870         vcpu->arch.cr2 = svm->vmcb->save.cr2;
4871         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4872         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4873         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4874
4875         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4876                 kvm_before_handle_nmi(&svm->vcpu);
4877
4878         stgi();
4879
4880         /* Any pending NMI will happen here */
4881
4882         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4883                 kvm_after_handle_nmi(&svm->vcpu);
4884
4885         sync_cr8_to_lapic(vcpu);
4886
4887         svm->next_rip = 0;
4888
4889         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4890
4891         /* if exit due to PF check for async PF */
4892         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4893                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4894
4895         if (npt_enabled) {
4896                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4897                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4898         }
4899
4900         /*
4901          * We need to handle MC intercepts here before the vcpu has a chance to
4902          * change the physical cpu
4903          */
4904         if (unlikely(svm->vmcb->control.exit_code ==
4905                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4906                 svm_handle_mce(svm);
4907
4908         mark_all_clean(svm->vmcb);
4909 }
4910
4911 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4912 {
4913         struct vcpu_svm *svm = to_svm(vcpu);
4914
4915         svm->vmcb->save.cr3 = root;
4916         mark_dirty(svm->vmcb, VMCB_CR);
4917         svm_flush_tlb(vcpu);
4918 }
4919
4920 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4921 {
4922         struct vcpu_svm *svm = to_svm(vcpu);
4923
4924         svm->vmcb->control.nested_cr3 = root;
4925         mark_dirty(svm->vmcb, VMCB_NPT);
4926
4927         /* Also sync guest cr3 here in case we live migrate */
4928         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4929         mark_dirty(svm->vmcb, VMCB_CR);
4930
4931         svm_flush_tlb(vcpu);
4932 }
4933
4934 static int is_disabled(void)
4935 {
4936         u64 vm_cr;
4937
4938         rdmsrl(MSR_VM_CR, vm_cr);
4939         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4940                 return 1;
4941
4942         return 0;
4943 }
4944
4945 static void
4946 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4947 {
4948         /*
4949          * Patch in the VMMCALL instruction:
4950          */
4951         hypercall[0] = 0x0f;
4952         hypercall[1] = 0x01;
4953         hypercall[2] = 0xd9;
4954 }
4955
4956 static void svm_check_processor_compat(void *rtn)
4957 {
4958         *(int *)rtn = 0;
4959 }
4960
4961 static bool svm_cpu_has_accelerated_tpr(void)
4962 {
4963         return false;
4964 }
4965
4966 static bool svm_has_high_real_mode_segbase(void)
4967 {
4968         return true;
4969 }
4970
4971 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4972 {
4973         return 0;
4974 }
4975
4976 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4977 {
4978         struct vcpu_svm *svm = to_svm(vcpu);
4979         struct kvm_cpuid_entry2 *entry;
4980
4981         /* Update nrips enabled cache */
4982         svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4983
4984         if (!kvm_vcpu_apicv_active(vcpu))
4985                 return;
4986
4987         entry = kvm_find_cpuid_entry(vcpu, 1, 0);
4988         if (entry)
4989                 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4990 }
4991
4992 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4993 {
4994         switch (func) {
4995         case 0x1:
4996                 if (avic)
4997                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4998                 break;
4999         case 0x80000001:
5000                 if (nested)
5001                         entry->ecx |= (1 << 2); /* Set SVM bit */
5002                 break;
5003         case 0x8000000A:
5004                 entry->eax = 1; /* SVM revision 1 */
5005                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5006                                    ASID emulation to nested SVM */
5007                 entry->ecx = 0; /* Reserved */
5008                 entry->edx = 0; /* Per default do not support any
5009                                    additional features */
5010
5011                 /* Support next_rip if host supports it */
5012                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5013                         entry->edx |= SVM_FEATURE_NRIP;
5014
5015                 /* Support NPT for the guest if enabled */
5016                 if (npt_enabled)
5017                         entry->edx |= SVM_FEATURE_NPT;
5018
5019                 break;
5020         }
5021 }
5022
5023 static int svm_get_lpage_level(void)
5024 {
5025         return PT_PDPE_LEVEL;
5026 }
5027
5028 static bool svm_rdtscp_supported(void)
5029 {
5030         return boot_cpu_has(X86_FEATURE_RDTSCP);
5031 }
5032
5033 static bool svm_invpcid_supported(void)
5034 {
5035         return false;
5036 }
5037
5038 static bool svm_mpx_supported(void)
5039 {
5040         return false;
5041 }
5042
5043 static bool svm_xsaves_supported(void)
5044 {
5045         return false;
5046 }
5047
5048 static bool svm_has_wbinvd_exit(void)
5049 {
5050         return true;
5051 }
5052
5053 #define PRE_EX(exit)  { .exit_code = (exit), \
5054                         .stage = X86_ICPT_PRE_EXCEPT, }
5055 #define POST_EX(exit) { .exit_code = (exit), \
5056                         .stage = X86_ICPT_POST_EXCEPT, }
5057 #define POST_MEM(exit) { .exit_code = (exit), \
5058                         .stage = X86_ICPT_POST_MEMACCESS, }
5059
5060 static const struct __x86_intercept {
5061         u32 exit_code;
5062         enum x86_intercept_stage stage;
5063 } x86_intercept_map[] = {
5064         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5065         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5066         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5067         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5068         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5069         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5070         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5071         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5072         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5073         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5074         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5075         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5076         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5077         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5078         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5079         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5080         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5081         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5082         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5083         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5084         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5085         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5086         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5087         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5088         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5089         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5090         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5091         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5092         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5093         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5094         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5095         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5096         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5097         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5098         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5099         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5100         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5101         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5102         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5103         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5104         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5105         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5106         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5107         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5108         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5109         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5110 };
5111
5112 #undef PRE_EX
5113 #undef POST_EX
5114 #undef POST_MEM
5115
5116 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5117                                struct x86_instruction_info *info,
5118                                enum x86_intercept_stage stage)
5119 {
5120         struct vcpu_svm *svm = to_svm(vcpu);
5121         int vmexit, ret = X86EMUL_CONTINUE;
5122         struct __x86_intercept icpt_info;
5123         struct vmcb *vmcb = svm->vmcb;
5124
5125         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5126                 goto out;
5127
5128         icpt_info = x86_intercept_map[info->intercept];
5129
5130         if (stage != icpt_info.stage)
5131                 goto out;
5132
5133         switch (icpt_info.exit_code) {
5134         case SVM_EXIT_READ_CR0:
5135                 if (info->intercept == x86_intercept_cr_read)
5136                         icpt_info.exit_code += info->modrm_reg;
5137                 break;
5138         case SVM_EXIT_WRITE_CR0: {
5139                 unsigned long cr0, val;
5140                 u64 intercept;
5141
5142                 if (info->intercept == x86_intercept_cr_write)
5143                         icpt_info.exit_code += info->modrm_reg;
5144
5145                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5146                     info->intercept == x86_intercept_clts)
5147                         break;
5148
5149                 intercept = svm->nested.intercept;
5150
5151                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5152                         break;
5153
5154                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5155                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5156
5157                 if (info->intercept == x86_intercept_lmsw) {
5158                         cr0 &= 0xfUL;
5159                         val &= 0xfUL;
5160                         /* lmsw can't clear PE - catch this here */
5161                         if (cr0 & X86_CR0_PE)
5162                                 val |= X86_CR0_PE;
5163                 }
5164
5165                 if (cr0 ^ val)
5166                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5167
5168                 break;
5169         }
5170         case SVM_EXIT_READ_DR0:
5171         case SVM_EXIT_WRITE_DR0:
5172                 icpt_info.exit_code += info->modrm_reg;
5173                 break;
5174         case SVM_EXIT_MSR:
5175                 if (info->intercept == x86_intercept_wrmsr)
5176                         vmcb->control.exit_info_1 = 1;
5177                 else
5178                         vmcb->control.exit_info_1 = 0;
5179                 break;
5180         case SVM_EXIT_PAUSE:
5181                 /*
5182                  * We get this for NOP only, but pause
5183                  * is rep not, check this here
5184                  */
5185                 if (info->rep_prefix != REPE_PREFIX)
5186                         goto out;
5187         case SVM_EXIT_IOIO: {
5188                 u64 exit_info;
5189                 u32 bytes;
5190
5191                 if (info->intercept == x86_intercept_in ||
5192                     info->intercept == x86_intercept_ins) {
5193                         exit_info = ((info->src_val & 0xffff) << 16) |
5194                                 SVM_IOIO_TYPE_MASK;
5195                         bytes = info->dst_bytes;
5196                 } else {
5197                         exit_info = (info->dst_val & 0xffff) << 16;
5198                         bytes = info->src_bytes;
5199                 }
5200
5201                 if (info->intercept == x86_intercept_outs ||
5202                     info->intercept == x86_intercept_ins)
5203                         exit_info |= SVM_IOIO_STR_MASK;
5204
5205                 if (info->rep_prefix)
5206                         exit_info |= SVM_IOIO_REP_MASK;
5207
5208                 bytes = min(bytes, 4u);
5209
5210                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5211
5212                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5213
5214                 vmcb->control.exit_info_1 = exit_info;
5215                 vmcb->control.exit_info_2 = info->next_rip;
5216
5217                 break;
5218         }
5219         default:
5220                 break;
5221         }
5222
5223         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5224         if (static_cpu_has(X86_FEATURE_NRIPS))
5225                 vmcb->control.next_rip  = info->next_rip;
5226         vmcb->control.exit_code = icpt_info.exit_code;
5227         vmexit = nested_svm_exit_handled(svm);
5228
5229         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5230                                            : X86EMUL_CONTINUE;
5231
5232 out:
5233         return ret;
5234 }
5235
5236 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5237 {
5238         local_irq_enable();
5239         /*
5240          * We must have an instruction with interrupts enabled, so
5241          * the timer interrupt isn't delayed by the interrupt shadow.
5242          */
5243         asm("nop");
5244         local_irq_disable();
5245 }
5246
5247 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5248 {
5249 }
5250
5251 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5252 {
5253         if (avic_handle_apic_id_update(vcpu) != 0)
5254                 return;
5255         if (avic_handle_dfr_update(vcpu) != 0)
5256                 return;
5257         avic_handle_ldr_update(vcpu);
5258 }
5259
5260 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5261 {
5262         /* [63:9] are reserved. */
5263         vcpu->arch.mcg_cap &= 0x1ff;
5264 }
5265
5266 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5267         .cpu_has_kvm_support = has_svm,
5268         .disabled_by_bios = is_disabled,
5269         .hardware_setup = svm_hardware_setup,
5270         .hardware_unsetup = svm_hardware_unsetup,
5271         .check_processor_compatibility = svm_check_processor_compat,
5272         .hardware_enable = svm_hardware_enable,
5273         .hardware_disable = svm_hardware_disable,
5274         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5275         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5276
5277         .vcpu_create = svm_create_vcpu,
5278         .vcpu_free = svm_free_vcpu,
5279         .vcpu_reset = svm_vcpu_reset,
5280
5281         .vm_init = avic_vm_init,
5282         .vm_destroy = avic_vm_destroy,
5283
5284         .prepare_guest_switch = svm_prepare_guest_switch,
5285         .vcpu_load = svm_vcpu_load,
5286         .vcpu_put = svm_vcpu_put,
5287         .vcpu_blocking = svm_vcpu_blocking,
5288         .vcpu_unblocking = svm_vcpu_unblocking,
5289
5290         .update_bp_intercept = update_bp_intercept,
5291         .get_msr = svm_get_msr,
5292         .set_msr = svm_set_msr,
5293         .get_segment_base = svm_get_segment_base,
5294         .get_segment = svm_get_segment,
5295         .set_segment = svm_set_segment,
5296         .get_cpl = svm_get_cpl,
5297         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5298         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5299         .decache_cr3 = svm_decache_cr3,
5300         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5301         .set_cr0 = svm_set_cr0,
5302         .set_cr3 = svm_set_cr3,
5303         .set_cr4 = svm_set_cr4,
5304         .set_efer = svm_set_efer,
5305         .get_idt = svm_get_idt,
5306         .set_idt = svm_set_idt,
5307         .get_gdt = svm_get_gdt,
5308         .set_gdt = svm_set_gdt,
5309         .get_dr6 = svm_get_dr6,
5310         .set_dr6 = svm_set_dr6,
5311         .set_dr7 = svm_set_dr7,
5312         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5313         .cache_reg = svm_cache_reg,
5314         .get_rflags = svm_get_rflags,
5315         .set_rflags = svm_set_rflags,
5316
5317         .get_pkru = svm_get_pkru,
5318
5319         .tlb_flush = svm_flush_tlb,
5320
5321         .run = svm_vcpu_run,
5322         .handle_exit = handle_exit,
5323         .skip_emulated_instruction = skip_emulated_instruction,
5324         .set_interrupt_shadow = svm_set_interrupt_shadow,
5325         .get_interrupt_shadow = svm_get_interrupt_shadow,
5326         .patch_hypercall = svm_patch_hypercall,
5327         .set_irq = svm_set_irq,
5328         .set_nmi = svm_inject_nmi,
5329         .queue_exception = svm_queue_exception,
5330         .cancel_injection = svm_cancel_injection,
5331         .interrupt_allowed = svm_interrupt_allowed,
5332         .nmi_allowed = svm_nmi_allowed,
5333         .get_nmi_mask = svm_get_nmi_mask,
5334         .set_nmi_mask = svm_set_nmi_mask,
5335         .enable_nmi_window = enable_nmi_window,
5336         .enable_irq_window = enable_irq_window,
5337         .update_cr8_intercept = update_cr8_intercept,
5338         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5339         .get_enable_apicv = svm_get_enable_apicv,
5340         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5341         .load_eoi_exitmap = svm_load_eoi_exitmap,
5342         .hwapic_irr_update = svm_hwapic_irr_update,
5343         .hwapic_isr_update = svm_hwapic_isr_update,
5344         .apicv_post_state_restore = avic_post_state_restore,
5345
5346         .set_tss_addr = svm_set_tss_addr,
5347         .get_tdp_level = get_npt_level,
5348         .get_mt_mask = svm_get_mt_mask,
5349
5350         .get_exit_info = svm_get_exit_info,
5351
5352         .get_lpage_level = svm_get_lpage_level,
5353
5354         .cpuid_update = svm_cpuid_update,
5355
5356         .rdtscp_supported = svm_rdtscp_supported,
5357         .invpcid_supported = svm_invpcid_supported,
5358         .mpx_supported = svm_mpx_supported,
5359         .xsaves_supported = svm_xsaves_supported,
5360
5361         .set_supported_cpuid = svm_set_supported_cpuid,
5362
5363         .has_wbinvd_exit = svm_has_wbinvd_exit,
5364
5365         .write_tsc_offset = svm_write_tsc_offset,
5366
5367         .set_tdp_cr3 = set_tdp_cr3,
5368
5369         .check_intercept = svm_check_intercept,
5370         .handle_external_intr = svm_handle_external_intr,
5371
5372         .sched_in = svm_sched_in,
5373
5374         .pmu_ops = &amd_pmu_ops,
5375         .deliver_posted_interrupt = svm_deliver_avic_intr,
5376         .update_pi_irte = svm_update_pi_irte,
5377         .setup_mce = svm_setup_mce,
5378 };
5379
5380 static int __init svm_init(void)
5381 {
5382         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5383                         __alignof__(struct vcpu_svm), THIS_MODULE);
5384 }
5385
5386 static void __exit svm_exit(void)
5387 {
5388         kvm_exit();
5389 }
5390
5391 module_init(svm_init)
5392 module_exit(svm_exit)