arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40
  41 #include <asm/apic.h>
  42 #include <asm/perf_event.h>
  43 #include <asm/tlbflush.h>
  44 #include <asm/desc.h>
  45 #include <asm/debugreg.h>
  46 #include <asm/kvm_para.h>
  47 #include <asm/irq_remapping.h>
  48 #include <asm/nospec-branch.h>
  49
  50 #include <asm/virtext.h>
  51 #include "trace.h"
  52
  53 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id svm_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  63
  64 #define IOPM_ALLOC_ORDER 2
  65 #define MSRPM_ALLOC_ORDER 1
  66
  67 #define SEG_TYPE_LDT 2
  68 #define SEG_TYPE_BUSY_TSS16 3
  69
  70 #define SVM_FEATURE_NPT            (1 <<  0)
  71 #define SVM_FEATURE_LBRV           (1 <<  1)
  72 #define SVM_FEATURE_SVML           (1 <<  2)
  73 #define SVM_FEATURE_NRIP           (1 <<  3)
  74 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  75 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  76 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  77 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  78 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  79
  80 #define SVM_AVIC_DOORBELL       0xc001011b
  81
  82 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  83 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  84 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  85
  86 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  87
  88 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  89 #define TSC_RATIO_MIN           0x0000000000000001ULL
  90 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  91
  92 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  93
  94 /*
  95  * 0xff is broadcast, so the max index allowed for physical APIC ID
  96  * table is 0xfe.  APIC IDs above 0xff are reserved.
  97  */
  98 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  99
 100 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 101 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 102 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 103
 104 /* AVIC GATAG is encoded using VM and VCPU IDs */
 105 #define AVIC_VCPU_ID_BITS               8
 106 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 107
 108 #define AVIC_VM_ID_BITS                 24
 109 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 110 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 111
 112 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 113                                                 (y & AVIC_VCPU_ID_MASK))
 114 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 115 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 116
 117 static bool erratum_383_found __read_mostly;
 118
 119 static const u32 host_save_user_msrs[] = {
 120 #ifdef CONFIG_X86_64
 121         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 122         MSR_FS_BASE,
 123 #endif
 124         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 125         MSR_TSC_AUX,
 126 };
 127
 128 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 129
 130 struct kvm_vcpu;
 131
 132 struct nested_state {
 133         struct vmcb *hsave;
 134         u64 hsave_msr;
 135         u64 vm_cr_msr;
 136         u64 vmcb;
 137
 138         /* These are the merged vectors */
 139         u32 *msrpm;
 140
 141         /* gpa pointers to the real vectors */
 142         u64 vmcb_msrpm;
 143         u64 vmcb_iopm;
 144
 145         /* A VMEXIT is required but not yet emulated */
 146         bool exit_required;
 147
 148         /* cache for intercepts of the guest */
 149         u32 intercept_cr;
 150         u32 intercept_dr;
 151         u32 intercept_exceptions;
 152         u64 intercept;
 153
 154         /* Nested Paging related state */
 155         u64 nested_cr3;
 156 };
 157
 158 #define MSRPM_OFFSETS   16
 159 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 160
 161 /*
 162  * Set osvw_len to higher value when updated Revision Guides
 163  * are published and we know what the new status bits are
 164  */
 165 static uint64_t osvw_len = 4, osvw_status;
 166
 167 struct vcpu_svm {
 168         struct kvm_vcpu vcpu;
 169         struct vmcb *vmcb;
 170         unsigned long vmcb_pa;
 171         struct svm_cpu_data *svm_data;
 172         uint64_t asid_generation;
 173         uint64_t sysenter_esp;
 174         uint64_t sysenter_eip;
 175         uint64_t tsc_aux;
 176
 177         u64 next_rip;
 178
 179         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 180         struct {
 181                 u16 fs;
 182                 u16 gs;
 183                 u16 ldt;
 184                 u64 gs_base;
 185         } host;
 186
 187         u32 *msrpm;
 188
 189         ulong nmi_iret_rip;
 190
 191         struct nested_state nested;
 192
 193         bool nmi_singlestep;
 194         u64 nmi_singlestep_guest_rflags;
 195
 196         unsigned int3_injected;
 197         unsigned long int3_rip;
 198
 199         /* cached guest cpuid flags for faster access */
 200         bool nrips_enabled      : 1;
 201
 202         u32 ldr_reg;
 203         struct page *avic_backing_page;
 204         u64 *avic_physical_id_cache;
 205         bool avic_is_running;
 206
 207         /*
 208          * Per-vcpu list of struct amd_svm_iommu_ir:
 209          * This is used mainly to store interrupt remapping information used
 210          * when update the vcpu affinity. This avoids the need to scan for
 211          * IRTE and try to match ga_tag in the IOMMU driver.
 212          */
 213         struct list_head ir_list;
 214         spinlock_t ir_list_lock;
 215 };
 216
 217 /*
 218  * This is a wrapper of struct amd_iommu_ir_data.
 219  */
 220 struct amd_svm_iommu_ir {
 221         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 222         void *data;             /* Storing pointer to struct amd_ir_data */
 223 };
 224
 225 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 226 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 227
 228 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 229 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 230 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 231 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 232
 233 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 234 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 235
 236 #define MSR_INVALID                     0xffffffffU
 237
 238 static const struct svm_direct_access_msrs {
 239         u32 index;   /* Index of the MSR */
 240         bool always; /* True if intercept is always on */
 241 } direct_access_msrs[] = {
 242         { .index = MSR_STAR,                            .always = true  },
 243         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 244 #ifdef CONFIG_X86_64
 245         { .index = MSR_GS_BASE,                         .always = true  },
 246         { .index = MSR_FS_BASE,                         .always = true  },
 247         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 248         { .index = MSR_LSTAR,                           .always = true  },
 249         { .index = MSR_CSTAR,                           .always = true  },
 250         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 251 #endif
 252         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 253         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 254         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 255         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 256         { .index = MSR_INVALID,                         .always = false },
 257 };
 258
 259 /* enable NPT for AMD64 and X86 with PAE */
 260 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 261 static bool npt_enabled = true;
 262 #else
 263 static bool npt_enabled;
 264 #endif
 265
 266 /* allow nested paging (virtualized MMU) for all guests */
 267 static int npt = true;
 268 module_param(npt, int, S_IRUGO);
 269
 270 /* allow nested virtualization in KVM/SVM */
 271 static int nested = true;
 272 module_param(nested, int, S_IRUGO);
 273
 274 /* enable / disable AVIC */
 275 static int avic;
 276 #ifdef CONFIG_X86_LOCAL_APIC
 277 module_param(avic, int, S_IRUGO);
 278 #endif
 279
 280 /* enable/disable Virtual VMLOAD VMSAVE */
 281 static int vls = true;
 282 module_param(vls, int, 0444);
 283
 284 /* enable/disable Virtual GIF */
 285 static int vgif = true;
 286 module_param(vgif, int, 0444);
 287
 288 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 289 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 290 static void svm_complete_interrupts(struct vcpu_svm *svm);
 291
 292 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 293 static int nested_svm_intercept(struct vcpu_svm *svm);
 294 static int nested_svm_vmexit(struct vcpu_svm *svm);
 295 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 296                                       bool has_error_code, u32 error_code);
 297
 298 enum {
 299         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 300                             pause filter count */
 301         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 302         VMCB_ASID,       /* ASID */
 303         VMCB_INTR,       /* int_ctl, int_vector */
 304         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 305         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 306         VMCB_DR,         /* DR6, DR7 */
 307         VMCB_DT,         /* GDT, IDT */
 308         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 309         VMCB_CR2,        /* CR2 only */
 310         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 311         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 312                           * AVIC PHYSICAL_TABLE pointer,
 313                           * AVIC LOGICAL_TABLE pointer
 314                           */
 315         VMCB_DIRTY_MAX,
 316 };
 317
 318 /* TPR and CR2 are always written before VMRUN */
 319 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 320
 321 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 322
 323 static inline void mark_all_dirty(struct vmcb *vmcb)
 324 {
 325         vmcb->control.clean = 0;
 326 }
 327
 328 static inline void mark_all_clean(struct vmcb *vmcb)
 329 {
 330         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 331                                & ~VMCB_ALWAYS_DIRTY_MASK;
 332 }
 333
 334 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 335 {
 336         vmcb->control.clean &= ~(1 << bit);
 337 }
 338
 339 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 340 {
 341         return container_of(vcpu, struct vcpu_svm, vcpu);
 342 }
 343
 344 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 345 {
 346         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 347         mark_dirty(svm->vmcb, VMCB_AVIC);
 348 }
 349
 350 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 351 {
 352         struct vcpu_svm *svm = to_svm(vcpu);
 353         u64 *entry = svm->avic_physical_id_cache;
 354
 355         if (!entry)
 356                 return false;
 357
 358         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 359 }
 360
 361 static void recalc_intercepts(struct vcpu_svm *svm)
 362 {
 363         struct vmcb_control_area *c, *h;
 364         struct nested_state *g;
 365
 366         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 367
 368         if (!is_guest_mode(&svm->vcpu))
 369                 return;
 370
 371         c = &svm->vmcb->control;
 372         h = &svm->nested.hsave->control;
 373         g = &svm->nested;
 374
 375         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 376         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 377         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 378         c->intercept = h->intercept | g->intercept;
 379 }
 380
 381 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 382 {
 383         if (is_guest_mode(&svm->vcpu))
 384                 return svm->nested.hsave;
 385         else
 386                 return svm->vmcb;
 387 }
 388
 389 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 390 {
 391         struct vmcb *vmcb = get_host_vmcb(svm);
 392
 393         vmcb->control.intercept_cr |= (1U << bit);
 394
 395         recalc_intercepts(svm);
 396 }
 397
 398 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 399 {
 400         struct vmcb *vmcb = get_host_vmcb(svm);
 401
 402         vmcb->control.intercept_cr &= ~(1U << bit);
 403
 404         recalc_intercepts(svm);
 405 }
 406
 407 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 408 {
 409         struct vmcb *vmcb = get_host_vmcb(svm);
 410
 411         return vmcb->control.intercept_cr & (1U << bit);
 412 }
 413
 414 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 415 {
 416         struct vmcb *vmcb = get_host_vmcb(svm);
 417
 418         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 419                 | (1 << INTERCEPT_DR1_READ)
 420                 | (1 << INTERCEPT_DR2_READ)
 421                 | (1 << INTERCEPT_DR3_READ)
 422                 | (1 << INTERCEPT_DR4_READ)
 423                 | (1 << INTERCEPT_DR5_READ)
 424                 | (1 << INTERCEPT_DR6_READ)
 425                 | (1 << INTERCEPT_DR7_READ)
 426                 | (1 << INTERCEPT_DR0_WRITE)
 427                 | (1 << INTERCEPT_DR1_WRITE)
 428                 | (1 << INTERCEPT_DR2_WRITE)
 429                 | (1 << INTERCEPT_DR3_WRITE)
 430                 | (1 << INTERCEPT_DR4_WRITE)
 431                 | (1 << INTERCEPT_DR5_WRITE)
 432                 | (1 << INTERCEPT_DR6_WRITE)
 433                 | (1 << INTERCEPT_DR7_WRITE);
 434
 435         recalc_intercepts(svm);
 436 }
 437
 438 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 439 {
 440         struct vmcb *vmcb = get_host_vmcb(svm);
 441
 442         vmcb->control.intercept_dr = 0;
 443
 444         recalc_intercepts(svm);
 445 }
 446
 447 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 448 {
 449         struct vmcb *vmcb = get_host_vmcb(svm);
 450
 451         vmcb->control.intercept_exceptions |= (1U << bit);
 452
 453         recalc_intercepts(svm);
 454 }
 455
 456 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 457 {
 458         struct vmcb *vmcb = get_host_vmcb(svm);
 459
 460         vmcb->control.intercept_exceptions &= ~(1U << bit);
 461
 462         recalc_intercepts(svm);
 463 }
 464
 465 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 466 {
 467         struct vmcb *vmcb = get_host_vmcb(svm);
 468
 469         vmcb->control.intercept |= (1ULL << bit);
 470
 471         recalc_intercepts(svm);
 472 }
 473
 474 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 475 {
 476         struct vmcb *vmcb = get_host_vmcb(svm);
 477
 478         vmcb->control.intercept &= ~(1ULL << bit);
 479
 480         recalc_intercepts(svm);
 481 }
 482
 483 static inline bool vgif_enabled(struct vcpu_svm *svm)
 484 {
 485         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 486 }
 487
 488 static inline void enable_gif(struct vcpu_svm *svm)
 489 {
 490         if (vgif_enabled(svm))
 491                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 492         else
 493                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 494 }
 495
 496 static inline void disable_gif(struct vcpu_svm *svm)
 497 {
 498         if (vgif_enabled(svm))
 499                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 500         else
 501                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 502 }
 503
 504 static inline bool gif_set(struct vcpu_svm *svm)
 505 {
 506         if (vgif_enabled(svm))
 507                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 508         else
 509                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 510 }
 511
 512 static unsigned long iopm_base;
 513
 514 struct kvm_ldttss_desc {
 515         u16 limit0;
 516         u16 base0;
 517         unsigned base1:8, type:5, dpl:2, p:1;
 518         unsigned limit1:4, zero0:3, g:1, base2:8;
 519         u32 base3;
 520         u32 zero1;
 521 } __attribute__((packed));
 522
 523 struct svm_cpu_data {
 524         int cpu;
 525
 526         u64 asid_generation;
 527         u32 max_asid;
 528         u32 next_asid;
 529         struct kvm_ldttss_desc *tss_desc;
 530
 531         struct page *save_area;
 532 };
 533
 534 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 535
 536 struct svm_init_data {
 537         int cpu;
 538         int r;
 539 };
 540
 541 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 542
 543 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 544 #define MSRS_RANGE_SIZE 2048
 545 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 546
 547 static u32 svm_msrpm_offset(u32 msr)
 548 {
 549         u32 offset;
 550         int i;
 551
 552         for (i = 0; i < NUM_MSR_MAPS; i++) {
 553                 if (msr < msrpm_ranges[i] ||
 554                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 555                         continue;
 556
 557                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 558                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 559
 560                 /* Now we have the u8 offset - but need the u32 offset */
 561                 return offset / 4;
 562         }
 563
 564         /* MSR not in any range */
 565         return MSR_INVALID;
 566 }
 567
 568 #define MAX_INST_SIZE 15
 569
 570 static inline void clgi(void)
 571 {
 572         asm volatile (__ex(SVM_CLGI));
 573 }
 574
 575 static inline void stgi(void)
 576 {
 577         asm volatile (__ex(SVM_STGI));
 578 }
 579
 580 static inline void invlpga(unsigned long addr, u32 asid)
 581 {
 582         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 583 }
 584
 585 static int get_npt_level(struct kvm_vcpu *vcpu)
 586 {
 587 #ifdef CONFIG_X86_64
 588         return PT64_ROOT_4LEVEL;
 589 #else
 590         return PT32E_ROOT_LEVEL;
 591 #endif
 592 }
 593
 594 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 595 {
 596         vcpu->arch.efer = efer;
 597         if (!npt_enabled && !(efer & EFER_LMA))
 598                 efer &= ~EFER_LME;
 599
 600         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 601         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 602 }
 603
 604 static int is_external_interrupt(u32 info)
 605 {
 606         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 607         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 608 }
 609
 610 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 611 {
 612         struct vcpu_svm *svm = to_svm(vcpu);
 613         u32 ret = 0;
 614
 615         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 616                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 617         return ret;
 618 }
 619
 620 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 621 {
 622         struct vcpu_svm *svm = to_svm(vcpu);
 623
 624         if (mask == 0)
 625                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 626         else
 627                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 628
 629 }
 630
 631 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 632 {
 633         struct vcpu_svm *svm = to_svm(vcpu);
 634
 635         if (svm->vmcb->control.next_rip != 0) {
 636                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 637                 svm->next_rip = svm->vmcb->control.next_rip;
 638         }
 639
 640         if (!svm->next_rip) {
 641                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 642                                 EMULATE_DONE)
 643                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 644                 return;
 645         }
 646         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 647                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 648                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 649
 650         kvm_rip_write(vcpu, svm->next_rip);
 651         svm_set_interrupt_shadow(vcpu, 0);
 652 }
 653
 654 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 655 {
 656         struct vcpu_svm *svm = to_svm(vcpu);
 657         unsigned nr = vcpu->arch.exception.nr;
 658         bool has_error_code = vcpu->arch.exception.has_error_code;
 659         bool reinject = vcpu->arch.exception.injected;
 660         u32 error_code = vcpu->arch.exception.error_code;
 661
 662         /*
 663          * If we are within a nested VM we'd better #VMEXIT and let the guest
 664          * handle the exception
 665          */
 666         if (!reinject &&
 667             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 668                 return;
 669
 670         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 671                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 672
 673                 /*
 674                  * For guest debugging where we have to reinject #BP if some
 675                  * INT3 is guest-owned:
 676                  * Emulate nRIP by moving RIP forward. Will fail if injection
 677                  * raises a fault that is not intercepted. Still better than
 678                  * failing in all cases.
 679                  */
 680                 skip_emulated_instruction(&svm->vcpu);
 681                 rip = kvm_rip_read(&svm->vcpu);
 682                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 683                 svm->int3_injected = rip - old_rip;
 684         }
 685
 686         svm->vmcb->control.event_inj = nr
 687                 | SVM_EVTINJ_VALID
 688                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 689                 | SVM_EVTINJ_TYPE_EXEPT;
 690         svm->vmcb->control.event_inj_err = error_code;
 691 }
 692
 693 static void svm_init_erratum_383(void)
 694 {
 695         u32 low, high;
 696         int err;
 697         u64 val;
 698
 699         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 700                 return;
 701
 702         /* Use _safe variants to not break nested virtualization */
 703         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 704         if (err)
 705                 return;
 706
 707         val |= (1ULL << 47);
 708
 709         low  = lower_32_bits(val);
 710         high = upper_32_bits(val);
 711
 712         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 713
 714         erratum_383_found = true;
 715 }
 716
 717 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 718 {
 719         /*
 720          * Guests should see errata 400 and 415 as fixed (assuming that
 721          * HLT and IO instructions are intercepted).
 722          */
 723         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 724         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 725
 726         /*
 727          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 728          * all osvw.status bits inside that length, including bit 0 (which is
 729          * reserved for erratum 298), are valid. However, if host processor's
 730          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 731          * be conservative here and therefore we tell the guest that erratum 298
 732          * is present (because we really don't know).
 733          */
 734         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 735                 vcpu->arch.osvw.status |= 1;
 736 }
 737
 738 static int has_svm(void)
 739 {
 740         const char *msg;
 741
 742         if (!cpu_has_svm(&msg)) {
 743                 printk(KERN_INFO "has_svm: %s\n", msg);
 744                 return 0;
 745         }
 746
 747         return 1;
 748 }
 749
 750 static void svm_hardware_disable(void)
 751 {
 752         /* Make sure we clean up behind us */
 753         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 754                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 755
 756         cpu_svm_disable();
 757
 758         amd_pmu_disable_virt();
 759 }
 760
 761 static int svm_hardware_enable(void)
 762 {
 763
 764         struct svm_cpu_data *sd;
 765         uint64_t efer;
 766         struct desc_struct *gdt;
 767         int me = raw_smp_processor_id();
 768
 769         rdmsrl(MSR_EFER, efer);
 770         if (efer & EFER_SVME)
 771                 return -EBUSY;
 772
 773         if (!has_svm()) {
 774                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 775                 return -EINVAL;
 776         }
 777         sd = per_cpu(svm_data, me);
 778         if (!sd) {
 779                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 780                 return -EINVAL;
 781         }
 782
 783         sd->asid_generation = 1;
 784         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 785         sd->next_asid = sd->max_asid + 1;
 786
 787         gdt = get_current_gdt_rw();
 788         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 789
 790         wrmsrl(MSR_EFER, efer | EFER_SVME);
 791
 792         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 793
 794         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 795                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 796                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 797         }
 798
 799
 800         /*
 801          * Get OSVW bits.
 802          *
 803          * Note that it is possible to have a system with mixed processor
 804          * revisions and therefore different OSVW bits. If bits are not the same
 805          * on different processors then choose the worst case (i.e. if erratum
 806          * is present on one processor and not on another then assume that the
 807          * erratum is present everywhere).
 808          */
 809         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 810                 uint64_t len, status = 0;
 811                 int err;
 812
 813                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 814                 if (!err)
 815                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 816                                                       &err);
 817
 818                 if (err)
 819                         osvw_status = osvw_len = 0;
 820                 else {
 821                         if (len < osvw_len)
 822                                 osvw_len = len;
 823                         osvw_status |= status;
 824                         osvw_status &= (1ULL << osvw_len) - 1;
 825                 }
 826         } else
 827                 osvw_status = osvw_len = 0;
 828
 829         svm_init_erratum_383();
 830
 831         amd_pmu_enable_virt();
 832
 833         return 0;
 834 }
 835
 836 static void svm_cpu_uninit(int cpu)
 837 {
 838         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 839
 840         if (!sd)
 841                 return;
 842
 843         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 844         __free_page(sd->save_area);
 845         kfree(sd);
 846 }
 847
 848 static int svm_cpu_init(int cpu)
 849 {
 850         struct svm_cpu_data *sd;
 851         int r;
 852
 853         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 854         if (!sd)
 855                 return -ENOMEM;
 856         sd->cpu = cpu;
 857         sd->save_area = alloc_page(GFP_KERNEL);
 858         r = -ENOMEM;
 859         if (!sd->save_area)
 860                 goto err_1;
 861
 862         per_cpu(svm_data, cpu) = sd;
 863
 864         return 0;
 865
 866 err_1:
 867         kfree(sd);
 868         return r;
 869
 870 }
 871
 872 static bool valid_msr_intercept(u32 index)
 873 {
 874         int i;
 875
 876         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 877                 if (direct_access_msrs[i].index == index)
 878                         return true;
 879
 880         return false;
 881 }
 882
 883 static void set_msr_interception(u32 *msrpm, unsigned msr,
 884                                  int read, int write)
 885 {
 886         u8 bit_read, bit_write;
 887         unsigned long tmp;
 888         u32 offset;
 889
 890         /*
 891          * If this warning triggers extend the direct_access_msrs list at the
 892          * beginning of the file
 893          */
 894         WARN_ON(!valid_msr_intercept(msr));
 895
 896         offset    = svm_msrpm_offset(msr);
 897         bit_read  = 2 * (msr & 0x0f);
 898         bit_write = 2 * (msr & 0x0f) + 1;
 899         tmp       = msrpm[offset];
 900
 901         BUG_ON(offset == MSR_INVALID);
 902
 903         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 904         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 905
 906         msrpm[offset] = tmp;
 907 }
 908
 909 static void svm_vcpu_init_msrpm(u32 *msrpm)
 910 {
 911         int i;
 912
 913         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 914
 915         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 916                 if (!direct_access_msrs[i].always)
 917                         continue;
 918
 919                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 920         }
 921 }
 922
 923 static void add_msr_offset(u32 offset)
 924 {
 925         int i;
 926
 927         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 928
 929                 /* Offset already in list? */
 930                 if (msrpm_offsets[i] == offset)
 931                         return;
 932
 933                 /* Slot used by another offset? */
 934                 if (msrpm_offsets[i] != MSR_INVALID)
 935                         continue;
 936
 937                 /* Add offset to list */
 938                 msrpm_offsets[i] = offset;
 939
 940                 return;
 941         }
 942
 943         /*
 944          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 945          * increase MSRPM_OFFSETS in this case.
 946          */
 947         BUG();
 948 }
 949
 950 static void init_msrpm_offsets(void)
 951 {
 952         int i;
 953
 954         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 955
 956         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 957                 u32 offset;
 958
 959                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 960                 BUG_ON(offset == MSR_INVALID);
 961
 962                 add_msr_offset(offset);
 963         }
 964 }
 965
 966 static void svm_enable_lbrv(struct vcpu_svm *svm)
 967 {
 968         u32 *msrpm = svm->msrpm;
 969
 970         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 971         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 972         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 973         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 974         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 975 }
 976
 977 static void svm_disable_lbrv(struct vcpu_svm *svm)
 978 {
 979         u32 *msrpm = svm->msrpm;
 980
 981         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 982         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 983         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 984         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 985         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 986 }
 987
 988 static void disable_nmi_singlestep(struct vcpu_svm *svm)
 989 {
 990         svm->nmi_singlestep = false;
 991
 992         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 993                 /* Clear our flags if they were not set by the guest */
 994                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 995                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 996                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 997                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 998         }
 999 }
1000
1001 /* Note:
1002  * This hash table is used to map VM_ID to a struct kvm_arch,
1003  * when handling AMD IOMMU GALOG notification to schedule in
1004  * a particular vCPU.
1005  */
1006 #define SVM_VM_DATA_HASH_BITS   8
1007 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1008 static u32 next_vm_id = 0;
1009 static bool next_vm_id_wrapped = 0;
1010 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1011
1012 /* Note:
1013  * This function is called from IOMMU driver to notify
1014  * SVM to schedule in a particular vCPU of a particular VM.
1015  */
1016 static int avic_ga_log_notifier(u32 ga_tag)
1017 {
1018         unsigned long flags;
1019         struct kvm_arch *ka = NULL;
1020         struct kvm_vcpu *vcpu = NULL;
1021         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1022         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1023
1024         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1025
1026         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1027         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1028                 struct kvm *kvm = container_of(ka, struct kvm, arch);
1029                 struct kvm_arch *vm_data = &kvm->arch;
1030
1031                 if (vm_data->avic_vm_id != vm_id)
1032                         continue;
1033                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1034                 break;
1035         }
1036         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1037
1038         /* Note:
1039          * At this point, the IOMMU should have already set the pending
1040          * bit in the vAPIC backing page. So, we just need to schedule
1041          * in the vcpu.
1042          */
1043         if (vcpu)
1044                 kvm_vcpu_wake_up(vcpu);
1045
1046         return 0;
1047 }
1048
1049 static __init int svm_hardware_setup(void)
1050 {
1051         int cpu;
1052         struct page *iopm_pages;
1053         void *iopm_va;
1054         int r;
1055
1056         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1057
1058         if (!iopm_pages)
1059                 return -ENOMEM;
1060
1061         iopm_va = page_address(iopm_pages);
1062         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1063         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1064
1065         init_msrpm_offsets();
1066
1067         if (boot_cpu_has(X86_FEATURE_NX))
1068                 kvm_enable_efer_bits(EFER_NX);
1069
1070         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1071                 kvm_enable_efer_bits(EFER_FFXSR);
1072
1073         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1074                 kvm_has_tsc_control = true;
1075                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1076                 kvm_tsc_scaling_ratio_frac_bits = 32;
1077         }
1078
1079         if (nested) {
1080                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1081                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1082         }
1083
1084         for_each_possible_cpu(cpu) {
1085                 r = svm_cpu_init(cpu);
1086                 if (r)
1087                         goto err;
1088         }
1089
1090         if (!boot_cpu_has(X86_FEATURE_NPT))
1091                 npt_enabled = false;
1092
1093         if (npt_enabled && !npt) {
1094                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1095                 npt_enabled = false;
1096         }
1097
1098         if (npt_enabled) {
1099                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1100                 kvm_enable_tdp();
1101         } else
1102                 kvm_disable_tdp();
1103
1104         if (avic) {
1105                 if (!npt_enabled ||
1106                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1107                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1108                         avic = false;
1109                 } else {
1110                         pr_info("AVIC enabled\n");
1111
1112                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1113                 }
1114         }
1115
1116         if (vls) {
1117                 if (!npt_enabled ||
1118                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1119                     !IS_ENABLED(CONFIG_X86_64)) {
1120                         vls = false;
1121                 } else {
1122                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1123                 }
1124         }
1125
1126         if (vgif) {
1127                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1128                         vgif = false;
1129                 else
1130                         pr_info("Virtual GIF supported\n");
1131         }
1132
1133         return 0;
1134
1135 err:
1136         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1137         iopm_base = 0;
1138         return r;
1139 }
1140
1141 static __exit void svm_hardware_unsetup(void)
1142 {
1143         int cpu;
1144
1145         for_each_possible_cpu(cpu)
1146                 svm_cpu_uninit(cpu);
1147
1148         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1149         iopm_base = 0;
1150 }
1151
1152 static void init_seg(struct vmcb_seg *seg)
1153 {
1154         seg->selector = 0;
1155         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1156                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1157         seg->limit = 0xffff;
1158         seg->base = 0;
1159 }
1160
1161 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1162 {
1163         seg->selector = 0;
1164         seg->attrib = SVM_SELECTOR_P_MASK | type;
1165         seg->limit = 0xffff;
1166         seg->base = 0;
1167 }
1168
1169 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1170 {
1171         struct vcpu_svm *svm = to_svm(vcpu);
1172         u64 g_tsc_offset = 0;
1173
1174         if (is_guest_mode(vcpu)) {
1175                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1176                                svm->nested.hsave->control.tsc_offset;
1177                 svm->nested.hsave->control.tsc_offset = offset;
1178         } else
1179                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1180                                            svm->vmcb->control.tsc_offset,
1181                                            offset);
1182
1183         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1184
1185         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1186 }
1187
1188 static void avic_init_vmcb(struct vcpu_svm *svm)
1189 {
1190         struct vmcb *vmcb = svm->vmcb;
1191         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1192         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1193         phys_addr_t lpa = __sme_set(page_to_phys(vm_data->avic_logical_id_table_page));
1194         phys_addr_t ppa = __sme_set(page_to_phys(vm_data->avic_physical_id_table_page));
1195
1196         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1197         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1198         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1199         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1200         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1201 }
1202
1203 static void init_vmcb(struct vcpu_svm *svm)
1204 {
1205         struct vmcb_control_area *control = &svm->vmcb->control;
1206         struct vmcb_save_area *save = &svm->vmcb->save;
1207
1208         svm->vcpu.arch.hflags = 0;
1209
1210         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1211         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1212         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1213         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1214         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1215         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1216         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1217                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1218
1219         set_dr_intercepts(svm);
1220
1221         set_exception_intercept(svm, PF_VECTOR);
1222         set_exception_intercept(svm, UD_VECTOR);
1223         set_exception_intercept(svm, MC_VECTOR);
1224         set_exception_intercept(svm, AC_VECTOR);
1225         set_exception_intercept(svm, DB_VECTOR);
1226
1227         set_intercept(svm, INTERCEPT_INTR);
1228         set_intercept(svm, INTERCEPT_NMI);
1229         set_intercept(svm, INTERCEPT_SMI);
1230         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1231         set_intercept(svm, INTERCEPT_RDPMC);
1232         set_intercept(svm, INTERCEPT_CPUID);
1233         set_intercept(svm, INTERCEPT_INVD);
1234         set_intercept(svm, INTERCEPT_HLT);
1235         set_intercept(svm, INTERCEPT_INVLPG);
1236         set_intercept(svm, INTERCEPT_INVLPGA);
1237         set_intercept(svm, INTERCEPT_IOIO_PROT);
1238         set_intercept(svm, INTERCEPT_MSR_PROT);
1239         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1240         set_intercept(svm, INTERCEPT_SHUTDOWN);
1241         set_intercept(svm, INTERCEPT_VMRUN);
1242         set_intercept(svm, INTERCEPT_VMMCALL);
1243         set_intercept(svm, INTERCEPT_VMLOAD);
1244         set_intercept(svm, INTERCEPT_VMSAVE);
1245         set_intercept(svm, INTERCEPT_STGI);
1246         set_intercept(svm, INTERCEPT_CLGI);
1247         set_intercept(svm, INTERCEPT_SKINIT);
1248         set_intercept(svm, INTERCEPT_WBINVD);
1249         set_intercept(svm, INTERCEPT_XSETBV);
1250
1251         if (!kvm_mwait_in_guest()) {
1252                 set_intercept(svm, INTERCEPT_MONITOR);
1253                 set_intercept(svm, INTERCEPT_MWAIT);
1254         }
1255
1256         control->iopm_base_pa = __sme_set(iopm_base);
1257         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1258         control->int_ctl = V_INTR_MASKING_MASK;
1259
1260         init_seg(&save->es);
1261         init_seg(&save->ss);
1262         init_seg(&save->ds);
1263         init_seg(&save->fs);
1264         init_seg(&save->gs);
1265
1266         save->cs.selector = 0xf000;
1267         save->cs.base = 0xffff0000;
1268         /* Executable/Readable Code Segment */
1269         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1270                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1271         save->cs.limit = 0xffff;
1272
1273         save->gdtr.limit = 0xffff;
1274         save->idtr.limit = 0xffff;
1275
1276         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1277         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1278
1279         svm_set_efer(&svm->vcpu, 0);
1280         save->dr6 = 0xffff0ff0;
1281         kvm_set_rflags(&svm->vcpu, 2);
1282         save->rip = 0x0000fff0;
1283         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1284
1285         /*
1286          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1287          * It also updates the guest-visible cr0 value.
1288          */
1289         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1290         kvm_mmu_reset_context(&svm->vcpu);
1291
1292         save->cr4 = X86_CR4_PAE;
1293         /* rdx = ?? */
1294
1295         if (npt_enabled) {
1296                 /* Setup VMCB for Nested Paging */
1297                 control->nested_ctl = 1;
1298                 clr_intercept(svm, INTERCEPT_INVLPG);
1299                 clr_exception_intercept(svm, PF_VECTOR);
1300                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1301                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1302                 save->g_pat = svm->vcpu.arch.pat;
1303                 save->cr3 = 0;
1304                 save->cr4 = 0;
1305         }
1306         svm->asid_generation = 0;
1307
1308         svm->nested.vmcb = 0;
1309         svm->vcpu.arch.hflags = 0;
1310
1311         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1312                 control->pause_filter_count = 3000;
1313                 set_intercept(svm, INTERCEPT_PAUSE);
1314         }
1315
1316         if (kvm_vcpu_apicv_active(&svm->vcpu))
1317                 avic_init_vmcb(svm);
1318
1319         /*
1320          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1321          * in VMCB and clear intercepts to avoid #VMEXIT.
1322          */
1323         if (vls) {
1324                 clr_intercept(svm, INTERCEPT_VMLOAD);
1325                 clr_intercept(svm, INTERCEPT_VMSAVE);
1326                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1327         }
1328
1329         if (vgif) {
1330                 clr_intercept(svm, INTERCEPT_STGI);
1331                 clr_intercept(svm, INTERCEPT_CLGI);
1332                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1333         }
1334
1335         mark_all_dirty(svm->vmcb);
1336
1337         enable_gif(svm);
1338
1339 }
1340
1341 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1342                                        unsigned int index)
1343 {
1344         u64 *avic_physical_id_table;
1345         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1346
1347         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1348                 return NULL;
1349
1350         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1351
1352         return &avic_physical_id_table[index];
1353 }
1354
1355 /**
1356  * Note:
1357  * AVIC hardware walks the nested page table to check permissions,
1358  * but does not use the SPA address specified in the leaf page
1359  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1360  * field of the VMCB. Therefore, we set up the
1361  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1362  */
1363 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1364 {
1365         struct kvm *kvm = vcpu->kvm;
1366         int ret;
1367
1368         if (kvm->arch.apic_access_page_done)
1369                 return 0;
1370
1371         ret = x86_set_memory_region(kvm,
1372                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1373                                     APIC_DEFAULT_PHYS_BASE,
1374                                     PAGE_SIZE);
1375         if (ret)
1376                 return ret;
1377
1378         kvm->arch.apic_access_page_done = true;
1379         return 0;
1380 }
1381
1382 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1383 {
1384         int ret;
1385         u64 *entry, new_entry;
1386         int id = vcpu->vcpu_id;
1387         struct vcpu_svm *svm = to_svm(vcpu);
1388
1389         ret = avic_init_access_page(vcpu);
1390         if (ret)
1391                 return ret;
1392
1393         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1394                 return -EINVAL;
1395
1396         if (!svm->vcpu.arch.apic->regs)
1397                 return -EINVAL;
1398
1399         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1400
1401         /* Setting AVIC backing page address in the phy APIC ID table */
1402         entry = avic_get_physical_id_entry(vcpu, id);
1403         if (!entry)
1404                 return -EINVAL;
1405
1406         new_entry = READ_ONCE(*entry);
1407         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1408                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1409                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1410         WRITE_ONCE(*entry, new_entry);
1411
1412         svm->avic_physical_id_cache = entry;
1413
1414         return 0;
1415 }
1416
1417 static void avic_vm_destroy(struct kvm *kvm)
1418 {
1419         unsigned long flags;
1420         struct kvm_arch *vm_data = &kvm->arch;
1421
1422         if (!avic)
1423                 return;
1424
1425         if (vm_data->avic_logical_id_table_page)
1426                 __free_page(vm_data->avic_logical_id_table_page);
1427         if (vm_data->avic_physical_id_table_page)
1428                 __free_page(vm_data->avic_physical_id_table_page);
1429
1430         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1431         hash_del(&vm_data->hnode);
1432         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1433 }
1434
1435 static int avic_vm_init(struct kvm *kvm)
1436 {
1437         unsigned long flags;
1438         int err = -ENOMEM;
1439         struct kvm_arch *vm_data = &kvm->arch;
1440         struct page *p_page;
1441         struct page *l_page;
1442         struct kvm_arch *ka;
1443         u32 vm_id;
1444
1445         if (!avic)
1446                 return 0;
1447
1448         /* Allocating physical APIC ID table (4KB) */
1449         p_page = alloc_page(GFP_KERNEL);
1450         if (!p_page)
1451                 goto free_avic;
1452
1453         vm_data->avic_physical_id_table_page = p_page;
1454         clear_page(page_address(p_page));
1455
1456         /* Allocating logical APIC ID table (4KB) */
1457         l_page = alloc_page(GFP_KERNEL);
1458         if (!l_page)
1459                 goto free_avic;
1460
1461         vm_data->avic_logical_id_table_page = l_page;
1462         clear_page(page_address(l_page));
1463
1464         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1465  again:
1466         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1467         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1468                 next_vm_id_wrapped = 1;
1469                 goto again;
1470         }
1471         /* Is it still in use? Only possible if wrapped at least once */
1472         if (next_vm_id_wrapped) {
1473                 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1474                         struct kvm *k2 = container_of(ka, struct kvm, arch);
1475                         struct kvm_arch *vd2 = &k2->arch;
1476                         if (vd2->avic_vm_id == vm_id)
1477                                 goto again;
1478                 }
1479         }
1480         vm_data->avic_vm_id = vm_id;
1481         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1482         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1483
1484         return 0;
1485
1486 free_avic:
1487         avic_vm_destroy(kvm);
1488         return err;
1489 }
1490
1491 static inline int
1492 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1493 {
1494         int ret = 0;
1495         unsigned long flags;
1496         struct amd_svm_iommu_ir *ir;
1497         struct vcpu_svm *svm = to_svm(vcpu);
1498
1499         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1500                 return 0;
1501
1502         /*
1503          * Here, we go through the per-vcpu ir_list to update all existing
1504          * interrupt remapping table entry targeting this vcpu.
1505          */
1506         spin_lock_irqsave(&svm->ir_list_lock, flags);
1507
1508         if (list_empty(&svm->ir_list))
1509                 goto out;
1510
1511         list_for_each_entry(ir, &svm->ir_list, node) {
1512                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1513                 if (ret)
1514                         break;
1515         }
1516 out:
1517         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1518         return ret;
1519 }
1520
1521 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1522 {
1523         u64 entry;
1524         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1525         int h_physical_id = kvm_cpu_get_apicid(cpu);
1526         struct vcpu_svm *svm = to_svm(vcpu);
1527
1528         if (!kvm_vcpu_apicv_active(vcpu))
1529                 return;
1530
1531         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1532                 return;
1533
1534         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1535         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1536
1537         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1538         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1539
1540         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1541         if (svm->avic_is_running)
1542                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1543
1544         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1545         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1546                                         svm->avic_is_running);
1547 }
1548
1549 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1550 {
1551         u64 entry;
1552         struct vcpu_svm *svm = to_svm(vcpu);
1553
1554         if (!kvm_vcpu_apicv_active(vcpu))
1555                 return;
1556
1557         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1558         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1559                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1560
1561         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1562         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1563 }
1564
1565 /**
1566  * This function is called during VCPU halt/unhalt.
1567  */
1568 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1569 {
1570         struct vcpu_svm *svm = to_svm(vcpu);
1571
1572         svm->avic_is_running = is_run;
1573         if (is_run)
1574                 avic_vcpu_load(vcpu, vcpu->cpu);
1575         else
1576                 avic_vcpu_put(vcpu);
1577 }
1578
1579 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1580 {
1581         struct vcpu_svm *svm = to_svm(vcpu);
1582         u32 dummy;
1583         u32 eax = 1;
1584
1585         if (!init_event) {
1586                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1587                                            MSR_IA32_APICBASE_ENABLE;
1588                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1589                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1590         }
1591         init_vmcb(svm);
1592
1593         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
1594         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1595
1596         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1597                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1598 }
1599
1600 static int avic_init_vcpu(struct vcpu_svm *svm)
1601 {
1602         int ret;
1603
1604         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1605                 return 0;
1606
1607         ret = avic_init_backing_page(&svm->vcpu);
1608         if (ret)
1609                 return ret;
1610
1611         INIT_LIST_HEAD(&svm->ir_list);
1612         spin_lock_init(&svm->ir_list_lock);
1613
1614         return ret;
1615 }
1616
1617 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1618 {
1619         struct vcpu_svm *svm;
1620         struct page *page;
1621         struct page *msrpm_pages;
1622         struct page *hsave_page;
1623         struct page *nested_msrpm_pages;
1624         int err;
1625
1626         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1627         if (!svm) {
1628                 err = -ENOMEM;
1629                 goto out;
1630         }
1631
1632         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1633         if (err)
1634                 goto free_svm;
1635
1636         err = -ENOMEM;
1637         page = alloc_page(GFP_KERNEL);
1638         if (!page)
1639                 goto uninit;
1640
1641         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1642         if (!msrpm_pages)
1643                 goto free_page1;
1644
1645         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1646         if (!nested_msrpm_pages)
1647                 goto free_page2;
1648
1649         hsave_page = alloc_page(GFP_KERNEL);
1650         if (!hsave_page)
1651                 goto free_page3;
1652
1653         err = avic_init_vcpu(svm);
1654         if (err)
1655                 goto free_page4;
1656
1657         /* We initialize this flag to true to make sure that the is_running
1658          * bit would be set the first time the vcpu is loaded.
1659          */
1660         svm->avic_is_running = true;
1661
1662         svm->nested.hsave = page_address(hsave_page);
1663
1664         svm->msrpm = page_address(msrpm_pages);
1665         svm_vcpu_init_msrpm(svm->msrpm);
1666
1667         svm->nested.msrpm = page_address(nested_msrpm_pages);
1668         svm_vcpu_init_msrpm(svm->nested.msrpm);
1669
1670         svm->vmcb = page_address(page);
1671         clear_page(svm->vmcb);
1672         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1673         svm->asid_generation = 0;
1674         init_vmcb(svm);
1675
1676         svm_init_osvw(&svm->vcpu);
1677
1678         return &svm->vcpu;
1679
1680 free_page4:
1681         __free_page(hsave_page);
1682 free_page3:
1683         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1684 free_page2:
1685         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1686 free_page1:
1687         __free_page(page);
1688 uninit:
1689         kvm_vcpu_uninit(&svm->vcpu);
1690 free_svm:
1691         kmem_cache_free(kvm_vcpu_cache, svm);
1692 out:
1693         return ERR_PTR(err);
1694 }
1695
1696 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1697 {
1698         struct vcpu_svm *svm = to_svm(vcpu);
1699
1700         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1701         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1702         __free_page(virt_to_page(svm->nested.hsave));
1703         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1704         kvm_vcpu_uninit(vcpu);
1705         kmem_cache_free(kvm_vcpu_cache, svm);
1706 }
1707
1708 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1709 {
1710         struct vcpu_svm *svm = to_svm(vcpu);
1711         int i;
1712
1713         if (unlikely(cpu != vcpu->cpu)) {
1714                 svm->asid_generation = 0;
1715                 mark_all_dirty(svm->vmcb);
1716         }
1717
1718 #ifdef CONFIG_X86_64
1719         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1720 #endif
1721         savesegment(fs, svm->host.fs);
1722         savesegment(gs, svm->host.gs);
1723         svm->host.ldt = kvm_read_ldt();
1724
1725         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1726                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1727
1728         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1729                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1730                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1731                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1732                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1733                 }
1734         }
1735         /* This assumes that the kernel never uses MSR_TSC_AUX */
1736         if (static_cpu_has(X86_FEATURE_RDTSCP))
1737                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1738
1739         avic_vcpu_load(vcpu, cpu);
1740 }
1741
1742 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1743 {
1744         struct vcpu_svm *svm = to_svm(vcpu);
1745         int i;
1746
1747         avic_vcpu_put(vcpu);
1748
1749         ++vcpu->stat.host_state_reload;
1750         kvm_load_ldt(svm->host.ldt);
1751 #ifdef CONFIG_X86_64
1752         loadsegment(fs, svm->host.fs);
1753         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1754         load_gs_index(svm->host.gs);
1755 #else
1756 #ifdef CONFIG_X86_32_LAZY_GS
1757         loadsegment(gs, svm->host.gs);
1758 #endif
1759 #endif
1760         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1761                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1762 }
1763
1764 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1765 {
1766         avic_set_running(vcpu, false);
1767 }
1768
1769 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1770 {
1771         avic_set_running(vcpu, true);
1772 }
1773
1774 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1775 {
1776         struct vcpu_svm *svm = to_svm(vcpu);
1777         unsigned long rflags = svm->vmcb->save.rflags;
1778
1779         if (svm->nmi_singlestep) {
1780                 /* Hide our flags if they were not set by the guest */
1781                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1782                         rflags &= ~X86_EFLAGS_TF;
1783                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1784                         rflags &= ~X86_EFLAGS_RF;
1785         }
1786         return rflags;
1787 }
1788
1789 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1790 {
1791         if (to_svm(vcpu)->nmi_singlestep)
1792                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1793
1794        /*
1795         * Any change of EFLAGS.VM is accompanied by a reload of SS
1796         * (caused by either a task switch or an inter-privilege IRET),
1797         * so we do not need to update the CPL here.
1798         */
1799         to_svm(vcpu)->vmcb->save.rflags = rflags;
1800 }
1801
1802 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1803 {
1804         switch (reg) {
1805         case VCPU_EXREG_PDPTR:
1806                 BUG_ON(!npt_enabled);
1807                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1808                 break;
1809         default:
1810                 BUG();
1811         }
1812 }
1813
1814 static void svm_set_vintr(struct vcpu_svm *svm)
1815 {
1816         set_intercept(svm, INTERCEPT_VINTR);
1817 }
1818
1819 static void svm_clear_vintr(struct vcpu_svm *svm)
1820 {
1821         clr_intercept(svm, INTERCEPT_VINTR);
1822 }
1823
1824 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1825 {
1826         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1827
1828         switch (seg) {
1829         case VCPU_SREG_CS: return &save->cs;
1830         case VCPU_SREG_DS: return &save->ds;
1831         case VCPU_SREG_ES: return &save->es;
1832         case VCPU_SREG_FS: return &save->fs;
1833         case VCPU_SREG_GS: return &save->gs;
1834         case VCPU_SREG_SS: return &save->ss;
1835         case VCPU_SREG_TR: return &save->tr;
1836         case VCPU_SREG_LDTR: return &save->ldtr;
1837         }
1838         BUG();
1839         return NULL;
1840 }
1841
1842 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1843 {
1844         struct vmcb_seg *s = svm_seg(vcpu, seg);
1845
1846         return s->base;
1847 }
1848
1849 static void svm_get_segment(struct kvm_vcpu *vcpu,
1850                             struct kvm_segment *var, int seg)
1851 {
1852         struct vmcb_seg *s = svm_seg(vcpu, seg);
1853
1854         var->base = s->base;
1855         var->limit = s->limit;
1856         var->selector = s->selector;
1857         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1858         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1859         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1860         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1861         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1862         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1863         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1864
1865         /*
1866          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1867          * However, the SVM spec states that the G bit is not observed by the
1868          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1869          * So let's synthesize a legal G bit for all segments, this helps
1870          * running KVM nested. It also helps cross-vendor migration, because
1871          * Intel's vmentry has a check on the 'G' bit.
1872          */
1873         var->g = s->limit > 0xfffff;
1874
1875         /*
1876          * AMD's VMCB does not have an explicit unusable field, so emulate it
1877          * for cross vendor migration purposes by "not present"
1878          */
1879         var->unusable = !var->present;
1880
1881         switch (seg) {
1882         case VCPU_SREG_TR:
1883                 /*
1884                  * Work around a bug where the busy flag in the tr selector
1885                  * isn't exposed
1886                  */
1887                 var->type |= 0x2;
1888                 break;
1889         case VCPU_SREG_DS:
1890         case VCPU_SREG_ES:
1891         case VCPU_SREG_FS:
1892         case VCPU_SREG_GS:
1893                 /*
1894                  * The accessed bit must always be set in the segment
1895                  * descriptor cache, although it can be cleared in the
1896                  * descriptor, the cached bit always remains at 1. Since
1897                  * Intel has a check on this, set it here to support
1898                  * cross-vendor migration.
1899                  */
1900                 if (!var->unusable)
1901                         var->type |= 0x1;
1902                 break;
1903         case VCPU_SREG_SS:
1904                 /*
1905                  * On AMD CPUs sometimes the DB bit in the segment
1906                  * descriptor is left as 1, although the whole segment has
1907                  * been made unusable. Clear it here to pass an Intel VMX
1908                  * entry check when cross vendor migrating.
1909                  */
1910                 if (var->unusable)
1911                         var->db = 0;
1912                 /* This is symmetric with svm_set_segment() */
1913                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1914                 break;
1915         }
1916 }
1917
1918 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1919 {
1920         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1921
1922         return save->cpl;
1923 }
1924
1925 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1926 {
1927         struct vcpu_svm *svm = to_svm(vcpu);
1928
1929         dt->size = svm->vmcb->save.idtr.limit;
1930         dt->address = svm->vmcb->save.idtr.base;
1931 }
1932
1933 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1934 {
1935         struct vcpu_svm *svm = to_svm(vcpu);
1936
1937         svm->vmcb->save.idtr.limit = dt->size;
1938         svm->vmcb->save.idtr.base = dt->address ;
1939         mark_dirty(svm->vmcb, VMCB_DT);
1940 }
1941
1942 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1943 {
1944         struct vcpu_svm *svm = to_svm(vcpu);
1945
1946         dt->size = svm->vmcb->save.gdtr.limit;
1947         dt->address = svm->vmcb->save.gdtr.base;
1948 }
1949
1950 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1951 {
1952         struct vcpu_svm *svm = to_svm(vcpu);
1953
1954         svm->vmcb->save.gdtr.limit = dt->size;
1955         svm->vmcb->save.gdtr.base = dt->address ;
1956         mark_dirty(svm->vmcb, VMCB_DT);
1957 }
1958
1959 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1960 {
1961 }
1962
1963 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1964 {
1965 }
1966
1967 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1968 {
1969 }
1970
1971 static void update_cr0_intercept(struct vcpu_svm *svm)
1972 {
1973         ulong gcr0 = svm->vcpu.arch.cr0;
1974         u64 *hcr0 = &svm->vmcb->save.cr0;
1975
1976         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1977                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1978
1979         mark_dirty(svm->vmcb, VMCB_CR);
1980
1981         if (gcr0 == *hcr0) {
1982                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1983                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1984         } else {
1985                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1986                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1987         }
1988 }
1989
1990 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1991 {
1992         struct vcpu_svm *svm = to_svm(vcpu);
1993
1994 #ifdef CONFIG_X86_64
1995         if (vcpu->arch.efer & EFER_LME) {
1996                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1997                         vcpu->arch.efer |= EFER_LMA;
1998                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1999                 }
2000
2001                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2002                         vcpu->arch.efer &= ~EFER_LMA;
2003                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2004                 }
2005         }
2006 #endif
2007         vcpu->arch.cr0 = cr0;
2008
2009         if (!npt_enabled)
2010                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2011
2012         /*
2013          * re-enable caching here because the QEMU bios
2014          * does not do it - this results in some delay at
2015          * reboot
2016          */
2017         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2018                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2019         svm->vmcb->save.cr0 = cr0;
2020         mark_dirty(svm->vmcb, VMCB_CR);
2021         update_cr0_intercept(svm);
2022 }
2023
2024 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2025 {
2026         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2027         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2028
2029         if (cr4 & X86_CR4_VMXE)
2030                 return 1;
2031
2032         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2033                 svm_flush_tlb(vcpu);
2034
2035         vcpu->arch.cr4 = cr4;
2036         if (!npt_enabled)
2037                 cr4 |= X86_CR4_PAE;
2038         cr4 |= host_cr4_mce;
2039         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2040         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2041         return 0;
2042 }
2043
2044 static void svm_set_segment(struct kvm_vcpu *vcpu,
2045                             struct kvm_segment *var, int seg)
2046 {
2047         struct vcpu_svm *svm = to_svm(vcpu);
2048         struct vmcb_seg *s = svm_seg(vcpu, seg);
2049
2050         s->base = var->base;
2051         s->limit = var->limit;
2052         s->selector = var->selector;
2053         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2054         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2055         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2056         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2057         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2058         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2059         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2060         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2061
2062         /*
2063          * This is always accurate, except if SYSRET returned to a segment
2064          * with SS.DPL != 3.  Intel does not have this quirk, and always
2065          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2066          * would entail passing the CPL to userspace and back.
2067          */
2068         if (seg == VCPU_SREG_SS)
2069                 /* This is symmetric with svm_get_segment() */
2070                 svm->vmcb->save.cpl = (var->dpl & 3);
2071
2072         mark_dirty(svm->vmcb, VMCB_SEG);
2073 }
2074
2075 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2076 {
2077         struct vcpu_svm *svm = to_svm(vcpu);
2078
2079         clr_exception_intercept(svm, BP_VECTOR);
2080
2081         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2082                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2083                         set_exception_intercept(svm, BP_VECTOR);
2084         } else
2085                 vcpu->guest_debug = 0;
2086 }
2087
2088 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2089 {
2090         if (sd->next_asid > sd->max_asid) {
2091                 ++sd->asid_generation;
2092                 sd->next_asid = 1;
2093                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2094         }
2095
2096         svm->asid_generation = sd->asid_generation;
2097         svm->vmcb->control.asid = sd->next_asid++;
2098
2099         mark_dirty(svm->vmcb, VMCB_ASID);
2100 }
2101
2102 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2103 {
2104         return to_svm(vcpu)->vmcb->save.dr6;
2105 }
2106
2107 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2108 {
2109         struct vcpu_svm *svm = to_svm(vcpu);
2110
2111         svm->vmcb->save.dr6 = value;
2112         mark_dirty(svm->vmcb, VMCB_DR);
2113 }
2114
2115 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2116 {
2117         struct vcpu_svm *svm = to_svm(vcpu);
2118
2119         get_debugreg(vcpu->arch.db[0], 0);
2120         get_debugreg(vcpu->arch.db[1], 1);
2121         get_debugreg(vcpu->arch.db[2], 2);
2122         get_debugreg(vcpu->arch.db[3], 3);
2123         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2124         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2125
2126         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2127         set_dr_intercepts(svm);
2128 }
2129
2130 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2131 {
2132         struct vcpu_svm *svm = to_svm(vcpu);
2133
2134         svm->vmcb->save.dr7 = value;
2135         mark_dirty(svm->vmcb, VMCB_DR);
2136 }
2137
2138 static int pf_interception(struct vcpu_svm *svm)
2139 {
2140         u64 fault_address = svm->vmcb->control.exit_info_2;
2141         u64 error_code = svm->vmcb->control.exit_info_1;
2142
2143         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2144                         svm->vmcb->control.insn_bytes,
2145                         svm->vmcb->control.insn_len);
2146 }
2147
2148 static int npf_interception(struct vcpu_svm *svm)
2149 {
2150         u64 fault_address = svm->vmcb->control.exit_info_2;
2151         u64 error_code = svm->vmcb->control.exit_info_1;
2152
2153         trace_kvm_page_fault(fault_address, error_code);
2154         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2155                         svm->vmcb->control.insn_bytes,
2156                         svm->vmcb->control.insn_len);
2157 }
2158
2159 static int db_interception(struct vcpu_svm *svm)
2160 {
2161         struct kvm_run *kvm_run = svm->vcpu.run;
2162
2163         if (!(svm->vcpu.guest_debug &
2164               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2165                 !svm->nmi_singlestep) {
2166                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2167                 return 1;
2168         }
2169
2170         if (svm->nmi_singlestep) {
2171                 disable_nmi_singlestep(svm);
2172         }
2173
2174         if (svm->vcpu.guest_debug &
2175             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2176                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2177                 kvm_run->debug.arch.pc =
2178                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2179                 kvm_run->debug.arch.exception = DB_VECTOR;
2180                 return 0;
2181         }
2182
2183         return 1;
2184 }
2185
2186 static int bp_interception(struct vcpu_svm *svm)
2187 {
2188         struct kvm_run *kvm_run = svm->vcpu.run;
2189
2190         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2191         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2192         kvm_run->debug.arch.exception = BP_VECTOR;
2193         return 0;
2194 }
2195
2196 static int ud_interception(struct vcpu_svm *svm)
2197 {
2198         int er;
2199
2200         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2201         if (er == EMULATE_USER_EXIT)
2202                 return 0;
2203         if (er != EMULATE_DONE)
2204                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2205         return 1;
2206 }
2207
2208 static int ac_interception(struct vcpu_svm *svm)
2209 {
2210         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2211         return 1;
2212 }
2213
2214 static bool is_erratum_383(void)
2215 {
2216         int err, i;
2217         u64 value;
2218
2219         if (!erratum_383_found)
2220                 return false;
2221
2222         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2223         if (err)
2224                 return false;
2225
2226         /* Bit 62 may or may not be set for this mce */
2227         value &= ~(1ULL << 62);
2228
2229         if (value != 0xb600000000010015ULL)
2230                 return false;
2231
2232         /* Clear MCi_STATUS registers */
2233         for (i = 0; i < 6; ++i)
2234                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2235
2236         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2237         if (!err) {
2238                 u32 low, high;
2239
2240                 value &= ~(1ULL << 2);
2241                 low    = lower_32_bits(value);
2242                 high   = upper_32_bits(value);
2243
2244                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2245         }
2246
2247         /* Flush tlb to evict multi-match entries */
2248         __flush_tlb_all();
2249
2250         return true;
2251 }
2252
2253 static void svm_handle_mce(struct vcpu_svm *svm)
2254 {
2255         if (is_erratum_383()) {
2256                 /*
2257                  * Erratum 383 triggered. Guest state is corrupt so kill the
2258                  * guest.
2259                  */
2260                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2261
2262                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2263
2264                 return;
2265         }
2266
2267         /*
2268          * On an #MC intercept the MCE handler is not called automatically in
2269          * the host. So do it by hand here.
2270          */
2271         asm volatile (
2272                 "int $0x12\n");
2273         /* not sure if we ever come back to this point */
2274
2275         return;
2276 }
2277
2278 static int mc_interception(struct vcpu_svm *svm)
2279 {
2280         return 1;
2281 }
2282
2283 static int shutdown_interception(struct vcpu_svm *svm)
2284 {
2285         struct kvm_run *kvm_run = svm->vcpu.run;
2286
2287         /*
2288          * VMCB is undefined after a SHUTDOWN intercept
2289          * so reinitialize it.
2290          */
2291         clear_page(svm->vmcb);
2292         init_vmcb(svm);
2293
2294         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2295         return 0;
2296 }
2297
2298 static int io_interception(struct vcpu_svm *svm)
2299 {
2300         struct kvm_vcpu *vcpu = &svm->vcpu;
2301         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2302         int size, in, string, ret;
2303         unsigned port;
2304
2305         ++svm->vcpu.stat.io_exits;
2306         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2307         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2308         if (string)
2309                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2310
2311         port = io_info >> 16;
2312         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2313         svm->next_rip = svm->vmcb->control.exit_info_2;
2314         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2315
2316         /*
2317          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2318          * KVM_EXIT_DEBUG here.
2319          */
2320         if (in)
2321                 return kvm_fast_pio_in(vcpu, size, port) && ret;
2322         else
2323                 return kvm_fast_pio_out(vcpu, size, port) && ret;
2324 }
2325
2326 static int nmi_interception(struct vcpu_svm *svm)
2327 {
2328         return 1;
2329 }
2330
2331 static int intr_interception(struct vcpu_svm *svm)
2332 {
2333         ++svm->vcpu.stat.irq_exits;
2334         return 1;
2335 }
2336
2337 static int nop_on_interception(struct vcpu_svm *svm)
2338 {
2339         return 1;
2340 }
2341
2342 static int halt_interception(struct vcpu_svm *svm)
2343 {
2344         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2345         return kvm_emulate_halt(&svm->vcpu);
2346 }
2347
2348 static int vmmcall_interception(struct vcpu_svm *svm)
2349 {
2350         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2351         return kvm_emulate_hypercall(&svm->vcpu);
2352 }
2353
2354 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2355 {
2356         struct vcpu_svm *svm = to_svm(vcpu);
2357
2358         return svm->nested.nested_cr3;
2359 }
2360
2361 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2362 {
2363         struct vcpu_svm *svm = to_svm(vcpu);
2364         u64 cr3 = svm->nested.nested_cr3;
2365         u64 pdpte;
2366         int ret;
2367
2368         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2369                                        offset_in_page(cr3) + index * 8, 8);
2370         if (ret)
2371                 return 0;
2372         return pdpte;
2373 }
2374
2375 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2376                                    unsigned long root)
2377 {
2378         struct vcpu_svm *svm = to_svm(vcpu);
2379
2380         svm->vmcb->control.nested_cr3 = __sme_set(root);
2381         mark_dirty(svm->vmcb, VMCB_NPT);
2382         svm_flush_tlb(vcpu);
2383 }
2384
2385 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2386                                        struct x86_exception *fault)
2387 {
2388         struct vcpu_svm *svm = to_svm(vcpu);
2389
2390         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2391                 /*
2392                  * TODO: track the cause of the nested page fault, and
2393                  * correctly fill in the high bits of exit_info_1.
2394                  */
2395                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2396                 svm->vmcb->control.exit_code_hi = 0;
2397                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2398                 svm->vmcb->control.exit_info_2 = fault->address;
2399         }
2400
2401         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2402         svm->vmcb->control.exit_info_1 |= fault->error_code;
2403
2404         /*
2405          * The present bit is always zero for page structure faults on real
2406          * hardware.
2407          */
2408         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2409                 svm->vmcb->control.exit_info_1 &= ~1;
2410
2411         nested_svm_vmexit(svm);
2412 }
2413
2414 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2415 {
2416         WARN_ON(mmu_is_nested(vcpu));
2417         kvm_init_shadow_mmu(vcpu);
2418         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2419         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2420         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2421         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2422         vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2423         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2424         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2425 }
2426
2427 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2428 {
2429         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2430 }
2431
2432 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2433 {
2434         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2435             !is_paging(&svm->vcpu)) {
2436                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2437                 return 1;
2438         }
2439
2440         if (svm->vmcb->save.cpl) {
2441                 kvm_inject_gp(&svm->vcpu, 0);
2442                 return 1;
2443         }
2444
2445         return 0;
2446 }
2447
2448 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2449                                       bool has_error_code, u32 error_code)
2450 {
2451         int vmexit;
2452
2453         if (!is_guest_mode(&svm->vcpu))
2454                 return 0;
2455
2456         vmexit = nested_svm_intercept(svm);
2457         if (vmexit != NESTED_EXIT_DONE)
2458                 return 0;
2459
2460         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2461         svm->vmcb->control.exit_code_hi = 0;
2462         svm->vmcb->control.exit_info_1 = error_code;
2463
2464         /*
2465          * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2466          * The fix is to add the ancillary datum (CR2 or DR6) to structs
2467          * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2468          * written only when inject_pending_event runs (DR6 would written here
2469          * too).  This should be conditional on a new capability---if the
2470          * capability is disabled, kvm_multiple_exception would write the
2471          * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2472          */
2473         if (svm->vcpu.arch.exception.nested_apf)
2474                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2475         else
2476                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2477
2478         svm->nested.exit_required = true;
2479         return vmexit;
2480 }
2481
2482 /* This function returns true if it is save to enable the irq window */
2483 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2484 {
2485         if (!is_guest_mode(&svm->vcpu))
2486                 return true;
2487
2488         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2489                 return true;
2490
2491         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2492                 return false;
2493
2494         /*
2495          * if vmexit was already requested (by intercepted exception
2496          * for instance) do not overwrite it with "external interrupt"
2497          * vmexit.
2498          */
2499         if (svm->nested.exit_required)
2500                 return false;
2501
2502         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2503         svm->vmcb->control.exit_info_1 = 0;
2504         svm->vmcb->control.exit_info_2 = 0;
2505
2506         if (svm->nested.intercept & 1ULL) {
2507                 /*
2508                  * The #vmexit can't be emulated here directly because this
2509                  * code path runs with irqs and preemption disabled. A
2510                  * #vmexit emulation might sleep. Only signal request for
2511                  * the #vmexit here.
2512                  */
2513                 svm->nested.exit_required = true;
2514                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2515                 return false;
2516         }
2517
2518         return true;
2519 }
2520
2521 /* This function returns true if it is save to enable the nmi window */
2522 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2523 {
2524         if (!is_guest_mode(&svm->vcpu))
2525                 return true;
2526
2527         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2528                 return true;
2529
2530         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2531         svm->nested.exit_required = true;
2532
2533         return false;
2534 }
2535
2536 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2537 {
2538         struct page *page;
2539
2540         might_sleep();
2541
2542         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2543         if (is_error_page(page))
2544                 goto error;
2545
2546         *_page = page;
2547
2548         return kmap(page);
2549
2550 error:
2551         kvm_inject_gp(&svm->vcpu, 0);
2552
2553         return NULL;
2554 }
2555
2556 static void nested_svm_unmap(struct page *page)
2557 {
2558         kunmap(page);
2559         kvm_release_page_dirty(page);
2560 }
2561
2562 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2563 {
2564         unsigned port, size, iopm_len;
2565         u16 val, mask;
2566         u8 start_bit;
2567         u64 gpa;
2568
2569         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2570                 return NESTED_EXIT_HOST;
2571
2572         port = svm->vmcb->control.exit_info_1 >> 16;
2573         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2574                 SVM_IOIO_SIZE_SHIFT;
2575         gpa  = svm->nested.vmcb_iopm + (port / 8);
2576         start_bit = port % 8;
2577         iopm_len = (start_bit + size > 8) ? 2 : 1;
2578         mask = (0xf >> (4 - size)) << start_bit;
2579         val = 0;
2580
2581         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2582                 return NESTED_EXIT_DONE;
2583
2584         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2585 }
2586
2587 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2588 {
2589         u32 offset, msr, value;
2590         int write, mask;
2591
2592         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2593                 return NESTED_EXIT_HOST;
2594
2595         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2596         offset = svm_msrpm_offset(msr);
2597         write  = svm->vmcb->control.exit_info_1 & 1;
2598         mask   = 1 << ((2 * (msr & 0xf)) + write);
2599
2600         if (offset == MSR_INVALID)
2601                 return NESTED_EXIT_DONE;
2602
2603         /* Offset is in 32 bit units but need in 8 bit units */
2604         offset *= 4;
2605
2606         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2607                 return NESTED_EXIT_DONE;
2608
2609         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2610 }
2611
2612 /* DB exceptions for our internal use must not cause vmexit */
2613 static int nested_svm_intercept_db(struct vcpu_svm *svm)
2614 {
2615         unsigned long dr6;
2616
2617         /* if we're not singlestepping, it's not ours */
2618         if (!svm->nmi_singlestep)
2619                 return NESTED_EXIT_DONE;
2620
2621         /* if it's not a singlestep exception, it's not ours */
2622         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
2623                 return NESTED_EXIT_DONE;
2624         if (!(dr6 & DR6_BS))
2625                 return NESTED_EXIT_DONE;
2626
2627         /* if the guest is singlestepping, it should get the vmexit */
2628         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
2629                 disable_nmi_singlestep(svm);
2630                 return NESTED_EXIT_DONE;
2631         }
2632
2633         /* it's ours, the nested hypervisor must not see this one */
2634         return NESTED_EXIT_HOST;
2635 }
2636
2637 static int nested_svm_exit_special(struct vcpu_svm *svm)
2638 {
2639         u32 exit_code = svm->vmcb->control.exit_code;
2640
2641         switch (exit_code) {
2642         case SVM_EXIT_INTR:
2643         case SVM_EXIT_NMI:
2644         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2645                 return NESTED_EXIT_HOST;
2646         case SVM_EXIT_NPF:
2647                 /* For now we are always handling NPFs when using them */
2648                 if (npt_enabled)
2649                         return NESTED_EXIT_HOST;
2650                 break;
2651         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2652                 /* When we're shadowing, trap PFs, but not async PF */
2653                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
2654                         return NESTED_EXIT_HOST;
2655                 break;
2656         default:
2657                 break;
2658         }
2659
2660         return NESTED_EXIT_CONTINUE;
2661 }
2662
2663 /*
2664  * If this function returns true, this #vmexit was already handled
2665  */
2666 static int nested_svm_intercept(struct vcpu_svm *svm)
2667 {
2668         u32 exit_code = svm->vmcb->control.exit_code;
2669         int vmexit = NESTED_EXIT_HOST;
2670
2671         switch (exit_code) {
2672         case SVM_EXIT_MSR:
2673                 vmexit = nested_svm_exit_handled_msr(svm);
2674                 break;
2675         case SVM_EXIT_IOIO:
2676                 vmexit = nested_svm_intercept_ioio(svm);
2677                 break;
2678         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2679                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2680                 if (svm->nested.intercept_cr & bit)
2681                         vmexit = NESTED_EXIT_DONE;
2682                 break;
2683         }
2684         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2685                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2686                 if (svm->nested.intercept_dr & bit)
2687                         vmexit = NESTED_EXIT_DONE;
2688                 break;
2689         }
2690         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2691                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2692                 if (svm->nested.intercept_exceptions & excp_bits) {
2693                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
2694                                 vmexit = nested_svm_intercept_db(svm);
2695                         else
2696                                 vmexit = NESTED_EXIT_DONE;
2697                 }
2698                 /* async page fault always cause vmexit */
2699                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2700                          svm->vcpu.arch.exception.nested_apf != 0)
2701                         vmexit = NESTED_EXIT_DONE;
2702                 break;
2703         }
2704         case SVM_EXIT_ERR: {
2705                 vmexit = NESTED_EXIT_DONE;
2706                 break;
2707         }
2708         default: {
2709                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2710                 if (svm->nested.intercept & exit_bits)
2711                         vmexit = NESTED_EXIT_DONE;
2712         }
2713         }
2714
2715         return vmexit;
2716 }
2717
2718 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2719 {
2720         int vmexit;
2721
2722         vmexit = nested_svm_intercept(svm);
2723
2724         if (vmexit == NESTED_EXIT_DONE)
2725                 nested_svm_vmexit(svm);
2726
2727         return vmexit;
2728 }
2729
2730 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2731 {
2732         struct vmcb_control_area *dst  = &dst_vmcb->control;
2733         struct vmcb_control_area *from = &from_vmcb->control;
2734
2735         dst->intercept_cr         = from->intercept_cr;
2736         dst->intercept_dr         = from->intercept_dr;
2737         dst->intercept_exceptions = from->intercept_exceptions;
2738         dst->intercept            = from->intercept;
2739         dst->iopm_base_pa         = from->iopm_base_pa;
2740         dst->msrpm_base_pa        = from->msrpm_base_pa;
2741         dst->tsc_offset           = from->tsc_offset;
2742         dst->asid                 = from->asid;
2743         dst->tlb_ctl              = from->tlb_ctl;
2744         dst->int_ctl              = from->int_ctl;
2745         dst->int_vector           = from->int_vector;
2746         dst->int_state            = from->int_state;
2747         dst->exit_code            = from->exit_code;
2748         dst->exit_code_hi         = from->exit_code_hi;
2749         dst->exit_info_1          = from->exit_info_1;
2750         dst->exit_info_2          = from->exit_info_2;
2751         dst->exit_int_info        = from->exit_int_info;
2752         dst->exit_int_info_err    = from->exit_int_info_err;
2753         dst->nested_ctl           = from->nested_ctl;
2754         dst->event_inj            = from->event_inj;
2755         dst->event_inj_err        = from->event_inj_err;
2756         dst->nested_cr3           = from->nested_cr3;
2757         dst->virt_ext              = from->virt_ext;
2758 }
2759
2760 static int nested_svm_vmexit(struct vcpu_svm *svm)
2761 {
2762         struct vmcb *nested_vmcb;
2763         struct vmcb *hsave = svm->nested.hsave;
2764         struct vmcb *vmcb = svm->vmcb;
2765         struct page *page;
2766
2767         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2768                                        vmcb->control.exit_info_1,
2769                                        vmcb->control.exit_info_2,
2770                                        vmcb->control.exit_int_info,
2771                                        vmcb->control.exit_int_info_err,
2772                                        KVM_ISA_SVM);
2773
2774         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2775         if (!nested_vmcb)
2776                 return 1;
2777
2778         /* Exit Guest-Mode */
2779         leave_guest_mode(&svm->vcpu);
2780         svm->nested.vmcb = 0;
2781
2782         /* Give the current vmcb to the guest */
2783         disable_gif(svm);
2784
2785         nested_vmcb->save.es     = vmcb->save.es;
2786         nested_vmcb->save.cs     = vmcb->save.cs;
2787         nested_vmcb->save.ss     = vmcb->save.ss;
2788         nested_vmcb->save.ds     = vmcb->save.ds;
2789         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2790         nested_vmcb->save.idtr   = vmcb->save.idtr;
2791         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2792         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2793         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2794         nested_vmcb->save.cr2    = vmcb->save.cr2;
2795         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2796         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2797         nested_vmcb->save.rip    = vmcb->save.rip;
2798         nested_vmcb->save.rsp    = vmcb->save.rsp;
2799         nested_vmcb->save.rax    = vmcb->save.rax;
2800         nested_vmcb->save.dr7    = vmcb->save.dr7;
2801         nested_vmcb->save.dr6    = vmcb->save.dr6;
2802         nested_vmcb->save.cpl    = vmcb->save.cpl;
2803
2804         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2805         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2806         nested_vmcb->control.int_state         = vmcb->control.int_state;
2807         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2808         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2809         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2810         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2811         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2812         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2813
2814         if (svm->nrips_enabled)
2815                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2816
2817         /*
2818          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2819          * to make sure that we do not lose injected events. So check event_inj
2820          * here and copy it to exit_int_info if it is valid.
2821          * Exit_int_info and event_inj can't be both valid because the case
2822          * below only happens on a VMRUN instruction intercept which has
2823          * no valid exit_int_info set.
2824          */
2825         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2826                 struct vmcb_control_area *nc = &nested_vmcb->control;
2827
2828                 nc->exit_int_info     = vmcb->control.event_inj;
2829                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2830         }
2831
2832         nested_vmcb->control.tlb_ctl           = 0;
2833         nested_vmcb->control.event_inj         = 0;
2834         nested_vmcb->control.event_inj_err     = 0;
2835
2836         /* We always set V_INTR_MASKING and remember the old value in hflags */
2837         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2838                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2839
2840         /* Restore the original control entries */
2841         copy_vmcb_control_area(vmcb, hsave);
2842
2843         kvm_clear_exception_queue(&svm->vcpu);
2844         kvm_clear_interrupt_queue(&svm->vcpu);
2845
2846         svm->nested.nested_cr3 = 0;
2847
2848         /* Restore selected save entries */
2849         svm->vmcb->save.es = hsave->save.es;
2850         svm->vmcb->save.cs = hsave->save.cs;
2851         svm->vmcb->save.ss = hsave->save.ss;
2852         svm->vmcb->save.ds = hsave->save.ds;
2853         svm->vmcb->save.gdtr = hsave->save.gdtr;
2854         svm->vmcb->save.idtr = hsave->save.idtr;
2855         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2856         svm_set_efer(&svm->vcpu, hsave->save.efer);
2857         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2858         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2859         if (npt_enabled) {
2860                 svm->vmcb->save.cr3 = hsave->save.cr3;
2861                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2862         } else {
2863                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2864         }
2865         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2866         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2867         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2868         svm->vmcb->save.dr7 = 0;
2869         svm->vmcb->save.cpl = 0;
2870         svm->vmcb->control.exit_int_info = 0;
2871
2872         mark_all_dirty(svm->vmcb);
2873
2874         nested_svm_unmap(page);
2875
2876         nested_svm_uninit_mmu_context(&svm->vcpu);
2877         kvm_mmu_reset_context(&svm->vcpu);
2878         kvm_mmu_load(&svm->vcpu);
2879
2880         return 0;
2881 }
2882
2883 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2884 {
2885         /*
2886          * This function merges the msr permission bitmaps of kvm and the
2887          * nested vmcb. It is optimized in that it only merges the parts where
2888          * the kvm msr permission bitmap may contain zero bits
2889          */
2890         int i;
2891
2892         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2893                 return true;
2894
2895         for (i = 0; i < MSRPM_OFFSETS; i++) {
2896                 u32 value, p;
2897                 u64 offset;
2898
2899                 if (msrpm_offsets[i] == 0xffffffff)
2900                         break;
2901
2902                 p      = msrpm_offsets[i];
2903                 offset = svm->nested.vmcb_msrpm + (p * 4);
2904
2905                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2906                         return false;
2907
2908                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2909         }
2910
2911         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
2912
2913         return true;
2914 }
2915
2916 static bool nested_vmcb_checks(struct vmcb *vmcb)
2917 {
2918         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2919                 return false;
2920
2921         if (vmcb->control.asid == 0)
2922                 return false;
2923
2924         if (vmcb->control.nested_ctl && !npt_enabled)
2925                 return false;
2926
2927         return true;
2928 }
2929
2930 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
2931                                  struct vmcb *nested_vmcb, struct page *page)
2932 {
2933         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2934                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2935         else
2936                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2937
2938         if (nested_vmcb->control.nested_ctl) {
2939                 kvm_mmu_unload(&svm->vcpu);
2940                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2941                 nested_svm_init_mmu_context(&svm->vcpu);
2942         }
2943
2944         /* Load the nested guest state */
2945         svm->vmcb->save.es = nested_vmcb->save.es;
2946         svm->vmcb->save.cs = nested_vmcb->save.cs;
2947         svm->vmcb->save.ss = nested_vmcb->save.ss;
2948         svm->vmcb->save.ds = nested_vmcb->save.ds;
2949         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2950         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2951         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2952         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2953         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2954         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2955         if (npt_enabled) {
2956                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2957                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2958         } else
2959                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2960
2961         /* Guest paging mode is active - reset mmu */
2962         kvm_mmu_reset_context(&svm->vcpu);
2963
2964         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2965         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2966         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2967         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2968
2969         /* In case we don't even reach vcpu_run, the fields are not updated */
2970         svm->vmcb->save.rax = nested_vmcb->save.rax;
2971         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2972         svm->vmcb->save.rip = nested_vmcb->save.rip;
2973         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2974         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2975         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2976
2977         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2978         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2979
2980         /* cache intercepts */
2981         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2982         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2983         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2984         svm->nested.intercept            = nested_vmcb->control.intercept;
2985
2986         svm_flush_tlb(&svm->vcpu);
2987         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2988         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2989                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2990         else
2991                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2992
2993         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2994                 /* We only want the cr8 intercept bits of the guest */
2995                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2996                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2997         }
2998
2999         /* We don't want to see VMMCALLs from a nested guest */
3000         clr_intercept(svm, INTERCEPT_VMMCALL);
3001
3002         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3003         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3004         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3005         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3006         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3007         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3008
3009         nested_svm_unmap(page);
3010
3011         /* Enter Guest-Mode */
3012         enter_guest_mode(&svm->vcpu);
3013
3014         /*
3015          * Merge guest and host intercepts - must be called  with vcpu in
3016          * guest-mode to take affect here
3017          */
3018         recalc_intercepts(svm);
3019
3020         svm->nested.vmcb = vmcb_gpa;
3021
3022         enable_gif(svm);
3023
3024         mark_all_dirty(svm->vmcb);
3025 }
3026
3027 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3028 {
3029         struct vmcb *nested_vmcb;
3030         struct vmcb *hsave = svm->nested.hsave;
3031         struct vmcb *vmcb = svm->vmcb;
3032         struct page *page;
3033         u64 vmcb_gpa;
3034
3035         vmcb_gpa = svm->vmcb->save.rax;
3036
3037         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3038         if (!nested_vmcb)
3039                 return false;
3040
3041         if (!nested_vmcb_checks(nested_vmcb)) {
3042                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3043                 nested_vmcb->control.exit_code_hi = 0;
3044                 nested_vmcb->control.exit_info_1  = 0;
3045                 nested_vmcb->control.exit_info_2  = 0;
3046
3047                 nested_svm_unmap(page);
3048
3049                 return false;
3050         }
3051
3052         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3053                                nested_vmcb->save.rip,
3054                                nested_vmcb->control.int_ctl,
3055                                nested_vmcb->control.event_inj,
3056                                nested_vmcb->control.nested_ctl);
3057
3058         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3059                                     nested_vmcb->control.intercept_cr >> 16,
3060                                     nested_vmcb->control.intercept_exceptions,
3061                                     nested_vmcb->control.intercept);
3062
3063         /* Clear internal status */
3064         kvm_clear_exception_queue(&svm->vcpu);
3065         kvm_clear_interrupt_queue(&svm->vcpu);
3066
3067         /*
3068          * Save the old vmcb, so we don't need to pick what we save, but can
3069          * restore everything when a VMEXIT occurs
3070          */
3071         hsave->save.es     = vmcb->save.es;
3072         hsave->save.cs     = vmcb->save.cs;
3073         hsave->save.ss     = vmcb->save.ss;
3074         hsave->save.ds     = vmcb->save.ds;
3075         hsave->save.gdtr   = vmcb->save.gdtr;
3076         hsave->save.idtr   = vmcb->save.idtr;
3077         hsave->save.efer   = svm->vcpu.arch.efer;
3078         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3079         hsave->save.cr4    = svm->vcpu.arch.cr4;
3080         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3081         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3082         hsave->save.rsp    = vmcb->save.rsp;
3083         hsave->save.rax    = vmcb->save.rax;
3084         if (npt_enabled)
3085                 hsave->save.cr3    = vmcb->save.cr3;
3086         else
3087                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3088
3089         copy_vmcb_control_area(hsave, vmcb);
3090
3091         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3092
3093         return true;
3094 }
3095
3096 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3097 {
3098         to_vmcb->save.fs = from_vmcb->save.fs;
3099         to_vmcb->save.gs = from_vmcb->save.gs;
3100         to_vmcb->save.tr = from_vmcb->save.tr;
3101         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3102         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3103         to_vmcb->save.star = from_vmcb->save.star;
3104         to_vmcb->save.lstar = from_vmcb->save.lstar;
3105         to_vmcb->save.cstar = from_vmcb->save.cstar;
3106         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3107         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3108         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3109         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3110 }
3111
3112 static int vmload_interception(struct vcpu_svm *svm)
3113 {
3114         struct vmcb *nested_vmcb;
3115         struct page *page;
3116         int ret;
3117
3118         if (nested_svm_check_permissions(svm))
3119                 return 1;
3120
3121         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3122         if (!nested_vmcb)
3123                 return 1;
3124
3125         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3126         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3127
3128         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3129         nested_svm_unmap(page);
3130
3131         return ret;
3132 }
3133
3134 static int vmsave_interception(struct vcpu_svm *svm)
3135 {
3136         struct vmcb *nested_vmcb;
3137         struct page *page;
3138         int ret;
3139
3140         if (nested_svm_check_permissions(svm))
3141                 return 1;
3142
3143         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3144         if (!nested_vmcb)
3145                 return 1;
3146
3147         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3148         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3149
3150         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3151         nested_svm_unmap(page);
3152
3153         return ret;
3154 }
3155
3156 static int vmrun_interception(struct vcpu_svm *svm)
3157 {
3158         if (nested_svm_check_permissions(svm))
3159                 return 1;
3160
3161         /* Save rip after vmrun instruction */
3162         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3163
3164         if (!nested_svm_vmrun(svm))
3165                 return 1;
3166
3167         if (!nested_svm_vmrun_msrpm(svm))
3168                 goto failed;
3169
3170         return 1;
3171
3172 failed:
3173
3174         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3175         svm->vmcb->control.exit_code_hi = 0;
3176         svm->vmcb->control.exit_info_1  = 0;
3177         svm->vmcb->control.exit_info_2  = 0;
3178
3179         nested_svm_vmexit(svm);
3180
3181         return 1;
3182 }
3183
3184 static int stgi_interception(struct vcpu_svm *svm)
3185 {
3186         int ret;
3187
3188         if (nested_svm_check_permissions(svm))
3189                 return 1;
3190
3191         /*
3192          * If VGIF is enabled, the STGI intercept is only added to
3193          * detect the opening of the SMI/NMI window; remove it now.
3194          */
3195         if (vgif_enabled(svm))
3196                 clr_intercept(svm, INTERCEPT_STGI);
3197
3198         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3199         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3200         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3201
3202         enable_gif(svm);
3203
3204         return ret;
3205 }
3206
3207 static int clgi_interception(struct vcpu_svm *svm)
3208 {
3209         int ret;
3210
3211         if (nested_svm_check_permissions(svm))
3212                 return 1;
3213
3214         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3215         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3216
3217         disable_gif(svm);
3218
3219         /* After a CLGI no interrupts should come */
3220         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3221                 svm_clear_vintr(svm);
3222                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3223                 mark_dirty(svm->vmcb, VMCB_INTR);
3224         }
3225
3226         return ret;
3227 }
3228
3229 static int invlpga_interception(struct vcpu_svm *svm)
3230 {
3231         struct kvm_vcpu *vcpu = &svm->vcpu;
3232
3233         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3234                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3235
3236         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3237         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3238
3239         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3240         return kvm_skip_emulated_instruction(&svm->vcpu);
3241 }
3242
3243 static int skinit_interception(struct vcpu_svm *svm)
3244 {
3245         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3246
3247         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3248         return 1;
3249 }
3250
3251 static int wbinvd_interception(struct vcpu_svm *svm)
3252 {
3253         return kvm_emulate_wbinvd(&svm->vcpu);
3254 }
3255
3256 static int xsetbv_interception(struct vcpu_svm *svm)
3257 {
3258         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3259         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3260
3261         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3262                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3263                 return kvm_skip_emulated_instruction(&svm->vcpu);
3264         }
3265
3266         return 1;
3267 }
3268
3269 static int task_switch_interception(struct vcpu_svm *svm)
3270 {
3271         u16 tss_selector;
3272         int reason;
3273         int int_type = svm->vmcb->control.exit_int_info &
3274                 SVM_EXITINTINFO_TYPE_MASK;
3275         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3276         uint32_t type =
3277                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3278         uint32_t idt_v =
3279                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3280         bool has_error_code = false;
3281         u32 error_code = 0;
3282
3283         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3284
3285         if (svm->vmcb->control.exit_info_2 &
3286             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3287                 reason = TASK_SWITCH_IRET;
3288         else if (svm->vmcb->control.exit_info_2 &
3289                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3290                 reason = TASK_SWITCH_JMP;
3291         else if (idt_v)
3292                 reason = TASK_SWITCH_GATE;
3293         else
3294                 reason = TASK_SWITCH_CALL;
3295
3296         if (reason == TASK_SWITCH_GATE) {
3297                 switch (type) {
3298                 case SVM_EXITINTINFO_TYPE_NMI:
3299                         svm->vcpu.arch.nmi_injected = false;
3300                         break;
3301                 case SVM_EXITINTINFO_TYPE_EXEPT:
3302                         if (svm->vmcb->control.exit_info_2 &
3303                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3304                                 has_error_code = true;
3305                                 error_code =
3306                                         (u32)svm->vmcb->control.exit_info_2;
3307                         }
3308                         kvm_clear_exception_queue(&svm->vcpu);
3309                         break;
3310                 case SVM_EXITINTINFO_TYPE_INTR:
3311                         kvm_clear_interrupt_queue(&svm->vcpu);
3312                         break;
3313                 default:
3314                         break;
3315                 }
3316         }
3317
3318         if (reason != TASK_SWITCH_GATE ||
3319             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3320             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3321              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3322                 skip_emulated_instruction(&svm->vcpu);
3323
3324         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3325                 int_vec = -1;
3326
3327         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3328                                 has_error_code, error_code) == EMULATE_FAIL) {
3329                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3330                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3331                 svm->vcpu.run->internal.ndata = 0;
3332                 return 0;
3333         }
3334         return 1;
3335 }
3336
3337 static int cpuid_interception(struct vcpu_svm *svm)
3338 {
3339         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3340         return kvm_emulate_cpuid(&svm->vcpu);
3341 }
3342
3343 static int iret_interception(struct vcpu_svm *svm)
3344 {
3345         ++svm->vcpu.stat.nmi_window_exits;
3346         clr_intercept(svm, INTERCEPT_IRET);
3347         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3348         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3349         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3350         return 1;
3351 }
3352
3353 static int invlpg_interception(struct vcpu_svm *svm)
3354 {
3355         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3356                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3357
3358         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3359         return kvm_skip_emulated_instruction(&svm->vcpu);
3360 }
3361
3362 static int emulate_on_interception(struct vcpu_svm *svm)
3363 {
3364         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3365 }
3366
3367 static int rdpmc_interception(struct vcpu_svm *svm)
3368 {
3369         int err;
3370
3371         if (!static_cpu_has(X86_FEATURE_NRIPS))
3372                 return emulate_on_interception(svm);
3373
3374         err = kvm_rdpmc(&svm->vcpu);
3375         return kvm_complete_insn_gp(&svm->vcpu, err);
3376 }
3377
3378 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3379                                             unsigned long val)
3380 {
3381         unsigned long cr0 = svm->vcpu.arch.cr0;
3382         bool ret = false;
3383         u64 intercept;
3384
3385         intercept = svm->nested.intercept;
3386
3387         if (!is_guest_mode(&svm->vcpu) ||
3388             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3389                 return false;
3390
3391         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3392         val &= ~SVM_CR0_SELECTIVE_MASK;
3393
3394         if (cr0 ^ val) {
3395                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3396                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3397         }
3398
3399         return ret;
3400 }
3401
3402 #define CR_VALID (1ULL << 63)
3403
3404 static int cr_interception(struct vcpu_svm *svm)
3405 {
3406         int reg, cr;
3407         unsigned long val;
3408         int err;
3409
3410         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3411                 return emulate_on_interception(svm);
3412
3413         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3414                 return emulate_on_interception(svm);
3415
3416         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3417         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3418                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3419         else
3420                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3421
3422         err = 0;
3423         if (cr >= 16) { /* mov to cr */
3424                 cr -= 16;
3425                 val = kvm_register_read(&svm->vcpu, reg);
3426                 switch (cr) {
3427                 case 0:
3428                         if (!check_selective_cr0_intercepted(svm, val))
3429                                 err = kvm_set_cr0(&svm->vcpu, val);
3430                         else
3431                                 return 1;
3432
3433                         break;
3434                 case 3:
3435                         err = kvm_set_cr3(&svm->vcpu, val);
3436                         break;
3437                 case 4:
3438                         err = kvm_set_cr4(&svm->vcpu, val);
3439                         break;
3440                 case 8:
3441                         err = kvm_set_cr8(&svm->vcpu, val);
3442                         break;
3443                 default:
3444                         WARN(1, "unhandled write to CR%d", cr);
3445                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3446                         return 1;
3447                 }
3448         } else { /* mov from cr */
3449                 switch (cr) {
3450                 case 0:
3451                         val = kvm_read_cr0(&svm->vcpu);
3452                         break;
3453                 case 2:
3454                         val = svm->vcpu.arch.cr2;
3455                         break;
3456                 case 3:
3457                         val = kvm_read_cr3(&svm->vcpu);
3458                         break;
3459                 case 4:
3460                         val = kvm_read_cr4(&svm->vcpu);
3461                         break;
3462                 case 8:
3463                         val = kvm_get_cr8(&svm->vcpu);
3464                         break;
3465                 default:
3466                         WARN(1, "unhandled read from CR%d", cr);
3467                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3468                         return 1;
3469                 }
3470                 kvm_register_write(&svm->vcpu, reg, val);
3471         }
3472         return kvm_complete_insn_gp(&svm->vcpu, err);
3473 }
3474
3475 static int dr_interception(struct vcpu_svm *svm)
3476 {
3477         int reg, dr;
3478         unsigned long val;
3479
3480         if (svm->vcpu.guest_debug == 0) {
3481                 /*
3482                  * No more DR vmexits; force a reload of the debug registers
3483                  * and reenter on this instruction.  The next vmexit will
3484                  * retrieve the full state of the debug registers.
3485                  */
3486                 clr_dr_intercepts(svm);
3487                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3488                 return 1;
3489         }
3490
3491         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3492                 return emulate_on_interception(svm);
3493
3494         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3495         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3496
3497         if (dr >= 16) { /* mov to DRn */
3498                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3499                         return 1;
3500                 val = kvm_register_read(&svm->vcpu, reg);
3501                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3502         } else {
3503                 if (!kvm_require_dr(&svm->vcpu, dr))
3504                         return 1;
3505                 kvm_get_dr(&svm->vcpu, dr, &val);
3506                 kvm_register_write(&svm->vcpu, reg, val);
3507         }
3508
3509         return kvm_skip_emulated_instruction(&svm->vcpu);
3510 }
3511
3512 static int cr8_write_interception(struct vcpu_svm *svm)
3513 {
3514         struct kvm_run *kvm_run = svm->vcpu.run;
3515         int r;
3516
3517         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3518         /* instruction emulation calls kvm_set_cr8() */
3519         r = cr_interception(svm);
3520         if (lapic_in_kernel(&svm->vcpu))
3521                 return r;
3522         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3523                 return r;
3524         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3525         return 0;
3526 }
3527
3528 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3529 {
3530         struct vcpu_svm *svm = to_svm(vcpu);
3531
3532         switch (msr_info->index) {
3533         case MSR_IA32_TSC: {
3534                 msr_info->data = svm->vmcb->control.tsc_offset +
3535                         kvm_scale_tsc(vcpu, rdtsc());
3536
3537                 break;
3538         }
3539         case MSR_STAR:
3540                 msr_info->data = svm->vmcb->save.star;
3541                 break;
3542 #ifdef CONFIG_X86_64
3543         case MSR_LSTAR:
3544                 msr_info->data = svm->vmcb->save.lstar;
3545                 break;
3546         case MSR_CSTAR:
3547                 msr_info->data = svm->vmcb->save.cstar;
3548                 break;
3549         case MSR_KERNEL_GS_BASE:
3550                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3551                 break;
3552         case MSR_SYSCALL_MASK:
3553                 msr_info->data = svm->vmcb->save.sfmask;
3554                 break;
3555 #endif
3556         case MSR_IA32_SYSENTER_CS:
3557                 msr_info->data = svm->vmcb->save.sysenter_cs;
3558                 break;
3559         case MSR_IA32_SYSENTER_EIP:
3560                 msr_info->data = svm->sysenter_eip;
3561                 break;
3562         case MSR_IA32_SYSENTER_ESP:
3563                 msr_info->data = svm->sysenter_esp;
3564                 break;
3565         case MSR_TSC_AUX:
3566                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3567                         return 1;
3568                 msr_info->data = svm->tsc_aux;
3569                 break;
3570         /*
3571          * Nobody will change the following 5 values in the VMCB so we can
3572          * safely return them on rdmsr. They will always be 0 until LBRV is
3573          * implemented.
3574          */
3575         case MSR_IA32_DEBUGCTLMSR:
3576                 msr_info->data = svm->vmcb->save.dbgctl;
3577                 break;
3578         case MSR_IA32_LASTBRANCHFROMIP:
3579                 msr_info->data = svm->vmcb->save.br_from;
3580                 break;
3581         case MSR_IA32_LASTBRANCHTOIP:
3582                 msr_info->data = svm->vmcb->save.br_to;
3583                 break;
3584         case MSR_IA32_LASTINTFROMIP:
3585                 msr_info->data = svm->vmcb->save.last_excp_from;
3586                 break;
3587         case MSR_IA32_LASTINTTOIP:
3588                 msr_info->data = svm->vmcb->save.last_excp_to;
3589                 break;
3590         case MSR_VM_HSAVE_PA:
3591                 msr_info->data = svm->nested.hsave_msr;
3592                 break;
3593         case MSR_VM_CR:
3594                 msr_info->data = svm->nested.vm_cr_msr;
3595                 break;
3596         case MSR_IA32_UCODE_REV:
3597                 msr_info->data = 0x01000065;
3598                 break;
3599         case MSR_F15H_IC_CFG: {
3600
3601                 int family, model;
3602
3603                 family = guest_cpuid_family(vcpu);
3604                 model  = guest_cpuid_model(vcpu);
3605
3606                 if (family < 0 || model < 0)
3607                         return kvm_get_msr_common(vcpu, msr_info);
3608
3609                 msr_info->data = 0;
3610
3611                 if (family == 0x15 &&
3612                     (model >= 0x2 && model < 0x20))
3613                         msr_info->data = 0x1E;
3614                 }
3615                 break;
3616         default:
3617                 return kvm_get_msr_common(vcpu, msr_info);
3618         }
3619         return 0;
3620 }
3621
3622 static int rdmsr_interception(struct vcpu_svm *svm)
3623 {
3624         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3625         struct msr_data msr_info;
3626
3627         msr_info.index = ecx;
3628         msr_info.host_initiated = false;
3629         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3630                 trace_kvm_msr_read_ex(ecx);
3631                 kvm_inject_gp(&svm->vcpu, 0);
3632                 return 1;
3633         } else {
3634                 trace_kvm_msr_read(ecx, msr_info.data);
3635
3636                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3637                                    msr_info.data & 0xffffffff);
3638                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3639                                    msr_info.data >> 32);
3640                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3641                 return kvm_skip_emulated_instruction(&svm->vcpu);
3642         }
3643 }
3644
3645 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3646 {
3647         struct vcpu_svm *svm = to_svm(vcpu);
3648         int svm_dis, chg_mask;
3649
3650         if (data & ~SVM_VM_CR_VALID_MASK)
3651                 return 1;
3652
3653         chg_mask = SVM_VM_CR_VALID_MASK;
3654
3655         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3656                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3657
3658         svm->nested.vm_cr_msr &= ~chg_mask;
3659         svm->nested.vm_cr_msr |= (data & chg_mask);
3660
3661         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3662
3663         /* check for svm_disable while efer.svme is set */
3664         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3665                 return 1;
3666
3667         return 0;
3668 }
3669
3670 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3671 {
3672         struct vcpu_svm *svm = to_svm(vcpu);
3673
3674         u32 ecx = msr->index;
3675         u64 data = msr->data;
3676         switch (ecx) {
3677         case MSR_IA32_CR_PAT:
3678                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3679                         return 1;
3680                 vcpu->arch.pat = data;
3681                 svm->vmcb->save.g_pat = data;
3682                 mark_dirty(svm->vmcb, VMCB_NPT);
3683                 break;
3684         case MSR_IA32_TSC:
3685                 kvm_write_tsc(vcpu, msr);
3686                 break;
3687         case MSR_STAR:
3688                 svm->vmcb->save.star = data;
3689                 break;
3690 #ifdef CONFIG_X86_64
3691         case MSR_LSTAR:
3692                 svm->vmcb->save.lstar = data;
3693                 break;
3694         case MSR_CSTAR:
3695                 svm->vmcb->save.cstar = data;
3696                 break;
3697         case MSR_KERNEL_GS_BASE:
3698                 svm->vmcb->save.kernel_gs_base = data;
3699                 break;
3700         case MSR_SYSCALL_MASK:
3701                 svm->vmcb->save.sfmask = data;
3702                 break;
3703 #endif
3704         case MSR_IA32_SYSENTER_CS:
3705                 svm->vmcb->save.sysenter_cs = data;
3706                 break;
3707         case MSR_IA32_SYSENTER_EIP:
3708                 svm->sysenter_eip = data;
3709                 svm->vmcb->save.sysenter_eip = data;
3710                 break;
3711         case MSR_IA32_SYSENTER_ESP:
3712                 svm->sysenter_esp = data;
3713                 svm->vmcb->save.sysenter_esp = data;
3714                 break;
3715         case MSR_TSC_AUX:
3716                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3717                         return 1;
3718
3719                 /*
3720                  * This is rare, so we update the MSR here instead of using
3721                  * direct_access_msrs.  Doing that would require a rdmsr in
3722                  * svm_vcpu_put.
3723                  */
3724                 svm->tsc_aux = data;
3725                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3726                 break;
3727         case MSR_IA32_DEBUGCTLMSR:
3728                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3729                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3730                                     __func__, data);
3731                         break;
3732                 }
3733                 if (data & DEBUGCTL_RESERVED_BITS)
3734                         return 1;
3735
3736                 svm->vmcb->save.dbgctl = data;
3737                 mark_dirty(svm->vmcb, VMCB_LBR);
3738                 if (data & (1ULL<<0))
3739                         svm_enable_lbrv(svm);
3740                 else
3741                         svm_disable_lbrv(svm);
3742                 break;
3743         case MSR_VM_HSAVE_PA:
3744                 svm->nested.hsave_msr = data;
3745                 break;
3746         case MSR_VM_CR:
3747                 return svm_set_vm_cr(vcpu, data);
3748         case MSR_VM_IGNNE:
3749                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3750                 break;
3751         case MSR_IA32_APICBASE:
3752                 if (kvm_vcpu_apicv_active(vcpu))
3753                         avic_update_vapic_bar(to_svm(vcpu), data);
3754                 /* Follow through */
3755         default:
3756                 return kvm_set_msr_common(vcpu, msr);
3757         }
3758         return 0;
3759 }
3760
3761 static int wrmsr_interception(struct vcpu_svm *svm)
3762 {
3763         struct msr_data msr;
3764         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3765         u64 data = kvm_read_edx_eax(&svm->vcpu);
3766
3767         msr.data = data;
3768         msr.index = ecx;
3769         msr.host_initiated = false;
3770
3771         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3772         if (kvm_set_msr(&svm->vcpu, &msr)) {
3773                 trace_kvm_msr_write_ex(ecx, data);
3774                 kvm_inject_gp(&svm->vcpu, 0);
3775                 return 1;
3776         } else {
3777                 trace_kvm_msr_write(ecx, data);
3778                 return kvm_skip_emulated_instruction(&svm->vcpu);
3779         }
3780 }
3781
3782 static int msr_interception(struct vcpu_svm *svm)
3783 {
3784         if (svm->vmcb->control.exit_info_1)
3785                 return wrmsr_interception(svm);
3786         else
3787                 return rdmsr_interception(svm);
3788 }
3789
3790 static int interrupt_window_interception(struct vcpu_svm *svm)
3791 {
3792         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3793         svm_clear_vintr(svm);
3794         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3795         mark_dirty(svm->vmcb, VMCB_INTR);
3796         ++svm->vcpu.stat.irq_window_exits;
3797         return 1;
3798 }
3799
3800 static int pause_interception(struct vcpu_svm *svm)
3801 {
3802         struct kvm_vcpu *vcpu = &svm->vcpu;
3803         bool in_kernel = (svm_get_cpl(vcpu) == 0);
3804
3805         kvm_vcpu_on_spin(vcpu, in_kernel);
3806         return 1;
3807 }
3808
3809 static int nop_interception(struct vcpu_svm *svm)
3810 {
3811         return kvm_skip_emulated_instruction(&(svm->vcpu));
3812 }
3813
3814 static int monitor_interception(struct vcpu_svm *svm)
3815 {
3816         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3817         return nop_interception(svm);
3818 }
3819
3820 static int mwait_interception(struct vcpu_svm *svm)
3821 {
3822         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3823         return nop_interception(svm);
3824 }
3825
3826 enum avic_ipi_failure_cause {
3827         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3828         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3829         AVIC_IPI_FAILURE_INVALID_TARGET,
3830         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3831 };
3832
3833 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3834 {
3835         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3836         u32 icrl = svm->vmcb->control.exit_info_1;
3837         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3838         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3839         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3840
3841         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3842
3843         switch (id) {
3844         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3845                 /*
3846                  * AVIC hardware handles the generation of
3847                  * IPIs when the specified Message Type is Fixed
3848                  * (also known as fixed delivery mode) and
3849                  * the Trigger Mode is edge-triggered. The hardware
3850                  * also supports self and broadcast delivery modes
3851                  * specified via the Destination Shorthand(DSH)
3852                  * field of the ICRL. Logical and physical APIC ID
3853                  * formats are supported. All other IPI types cause
3854                  * a #VMEXIT, which needs to emulated.
3855                  */
3856                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3857                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3858                 break;
3859         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3860                 int i;
3861                 struct kvm_vcpu *vcpu;
3862                 struct kvm *kvm = svm->vcpu.kvm;
3863                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3864
3865                 /*
3866                  * At this point, we expect that the AVIC HW has already
3867                  * set the appropriate IRR bits on the valid target
3868                  * vcpus. So, we just need to kick the appropriate vcpu.
3869                  */
3870                 kvm_for_each_vcpu(i, vcpu, kvm) {
3871                         bool m = kvm_apic_match_dest(vcpu, apic,
3872                                                      icrl & KVM_APIC_SHORT_MASK,
3873                                                      GET_APIC_DEST_FIELD(icrh),
3874                                                      icrl & KVM_APIC_DEST_MASK);
3875
3876                         if (m && !avic_vcpu_is_running(vcpu))
3877                                 kvm_vcpu_wake_up(vcpu);
3878                 }
3879                 break;
3880         }
3881         case AVIC_IPI_FAILURE_INVALID_TARGET:
3882                 break;
3883         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3884                 WARN_ONCE(1, "Invalid backing page\n");
3885                 break;
3886         default:
3887                 pr_err("Unknown IPI interception\n");
3888         }
3889
3890         return 1;
3891 }
3892
3893 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3894 {
3895         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3896         int index;
3897         u32 *logical_apic_id_table;
3898         int dlid = GET_APIC_LOGICAL_ID(ldr);
3899
3900         if (!dlid)
3901                 return NULL;
3902
3903         if (flat) { /* flat */
3904                 index = ffs(dlid) - 1;
3905                 if (index > 7)
3906                         return NULL;
3907         } else { /* cluster */
3908                 int cluster = (dlid & 0xf0) >> 4;
3909                 int apic = ffs(dlid & 0x0f) - 1;
3910
3911                 if ((apic < 0) || (apic > 7) ||
3912                     (cluster >= 0xf))
3913                         return NULL;
3914                 index = (cluster << 2) + apic;
3915         }
3916
3917         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3918
3919         return &logical_apic_id_table[index];
3920 }
3921
3922 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3923                           bool valid)
3924 {
3925         bool flat;
3926         u32 *entry, new_entry;
3927
3928         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3929         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3930         if (!entry)
3931                 return -EINVAL;
3932
3933         new_entry = READ_ONCE(*entry);
3934         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3935         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3936         if (valid)
3937                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3938         else
3939                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3940         WRITE_ONCE(*entry, new_entry);
3941
3942         return 0;
3943 }
3944
3945 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3946 {
3947         int ret;
3948         struct vcpu_svm *svm = to_svm(vcpu);
3949         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3950
3951         if (!ldr)
3952                 return 1;
3953
3954         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3955         if (ret && svm->ldr_reg) {
3956                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3957                 svm->ldr_reg = 0;
3958         } else {
3959                 svm->ldr_reg = ldr;
3960         }
3961         return ret;
3962 }
3963
3964 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3965 {
3966         u64 *old, *new;
3967         struct vcpu_svm *svm = to_svm(vcpu);
3968         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3969         u32 id = (apic_id_reg >> 24) & 0xff;
3970
3971         if (vcpu->vcpu_id == id)
3972                 return 0;
3973
3974         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3975         new = avic_get_physical_id_entry(vcpu, id);
3976         if (!new || !old)
3977                 return 1;
3978
3979         /* We need to move physical_id_entry to new offset */
3980         *new = *old;
3981         *old = 0ULL;
3982         to_svm(vcpu)->avic_physical_id_cache = new;
3983
3984         /*
3985          * Also update the guest physical APIC ID in the logical
3986          * APIC ID table entry if already setup the LDR.
3987          */
3988         if (svm->ldr_reg)
3989                 avic_handle_ldr_update(vcpu);
3990
3991         return 0;
3992 }
3993
3994 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3995 {
3996         struct vcpu_svm *svm = to_svm(vcpu);
3997         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3998         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3999         u32 mod = (dfr >> 28) & 0xf;
4000
4001         /*
4002          * We assume that all local APICs are using the same type.
4003          * If this changes, we need to flush the AVIC logical
4004          * APID id table.
4005          */
4006         if (vm_data->ldr_mode == mod)
4007                 return 0;
4008
4009         clear_page(page_address(vm_data->avic_logical_id_table_page));
4010         vm_data->ldr_mode = mod;
4011
4012         if (svm->ldr_reg)
4013                 avic_handle_ldr_update(vcpu);
4014         return 0;
4015 }
4016
4017 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4018 {
4019         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4020         u32 offset = svm->vmcb->control.exit_info_1 &
4021                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4022
4023         switch (offset) {
4024         case APIC_ID:
4025                 if (avic_handle_apic_id_update(&svm->vcpu))
4026                         return 0;
4027                 break;
4028         case APIC_LDR:
4029                 if (avic_handle_ldr_update(&svm->vcpu))
4030                         return 0;
4031                 break;
4032         case APIC_DFR:
4033                 avic_handle_dfr_update(&svm->vcpu);
4034                 break;
4035         default:
4036                 break;
4037         }
4038
4039         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4040
4041         return 1;
4042 }
4043
4044 static bool is_avic_unaccelerated_access_trap(u32 offset)
4045 {
4046         bool ret = false;
4047
4048         switch (offset) {
4049         case APIC_ID:
4050         case APIC_EOI:
4051         case APIC_RRR:
4052         case APIC_LDR:
4053         case APIC_DFR:
4054         case APIC_SPIV:
4055         case APIC_ESR:
4056         case APIC_ICR:
4057         case APIC_LVTT:
4058         case APIC_LVTTHMR:
4059         case APIC_LVTPC:
4060         case APIC_LVT0:
4061         case APIC_LVT1:
4062         case APIC_LVTERR:
4063         case APIC_TMICT:
4064         case APIC_TDCR:
4065                 ret = true;
4066                 break;
4067         default:
4068                 break;
4069         }
4070         return ret;
4071 }
4072
4073 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4074 {
4075         int ret = 0;
4076         u32 offset = svm->vmcb->control.exit_info_1 &
4077                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4078         u32 vector = svm->vmcb->control.exit_info_2 &
4079                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4080         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4081                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4082         bool trap = is_avic_unaccelerated_access_trap(offset);
4083
4084         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4085                                             trap, write, vector);
4086         if (trap) {
4087                 /* Handling Trap */
4088                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4089                 ret = avic_unaccel_trap_write(svm);
4090         } else {
4091                 /* Handling Fault */
4092                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4093         }
4094
4095         return ret;
4096 }
4097
4098 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4099         [SVM_EXIT_READ_CR0]                     = cr_interception,
4100         [SVM_EXIT_READ_CR3]                     = cr_interception,
4101         [SVM_EXIT_READ_CR4]                     = cr_interception,
4102         [SVM_EXIT_READ_CR8]                     = cr_interception,
4103         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4104         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4105         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4106         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4107         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4108         [SVM_EXIT_READ_DR0]                     = dr_interception,
4109         [SVM_EXIT_READ_DR1]                     = dr_interception,
4110         [SVM_EXIT_READ_DR2]                     = dr_interception,
4111         [SVM_EXIT_READ_DR3]                     = dr_interception,
4112         [SVM_EXIT_READ_DR4]                     = dr_interception,
4113         [SVM_EXIT_READ_DR5]                     = dr_interception,
4114         [SVM_EXIT_READ_DR6]                     = dr_interception,
4115         [SVM_EXIT_READ_DR7]                     = dr_interception,
4116         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4117         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4118         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4119         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4120         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4121         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4122         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4123         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4124         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4125         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4126         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4127         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4128         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4129         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4130         [SVM_EXIT_INTR]                         = intr_interception,
4131         [SVM_EXIT_NMI]                          = nmi_interception,
4132         [SVM_EXIT_SMI]                          = nop_on_interception,
4133         [SVM_EXIT_INIT]                         = nop_on_interception,
4134         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4135         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4136         [SVM_EXIT_CPUID]                        = cpuid_interception,
4137         [SVM_EXIT_IRET]                         = iret_interception,
4138         [SVM_EXIT_INVD]                         = emulate_on_interception,
4139         [SVM_EXIT_PAUSE]                        = pause_interception,
4140         [SVM_EXIT_HLT]                          = halt_interception,
4141         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4142         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4143         [SVM_EXIT_IOIO]                         = io_interception,
4144         [SVM_EXIT_MSR]                          = msr_interception,
4145         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4146         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4147         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4148         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4149         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4150         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4151         [SVM_EXIT_STGI]                         = stgi_interception,
4152         [SVM_EXIT_CLGI]                         = clgi_interception,
4153         [SVM_EXIT_SKINIT]                       = skinit_interception,
4154         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4155         [SVM_EXIT_MONITOR]                      = monitor_interception,
4156         [SVM_EXIT_MWAIT]                        = mwait_interception,
4157         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4158         [SVM_EXIT_NPF]                          = npf_interception,
4159         [SVM_EXIT_RSM]                          = emulate_on_interception,
4160         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4161         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4162 };
4163
4164 static void dump_vmcb(struct kvm_vcpu *vcpu)
4165 {
4166         struct vcpu_svm *svm = to_svm(vcpu);
4167         struct vmcb_control_area *control = &svm->vmcb->control;
4168         struct vmcb_save_area *save = &svm->vmcb->save;
4169
4170         pr_err("VMCB Control Area:\n");
4171         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4172         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4173         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4174         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4175         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4176         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4177         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4178         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4179         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4180         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4181         pr_err("%-20s%d\n", "asid:", control->asid);
4182         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4183         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4184         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4185         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4186         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4187         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4188         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4189         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4190         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4191         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4192         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4193         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4194         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4195         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4196         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4197         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4198         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4199         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4200         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4201         pr_err("VMCB State Save Area:\n");
4202         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4203                "es:",
4204                save->es.selector, save->es.attrib,
4205                save->es.limit, save->es.base);
4206         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4207                "cs:",
4208                save->cs.selector, save->cs.attrib,
4209                save->cs.limit, save->cs.base);
4210         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4211                "ss:",
4212                save->ss.selector, save->ss.attrib,
4213                save->ss.limit, save->ss.base);
4214         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4215                "ds:",
4216                save->ds.selector, save->ds.attrib,
4217                save->ds.limit, save->ds.base);
4218         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4219                "fs:",
4220                save->fs.selector, save->fs.attrib,
4221                save->fs.limit, save->fs.base);
4222         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4223                "gs:",
4224                save->gs.selector, save->gs.attrib,
4225                save->gs.limit, save->gs.base);
4226         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4227                "gdtr:",
4228                save->gdtr.selector, save->gdtr.attrib,
4229                save->gdtr.limit, save->gdtr.base);
4230         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4231                "ldtr:",
4232                save->ldtr.selector, save->ldtr.attrib,
4233                save->ldtr.limit, save->ldtr.base);
4234         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4235                "idtr:",
4236                save->idtr.selector, save->idtr.attrib,
4237                save->idtr.limit, save->idtr.base);
4238         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4239                "tr:",
4240                save->tr.selector, save->tr.attrib,
4241                save->tr.limit, save->tr.base);
4242         pr_err("cpl:            %d                efer:         %016llx\n",
4243                 save->cpl, save->efer);
4244         pr_err("%-15s %016llx %-13s %016llx\n",
4245                "cr0:", save->cr0, "cr2:", save->cr2);
4246         pr_err("%-15s %016llx %-13s %016llx\n",
4247                "cr3:", save->cr3, "cr4:", save->cr4);
4248         pr_err("%-15s %016llx %-13s %016llx\n",
4249                "dr6:", save->dr6, "dr7:", save->dr7);
4250         pr_err("%-15s %016llx %-13s %016llx\n",
4251                "rip:", save->rip, "rflags:", save->rflags);
4252         pr_err("%-15s %016llx %-13s %016llx\n",
4253                "rsp:", save->rsp, "rax:", save->rax);
4254         pr_err("%-15s %016llx %-13s %016llx\n",
4255                "star:", save->star, "lstar:", save->lstar);
4256         pr_err("%-15s %016llx %-13s %016llx\n",
4257                "cstar:", save->cstar, "sfmask:", save->sfmask);
4258         pr_err("%-15s %016llx %-13s %016llx\n",
4259                "kernel_gs_base:", save->kernel_gs_base,
4260                "sysenter_cs:", save->sysenter_cs);
4261         pr_err("%-15s %016llx %-13s %016llx\n",
4262                "sysenter_esp:", save->sysenter_esp,
4263                "sysenter_eip:", save->sysenter_eip);
4264         pr_err("%-15s %016llx %-13s %016llx\n",
4265                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4266         pr_err("%-15s %016llx %-13s %016llx\n",
4267                "br_from:", save->br_from, "br_to:", save->br_to);
4268         pr_err("%-15s %016llx %-13s %016llx\n",
4269                "excp_from:", save->last_excp_from,
4270                "excp_to:", save->last_excp_to);
4271 }
4272
4273 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4274 {
4275         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4276
4277         *info1 = control->exit_info_1;
4278         *info2 = control->exit_info_2;
4279 }
4280
4281 static int handle_exit(struct kvm_vcpu *vcpu)
4282 {
4283         struct vcpu_svm *svm = to_svm(vcpu);
4284         struct kvm_run *kvm_run = vcpu->run;
4285         u32 exit_code = svm->vmcb->control.exit_code;
4286
4287         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4288
4289         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4290                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4291         if (npt_enabled)
4292                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4293
4294         if (unlikely(svm->nested.exit_required)) {
4295                 nested_svm_vmexit(svm);
4296                 svm->nested.exit_required = false;
4297
4298                 return 1;
4299         }
4300
4301         if (is_guest_mode(vcpu)) {
4302                 int vmexit;
4303
4304                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4305                                         svm->vmcb->control.exit_info_1,
4306                                         svm->vmcb->control.exit_info_2,
4307                                         svm->vmcb->control.exit_int_info,
4308                                         svm->vmcb->control.exit_int_info_err,
4309                                         KVM_ISA_SVM);
4310
4311                 vmexit = nested_svm_exit_special(svm);
4312
4313                 if (vmexit == NESTED_EXIT_CONTINUE)
4314                         vmexit = nested_svm_exit_handled(svm);
4315
4316                 if (vmexit == NESTED_EXIT_DONE)
4317                         return 1;
4318         }
4319
4320         svm_complete_interrupts(svm);
4321
4322         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4323                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4324                 kvm_run->fail_entry.hardware_entry_failure_reason
4325                         = svm->vmcb->control.exit_code;
4326                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4327                 dump_vmcb(vcpu);
4328                 return 0;
4329         }
4330
4331         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4332             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4333             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4334             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4335                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4336                        "exit_code 0x%x\n",
4337                        __func__, svm->vmcb->control.exit_int_info,
4338                        exit_code);
4339
4340         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4341             || !svm_exit_handlers[exit_code]) {
4342                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4343                 kvm_queue_exception(vcpu, UD_VECTOR);
4344                 return 1;
4345         }
4346
4347         return svm_exit_handlers[exit_code](svm);
4348 }
4349
4350 static void reload_tss(struct kvm_vcpu *vcpu)
4351 {
4352         int cpu = raw_smp_processor_id();
4353
4354         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4355         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4356         load_TR_desc();
4357 }
4358
4359 static void pre_svm_run(struct vcpu_svm *svm)
4360 {
4361         int cpu = raw_smp_processor_id();
4362
4363         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4364
4365         /* FIXME: handle wraparound of asid_generation */
4366         if (svm->asid_generation != sd->asid_generation)
4367                 new_asid(svm, sd);
4368 }
4369
4370 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4371 {
4372         struct vcpu_svm *svm = to_svm(vcpu);
4373
4374         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4375         vcpu->arch.hflags |= HF_NMI_MASK;
4376         set_intercept(svm, INTERCEPT_IRET);
4377         ++vcpu->stat.nmi_injections;
4378 }
4379
4380 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4381 {
4382         struct vmcb_control_area *control;
4383
4384         /* The following fields are ignored when AVIC is enabled */
4385         control = &svm->vmcb->control;
4386         control->int_vector = irq;
4387         control->int_ctl &= ~V_INTR_PRIO_MASK;
4388         control->int_ctl |= V_IRQ_MASK |
4389                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4390         mark_dirty(svm->vmcb, VMCB_INTR);
4391 }
4392
4393 static void svm_set_irq(struct kvm_vcpu *vcpu)
4394 {
4395         struct vcpu_svm *svm = to_svm(vcpu);
4396
4397         BUG_ON(!(gif_set(svm)));
4398
4399         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4400         ++vcpu->stat.irq_injections;
4401
4402         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4403                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4404 }
4405
4406 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4407 {
4408         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4409 }
4410
4411 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4412 {
4413         struct vcpu_svm *svm = to_svm(vcpu);
4414
4415         if (svm_nested_virtualize_tpr(vcpu) ||
4416             kvm_vcpu_apicv_active(vcpu))
4417                 return;
4418
4419         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4420
4421         if (irr == -1)
4422                 return;
4423
4424         if (tpr >= irr)
4425                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4426 }
4427
4428 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4429 {
4430         return;
4431 }
4432
4433 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
4434 {
4435         return avic && irqchip_split(vcpu->kvm);
4436 }
4437
4438 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4439 {
4440 }
4441
4442 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4443 {
4444 }
4445
4446 /* Note: Currently only used by Hyper-V. */
4447 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4448 {
4449         struct vcpu_svm *svm = to_svm(vcpu);
4450         struct vmcb *vmcb = svm->vmcb;
4451
4452         if (!kvm_vcpu_apicv_active(&svm->vcpu))
4453                 return;
4454
4455         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4456         mark_dirty(vmcb, VMCB_INTR);
4457 }
4458
4459 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4460 {
4461         return;
4462 }
4463
4464 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4465 {
4466         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4467         smp_mb__after_atomic();
4468
4469         if (avic_vcpu_is_running(vcpu))
4470                 wrmsrl(SVM_AVIC_DOORBELL,
4471                        kvm_cpu_get_apicid(vcpu->cpu));
4472         else
4473                 kvm_vcpu_wake_up(vcpu);
4474 }
4475
4476 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4477 {
4478         unsigned long flags;
4479         struct amd_svm_iommu_ir *cur;
4480
4481         spin_lock_irqsave(&svm->ir_list_lock, flags);
4482         list_for_each_entry(cur, &svm->ir_list, node) {
4483                 if (cur->data != pi->ir_data)
4484                         continue;
4485                 list_del(&cur->node);
4486                 kfree(cur);
4487                 break;
4488         }
4489         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4490 }
4491
4492 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4493 {
4494         int ret = 0;
4495         unsigned long flags;
4496         struct amd_svm_iommu_ir *ir;
4497
4498         /**
4499          * In some cases, the existing irte is updaed and re-set,
4500          * so we need to check here if it's already been * added
4501          * to the ir_list.
4502          */
4503         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4504                 struct kvm *kvm = svm->vcpu.kvm;
4505                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4506                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4507                 struct vcpu_svm *prev_svm;
4508
4509                 if (!prev_vcpu) {
4510                         ret = -EINVAL;
4511                         goto out;
4512                 }
4513
4514                 prev_svm = to_svm(prev_vcpu);
4515                 svm_ir_list_del(prev_svm, pi);
4516         }
4517
4518         /**
4519          * Allocating new amd_iommu_pi_data, which will get
4520          * add to the per-vcpu ir_list.
4521          */
4522         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4523         if (!ir) {
4524                 ret = -ENOMEM;
4525                 goto out;
4526         }
4527         ir->data = pi->ir_data;
4528
4529         spin_lock_irqsave(&svm->ir_list_lock, flags);
4530         list_add(&ir->node, &svm->ir_list);
4531         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4532 out:
4533         return ret;
4534 }
4535
4536 /**
4537  * Note:
4538  * The HW cannot support posting multicast/broadcast
4539  * interrupts to a vCPU. So, we still use legacy interrupt
4540  * remapping for these kind of interrupts.
4541  *
4542  * For lowest-priority interrupts, we only support
4543  * those with single CPU as the destination, e.g. user
4544  * configures the interrupts via /proc/irq or uses
4545  * irqbalance to make the interrupts single-CPU.
4546  */
4547 static int
4548 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4549                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4550 {
4551         struct kvm_lapic_irq irq;
4552         struct kvm_vcpu *vcpu = NULL;
4553
4554         kvm_set_msi_irq(kvm, e, &irq);
4555
4556         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4557                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4558                          __func__, irq.vector);
4559                 return -1;
4560         }
4561
4562         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4563                  irq.vector);
4564         *svm = to_svm(vcpu);
4565         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
4566         vcpu_info->vector = irq.vector;
4567
4568         return 0;
4569 }
4570
4571 /*
4572  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4573  *
4574  * @kvm: kvm
4575  * @host_irq: host irq of the interrupt
4576  * @guest_irq: gsi of the interrupt
4577  * @set: set or unset PI
4578  * returns 0 on success, < 0 on failure
4579  */
4580 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4581                               uint32_t guest_irq, bool set)
4582 {
4583         struct kvm_kernel_irq_routing_entry *e;
4584         struct kvm_irq_routing_table *irq_rt;
4585         int idx, ret = -EINVAL;
4586
4587         if (!kvm_arch_has_assigned_device(kvm) ||
4588             !irq_remapping_cap(IRQ_POSTING_CAP))
4589                 return 0;
4590
4591         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4592                  __func__, host_irq, guest_irq, set);
4593
4594         idx = srcu_read_lock(&kvm->irq_srcu);
4595         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4596         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4597
4598         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4599                 struct vcpu_data vcpu_info;
4600                 struct vcpu_svm *svm = NULL;
4601
4602                 if (e->type != KVM_IRQ_ROUTING_MSI)
4603                         continue;
4604
4605                 /**
4606                  * Here, we setup with legacy mode in the following cases:
4607                  * 1. When cannot target interrupt to a specific vcpu.
4608                  * 2. Unsetting posted interrupt.
4609                  * 3. APIC virtialization is disabled for the vcpu.
4610                  */
4611                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4612                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4613                         struct amd_iommu_pi_data pi;
4614
4615                         /* Try to enable guest_mode in IRTE */
4616                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
4617                                             AVIC_HPA_MASK);
4618                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4619                                                      svm->vcpu.vcpu_id);
4620                         pi.is_guest_mode = true;
4621                         pi.vcpu_data = &vcpu_info;
4622                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4623
4624                         /**
4625                          * Here, we successfully setting up vcpu affinity in
4626                          * IOMMU guest mode. Now, we need to store the posted
4627                          * interrupt information in a per-vcpu ir_list so that
4628                          * we can reference to them directly when we update vcpu
4629                          * scheduling information in IOMMU irte.
4630                          */
4631                         if (!ret && pi.is_guest_mode)
4632                                 svm_ir_list_add(svm, &pi);
4633                 } else {
4634                         /* Use legacy mode in IRTE */
4635                         struct amd_iommu_pi_data pi;
4636
4637                         /**
4638                          * Here, pi is used to:
4639                          * - Tell IOMMU to use legacy mode for this interrupt.
4640                          * - Retrieve ga_tag of prior interrupt remapping data.
4641                          */
4642                         pi.is_guest_mode = false;
4643                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4644
4645                         /**
4646                          * Check if the posted interrupt was previously
4647                          * setup with the guest_mode by checking if the ga_tag
4648                          * was cached. If so, we need to clean up the per-vcpu
4649                          * ir_list.
4650                          */
4651                         if (!ret && pi.prev_ga_tag) {
4652                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4653                                 struct kvm_vcpu *vcpu;
4654
4655                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4656                                 if (vcpu)
4657                                         svm_ir_list_del(to_svm(vcpu), &pi);
4658                         }
4659                 }
4660
4661                 if (!ret && svm) {
4662                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4663                                                  host_irq, e->gsi,
4664                                                  vcpu_info.vector,
4665                                                  vcpu_info.pi_desc_addr, set);
4666                 }
4667
4668                 if (ret < 0) {
4669                         pr_err("%s: failed to update PI IRTE\n", __func__);
4670                         goto out;
4671                 }
4672         }
4673
4674         ret = 0;
4675 out:
4676         srcu_read_unlock(&kvm->irq_srcu, idx);
4677         return ret;
4678 }
4679
4680 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4681 {
4682         struct vcpu_svm *svm = to_svm(vcpu);
4683         struct vmcb *vmcb = svm->vmcb;
4684         int ret;
4685         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4686               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4687         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4688
4689         return ret;
4690 }
4691
4692 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4693 {
4694         struct vcpu_svm *svm = to_svm(vcpu);
4695
4696         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4697 }
4698
4699 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4700 {
4701         struct vcpu_svm *svm = to_svm(vcpu);
4702
4703         if (masked) {
4704                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4705                 set_intercept(svm, INTERCEPT_IRET);
4706         } else {
4707                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4708                 clr_intercept(svm, INTERCEPT_IRET);
4709         }
4710 }
4711
4712 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4713 {
4714         struct vcpu_svm *svm = to_svm(vcpu);
4715         struct vmcb *vmcb = svm->vmcb;
4716         int ret;
4717
4718         if (!gif_set(svm) ||
4719              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4720                 return 0;
4721
4722         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4723
4724         if (is_guest_mode(vcpu))
4725                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4726
4727         return ret;
4728 }
4729
4730 static void enable_irq_window(struct kvm_vcpu *vcpu)
4731 {
4732         struct vcpu_svm *svm = to_svm(vcpu);
4733
4734         if (kvm_vcpu_apicv_active(vcpu))
4735                 return;
4736
4737         /*
4738          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4739          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4740          * get that intercept, this function will be called again though and
4741          * we'll get the vintr intercept. However, if the vGIF feature is
4742          * enabled, the STGI interception will not occur. Enable the irq
4743          * window under the assumption that the hardware will set the GIF.
4744          */
4745         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
4746                 svm_set_vintr(svm);
4747                 svm_inject_irq(svm, 0x0);
4748         }
4749 }
4750
4751 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4752 {
4753         struct vcpu_svm *svm = to_svm(vcpu);
4754
4755         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4756             == HF_NMI_MASK)
4757                 return; /* IRET will cause a vm exit */
4758
4759         if (!gif_set(svm)) {
4760                 if (vgif_enabled(svm))
4761                         set_intercept(svm, INTERCEPT_STGI);
4762                 return; /* STGI will cause a vm exit */
4763         }
4764
4765         if (svm->nested.exit_required)
4766                 return; /* we're not going to run the guest yet */
4767
4768         /*
4769          * Something prevents NMI from been injected. Single step over possible
4770          * problem (IRET or exception injection or interrupt shadow)
4771          */
4772         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
4773         svm->nmi_singlestep = true;
4774         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4775 }
4776
4777 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4778 {
4779         return 0;
4780 }
4781
4782 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4783 {
4784         struct vcpu_svm *svm = to_svm(vcpu);
4785
4786         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4787                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4788         else
4789                 svm->asid_generation--;
4790 }
4791
4792 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4793 {
4794 }
4795
4796 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4797 {
4798         struct vcpu_svm *svm = to_svm(vcpu);
4799
4800         if (svm_nested_virtualize_tpr(vcpu))
4801                 return;
4802
4803         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4804                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4805                 kvm_set_cr8(vcpu, cr8);
4806         }
4807 }
4808
4809 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4810 {
4811         struct vcpu_svm *svm = to_svm(vcpu);
4812         u64 cr8;
4813
4814         if (svm_nested_virtualize_tpr(vcpu) ||
4815             kvm_vcpu_apicv_active(vcpu))
4816                 return;
4817
4818         cr8 = kvm_get_cr8(vcpu);
4819         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4820         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4821 }
4822
4823 static void svm_complete_interrupts(struct vcpu_svm *svm)
4824 {
4825         u8 vector;
4826         int type;
4827         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4828         unsigned int3_injected = svm->int3_injected;
4829
4830         svm->int3_injected = 0;
4831
4832         /*
4833          * If we've made progress since setting HF_IRET_MASK, we've
4834          * executed an IRET and can allow NMI injection.
4835          */
4836         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4837             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4838                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4839                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4840         }
4841
4842         svm->vcpu.arch.nmi_injected = false;
4843         kvm_clear_exception_queue(&svm->vcpu);
4844         kvm_clear_interrupt_queue(&svm->vcpu);
4845
4846         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4847                 return;
4848
4849         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4850
4851         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4852         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4853
4854         switch (type) {
4855         case SVM_EXITINTINFO_TYPE_NMI:
4856                 svm->vcpu.arch.nmi_injected = true;
4857                 break;
4858         case SVM_EXITINTINFO_TYPE_EXEPT:
4859                 /*
4860                  * In case of software exceptions, do not reinject the vector,
4861                  * but re-execute the instruction instead. Rewind RIP first
4862                  * if we emulated INT3 before.
4863                  */
4864                 if (kvm_exception_is_soft(vector)) {
4865                         if (vector == BP_VECTOR && int3_injected &&
4866                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4867                                 kvm_rip_write(&svm->vcpu,
4868                                               kvm_rip_read(&svm->vcpu) -
4869                                               int3_injected);
4870                         break;
4871                 }
4872                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4873                         u32 err = svm->vmcb->control.exit_int_info_err;
4874                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4875
4876                 } else
4877                         kvm_requeue_exception(&svm->vcpu, vector);
4878                 break;
4879         case SVM_EXITINTINFO_TYPE_INTR:
4880                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4881                 break;
4882         default:
4883                 break;
4884         }
4885 }
4886
4887 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4888 {
4889         struct vcpu_svm *svm = to_svm(vcpu);
4890         struct vmcb_control_area *control = &svm->vmcb->control;
4891
4892         control->exit_int_info = control->event_inj;
4893         control->exit_int_info_err = control->event_inj_err;
4894         control->event_inj = 0;
4895         svm_complete_interrupts(svm);
4896 }
4897
4898 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4899 {
4900         struct vcpu_svm *svm = to_svm(vcpu);
4901
4902         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4903         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4904         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4905
4906         /*
4907          * A vmexit emulation is required before the vcpu can be executed
4908          * again.
4909          */
4910         if (unlikely(svm->nested.exit_required))
4911                 return;
4912
4913         /*
4914          * Disable singlestep if we're injecting an interrupt/exception.
4915          * We don't want our modified rflags to be pushed on the stack where
4916          * we might not be able to easily reset them if we disabled NMI
4917          * singlestep later.
4918          */
4919         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4920                 /*
4921                  * Event injection happens before external interrupts cause a
4922                  * vmexit and interrupts are disabled here, so smp_send_reschedule
4923                  * is enough to force an immediate vmexit.
4924                  */
4925                 disable_nmi_singlestep(svm);
4926                 smp_send_reschedule(vcpu->cpu);
4927         }
4928
4929         pre_svm_run(svm);
4930
4931         sync_lapic_to_cr8(vcpu);
4932
4933         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4934
4935         clgi();
4936
4937         local_irq_enable();
4938
4939         asm volatile (
4940                 "push %%" _ASM_BP "; \n\t"
4941                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4942                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4943                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4944                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4945                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4946                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4947 #ifdef CONFIG_X86_64
4948                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4949                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4950                 "mov %c[r10](%[svm]), %%r10 \n\t"
4951                 "mov %c[r11](%[svm]), %%r11 \n\t"
4952                 "mov %c[r12](%[svm]), %%r12 \n\t"
4953                 "mov %c[r13](%[svm]), %%r13 \n\t"
4954                 "mov %c[r14](%[svm]), %%r14 \n\t"
4955                 "mov %c[r15](%[svm]), %%r15 \n\t"
4956 #endif
4957
4958                 /* Enter guest mode */
4959                 "push %%" _ASM_AX " \n\t"
4960                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4961                 __ex(SVM_VMLOAD) "\n\t"
4962                 __ex(SVM_VMRUN) "\n\t"
4963                 __ex(SVM_VMSAVE) "\n\t"
4964                 "pop %%" _ASM_AX " \n\t"
4965
4966                 /* Save guest registers, load host registers */
4967                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4968                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4969                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4970                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4971                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4972                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4973 #ifdef CONFIG_X86_64
4974                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4975                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4976                 "mov %%r10, %c[r10](%[svm]) \n\t"
4977                 "mov %%r11, %c[r11](%[svm]) \n\t"
4978                 "mov %%r12, %c[r12](%[svm]) \n\t"
4979                 "mov %%r13, %c[r13](%[svm]) \n\t"
4980                 "mov %%r14, %c[r14](%[svm]) \n\t"
4981                 "mov %%r15, %c[r15](%[svm]) \n\t"
4982 #endif
4983                 /*
4984                 * Clear host registers marked as clobbered to prevent
4985                 * speculative use.
4986                 */
4987                 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
4988                 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
4989                 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
4990                 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
4991                 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
4992 #ifdef CONFIG_X86_64
4993                 "xor %%r8, %%r8 \n\t"
4994                 "xor %%r9, %%r9 \n\t"
4995                 "xor %%r10, %%r10 \n\t"
4996                 "xor %%r11, %%r11 \n\t"
4997                 "xor %%r12, %%r12 \n\t"
4998                 "xor %%r13, %%r13 \n\t"
4999                 "xor %%r14, %%r14 \n\t"
5000                 "xor %%r15, %%r15 \n\t"
5001 #endif
5002                 "pop %%" _ASM_BP
5003                 :
5004                 : [svm]"a"(svm),
5005                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5006                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5007                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5008                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5009                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5010                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5011                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5012 #ifdef CONFIG_X86_64
5013                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5014                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5015                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5016                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5017                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5018                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5019                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5020                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5021 #endif
5022                 : "cc", "memory"
5023 #ifdef CONFIG_X86_64
5024                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5025                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5026 #else
5027                 , "ebx", "ecx", "edx", "esi", "edi"
5028 #endif
5029                 );
5030
5031         /* Eliminate branch target predictions from guest mode */
5032         vmexit_fill_RSB();
5033
5034 #ifdef CONFIG_X86_64
5035         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5036 #else
5037         loadsegment(fs, svm->host.fs);
5038 #ifndef CONFIG_X86_32_LAZY_GS
5039         loadsegment(gs, svm->host.gs);
5040 #endif
5041 #endif
5042
5043         reload_tss(vcpu);
5044
5045         local_irq_disable();
5046
5047         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5048         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5049         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5050         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5051
5052         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5053                 kvm_before_handle_nmi(&svm->vcpu);
5054
5055         stgi();
5056
5057         /* Any pending NMI will happen here */
5058
5059         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5060                 kvm_after_handle_nmi(&svm->vcpu);
5061
5062         sync_cr8_to_lapic(vcpu);
5063
5064         svm->next_rip = 0;
5065
5066         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5067
5068         /* if exit due to PF check for async PF */
5069         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5070                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5071
5072         if (npt_enabled) {
5073                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5074                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5075         }
5076
5077         /*
5078          * We need to handle MC intercepts here before the vcpu has a chance to
5079          * change the physical cpu
5080          */
5081         if (unlikely(svm->vmcb->control.exit_code ==
5082                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5083                 svm_handle_mce(svm);
5084
5085         mark_all_clean(svm->vmcb);
5086 }
5087 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5088
5089 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5090 {
5091         struct vcpu_svm *svm = to_svm(vcpu);
5092
5093         svm->vmcb->save.cr3 = __sme_set(root);
5094         mark_dirty(svm->vmcb, VMCB_CR);
5095         svm_flush_tlb(vcpu);
5096 }
5097
5098 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5099 {
5100         struct vcpu_svm *svm = to_svm(vcpu);
5101
5102         svm->vmcb->control.nested_cr3 = __sme_set(root);
5103         mark_dirty(svm->vmcb, VMCB_NPT);
5104
5105         /* Also sync guest cr3 here in case we live migrate */
5106         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5107         mark_dirty(svm->vmcb, VMCB_CR);
5108
5109         svm_flush_tlb(vcpu);
5110 }
5111
5112 static int is_disabled(void)
5113 {
5114         u64 vm_cr;
5115
5116         rdmsrl(MSR_VM_CR, vm_cr);
5117         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5118                 return 1;
5119
5120         return 0;
5121 }
5122
5123 static void
5124 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5125 {
5126         /*
5127          * Patch in the VMMCALL instruction:
5128          */
5129         hypercall[0] = 0x0f;
5130         hypercall[1] = 0x01;
5131         hypercall[2] = 0xd9;
5132 }
5133
5134 static void svm_check_processor_compat(void *rtn)
5135 {
5136         *(int *)rtn = 0;
5137 }
5138
5139 static bool svm_cpu_has_accelerated_tpr(void)
5140 {
5141         return false;
5142 }
5143
5144 static bool svm_has_high_real_mode_segbase(void)
5145 {
5146         return true;
5147 }
5148
5149 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5150 {
5151         return 0;
5152 }
5153
5154 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5155 {
5156         struct vcpu_svm *svm = to_svm(vcpu);
5157
5158         /* Update nrips enabled cache */
5159         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5160
5161         if (!kvm_vcpu_apicv_active(vcpu))
5162                 return;
5163
5164         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5165 }
5166
5167 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5168 {
5169         switch (func) {
5170         case 0x1:
5171                 if (avic)
5172                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5173                 break;
5174         case 0x80000001:
5175                 if (nested)
5176                         entry->ecx |= (1 << 2); /* Set SVM bit */
5177                 break;
5178         case 0x8000000A:
5179                 entry->eax = 1; /* SVM revision 1 */
5180                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5181                                    ASID emulation to nested SVM */
5182                 entry->ecx = 0; /* Reserved */
5183                 entry->edx = 0; /* Per default do not support any
5184                                    additional features */
5185
5186                 /* Support next_rip if host supports it */
5187                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5188                         entry->edx |= SVM_FEATURE_NRIP;
5189
5190                 /* Support NPT for the guest if enabled */
5191                 if (npt_enabled)
5192                         entry->edx |= SVM_FEATURE_NPT;
5193
5194                 break;
5195         }
5196 }
5197
5198 static int svm_get_lpage_level(void)
5199 {
5200         return PT_PDPE_LEVEL;
5201 }
5202
5203 static bool svm_rdtscp_supported(void)
5204 {
5205         return boot_cpu_has(X86_FEATURE_RDTSCP);
5206 }
5207
5208 static bool svm_invpcid_supported(void)
5209 {
5210         return false;
5211 }
5212
5213 static bool svm_mpx_supported(void)
5214 {
5215         return false;
5216 }
5217
5218 static bool svm_xsaves_supported(void)
5219 {
5220         return false;
5221 }
5222
5223 static bool svm_has_wbinvd_exit(void)
5224 {
5225         return true;
5226 }
5227
5228 #define PRE_EX(exit)  { .exit_code = (exit), \
5229                         .stage = X86_ICPT_PRE_EXCEPT, }
5230 #define POST_EX(exit) { .exit_code = (exit), \
5231                         .stage = X86_ICPT_POST_EXCEPT, }
5232 #define POST_MEM(exit) { .exit_code = (exit), \
5233                         .stage = X86_ICPT_POST_MEMACCESS, }
5234
5235 static const struct __x86_intercept {
5236         u32 exit_code;
5237         enum x86_intercept_stage stage;
5238 } x86_intercept_map[] = {
5239         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5240         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5241         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5242         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5243         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5244         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5245         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5246         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5247         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5248         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5249         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5250         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5251         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5252         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5253         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5254         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5255         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5256         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5257         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5258         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5259         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5260         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5261         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5262         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5263         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5264         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5265         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5266         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5267         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5268         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5269         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5270         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5271         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5272         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5273         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5274         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5275         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5276         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5277         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5278         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5279         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5280         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5281         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5282         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5283         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5284         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5285 };
5286
5287 #undef PRE_EX
5288 #undef POST_EX
5289 #undef POST_MEM
5290
5291 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5292                                struct x86_instruction_info *info,
5293                                enum x86_intercept_stage stage)
5294 {
5295         struct vcpu_svm *svm = to_svm(vcpu);
5296         int vmexit, ret = X86EMUL_CONTINUE;
5297         struct __x86_intercept icpt_info;
5298         struct vmcb *vmcb = svm->vmcb;
5299
5300         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5301                 goto out;
5302
5303         icpt_info = x86_intercept_map[info->intercept];
5304
5305         if (stage != icpt_info.stage)
5306                 goto out;
5307
5308         switch (icpt_info.exit_code) {
5309         case SVM_EXIT_READ_CR0:
5310                 if (info->intercept == x86_intercept_cr_read)
5311                         icpt_info.exit_code += info->modrm_reg;
5312                 break;
5313         case SVM_EXIT_WRITE_CR0: {
5314                 unsigned long cr0, val;
5315                 u64 intercept;
5316
5317                 if (info->intercept == x86_intercept_cr_write)
5318                         icpt_info.exit_code += info->modrm_reg;
5319
5320                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5321                     info->intercept == x86_intercept_clts)
5322                         break;
5323
5324                 intercept = svm->nested.intercept;
5325
5326                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5327                         break;
5328
5329                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5330                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5331
5332                 if (info->intercept == x86_intercept_lmsw) {
5333                         cr0 &= 0xfUL;
5334                         val &= 0xfUL;
5335                         /* lmsw can't clear PE - catch this here */
5336                         if (cr0 & X86_CR0_PE)
5337                                 val |= X86_CR0_PE;
5338                 }
5339
5340                 if (cr0 ^ val)
5341                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5342
5343                 break;
5344         }
5345         case SVM_EXIT_READ_DR0:
5346         case SVM_EXIT_WRITE_DR0:
5347                 icpt_info.exit_code += info->modrm_reg;
5348                 break;
5349         case SVM_EXIT_MSR:
5350                 if (info->intercept == x86_intercept_wrmsr)
5351                         vmcb->control.exit_info_1 = 1;
5352                 else
5353                         vmcb->control.exit_info_1 = 0;
5354                 break;
5355         case SVM_EXIT_PAUSE:
5356                 /*
5357                  * We get this for NOP only, but pause
5358                  * is rep not, check this here
5359                  */
5360                 if (info->rep_prefix != REPE_PREFIX)
5361                         goto out;
5362                 break;
5363         case SVM_EXIT_IOIO: {
5364                 u64 exit_info;
5365                 u32 bytes;
5366
5367                 if (info->intercept == x86_intercept_in ||
5368                     info->intercept == x86_intercept_ins) {
5369                         exit_info = ((info->src_val & 0xffff) << 16) |
5370                                 SVM_IOIO_TYPE_MASK;
5371                         bytes = info->dst_bytes;
5372                 } else {
5373                         exit_info = (info->dst_val & 0xffff) << 16;
5374                         bytes = info->src_bytes;
5375                 }
5376
5377                 if (info->intercept == x86_intercept_outs ||
5378                     info->intercept == x86_intercept_ins)
5379                         exit_info |= SVM_IOIO_STR_MASK;
5380
5381                 if (info->rep_prefix)
5382                         exit_info |= SVM_IOIO_REP_MASK;
5383
5384                 bytes = min(bytes, 4u);
5385
5386                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5387
5388                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5389
5390                 vmcb->control.exit_info_1 = exit_info;
5391                 vmcb->control.exit_info_2 = info->next_rip;
5392
5393                 break;
5394         }
5395         default:
5396                 break;
5397         }
5398
5399         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5400         if (static_cpu_has(X86_FEATURE_NRIPS))
5401                 vmcb->control.next_rip  = info->next_rip;
5402         vmcb->control.exit_code = icpt_info.exit_code;
5403         vmexit = nested_svm_exit_handled(svm);
5404
5405         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5406                                            : X86EMUL_CONTINUE;
5407
5408 out:
5409         return ret;
5410 }
5411
5412 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5413 {
5414         local_irq_enable();
5415         /*
5416          * We must have an instruction with interrupts enabled, so
5417          * the timer interrupt isn't delayed by the interrupt shadow.
5418          */
5419         asm("nop");
5420         local_irq_disable();
5421 }
5422
5423 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5424 {
5425 }
5426
5427 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5428 {
5429         if (avic_handle_apic_id_update(vcpu) != 0)
5430                 return;
5431         if (avic_handle_dfr_update(vcpu) != 0)
5432                 return;
5433         avic_handle_ldr_update(vcpu);
5434 }
5435
5436 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5437 {
5438         /* [63:9] are reserved. */
5439         vcpu->arch.mcg_cap &= 0x1ff;
5440 }
5441
5442 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
5443 {
5444         struct vcpu_svm *svm = to_svm(vcpu);
5445
5446         /* Per APM Vol.2 15.22.2 "Response to SMI" */
5447         if (!gif_set(svm))
5448                 return 0;
5449
5450         if (is_guest_mode(&svm->vcpu) &&
5451             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
5452                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
5453                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
5454                 svm->nested.exit_required = true;
5455                 return 0;
5456         }
5457
5458         return 1;
5459 }
5460
5461 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
5462 {
5463         struct vcpu_svm *svm = to_svm(vcpu);
5464         int ret;
5465
5466         if (is_guest_mode(vcpu)) {
5467                 /* FED8h - SVM Guest */
5468                 put_smstate(u64, smstate, 0x7ed8, 1);
5469                 /* FEE0h - SVM Guest VMCB Physical Address */
5470                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
5471
5472                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5473                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5474                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5475
5476                 ret = nested_svm_vmexit(svm);
5477                 if (ret)
5478                         return ret;
5479         }
5480         return 0;
5481 }
5482
5483 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
5484 {
5485         struct vcpu_svm *svm = to_svm(vcpu);
5486         struct vmcb *nested_vmcb;
5487         struct page *page;
5488         struct {
5489                 u64 guest;
5490                 u64 vmcb;
5491         } svm_state_save;
5492         int ret;
5493
5494         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
5495                                   sizeof(svm_state_save));
5496         if (ret)
5497                 return ret;
5498
5499         if (svm_state_save.guest) {
5500                 vcpu->arch.hflags &= ~HF_SMM_MASK;
5501                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
5502                 if (nested_vmcb)
5503                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
5504                 else
5505                         ret = 1;
5506                 vcpu->arch.hflags |= HF_SMM_MASK;
5507         }
5508         return ret;
5509 }
5510
5511 static int enable_smi_window(struct kvm_vcpu *vcpu)
5512 {
5513         struct vcpu_svm *svm = to_svm(vcpu);
5514
5515         if (!gif_set(svm)) {
5516                 if (vgif_enabled(svm))
5517                         set_intercept(svm, INTERCEPT_STGI);
5518                 /* STGI will cause a vm exit */
5519                 return 1;
5520         }
5521         return 0;
5522 }
5523
5524 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5525         .cpu_has_kvm_support = has_svm,
5526         .disabled_by_bios = is_disabled,
5527         .hardware_setup = svm_hardware_setup,
5528         .hardware_unsetup = svm_hardware_unsetup,
5529         .check_processor_compatibility = svm_check_processor_compat,
5530         .hardware_enable = svm_hardware_enable,
5531         .hardware_disable = svm_hardware_disable,
5532         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5533         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5534
5535         .vcpu_create = svm_create_vcpu,
5536         .vcpu_free = svm_free_vcpu,
5537         .vcpu_reset = svm_vcpu_reset,
5538
5539         .vm_init = avic_vm_init,
5540         .vm_destroy = avic_vm_destroy,
5541
5542         .prepare_guest_switch = svm_prepare_guest_switch,
5543         .vcpu_load = svm_vcpu_load,
5544         .vcpu_put = svm_vcpu_put,
5545         .vcpu_blocking = svm_vcpu_blocking,
5546         .vcpu_unblocking = svm_vcpu_unblocking,
5547
5548         .update_bp_intercept = update_bp_intercept,
5549         .get_msr = svm_get_msr,
5550         .set_msr = svm_set_msr,
5551         .get_segment_base = svm_get_segment_base,
5552         .get_segment = svm_get_segment,
5553         .set_segment = svm_set_segment,
5554         .get_cpl = svm_get_cpl,
5555         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5556         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5557         .decache_cr3 = svm_decache_cr3,
5558         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5559         .set_cr0 = svm_set_cr0,
5560         .set_cr3 = svm_set_cr3,
5561         .set_cr4 = svm_set_cr4,
5562         .set_efer = svm_set_efer,
5563         .get_idt = svm_get_idt,
5564         .set_idt = svm_set_idt,
5565         .get_gdt = svm_get_gdt,
5566         .set_gdt = svm_set_gdt,
5567         .get_dr6 = svm_get_dr6,
5568         .set_dr6 = svm_set_dr6,
5569         .set_dr7 = svm_set_dr7,
5570         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5571         .cache_reg = svm_cache_reg,
5572         .get_rflags = svm_get_rflags,
5573         .set_rflags = svm_set_rflags,
5574
5575         .tlb_flush = svm_flush_tlb,
5576
5577         .run = svm_vcpu_run,
5578         .handle_exit = handle_exit,
5579         .skip_emulated_instruction = skip_emulated_instruction,
5580         .set_interrupt_shadow = svm_set_interrupt_shadow,
5581         .get_interrupt_shadow = svm_get_interrupt_shadow,
5582         .patch_hypercall = svm_patch_hypercall,
5583         .set_irq = svm_set_irq,
5584         .set_nmi = svm_inject_nmi,
5585         .queue_exception = svm_queue_exception,
5586         .cancel_injection = svm_cancel_injection,
5587         .interrupt_allowed = svm_interrupt_allowed,
5588         .nmi_allowed = svm_nmi_allowed,
5589         .get_nmi_mask = svm_get_nmi_mask,
5590         .set_nmi_mask = svm_set_nmi_mask,
5591         .enable_nmi_window = enable_nmi_window,
5592         .enable_irq_window = enable_irq_window,
5593         .update_cr8_intercept = update_cr8_intercept,
5594         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5595         .get_enable_apicv = svm_get_enable_apicv,
5596         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5597         .load_eoi_exitmap = svm_load_eoi_exitmap,
5598         .hwapic_irr_update = svm_hwapic_irr_update,
5599         .hwapic_isr_update = svm_hwapic_isr_update,
5600         .apicv_post_state_restore = avic_post_state_restore,
5601
5602         .set_tss_addr = svm_set_tss_addr,
5603         .get_tdp_level = get_npt_level,
5604         .get_mt_mask = svm_get_mt_mask,
5605
5606         .get_exit_info = svm_get_exit_info,
5607
5608         .get_lpage_level = svm_get_lpage_level,
5609
5610         .cpuid_update = svm_cpuid_update,
5611
5612         .rdtscp_supported = svm_rdtscp_supported,
5613         .invpcid_supported = svm_invpcid_supported,
5614         .mpx_supported = svm_mpx_supported,
5615         .xsaves_supported = svm_xsaves_supported,
5616
5617         .set_supported_cpuid = svm_set_supported_cpuid,
5618
5619         .has_wbinvd_exit = svm_has_wbinvd_exit,
5620
5621         .write_tsc_offset = svm_write_tsc_offset,
5622
5623         .set_tdp_cr3 = set_tdp_cr3,
5624
5625         .check_intercept = svm_check_intercept,
5626         .handle_external_intr = svm_handle_external_intr,
5627
5628         .sched_in = svm_sched_in,
5629
5630         .pmu_ops = &amd_pmu_ops,
5631         .deliver_posted_interrupt = svm_deliver_avic_intr,
5632         .update_pi_irte = svm_update_pi_irte,
5633         .setup_mce = svm_setup_mce,
5634
5635         .smi_allowed = svm_smi_allowed,
5636         .pre_enter_smm = svm_pre_enter_smm,
5637         .pre_leave_smm = svm_pre_leave_smm,
5638         .enable_smi_window = enable_smi_window,
5639 };
5640
5641 static int __init svm_init(void)
5642 {
5643         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5644                         __alignof__(struct vcpu_svm), THIS_MODULE);
5645 }
5646
5647 static void __exit svm_exit(void)
5648 {
5649         kvm_exit();
5650 }
5651
5652 module_init(svm_init)
5653 module_exit(svm_exit)