arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39
  40 #include <asm/apic.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/tlbflush.h>
  43 #include <asm/desc.h>
  44 #include <asm/debugreg.h>
  45 #include <asm/kvm_para.h>
  46 #include <asm/irq_remapping.h>
  47
  48 #include <asm/virtext.h>
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id svm_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  61
  62 #define IOPM_ALLOC_ORDER 2
  63 #define MSRPM_ALLOC_ORDER 1
  64
  65 #define SEG_TYPE_LDT 2
  66 #define SEG_TYPE_BUSY_TSS16 3
  67
  68 #define SVM_FEATURE_NPT            (1 <<  0)
  69 #define SVM_FEATURE_LBRV           (1 <<  1)
  70 #define SVM_FEATURE_SVML           (1 <<  2)
  71 #define SVM_FEATURE_NRIP           (1 <<  3)
  72 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  73 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  74 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  75 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  76 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  77
  78 #define SVM_AVIC_DOORBELL       0xc001011b
  79
  80 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  81 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  82 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  83
  84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  85
  86 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  87 #define TSC_RATIO_MIN           0x0000000000000001ULL
  88 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  89
  90 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  91
  92 /*
  93  * 0xff is broadcast, so the max index allowed for physical APIC ID
  94  * table is 0xfe.  APIC IDs above 0xff are reserved.
  95  */
  96 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  97
  98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
  99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 101
 102 /* AVIC GATAG is encoded using VM and VCPU IDs */
 103 #define AVIC_VCPU_ID_BITS               8
 104 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 105
 106 #define AVIC_VM_ID_BITS                 24
 107 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 108 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 109
 110 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 111                                                 (y & AVIC_VCPU_ID_MASK))
 112 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 113 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 114
 115 static bool erratum_383_found __read_mostly;
 116
 117 static const u32 host_save_user_msrs[] = {
 118 #ifdef CONFIG_X86_64
 119         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 120         MSR_FS_BASE,
 121 #endif
 122         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 123         MSR_TSC_AUX,
 124 };
 125
 126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 127
 128 struct kvm_vcpu;
 129
 130 struct nested_state {
 131         struct vmcb *hsave;
 132         u64 hsave_msr;
 133         u64 vm_cr_msr;
 134         u64 vmcb;
 135
 136         /* These are the merged vectors */
 137         u32 *msrpm;
 138
 139         /* gpa pointers to the real vectors */
 140         u64 vmcb_msrpm;
 141         u64 vmcb_iopm;
 142
 143         /* A VMEXIT is required but not yet emulated */
 144         bool exit_required;
 145
 146         /* cache for intercepts of the guest */
 147         u32 intercept_cr;
 148         u32 intercept_dr;
 149         u32 intercept_exceptions;
 150         u64 intercept;
 151
 152         /* Nested Paging related state */
 153         u64 nested_cr3;
 154 };
 155
 156 #define MSRPM_OFFSETS   16
 157 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 158
 159 /*
 160  * Set osvw_len to higher value when updated Revision Guides
 161  * are published and we know what the new status bits are
 162  */
 163 static uint64_t osvw_len = 4, osvw_status;
 164
 165 struct vcpu_svm {
 166         struct kvm_vcpu vcpu;
 167         struct vmcb *vmcb;
 168         unsigned long vmcb_pa;
 169         struct svm_cpu_data *svm_data;
 170         uint64_t asid_generation;
 171         uint64_t sysenter_esp;
 172         uint64_t sysenter_eip;
 173         uint64_t tsc_aux;
 174
 175         u64 next_rip;
 176
 177         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 178         struct {
 179                 u16 fs;
 180                 u16 gs;
 181                 u16 ldt;
 182                 u64 gs_base;
 183         } host;
 184
 185         u32 *msrpm;
 186
 187         ulong nmi_iret_rip;
 188
 189         struct nested_state nested;
 190
 191         bool nmi_singlestep;
 192
 193         unsigned int3_injected;
 194         unsigned long int3_rip;
 195         u32 apf_reason;
 196
 197         /* cached guest cpuid flags for faster access */
 198         bool nrips_enabled      : 1;
 199
 200         u32 ldr_reg;
 201         struct page *avic_backing_page;
 202         u64 *avic_physical_id_cache;
 203         bool avic_is_running;
 204
 205         /*
 206          * Per-vcpu list of struct amd_svm_iommu_ir:
 207          * This is used mainly to store interrupt remapping information used
 208          * when update the vcpu affinity. This avoids the need to scan for
 209          * IRTE and try to match ga_tag in the IOMMU driver.
 210          */
 211         struct list_head ir_list;
 212         spinlock_t ir_list_lock;
 213 };
 214
 215 /*
 216  * This is a wrapper of struct amd_iommu_ir_data.
 217  */
 218 struct amd_svm_iommu_ir {
 219         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 220         void *data;             /* Storing pointer to struct amd_ir_data */
 221 };
 222
 223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 225
 226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 230
 231 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 232 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 233
 234 #define MSR_INVALID                     0xffffffffU
 235
 236 static const struct svm_direct_access_msrs {
 237         u32 index;   /* Index of the MSR */
 238         bool always; /* True if intercept is always on */
 239 } direct_access_msrs[] = {
 240         { .index = MSR_STAR,                            .always = true  },
 241         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 242 #ifdef CONFIG_X86_64
 243         { .index = MSR_GS_BASE,                         .always = true  },
 244         { .index = MSR_FS_BASE,                         .always = true  },
 245         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 246         { .index = MSR_LSTAR,                           .always = true  },
 247         { .index = MSR_CSTAR,                           .always = true  },
 248         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 249 #endif
 250         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 251         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 252         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 253         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 254         { .index = MSR_INVALID,                         .always = false },
 255 };
 256
 257 /* enable NPT for AMD64 and X86 with PAE */
 258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 259 static bool npt_enabled = true;
 260 #else
 261 static bool npt_enabled;
 262 #endif
 263
 264 /* allow nested paging (virtualized MMU) for all guests */
 265 static int npt = true;
 266 module_param(npt, int, S_IRUGO);
 267
 268 /* allow nested virtualization in KVM/SVM */
 269 static int nested = true;
 270 module_param(nested, int, S_IRUGO);
 271
 272 /* enable / disable AVIC */
 273 static int avic;
 274 #ifdef CONFIG_X86_LOCAL_APIC
 275 module_param(avic, int, S_IRUGO);
 276 #endif
 277
 278 /* AVIC VM ID bit masks and lock */
 279 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
 280 static DEFINE_SPINLOCK(avic_vm_id_lock);
 281
 282 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 283 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 284 static void svm_complete_interrupts(struct vcpu_svm *svm);
 285
 286 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 287 static int nested_svm_intercept(struct vcpu_svm *svm);
 288 static int nested_svm_vmexit(struct vcpu_svm *svm);
 289 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 290                                       bool has_error_code, u32 error_code);
 291
 292 enum {
 293         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 294                             pause filter count */
 295         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 296         VMCB_ASID,       /* ASID */
 297         VMCB_INTR,       /* int_ctl, int_vector */
 298         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 299         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 300         VMCB_DR,         /* DR6, DR7 */
 301         VMCB_DT,         /* GDT, IDT */
 302         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 303         VMCB_CR2,        /* CR2 only */
 304         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 305         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 306                           * AVIC PHYSICAL_TABLE pointer,
 307                           * AVIC LOGICAL_TABLE pointer
 308                           */
 309         VMCB_DIRTY_MAX,
 310 };
 311
 312 /* TPR and CR2 are always written before VMRUN */
 313 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 314
 315 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 316
 317 static inline void mark_all_dirty(struct vmcb *vmcb)
 318 {
 319         vmcb->control.clean = 0;
 320 }
 321
 322 static inline void mark_all_clean(struct vmcb *vmcb)
 323 {
 324         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 325                                & ~VMCB_ALWAYS_DIRTY_MASK;
 326 }
 327
 328 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 329 {
 330         vmcb->control.clean &= ~(1 << bit);
 331 }
 332
 333 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 334 {
 335         return container_of(vcpu, struct vcpu_svm, vcpu);
 336 }
 337
 338 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 339 {
 340         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 341         mark_dirty(svm->vmcb, VMCB_AVIC);
 342 }
 343
 344 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 345 {
 346         struct vcpu_svm *svm = to_svm(vcpu);
 347         u64 *entry = svm->avic_physical_id_cache;
 348
 349         if (!entry)
 350                 return false;
 351
 352         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 353 }
 354
 355 static void recalc_intercepts(struct vcpu_svm *svm)
 356 {
 357         struct vmcb_control_area *c, *h;
 358         struct nested_state *g;
 359
 360         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 361
 362         if (!is_guest_mode(&svm->vcpu))
 363                 return;
 364
 365         c = &svm->vmcb->control;
 366         h = &svm->nested.hsave->control;
 367         g = &svm->nested;
 368
 369         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 370         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 371         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 372         c->intercept = h->intercept | g->intercept;
 373 }
 374
 375 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 376 {
 377         if (is_guest_mode(&svm->vcpu))
 378                 return svm->nested.hsave;
 379         else
 380                 return svm->vmcb;
 381 }
 382
 383 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 384 {
 385         struct vmcb *vmcb = get_host_vmcb(svm);
 386
 387         vmcb->control.intercept_cr |= (1U << bit);
 388
 389         recalc_intercepts(svm);
 390 }
 391
 392 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 393 {
 394         struct vmcb *vmcb = get_host_vmcb(svm);
 395
 396         vmcb->control.intercept_cr &= ~(1U << bit);
 397
 398         recalc_intercepts(svm);
 399 }
 400
 401 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 402 {
 403         struct vmcb *vmcb = get_host_vmcb(svm);
 404
 405         return vmcb->control.intercept_cr & (1U << bit);
 406 }
 407
 408 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 409 {
 410         struct vmcb *vmcb = get_host_vmcb(svm);
 411
 412         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 413                 | (1 << INTERCEPT_DR1_READ)
 414                 | (1 << INTERCEPT_DR2_READ)
 415                 | (1 << INTERCEPT_DR3_READ)
 416                 | (1 << INTERCEPT_DR4_READ)
 417                 | (1 << INTERCEPT_DR5_READ)
 418                 | (1 << INTERCEPT_DR6_READ)
 419                 | (1 << INTERCEPT_DR7_READ)
 420                 | (1 << INTERCEPT_DR0_WRITE)
 421                 | (1 << INTERCEPT_DR1_WRITE)
 422                 | (1 << INTERCEPT_DR2_WRITE)
 423                 | (1 << INTERCEPT_DR3_WRITE)
 424                 | (1 << INTERCEPT_DR4_WRITE)
 425                 | (1 << INTERCEPT_DR5_WRITE)
 426                 | (1 << INTERCEPT_DR6_WRITE)
 427                 | (1 << INTERCEPT_DR7_WRITE);
 428
 429         recalc_intercepts(svm);
 430 }
 431
 432 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 433 {
 434         struct vmcb *vmcb = get_host_vmcb(svm);
 435
 436         vmcb->control.intercept_dr = 0;
 437
 438         recalc_intercepts(svm);
 439 }
 440
 441 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 442 {
 443         struct vmcb *vmcb = get_host_vmcb(svm);
 444
 445         vmcb->control.intercept_exceptions |= (1U << bit);
 446
 447         recalc_intercepts(svm);
 448 }
 449
 450 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 451 {
 452         struct vmcb *vmcb = get_host_vmcb(svm);
 453
 454         vmcb->control.intercept_exceptions &= ~(1U << bit);
 455
 456         recalc_intercepts(svm);
 457 }
 458
 459 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 460 {
 461         struct vmcb *vmcb = get_host_vmcb(svm);
 462
 463         vmcb->control.intercept |= (1ULL << bit);
 464
 465         recalc_intercepts(svm);
 466 }
 467
 468 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 469 {
 470         struct vmcb *vmcb = get_host_vmcb(svm);
 471
 472         vmcb->control.intercept &= ~(1ULL << bit);
 473
 474         recalc_intercepts(svm);
 475 }
 476
 477 static inline void enable_gif(struct vcpu_svm *svm)
 478 {
 479         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 480 }
 481
 482 static inline void disable_gif(struct vcpu_svm *svm)
 483 {
 484         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 485 }
 486
 487 static inline bool gif_set(struct vcpu_svm *svm)
 488 {
 489         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 490 }
 491
 492 static unsigned long iopm_base;
 493
 494 struct kvm_ldttss_desc {
 495         u16 limit0;
 496         u16 base0;
 497         unsigned base1:8, type:5, dpl:2, p:1;
 498         unsigned limit1:4, zero0:3, g:1, base2:8;
 499         u32 base3;
 500         u32 zero1;
 501 } __attribute__((packed));
 502
 503 struct svm_cpu_data {
 504         int cpu;
 505
 506         u64 asid_generation;
 507         u32 max_asid;
 508         u32 next_asid;
 509         struct kvm_ldttss_desc *tss_desc;
 510
 511         struct page *save_area;
 512 };
 513
 514 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 515
 516 struct svm_init_data {
 517         int cpu;
 518         int r;
 519 };
 520
 521 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 522
 523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 524 #define MSRS_RANGE_SIZE 2048
 525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 526
 527 static u32 svm_msrpm_offset(u32 msr)
 528 {
 529         u32 offset;
 530         int i;
 531
 532         for (i = 0; i < NUM_MSR_MAPS; i++) {
 533                 if (msr < msrpm_ranges[i] ||
 534                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 535                         continue;
 536
 537                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 538                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 539
 540                 /* Now we have the u8 offset - but need the u32 offset */
 541                 return offset / 4;
 542         }
 543
 544         /* MSR not in any range */
 545         return MSR_INVALID;
 546 }
 547
 548 #define MAX_INST_SIZE 15
 549
 550 static inline void clgi(void)
 551 {
 552         asm volatile (__ex(SVM_CLGI));
 553 }
 554
 555 static inline void stgi(void)
 556 {
 557         asm volatile (__ex(SVM_STGI));
 558 }
 559
 560 static inline void invlpga(unsigned long addr, u32 asid)
 561 {
 562         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 563 }
 564
 565 static int get_npt_level(void)
 566 {
 567 #ifdef CONFIG_X86_64
 568         return PT64_ROOT_LEVEL;
 569 #else
 570         return PT32E_ROOT_LEVEL;
 571 #endif
 572 }
 573
 574 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 575 {
 576         vcpu->arch.efer = efer;
 577         if (!npt_enabled && !(efer & EFER_LMA))
 578                 efer &= ~EFER_LME;
 579
 580         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 581         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 582 }
 583
 584 static int is_external_interrupt(u32 info)
 585 {
 586         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 587         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 588 }
 589
 590 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 591 {
 592         struct vcpu_svm *svm = to_svm(vcpu);
 593         u32 ret = 0;
 594
 595         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 596                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 597         return ret;
 598 }
 599
 600 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         if (mask == 0)
 605                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 606         else
 607                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 608
 609 }
 610
 611 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         if (svm->vmcb->control.next_rip != 0) {
 616                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 617                 svm->next_rip = svm->vmcb->control.next_rip;
 618         }
 619
 620         if (!svm->next_rip) {
 621                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 622                                 EMULATE_DONE)
 623                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 624                 return;
 625         }
 626         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 627                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 628                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 629
 630         kvm_rip_write(vcpu, svm->next_rip);
 631         svm_set_interrupt_shadow(vcpu, 0);
 632 }
 633
 634 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 635                                 bool has_error_code, u32 error_code,
 636                                 bool reinject)
 637 {
 638         struct vcpu_svm *svm = to_svm(vcpu);
 639
 640         /*
 641          * If we are within a nested VM we'd better #VMEXIT and let the guest
 642          * handle the exception
 643          */
 644         if (!reinject &&
 645             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 646                 return;
 647
 648         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 649                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 650
 651                 /*
 652                  * For guest debugging where we have to reinject #BP if some
 653                  * INT3 is guest-owned:
 654                  * Emulate nRIP by moving RIP forward. Will fail if injection
 655                  * raises a fault that is not intercepted. Still better than
 656                  * failing in all cases.
 657                  */
 658                 skip_emulated_instruction(&svm->vcpu);
 659                 rip = kvm_rip_read(&svm->vcpu);
 660                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 661                 svm->int3_injected = rip - old_rip;
 662         }
 663
 664         svm->vmcb->control.event_inj = nr
 665                 | SVM_EVTINJ_VALID
 666                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 667                 | SVM_EVTINJ_TYPE_EXEPT;
 668         svm->vmcb->control.event_inj_err = error_code;
 669 }
 670
 671 static void svm_init_erratum_383(void)
 672 {
 673         u32 low, high;
 674         int err;
 675         u64 val;
 676
 677         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 678                 return;
 679
 680         /* Use _safe variants to not break nested virtualization */
 681         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 682         if (err)
 683                 return;
 684
 685         val |= (1ULL << 47);
 686
 687         low  = lower_32_bits(val);
 688         high = upper_32_bits(val);
 689
 690         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 691
 692         erratum_383_found = true;
 693 }
 694
 695 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 696 {
 697         /*
 698          * Guests should see errata 400 and 415 as fixed (assuming that
 699          * HLT and IO instructions are intercepted).
 700          */
 701         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 702         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 703
 704         /*
 705          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 706          * all osvw.status bits inside that length, including bit 0 (which is
 707          * reserved for erratum 298), are valid. However, if host processor's
 708          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 709          * be conservative here and therefore we tell the guest that erratum 298
 710          * is present (because we really don't know).
 711          */
 712         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 713                 vcpu->arch.osvw.status |= 1;
 714 }
 715
 716 static int has_svm(void)
 717 {
 718         const char *msg;
 719
 720         if (!cpu_has_svm(&msg)) {
 721                 printk(KERN_INFO "has_svm: %s\n", msg);
 722                 return 0;
 723         }
 724
 725         return 1;
 726 }
 727
 728 static void svm_hardware_disable(void)
 729 {
 730         /* Make sure we clean up behind us */
 731         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 732                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 733
 734         cpu_svm_disable();
 735
 736         amd_pmu_disable_virt();
 737 }
 738
 739 static int svm_hardware_enable(void)
 740 {
 741
 742         struct svm_cpu_data *sd;
 743         uint64_t efer;
 744         struct desc_struct *gdt;
 745         int me = raw_smp_processor_id();
 746
 747         rdmsrl(MSR_EFER, efer);
 748         if (efer & EFER_SVME)
 749                 return -EBUSY;
 750
 751         if (!has_svm()) {
 752                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 753                 return -EINVAL;
 754         }
 755         sd = per_cpu(svm_data, me);
 756         if (!sd) {
 757                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 758                 return -EINVAL;
 759         }
 760
 761         sd->asid_generation = 1;
 762         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 763         sd->next_asid = sd->max_asid + 1;
 764
 765         gdt = get_current_gdt_rw();
 766         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 767
 768         wrmsrl(MSR_EFER, efer | EFER_SVME);
 769
 770         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 771
 772         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 773                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 774                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 775         }
 776
 777
 778         /*
 779          * Get OSVW bits.
 780          *
 781          * Note that it is possible to have a system with mixed processor
 782          * revisions and therefore different OSVW bits. If bits are not the same
 783          * on different processors then choose the worst case (i.e. if erratum
 784          * is present on one processor and not on another then assume that the
 785          * erratum is present everywhere).
 786          */
 787         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 788                 uint64_t len, status = 0;
 789                 int err;
 790
 791                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 792                 if (!err)
 793                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 794                                                       &err);
 795
 796                 if (err)
 797                         osvw_status = osvw_len = 0;
 798                 else {
 799                         if (len < osvw_len)
 800                                 osvw_len = len;
 801                         osvw_status |= status;
 802                         osvw_status &= (1ULL << osvw_len) - 1;
 803                 }
 804         } else
 805                 osvw_status = osvw_len = 0;
 806
 807         svm_init_erratum_383();
 808
 809         amd_pmu_enable_virt();
 810
 811         return 0;
 812 }
 813
 814 static void svm_cpu_uninit(int cpu)
 815 {
 816         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 817
 818         if (!sd)
 819                 return;
 820
 821         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 822         __free_page(sd->save_area);
 823         kfree(sd);
 824 }
 825
 826 static int svm_cpu_init(int cpu)
 827 {
 828         struct svm_cpu_data *sd;
 829         int r;
 830
 831         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 832         if (!sd)
 833                 return -ENOMEM;
 834         sd->cpu = cpu;
 835         sd->save_area = alloc_page(GFP_KERNEL);
 836         r = -ENOMEM;
 837         if (!sd->save_area)
 838                 goto err_1;
 839
 840         per_cpu(svm_data, cpu) = sd;
 841
 842         return 0;
 843
 844 err_1:
 845         kfree(sd);
 846         return r;
 847
 848 }
 849
 850 static bool valid_msr_intercept(u32 index)
 851 {
 852         int i;
 853
 854         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 855                 if (direct_access_msrs[i].index == index)
 856                         return true;
 857
 858         return false;
 859 }
 860
 861 static void set_msr_interception(u32 *msrpm, unsigned msr,
 862                                  int read, int write)
 863 {
 864         u8 bit_read, bit_write;
 865         unsigned long tmp;
 866         u32 offset;
 867
 868         /*
 869          * If this warning triggers extend the direct_access_msrs list at the
 870          * beginning of the file
 871          */
 872         WARN_ON(!valid_msr_intercept(msr));
 873
 874         offset    = svm_msrpm_offset(msr);
 875         bit_read  = 2 * (msr & 0x0f);
 876         bit_write = 2 * (msr & 0x0f) + 1;
 877         tmp       = msrpm[offset];
 878
 879         BUG_ON(offset == MSR_INVALID);
 880
 881         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 882         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 883
 884         msrpm[offset] = tmp;
 885 }
 886
 887 static void svm_vcpu_init_msrpm(u32 *msrpm)
 888 {
 889         int i;
 890
 891         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 892
 893         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 894                 if (!direct_access_msrs[i].always)
 895                         continue;
 896
 897                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 898         }
 899 }
 900
 901 static void add_msr_offset(u32 offset)
 902 {
 903         int i;
 904
 905         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 906
 907                 /* Offset already in list? */
 908                 if (msrpm_offsets[i] == offset)
 909                         return;
 910
 911                 /* Slot used by another offset? */
 912                 if (msrpm_offsets[i] != MSR_INVALID)
 913                         continue;
 914
 915                 /* Add offset to list */
 916                 msrpm_offsets[i] = offset;
 917
 918                 return;
 919         }
 920
 921         /*
 922          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 923          * increase MSRPM_OFFSETS in this case.
 924          */
 925         BUG();
 926 }
 927
 928 static void init_msrpm_offsets(void)
 929 {
 930         int i;
 931
 932         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 933
 934         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 935                 u32 offset;
 936
 937                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 938                 BUG_ON(offset == MSR_INVALID);
 939
 940                 add_msr_offset(offset);
 941         }
 942 }
 943
 944 static void svm_enable_lbrv(struct vcpu_svm *svm)
 945 {
 946         u32 *msrpm = svm->msrpm;
 947
 948         svm->vmcb->control.lbr_ctl = 1;
 949         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 950         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 951         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 952         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 953 }
 954
 955 static void svm_disable_lbrv(struct vcpu_svm *svm)
 956 {
 957         u32 *msrpm = svm->msrpm;
 958
 959         svm->vmcb->control.lbr_ctl = 0;
 960         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 961         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 962         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 963         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 964 }
 965
 966 /* Note:
 967  * This hash table is used to map VM_ID to a struct kvm_arch,
 968  * when handling AMD IOMMU GALOG notification to schedule in
 969  * a particular vCPU.
 970  */
 971 #define SVM_VM_DATA_HASH_BITS   8
 972 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
 973 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
 974
 975 /* Note:
 976  * This function is called from IOMMU driver to notify
 977  * SVM to schedule in a particular vCPU of a particular VM.
 978  */
 979 static int avic_ga_log_notifier(u32 ga_tag)
 980 {
 981         unsigned long flags;
 982         struct kvm_arch *ka = NULL;
 983         struct kvm_vcpu *vcpu = NULL;
 984         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
 985         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
 986
 987         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
 988
 989         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
 990         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
 991                 struct kvm *kvm = container_of(ka, struct kvm, arch);
 992                 struct kvm_arch *vm_data = &kvm->arch;
 993
 994                 if (vm_data->avic_vm_id != vm_id)
 995                         continue;
 996                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
 997                 break;
 998         }
 999         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1000
1001         if (!vcpu)
1002                 return 0;
1003
1004         /* Note:
1005          * At this point, the IOMMU should have already set the pending
1006          * bit in the vAPIC backing page. So, we just need to schedule
1007          * in the vcpu.
1008          */
1009         if (vcpu->mode == OUTSIDE_GUEST_MODE)
1010                 kvm_vcpu_wake_up(vcpu);
1011
1012         return 0;
1013 }
1014
1015 static __init int svm_hardware_setup(void)
1016 {
1017         int cpu;
1018         struct page *iopm_pages;
1019         void *iopm_va;
1020         int r;
1021
1022         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1023
1024         if (!iopm_pages)
1025                 return -ENOMEM;
1026
1027         iopm_va = page_address(iopm_pages);
1028         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1029         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1030
1031         init_msrpm_offsets();
1032
1033         if (boot_cpu_has(X86_FEATURE_NX))
1034                 kvm_enable_efer_bits(EFER_NX);
1035
1036         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1037                 kvm_enable_efer_bits(EFER_FFXSR);
1038
1039         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1040                 kvm_has_tsc_control = true;
1041                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1042                 kvm_tsc_scaling_ratio_frac_bits = 32;
1043         }
1044
1045         if (nested) {
1046                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1047                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1048         }
1049
1050         for_each_possible_cpu(cpu) {
1051                 r = svm_cpu_init(cpu);
1052                 if (r)
1053                         goto err;
1054         }
1055
1056         if (!boot_cpu_has(X86_FEATURE_NPT))
1057                 npt_enabled = false;
1058
1059         if (npt_enabled && !npt) {
1060                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1061                 npt_enabled = false;
1062         }
1063
1064         if (npt_enabled) {
1065                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1066                 kvm_enable_tdp();
1067         } else
1068                 kvm_disable_tdp();
1069
1070         if (avic) {
1071                 if (!npt_enabled ||
1072                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1073                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1074                         avic = false;
1075                 } else {
1076                         pr_info("AVIC enabled\n");
1077
1078                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1079                 }
1080         }
1081
1082         return 0;
1083
1084 err:
1085         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1086         iopm_base = 0;
1087         return r;
1088 }
1089
1090 static __exit void svm_hardware_unsetup(void)
1091 {
1092         int cpu;
1093
1094         for_each_possible_cpu(cpu)
1095                 svm_cpu_uninit(cpu);
1096
1097         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1098         iopm_base = 0;
1099 }
1100
1101 static void init_seg(struct vmcb_seg *seg)
1102 {
1103         seg->selector = 0;
1104         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1105                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1106         seg->limit = 0xffff;
1107         seg->base = 0;
1108 }
1109
1110 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1111 {
1112         seg->selector = 0;
1113         seg->attrib = SVM_SELECTOR_P_MASK | type;
1114         seg->limit = 0xffff;
1115         seg->base = 0;
1116 }
1117
1118 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1119 {
1120         struct vcpu_svm *svm = to_svm(vcpu);
1121         u64 g_tsc_offset = 0;
1122
1123         if (is_guest_mode(vcpu)) {
1124                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1125                                svm->nested.hsave->control.tsc_offset;
1126                 svm->nested.hsave->control.tsc_offset = offset;
1127         } else
1128                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1129                                            svm->vmcb->control.tsc_offset,
1130                                            offset);
1131
1132         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1133
1134         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1135 }
1136
1137 static void avic_init_vmcb(struct vcpu_svm *svm)
1138 {
1139         struct vmcb *vmcb = svm->vmcb;
1140         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1141         phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1142         phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1143         phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1144
1145         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1146         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1147         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1148         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1149         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1150         svm->vcpu.arch.apicv_active = true;
1151 }
1152
1153 static void init_vmcb(struct vcpu_svm *svm)
1154 {
1155         struct vmcb_control_area *control = &svm->vmcb->control;
1156         struct vmcb_save_area *save = &svm->vmcb->save;
1157
1158         svm->vcpu.arch.hflags = 0;
1159
1160         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1161         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1162         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1163         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1164         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1165         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1166         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1167                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1168
1169         set_dr_intercepts(svm);
1170
1171         set_exception_intercept(svm, PF_VECTOR);
1172         set_exception_intercept(svm, UD_VECTOR);
1173         set_exception_intercept(svm, MC_VECTOR);
1174         set_exception_intercept(svm, AC_VECTOR);
1175         set_exception_intercept(svm, DB_VECTOR);
1176
1177         set_intercept(svm, INTERCEPT_INTR);
1178         set_intercept(svm, INTERCEPT_NMI);
1179         set_intercept(svm, INTERCEPT_SMI);
1180         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1181         set_intercept(svm, INTERCEPT_RDPMC);
1182         set_intercept(svm, INTERCEPT_CPUID);
1183         set_intercept(svm, INTERCEPT_INVD);
1184         set_intercept(svm, INTERCEPT_HLT);
1185         set_intercept(svm, INTERCEPT_INVLPG);
1186         set_intercept(svm, INTERCEPT_INVLPGA);
1187         set_intercept(svm, INTERCEPT_IOIO_PROT);
1188         set_intercept(svm, INTERCEPT_MSR_PROT);
1189         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1190         set_intercept(svm, INTERCEPT_SHUTDOWN);
1191         set_intercept(svm, INTERCEPT_VMRUN);
1192         set_intercept(svm, INTERCEPT_VMMCALL);
1193         set_intercept(svm, INTERCEPT_VMLOAD);
1194         set_intercept(svm, INTERCEPT_VMSAVE);
1195         set_intercept(svm, INTERCEPT_STGI);
1196         set_intercept(svm, INTERCEPT_CLGI);
1197         set_intercept(svm, INTERCEPT_SKINIT);
1198         set_intercept(svm, INTERCEPT_WBINVD);
1199         set_intercept(svm, INTERCEPT_XSETBV);
1200
1201         if (!kvm_mwait_in_guest()) {
1202                 set_intercept(svm, INTERCEPT_MONITOR);
1203                 set_intercept(svm, INTERCEPT_MWAIT);
1204         }
1205
1206         control->iopm_base_pa = iopm_base;
1207         control->msrpm_base_pa = __pa(svm->msrpm);
1208         control->int_ctl = V_INTR_MASKING_MASK;
1209
1210         init_seg(&save->es);
1211         init_seg(&save->ss);
1212         init_seg(&save->ds);
1213         init_seg(&save->fs);
1214         init_seg(&save->gs);
1215
1216         save->cs.selector = 0xf000;
1217         save->cs.base = 0xffff0000;
1218         /* Executable/Readable Code Segment */
1219         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1220                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1221         save->cs.limit = 0xffff;
1222
1223         save->gdtr.limit = 0xffff;
1224         save->idtr.limit = 0xffff;
1225
1226         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1227         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1228
1229         svm_set_efer(&svm->vcpu, 0);
1230         save->dr6 = 0xffff0ff0;
1231         kvm_set_rflags(&svm->vcpu, 2);
1232         save->rip = 0x0000fff0;
1233         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1234
1235         /*
1236          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1237          * It also updates the guest-visible cr0 value.
1238          */
1239         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1240         kvm_mmu_reset_context(&svm->vcpu);
1241
1242         save->cr4 = X86_CR4_PAE;
1243         /* rdx = ?? */
1244
1245         if (npt_enabled) {
1246                 /* Setup VMCB for Nested Paging */
1247                 control->nested_ctl = 1;
1248                 clr_intercept(svm, INTERCEPT_INVLPG);
1249                 clr_exception_intercept(svm, PF_VECTOR);
1250                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1251                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1252                 save->g_pat = svm->vcpu.arch.pat;
1253                 save->cr3 = 0;
1254                 save->cr4 = 0;
1255         }
1256         svm->asid_generation = 0;
1257
1258         svm->nested.vmcb = 0;
1259         svm->vcpu.arch.hflags = 0;
1260
1261         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1262                 control->pause_filter_count = 3000;
1263                 set_intercept(svm, INTERCEPT_PAUSE);
1264         }
1265
1266         if (avic)
1267                 avic_init_vmcb(svm);
1268
1269         mark_all_dirty(svm->vmcb);
1270
1271         enable_gif(svm);
1272
1273 }
1274
1275 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1276                                        unsigned int index)
1277 {
1278         u64 *avic_physical_id_table;
1279         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1280
1281         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1282                 return NULL;
1283
1284         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1285
1286         return &avic_physical_id_table[index];
1287 }
1288
1289 /**
1290  * Note:
1291  * AVIC hardware walks the nested page table to check permissions,
1292  * but does not use the SPA address specified in the leaf page
1293  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1294  * field of the VMCB. Therefore, we set up the
1295  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1296  */
1297 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1298 {
1299         struct kvm *kvm = vcpu->kvm;
1300         int ret;
1301
1302         if (kvm->arch.apic_access_page_done)
1303                 return 0;
1304
1305         ret = x86_set_memory_region(kvm,
1306                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1307                                     APIC_DEFAULT_PHYS_BASE,
1308                                     PAGE_SIZE);
1309         if (ret)
1310                 return ret;
1311
1312         kvm->arch.apic_access_page_done = true;
1313         return 0;
1314 }
1315
1316 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1317 {
1318         int ret;
1319         u64 *entry, new_entry;
1320         int id = vcpu->vcpu_id;
1321         struct vcpu_svm *svm = to_svm(vcpu);
1322
1323         ret = avic_init_access_page(vcpu);
1324         if (ret)
1325                 return ret;
1326
1327         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1328                 return -EINVAL;
1329
1330         if (!svm->vcpu.arch.apic->regs)
1331                 return -EINVAL;
1332
1333         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1334
1335         /* Setting AVIC backing page address in the phy APIC ID table */
1336         entry = avic_get_physical_id_entry(vcpu, id);
1337         if (!entry)
1338                 return -EINVAL;
1339
1340         new_entry = READ_ONCE(*entry);
1341         new_entry = (page_to_phys(svm->avic_backing_page) &
1342                      AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1343                      AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1344         WRITE_ONCE(*entry, new_entry);
1345
1346         svm->avic_physical_id_cache = entry;
1347
1348         return 0;
1349 }
1350
1351 static inline int avic_get_next_vm_id(void)
1352 {
1353         int id;
1354
1355         spin_lock(&avic_vm_id_lock);
1356
1357         /* AVIC VM ID is one-based. */
1358         id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1359         if (id <= AVIC_VM_ID_MASK)
1360                 __set_bit(id, avic_vm_id_bitmap);
1361         else
1362                 id = -EAGAIN;
1363
1364         spin_unlock(&avic_vm_id_lock);
1365         return id;
1366 }
1367
1368 static inline int avic_free_vm_id(int id)
1369 {
1370         if (id <= 0 || id > AVIC_VM_ID_MASK)
1371                 return -EINVAL;
1372
1373         spin_lock(&avic_vm_id_lock);
1374         __clear_bit(id, avic_vm_id_bitmap);
1375         spin_unlock(&avic_vm_id_lock);
1376         return 0;
1377 }
1378
1379 static void avic_vm_destroy(struct kvm *kvm)
1380 {
1381         unsigned long flags;
1382         struct kvm_arch *vm_data = &kvm->arch;
1383
1384         if (!avic)
1385                 return;
1386
1387         avic_free_vm_id(vm_data->avic_vm_id);
1388
1389         if (vm_data->avic_logical_id_table_page)
1390                 __free_page(vm_data->avic_logical_id_table_page);
1391         if (vm_data->avic_physical_id_table_page)
1392                 __free_page(vm_data->avic_physical_id_table_page);
1393
1394         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1395         hash_del(&vm_data->hnode);
1396         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1397 }
1398
1399 static int avic_vm_init(struct kvm *kvm)
1400 {
1401         unsigned long flags;
1402         int vm_id, err = -ENOMEM;
1403         struct kvm_arch *vm_data = &kvm->arch;
1404         struct page *p_page;
1405         struct page *l_page;
1406
1407         if (!avic)
1408                 return 0;
1409
1410         vm_id = avic_get_next_vm_id();
1411         if (vm_id < 0)
1412                 return vm_id;
1413         vm_data->avic_vm_id = (u32)vm_id;
1414
1415         /* Allocating physical APIC ID table (4KB) */
1416         p_page = alloc_page(GFP_KERNEL);
1417         if (!p_page)
1418                 goto free_avic;
1419
1420         vm_data->avic_physical_id_table_page = p_page;
1421         clear_page(page_address(p_page));
1422
1423         /* Allocating logical APIC ID table (4KB) */
1424         l_page = alloc_page(GFP_KERNEL);
1425         if (!l_page)
1426                 goto free_avic;
1427
1428         vm_data->avic_logical_id_table_page = l_page;
1429         clear_page(page_address(l_page));
1430
1431         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1432         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1433         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1434
1435         return 0;
1436
1437 free_avic:
1438         avic_vm_destroy(kvm);
1439         return err;
1440 }
1441
1442 static inline int
1443 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1444 {
1445         int ret = 0;
1446         unsigned long flags;
1447         struct amd_svm_iommu_ir *ir;
1448         struct vcpu_svm *svm = to_svm(vcpu);
1449
1450         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1451                 return 0;
1452
1453         /*
1454          * Here, we go through the per-vcpu ir_list to update all existing
1455          * interrupt remapping table entry targeting this vcpu.
1456          */
1457         spin_lock_irqsave(&svm->ir_list_lock, flags);
1458
1459         if (list_empty(&svm->ir_list))
1460                 goto out;
1461
1462         list_for_each_entry(ir, &svm->ir_list, node) {
1463                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1464                 if (ret)
1465                         break;
1466         }
1467 out:
1468         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1469         return ret;
1470 }
1471
1472 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1473 {
1474         u64 entry;
1475         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1476         int h_physical_id = kvm_cpu_get_apicid(cpu);
1477         struct vcpu_svm *svm = to_svm(vcpu);
1478
1479         if (!kvm_vcpu_apicv_active(vcpu))
1480                 return;
1481
1482         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1483                 return;
1484
1485         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1486         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1487
1488         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1489         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1490
1491         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1492         if (svm->avic_is_running)
1493                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1494
1495         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1496         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1497                                         svm->avic_is_running);
1498 }
1499
1500 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1501 {
1502         u64 entry;
1503         struct vcpu_svm *svm = to_svm(vcpu);
1504
1505         if (!kvm_vcpu_apicv_active(vcpu))
1506                 return;
1507
1508         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1509         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1510                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1511
1512         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1513         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1514 }
1515
1516 /**
1517  * This function is called during VCPU halt/unhalt.
1518  */
1519 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1520 {
1521         struct vcpu_svm *svm = to_svm(vcpu);
1522
1523         svm->avic_is_running = is_run;
1524         if (is_run)
1525                 avic_vcpu_load(vcpu, vcpu->cpu);
1526         else
1527                 avic_vcpu_put(vcpu);
1528 }
1529
1530 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1531 {
1532         struct vcpu_svm *svm = to_svm(vcpu);
1533         u32 dummy;
1534         u32 eax = 1;
1535
1536         if (!init_event) {
1537                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1538                                            MSR_IA32_APICBASE_ENABLE;
1539                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1540                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1541         }
1542         init_vmcb(svm);
1543
1544         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1545         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1546
1547         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1548                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1549 }
1550
1551 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1552 {
1553         struct vcpu_svm *svm;
1554         struct page *page;
1555         struct page *msrpm_pages;
1556         struct page *hsave_page;
1557         struct page *nested_msrpm_pages;
1558         int err;
1559
1560         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1561         if (!svm) {
1562                 err = -ENOMEM;
1563                 goto out;
1564         }
1565
1566         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1567         if (err)
1568                 goto free_svm;
1569
1570         err = -ENOMEM;
1571         page = alloc_page(GFP_KERNEL);
1572         if (!page)
1573                 goto uninit;
1574
1575         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1576         if (!msrpm_pages)
1577                 goto free_page1;
1578
1579         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1580         if (!nested_msrpm_pages)
1581                 goto free_page2;
1582
1583         hsave_page = alloc_page(GFP_KERNEL);
1584         if (!hsave_page)
1585                 goto free_page3;
1586
1587         if (avic) {
1588                 err = avic_init_backing_page(&svm->vcpu);
1589                 if (err)
1590                         goto free_page4;
1591
1592                 INIT_LIST_HEAD(&svm->ir_list);
1593                 spin_lock_init(&svm->ir_list_lock);
1594         }
1595
1596         /* We initialize this flag to true to make sure that the is_running
1597          * bit would be set the first time the vcpu is loaded.
1598          */
1599         svm->avic_is_running = true;
1600
1601         svm->nested.hsave = page_address(hsave_page);
1602
1603         svm->msrpm = page_address(msrpm_pages);
1604         svm_vcpu_init_msrpm(svm->msrpm);
1605
1606         svm->nested.msrpm = page_address(nested_msrpm_pages);
1607         svm_vcpu_init_msrpm(svm->nested.msrpm);
1608
1609         svm->vmcb = page_address(page);
1610         clear_page(svm->vmcb);
1611         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1612         svm->asid_generation = 0;
1613         init_vmcb(svm);
1614
1615         svm_init_osvw(&svm->vcpu);
1616
1617         return &svm->vcpu;
1618
1619 free_page4:
1620         __free_page(hsave_page);
1621 free_page3:
1622         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1623 free_page2:
1624         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1625 free_page1:
1626         __free_page(page);
1627 uninit:
1628         kvm_vcpu_uninit(&svm->vcpu);
1629 free_svm:
1630         kmem_cache_free(kvm_vcpu_cache, svm);
1631 out:
1632         return ERR_PTR(err);
1633 }
1634
1635 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1636 {
1637         struct vcpu_svm *svm = to_svm(vcpu);
1638
1639         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1640         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1641         __free_page(virt_to_page(svm->nested.hsave));
1642         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1643         kvm_vcpu_uninit(vcpu);
1644         kmem_cache_free(kvm_vcpu_cache, svm);
1645 }
1646
1647 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1648 {
1649         struct vcpu_svm *svm = to_svm(vcpu);
1650         int i;
1651
1652         if (unlikely(cpu != vcpu->cpu)) {
1653                 svm->asid_generation = 0;
1654                 mark_all_dirty(svm->vmcb);
1655         }
1656
1657 #ifdef CONFIG_X86_64
1658         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1659 #endif
1660         savesegment(fs, svm->host.fs);
1661         savesegment(gs, svm->host.gs);
1662         svm->host.ldt = kvm_read_ldt();
1663
1664         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1665                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1666
1667         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1668                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1669                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1670                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1671                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1672                 }
1673         }
1674         /* This assumes that the kernel never uses MSR_TSC_AUX */
1675         if (static_cpu_has(X86_FEATURE_RDTSCP))
1676                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1677
1678         avic_vcpu_load(vcpu, cpu);
1679 }
1680
1681 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1682 {
1683         struct vcpu_svm *svm = to_svm(vcpu);
1684         int i;
1685
1686         avic_vcpu_put(vcpu);
1687
1688         ++vcpu->stat.host_state_reload;
1689         kvm_load_ldt(svm->host.ldt);
1690 #ifdef CONFIG_X86_64
1691         loadsegment(fs, svm->host.fs);
1692         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1693         load_gs_index(svm->host.gs);
1694 #else
1695 #ifdef CONFIG_X86_32_LAZY_GS
1696         loadsegment(gs, svm->host.gs);
1697 #endif
1698 #endif
1699         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1700                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1701 }
1702
1703 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1704 {
1705         avic_set_running(vcpu, false);
1706 }
1707
1708 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1709 {
1710         avic_set_running(vcpu, true);
1711 }
1712
1713 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1714 {
1715         return to_svm(vcpu)->vmcb->save.rflags;
1716 }
1717
1718 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1719 {
1720        /*
1721         * Any change of EFLAGS.VM is accompanied by a reload of SS
1722         * (caused by either a task switch or an inter-privilege IRET),
1723         * so we do not need to update the CPL here.
1724         */
1725         to_svm(vcpu)->vmcb->save.rflags = rflags;
1726 }
1727
1728 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1729 {
1730         return 0;
1731 }
1732
1733 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1734 {
1735         switch (reg) {
1736         case VCPU_EXREG_PDPTR:
1737                 BUG_ON(!npt_enabled);
1738                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1739                 break;
1740         default:
1741                 BUG();
1742         }
1743 }
1744
1745 static void svm_set_vintr(struct vcpu_svm *svm)
1746 {
1747         set_intercept(svm, INTERCEPT_VINTR);
1748 }
1749
1750 static void svm_clear_vintr(struct vcpu_svm *svm)
1751 {
1752         clr_intercept(svm, INTERCEPT_VINTR);
1753 }
1754
1755 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1756 {
1757         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1758
1759         switch (seg) {
1760         case VCPU_SREG_CS: return &save->cs;
1761         case VCPU_SREG_DS: return &save->ds;
1762         case VCPU_SREG_ES: return &save->es;
1763         case VCPU_SREG_FS: return &save->fs;
1764         case VCPU_SREG_GS: return &save->gs;
1765         case VCPU_SREG_SS: return &save->ss;
1766         case VCPU_SREG_TR: return &save->tr;
1767         case VCPU_SREG_LDTR: return &save->ldtr;
1768         }
1769         BUG();
1770         return NULL;
1771 }
1772
1773 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1774 {
1775         struct vmcb_seg *s = svm_seg(vcpu, seg);
1776
1777         return s->base;
1778 }
1779
1780 static void svm_get_segment(struct kvm_vcpu *vcpu,
1781                             struct kvm_segment *var, int seg)
1782 {
1783         struct vmcb_seg *s = svm_seg(vcpu, seg);
1784
1785         var->base = s->base;
1786         var->limit = s->limit;
1787         var->selector = s->selector;
1788         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1789         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1790         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1791         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1792         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1793         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1794         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1795
1796         /*
1797          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1798          * However, the SVM spec states that the G bit is not observed by the
1799          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1800          * So let's synthesize a legal G bit for all segments, this helps
1801          * running KVM nested. It also helps cross-vendor migration, because
1802          * Intel's vmentry has a check on the 'G' bit.
1803          */
1804         var->g = s->limit > 0xfffff;
1805
1806         /*
1807          * AMD's VMCB does not have an explicit unusable field, so emulate it
1808          * for cross vendor migration purposes by "not present"
1809          */
1810         var->unusable = !var->present || (var->type == 0);
1811
1812         switch (seg) {
1813         case VCPU_SREG_TR:
1814                 /*
1815                  * Work around a bug where the busy flag in the tr selector
1816                  * isn't exposed
1817                  */
1818                 var->type |= 0x2;
1819                 break;
1820         case VCPU_SREG_DS:
1821         case VCPU_SREG_ES:
1822         case VCPU_SREG_FS:
1823         case VCPU_SREG_GS:
1824                 /*
1825                  * The accessed bit must always be set in the segment
1826                  * descriptor cache, although it can be cleared in the
1827                  * descriptor, the cached bit always remains at 1. Since
1828                  * Intel has a check on this, set it here to support
1829                  * cross-vendor migration.
1830                  */
1831                 if (!var->unusable)
1832                         var->type |= 0x1;
1833                 break;
1834         case VCPU_SREG_SS:
1835                 /*
1836                  * On AMD CPUs sometimes the DB bit in the segment
1837                  * descriptor is left as 1, although the whole segment has
1838                  * been made unusable. Clear it here to pass an Intel VMX
1839                  * entry check when cross vendor migrating.
1840                  */
1841                 if (var->unusable)
1842                         var->db = 0;
1843                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1844                 break;
1845         }
1846 }
1847
1848 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1849 {
1850         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1851
1852         return save->cpl;
1853 }
1854
1855 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1856 {
1857         struct vcpu_svm *svm = to_svm(vcpu);
1858
1859         dt->size = svm->vmcb->save.idtr.limit;
1860         dt->address = svm->vmcb->save.idtr.base;
1861 }
1862
1863 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1864 {
1865         struct vcpu_svm *svm = to_svm(vcpu);
1866
1867         svm->vmcb->save.idtr.limit = dt->size;
1868         svm->vmcb->save.idtr.base = dt->address ;
1869         mark_dirty(svm->vmcb, VMCB_DT);
1870 }
1871
1872 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1873 {
1874         struct vcpu_svm *svm = to_svm(vcpu);
1875
1876         dt->size = svm->vmcb->save.gdtr.limit;
1877         dt->address = svm->vmcb->save.gdtr.base;
1878 }
1879
1880 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1881 {
1882         struct vcpu_svm *svm = to_svm(vcpu);
1883
1884         svm->vmcb->save.gdtr.limit = dt->size;
1885         svm->vmcb->save.gdtr.base = dt->address ;
1886         mark_dirty(svm->vmcb, VMCB_DT);
1887 }
1888
1889 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1890 {
1891 }
1892
1893 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1894 {
1895 }
1896
1897 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1898 {
1899 }
1900
1901 static void update_cr0_intercept(struct vcpu_svm *svm)
1902 {
1903         ulong gcr0 = svm->vcpu.arch.cr0;
1904         u64 *hcr0 = &svm->vmcb->save.cr0;
1905
1906         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1907                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1908
1909         mark_dirty(svm->vmcb, VMCB_CR);
1910
1911         if (gcr0 == *hcr0) {
1912                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1913                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1914         } else {
1915                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1916                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1917         }
1918 }
1919
1920 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1921 {
1922         struct vcpu_svm *svm = to_svm(vcpu);
1923
1924 #ifdef CONFIG_X86_64
1925         if (vcpu->arch.efer & EFER_LME) {
1926                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1927                         vcpu->arch.efer |= EFER_LMA;
1928                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1929                 }
1930
1931                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1932                         vcpu->arch.efer &= ~EFER_LMA;
1933                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1934                 }
1935         }
1936 #endif
1937         vcpu->arch.cr0 = cr0;
1938
1939         if (!npt_enabled)
1940                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1941
1942         /*
1943          * re-enable caching here because the QEMU bios
1944          * does not do it - this results in some delay at
1945          * reboot
1946          */
1947         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1948                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1949         svm->vmcb->save.cr0 = cr0;
1950         mark_dirty(svm->vmcb, VMCB_CR);
1951         update_cr0_intercept(svm);
1952 }
1953
1954 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1955 {
1956         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1957         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1958
1959         if (cr4 & X86_CR4_VMXE)
1960                 return 1;
1961
1962         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1963                 svm_flush_tlb(vcpu);
1964
1965         vcpu->arch.cr4 = cr4;
1966         if (!npt_enabled)
1967                 cr4 |= X86_CR4_PAE;
1968         cr4 |= host_cr4_mce;
1969         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1970         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1971         return 0;
1972 }
1973
1974 static void svm_set_segment(struct kvm_vcpu *vcpu,
1975                             struct kvm_segment *var, int seg)
1976 {
1977         struct vcpu_svm *svm = to_svm(vcpu);
1978         struct vmcb_seg *s = svm_seg(vcpu, seg);
1979
1980         s->base = var->base;
1981         s->limit = var->limit;
1982         s->selector = var->selector;
1983         if (var->unusable)
1984                 s->attrib = 0;
1985         else {
1986                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1987                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1988                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1989                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1990                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1991                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1992                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1993                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1994         }
1995
1996         /*
1997          * This is always accurate, except if SYSRET returned to a segment
1998          * with SS.DPL != 3.  Intel does not have this quirk, and always
1999          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2000          * would entail passing the CPL to userspace and back.
2001          */
2002         if (seg == VCPU_SREG_SS)
2003                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2004
2005         mark_dirty(svm->vmcb, VMCB_SEG);
2006 }
2007
2008 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2009 {
2010         struct vcpu_svm *svm = to_svm(vcpu);
2011
2012         clr_exception_intercept(svm, BP_VECTOR);
2013
2014         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2015                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2016                         set_exception_intercept(svm, BP_VECTOR);
2017         } else
2018                 vcpu->guest_debug = 0;
2019 }
2020
2021 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2022 {
2023         if (sd->next_asid > sd->max_asid) {
2024                 ++sd->asid_generation;
2025                 sd->next_asid = 1;
2026                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2027         }
2028
2029         svm->asid_generation = sd->asid_generation;
2030         svm->vmcb->control.asid = sd->next_asid++;
2031
2032         mark_dirty(svm->vmcb, VMCB_ASID);
2033 }
2034
2035 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2036 {
2037         return to_svm(vcpu)->vmcb->save.dr6;
2038 }
2039
2040 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2041 {
2042         struct vcpu_svm *svm = to_svm(vcpu);
2043
2044         svm->vmcb->save.dr6 = value;
2045         mark_dirty(svm->vmcb, VMCB_DR);
2046 }
2047
2048 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2049 {
2050         struct vcpu_svm *svm = to_svm(vcpu);
2051
2052         get_debugreg(vcpu->arch.db[0], 0);
2053         get_debugreg(vcpu->arch.db[1], 1);
2054         get_debugreg(vcpu->arch.db[2], 2);
2055         get_debugreg(vcpu->arch.db[3], 3);
2056         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2057         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2058
2059         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2060         set_dr_intercepts(svm);
2061 }
2062
2063 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2064 {
2065         struct vcpu_svm *svm = to_svm(vcpu);
2066
2067         svm->vmcb->save.dr7 = value;
2068         mark_dirty(svm->vmcb, VMCB_DR);
2069 }
2070
2071 static int pf_interception(struct vcpu_svm *svm)
2072 {
2073         u64 fault_address = svm->vmcb->control.exit_info_2;
2074         u64 error_code;
2075         int r = 1;
2076
2077         switch (svm->apf_reason) {
2078         default:
2079                 error_code = svm->vmcb->control.exit_info_1;
2080
2081                 trace_kvm_page_fault(fault_address, error_code);
2082                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2083                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2084                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2085                         svm->vmcb->control.insn_bytes,
2086                         svm->vmcb->control.insn_len);
2087                 break;
2088         case KVM_PV_REASON_PAGE_NOT_PRESENT:
2089                 svm->apf_reason = 0;
2090                 local_irq_disable();
2091                 kvm_async_pf_task_wait(fault_address);
2092                 local_irq_enable();
2093                 break;
2094         case KVM_PV_REASON_PAGE_READY:
2095                 svm->apf_reason = 0;
2096                 local_irq_disable();
2097                 kvm_async_pf_task_wake(fault_address);
2098                 local_irq_enable();
2099                 break;
2100         }
2101         return r;
2102 }
2103
2104 static int db_interception(struct vcpu_svm *svm)
2105 {
2106         struct kvm_run *kvm_run = svm->vcpu.run;
2107
2108         if (!(svm->vcpu.guest_debug &
2109               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2110                 !svm->nmi_singlestep) {
2111                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2112                 return 1;
2113         }
2114
2115         if (svm->nmi_singlestep) {
2116                 svm->nmi_singlestep = false;
2117                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2118                         svm->vmcb->save.rflags &=
2119                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2120         }
2121
2122         if (svm->vcpu.guest_debug &
2123             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2124                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2125                 kvm_run->debug.arch.pc =
2126                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2127                 kvm_run->debug.arch.exception = DB_VECTOR;
2128                 return 0;
2129         }
2130
2131         return 1;
2132 }
2133
2134 static int bp_interception(struct vcpu_svm *svm)
2135 {
2136         struct kvm_run *kvm_run = svm->vcpu.run;
2137
2138         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2139         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2140         kvm_run->debug.arch.exception = BP_VECTOR;
2141         return 0;
2142 }
2143
2144 static int ud_interception(struct vcpu_svm *svm)
2145 {
2146         int er;
2147
2148         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2149         if (er != EMULATE_DONE)
2150                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2151         return 1;
2152 }
2153
2154 static int ac_interception(struct vcpu_svm *svm)
2155 {
2156         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2157         return 1;
2158 }
2159
2160 static bool is_erratum_383(void)
2161 {
2162         int err, i;
2163         u64 value;
2164
2165         if (!erratum_383_found)
2166                 return false;
2167
2168         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2169         if (err)
2170                 return false;
2171
2172         /* Bit 62 may or may not be set for this mce */
2173         value &= ~(1ULL << 62);
2174
2175         if (value != 0xb600000000010015ULL)
2176                 return false;
2177
2178         /* Clear MCi_STATUS registers */
2179         for (i = 0; i < 6; ++i)
2180                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2181
2182         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2183         if (!err) {
2184                 u32 low, high;
2185
2186                 value &= ~(1ULL << 2);
2187                 low    = lower_32_bits(value);
2188                 high   = upper_32_bits(value);
2189
2190                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2191         }
2192
2193         /* Flush tlb to evict multi-match entries */
2194         __flush_tlb_all();
2195
2196         return true;
2197 }
2198
2199 static void svm_handle_mce(struct vcpu_svm *svm)
2200 {
2201         if (is_erratum_383()) {
2202                 /*
2203                  * Erratum 383 triggered. Guest state is corrupt so kill the
2204                  * guest.
2205                  */
2206                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2207
2208                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2209
2210                 return;
2211         }
2212
2213         /*
2214          * On an #MC intercept the MCE handler is not called automatically in
2215          * the host. So do it by hand here.
2216          */
2217         asm volatile (
2218                 "int $0x12\n");
2219         /* not sure if we ever come back to this point */
2220
2221         return;
2222 }
2223
2224 static int mc_interception(struct vcpu_svm *svm)
2225 {
2226         return 1;
2227 }
2228
2229 static int shutdown_interception(struct vcpu_svm *svm)
2230 {
2231         struct kvm_run *kvm_run = svm->vcpu.run;
2232
2233         /*
2234          * VMCB is undefined after a SHUTDOWN intercept
2235          * so reinitialize it.
2236          */
2237         clear_page(svm->vmcb);
2238         init_vmcb(svm);
2239
2240         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2241         return 0;
2242 }
2243
2244 static int io_interception(struct vcpu_svm *svm)
2245 {
2246         struct kvm_vcpu *vcpu = &svm->vcpu;
2247         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2248         int size, in, string;
2249         unsigned port;
2250
2251         ++svm->vcpu.stat.io_exits;
2252         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2253         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2254         if (string)
2255                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2256
2257         port = io_info >> 16;
2258         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2259         svm->next_rip = svm->vmcb->control.exit_info_2;
2260         skip_emulated_instruction(&svm->vcpu);
2261
2262         return in ? kvm_fast_pio_in(vcpu, size, port)
2263                   : kvm_fast_pio_out(vcpu, size, port);
2264 }
2265
2266 static int nmi_interception(struct vcpu_svm *svm)
2267 {
2268         return 1;
2269 }
2270
2271 static int intr_interception(struct vcpu_svm *svm)
2272 {
2273         ++svm->vcpu.stat.irq_exits;
2274         return 1;
2275 }
2276
2277 static int nop_on_interception(struct vcpu_svm *svm)
2278 {
2279         return 1;
2280 }
2281
2282 static int halt_interception(struct vcpu_svm *svm)
2283 {
2284         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2285         return kvm_emulate_halt(&svm->vcpu);
2286 }
2287
2288 static int vmmcall_interception(struct vcpu_svm *svm)
2289 {
2290         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2291         return kvm_emulate_hypercall(&svm->vcpu);
2292 }
2293
2294 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2295 {
2296         struct vcpu_svm *svm = to_svm(vcpu);
2297
2298         return svm->nested.nested_cr3;
2299 }
2300
2301 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2302 {
2303         struct vcpu_svm *svm = to_svm(vcpu);
2304         u64 cr3 = svm->nested.nested_cr3;
2305         u64 pdpte;
2306         int ret;
2307
2308         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2309                                        offset_in_page(cr3) + index * 8, 8);
2310         if (ret)
2311                 return 0;
2312         return pdpte;
2313 }
2314
2315 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2316                                    unsigned long root)
2317 {
2318         struct vcpu_svm *svm = to_svm(vcpu);
2319
2320         svm->vmcb->control.nested_cr3 = root;
2321         mark_dirty(svm->vmcb, VMCB_NPT);
2322         svm_flush_tlb(vcpu);
2323 }
2324
2325 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2326                                        struct x86_exception *fault)
2327 {
2328         struct vcpu_svm *svm = to_svm(vcpu);
2329
2330         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2331                 /*
2332                  * TODO: track the cause of the nested page fault, and
2333                  * correctly fill in the high bits of exit_info_1.
2334                  */
2335                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2336                 svm->vmcb->control.exit_code_hi = 0;
2337                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2338                 svm->vmcb->control.exit_info_2 = fault->address;
2339         }
2340
2341         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2342         svm->vmcb->control.exit_info_1 |= fault->error_code;
2343
2344         /*
2345          * The present bit is always zero for page structure faults on real
2346          * hardware.
2347          */
2348         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2349                 svm->vmcb->control.exit_info_1 &= ~1;
2350
2351         nested_svm_vmexit(svm);
2352 }
2353
2354 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2355 {
2356         WARN_ON(mmu_is_nested(vcpu));
2357         kvm_init_shadow_mmu(vcpu);
2358         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2359         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2360         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2361         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2362         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2363         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2364         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2365 }
2366
2367 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2368 {
2369         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2370 }
2371
2372 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2373 {
2374         if (!(svm->vcpu.arch.efer & EFER_SVME)
2375             || !is_paging(&svm->vcpu)) {
2376                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2377                 return 1;
2378         }
2379
2380         if (svm->vmcb->save.cpl) {
2381                 kvm_inject_gp(&svm->vcpu, 0);
2382                 return 1;
2383         }
2384
2385        return 0;
2386 }
2387
2388 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2389                                       bool has_error_code, u32 error_code)
2390 {
2391         int vmexit;
2392
2393         if (!is_guest_mode(&svm->vcpu))
2394                 return 0;
2395
2396         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2397         svm->vmcb->control.exit_code_hi = 0;
2398         svm->vmcb->control.exit_info_1 = error_code;
2399         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2400
2401         vmexit = nested_svm_intercept(svm);
2402         if (vmexit == NESTED_EXIT_DONE)
2403                 svm->nested.exit_required = true;
2404
2405         return vmexit;
2406 }
2407
2408 /* This function returns true if it is save to enable the irq window */
2409 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2410 {
2411         if (!is_guest_mode(&svm->vcpu))
2412                 return true;
2413
2414         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2415                 return true;
2416
2417         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2418                 return false;
2419
2420         /*
2421          * if vmexit was already requested (by intercepted exception
2422          * for instance) do not overwrite it with "external interrupt"
2423          * vmexit.
2424          */
2425         if (svm->nested.exit_required)
2426                 return false;
2427
2428         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2429         svm->vmcb->control.exit_info_1 = 0;
2430         svm->vmcb->control.exit_info_2 = 0;
2431
2432         if (svm->nested.intercept & 1ULL) {
2433                 /*
2434                  * The #vmexit can't be emulated here directly because this
2435                  * code path runs with irqs and preemption disabled. A
2436                  * #vmexit emulation might sleep. Only signal request for
2437                  * the #vmexit here.
2438                  */
2439                 svm->nested.exit_required = true;
2440                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2441                 return false;
2442         }
2443
2444         return true;
2445 }
2446
2447 /* This function returns true if it is save to enable the nmi window */
2448 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2449 {
2450         if (!is_guest_mode(&svm->vcpu))
2451                 return true;
2452
2453         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2454                 return true;
2455
2456         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2457         svm->nested.exit_required = true;
2458
2459         return false;
2460 }
2461
2462 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2463 {
2464         struct page *page;
2465
2466         might_sleep();
2467
2468         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2469         if (is_error_page(page))
2470                 goto error;
2471
2472         *_page = page;
2473
2474         return kmap(page);
2475
2476 error:
2477         kvm_inject_gp(&svm->vcpu, 0);
2478
2479         return NULL;
2480 }
2481
2482 static void nested_svm_unmap(struct page *page)
2483 {
2484         kunmap(page);
2485         kvm_release_page_dirty(page);
2486 }
2487
2488 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2489 {
2490         unsigned port, size, iopm_len;
2491         u16 val, mask;
2492         u8 start_bit;
2493         u64 gpa;
2494
2495         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2496                 return NESTED_EXIT_HOST;
2497
2498         port = svm->vmcb->control.exit_info_1 >> 16;
2499         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2500                 SVM_IOIO_SIZE_SHIFT;
2501         gpa  = svm->nested.vmcb_iopm + (port / 8);
2502         start_bit = port % 8;
2503         iopm_len = (start_bit + size > 8) ? 2 : 1;
2504         mask = (0xf >> (4 - size)) << start_bit;
2505         val = 0;
2506
2507         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2508                 return NESTED_EXIT_DONE;
2509
2510         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2511 }
2512
2513 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2514 {
2515         u32 offset, msr, value;
2516         int write, mask;
2517
2518         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2519                 return NESTED_EXIT_HOST;
2520
2521         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2522         offset = svm_msrpm_offset(msr);
2523         write  = svm->vmcb->control.exit_info_1 & 1;
2524         mask   = 1 << ((2 * (msr & 0xf)) + write);
2525
2526         if (offset == MSR_INVALID)
2527                 return NESTED_EXIT_DONE;
2528
2529         /* Offset is in 32 bit units but need in 8 bit units */
2530         offset *= 4;
2531
2532         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2533                 return NESTED_EXIT_DONE;
2534
2535         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2536 }
2537
2538 static int nested_svm_exit_special(struct vcpu_svm *svm)
2539 {
2540         u32 exit_code = svm->vmcb->control.exit_code;
2541
2542         switch (exit_code) {
2543         case SVM_EXIT_INTR:
2544         case SVM_EXIT_NMI:
2545         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2546                 return NESTED_EXIT_HOST;
2547         case SVM_EXIT_NPF:
2548                 /* For now we are always handling NPFs when using them */
2549                 if (npt_enabled)
2550                         return NESTED_EXIT_HOST;
2551                 break;
2552         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2553                 /* When we're shadowing, trap PFs, but not async PF */
2554                 if (!npt_enabled && svm->apf_reason == 0)
2555                         return NESTED_EXIT_HOST;
2556                 break;
2557         default:
2558                 break;
2559         }
2560
2561         return NESTED_EXIT_CONTINUE;
2562 }
2563
2564 /*
2565  * If this function returns true, this #vmexit was already handled
2566  */
2567 static int nested_svm_intercept(struct vcpu_svm *svm)
2568 {
2569         u32 exit_code = svm->vmcb->control.exit_code;
2570         int vmexit = NESTED_EXIT_HOST;
2571
2572         switch (exit_code) {
2573         case SVM_EXIT_MSR:
2574                 vmexit = nested_svm_exit_handled_msr(svm);
2575                 break;
2576         case SVM_EXIT_IOIO:
2577                 vmexit = nested_svm_intercept_ioio(svm);
2578                 break;
2579         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2580                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2581                 if (svm->nested.intercept_cr & bit)
2582                         vmexit = NESTED_EXIT_DONE;
2583                 break;
2584         }
2585         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2586                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2587                 if (svm->nested.intercept_dr & bit)
2588                         vmexit = NESTED_EXIT_DONE;
2589                 break;
2590         }
2591         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2592                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2593                 if (svm->nested.intercept_exceptions & excp_bits)
2594                         vmexit = NESTED_EXIT_DONE;
2595                 /* async page fault always cause vmexit */
2596                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2597                          svm->apf_reason != 0)
2598                         vmexit = NESTED_EXIT_DONE;
2599                 break;
2600         }
2601         case SVM_EXIT_ERR: {
2602                 vmexit = NESTED_EXIT_DONE;
2603                 break;
2604         }
2605         default: {
2606                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2607                 if (svm->nested.intercept & exit_bits)
2608                         vmexit = NESTED_EXIT_DONE;
2609         }
2610         }
2611
2612         return vmexit;
2613 }
2614
2615 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2616 {
2617         int vmexit;
2618
2619         vmexit = nested_svm_intercept(svm);
2620
2621         if (vmexit == NESTED_EXIT_DONE)
2622                 nested_svm_vmexit(svm);
2623
2624         return vmexit;
2625 }
2626
2627 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2628 {
2629         struct vmcb_control_area *dst  = &dst_vmcb->control;
2630         struct vmcb_control_area *from = &from_vmcb->control;
2631
2632         dst->intercept_cr         = from->intercept_cr;
2633         dst->intercept_dr         = from->intercept_dr;
2634         dst->intercept_exceptions = from->intercept_exceptions;
2635         dst->intercept            = from->intercept;
2636         dst->iopm_base_pa         = from->iopm_base_pa;
2637         dst->msrpm_base_pa        = from->msrpm_base_pa;
2638         dst->tsc_offset           = from->tsc_offset;
2639         dst->asid                 = from->asid;
2640         dst->tlb_ctl              = from->tlb_ctl;
2641         dst->int_ctl              = from->int_ctl;
2642         dst->int_vector           = from->int_vector;
2643         dst->int_state            = from->int_state;
2644         dst->exit_code            = from->exit_code;
2645         dst->exit_code_hi         = from->exit_code_hi;
2646         dst->exit_info_1          = from->exit_info_1;
2647         dst->exit_info_2          = from->exit_info_2;
2648         dst->exit_int_info        = from->exit_int_info;
2649         dst->exit_int_info_err    = from->exit_int_info_err;
2650         dst->nested_ctl           = from->nested_ctl;
2651         dst->event_inj            = from->event_inj;
2652         dst->event_inj_err        = from->event_inj_err;
2653         dst->nested_cr3           = from->nested_cr3;
2654         dst->lbr_ctl              = from->lbr_ctl;
2655 }
2656
2657 static int nested_svm_vmexit(struct vcpu_svm *svm)
2658 {
2659         struct vmcb *nested_vmcb;
2660         struct vmcb *hsave = svm->nested.hsave;
2661         struct vmcb *vmcb = svm->vmcb;
2662         struct page *page;
2663
2664         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2665                                        vmcb->control.exit_info_1,
2666                                        vmcb->control.exit_info_2,
2667                                        vmcb->control.exit_int_info,
2668                                        vmcb->control.exit_int_info_err,
2669                                        KVM_ISA_SVM);
2670
2671         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2672         if (!nested_vmcb)
2673                 return 1;
2674
2675         /* Exit Guest-Mode */
2676         leave_guest_mode(&svm->vcpu);
2677         svm->nested.vmcb = 0;
2678
2679         /* Give the current vmcb to the guest */
2680         disable_gif(svm);
2681
2682         nested_vmcb->save.es     = vmcb->save.es;
2683         nested_vmcb->save.cs     = vmcb->save.cs;
2684         nested_vmcb->save.ss     = vmcb->save.ss;
2685         nested_vmcb->save.ds     = vmcb->save.ds;
2686         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2687         nested_vmcb->save.idtr   = vmcb->save.idtr;
2688         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2689         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2690         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2691         nested_vmcb->save.cr2    = vmcb->save.cr2;
2692         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2693         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2694         nested_vmcb->save.rip    = vmcb->save.rip;
2695         nested_vmcb->save.rsp    = vmcb->save.rsp;
2696         nested_vmcb->save.rax    = vmcb->save.rax;
2697         nested_vmcb->save.dr7    = vmcb->save.dr7;
2698         nested_vmcb->save.dr6    = vmcb->save.dr6;
2699         nested_vmcb->save.cpl    = vmcb->save.cpl;
2700
2701         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2702         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2703         nested_vmcb->control.int_state         = vmcb->control.int_state;
2704         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2705         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2706         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2707         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2708         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2709         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2710
2711         if (svm->nrips_enabled)
2712                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2713
2714         /*
2715          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2716          * to make sure that we do not lose injected events. So check event_inj
2717          * here and copy it to exit_int_info if it is valid.
2718          * Exit_int_info and event_inj can't be both valid because the case
2719          * below only happens on a VMRUN instruction intercept which has
2720          * no valid exit_int_info set.
2721          */
2722         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2723                 struct vmcb_control_area *nc = &nested_vmcb->control;
2724
2725                 nc->exit_int_info     = vmcb->control.event_inj;
2726                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2727         }
2728
2729         nested_vmcb->control.tlb_ctl           = 0;
2730         nested_vmcb->control.event_inj         = 0;
2731         nested_vmcb->control.event_inj_err     = 0;
2732
2733         /* We always set V_INTR_MASKING and remember the old value in hflags */
2734         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2735                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2736
2737         /* Restore the original control entries */
2738         copy_vmcb_control_area(vmcb, hsave);
2739
2740         kvm_clear_exception_queue(&svm->vcpu);
2741         kvm_clear_interrupt_queue(&svm->vcpu);
2742
2743         svm->nested.nested_cr3 = 0;
2744
2745         /* Restore selected save entries */
2746         svm->vmcb->save.es = hsave->save.es;
2747         svm->vmcb->save.cs = hsave->save.cs;
2748         svm->vmcb->save.ss = hsave->save.ss;
2749         svm->vmcb->save.ds = hsave->save.ds;
2750         svm->vmcb->save.gdtr = hsave->save.gdtr;
2751         svm->vmcb->save.idtr = hsave->save.idtr;
2752         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2753         svm_set_efer(&svm->vcpu, hsave->save.efer);
2754         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2755         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2756         if (npt_enabled) {
2757                 svm->vmcb->save.cr3 = hsave->save.cr3;
2758                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2759         } else {
2760                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2761         }
2762         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2763         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2764         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2765         svm->vmcb->save.dr7 = 0;
2766         svm->vmcb->save.cpl = 0;
2767         svm->vmcb->control.exit_int_info = 0;
2768
2769         mark_all_dirty(svm->vmcb);
2770
2771         nested_svm_unmap(page);
2772
2773         nested_svm_uninit_mmu_context(&svm->vcpu);
2774         kvm_mmu_reset_context(&svm->vcpu);
2775         kvm_mmu_load(&svm->vcpu);
2776
2777         return 0;
2778 }
2779
2780 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2781 {
2782         /*
2783          * This function merges the msr permission bitmaps of kvm and the
2784          * nested vmcb. It is optimized in that it only merges the parts where
2785          * the kvm msr permission bitmap may contain zero bits
2786          */
2787         int i;
2788
2789         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2790                 return true;
2791
2792         for (i = 0; i < MSRPM_OFFSETS; i++) {
2793                 u32 value, p;
2794                 u64 offset;
2795
2796                 if (msrpm_offsets[i] == 0xffffffff)
2797                         break;
2798
2799                 p      = msrpm_offsets[i];
2800                 offset = svm->nested.vmcb_msrpm + (p * 4);
2801
2802                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2803                         return false;
2804
2805                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2806         }
2807
2808         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2809
2810         return true;
2811 }
2812
2813 static bool nested_vmcb_checks(struct vmcb *vmcb)
2814 {
2815         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2816                 return false;
2817
2818         if (vmcb->control.asid == 0)
2819                 return false;
2820
2821         if (vmcb->control.nested_ctl && !npt_enabled)
2822                 return false;
2823
2824         return true;
2825 }
2826
2827 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2828 {
2829         struct vmcb *nested_vmcb;
2830         struct vmcb *hsave = svm->nested.hsave;
2831         struct vmcb *vmcb = svm->vmcb;
2832         struct page *page;
2833         u64 vmcb_gpa;
2834
2835         vmcb_gpa = svm->vmcb->save.rax;
2836
2837         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2838         if (!nested_vmcb)
2839                 return false;
2840
2841         if (!nested_vmcb_checks(nested_vmcb)) {
2842                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2843                 nested_vmcb->control.exit_code_hi = 0;
2844                 nested_vmcb->control.exit_info_1  = 0;
2845                 nested_vmcb->control.exit_info_2  = 0;
2846
2847                 nested_svm_unmap(page);
2848
2849                 return false;
2850         }
2851
2852         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2853                                nested_vmcb->save.rip,
2854                                nested_vmcb->control.int_ctl,
2855                                nested_vmcb->control.event_inj,
2856                                nested_vmcb->control.nested_ctl);
2857
2858         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2859                                     nested_vmcb->control.intercept_cr >> 16,
2860                                     nested_vmcb->control.intercept_exceptions,
2861                                     nested_vmcb->control.intercept);
2862
2863         /* Clear internal status */
2864         kvm_clear_exception_queue(&svm->vcpu);
2865         kvm_clear_interrupt_queue(&svm->vcpu);
2866
2867         /*
2868          * Save the old vmcb, so we don't need to pick what we save, but can
2869          * restore everything when a VMEXIT occurs
2870          */
2871         hsave->save.es     = vmcb->save.es;
2872         hsave->save.cs     = vmcb->save.cs;
2873         hsave->save.ss     = vmcb->save.ss;
2874         hsave->save.ds     = vmcb->save.ds;
2875         hsave->save.gdtr   = vmcb->save.gdtr;
2876         hsave->save.idtr   = vmcb->save.idtr;
2877         hsave->save.efer   = svm->vcpu.arch.efer;
2878         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2879         hsave->save.cr4    = svm->vcpu.arch.cr4;
2880         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2881         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2882         hsave->save.rsp    = vmcb->save.rsp;
2883         hsave->save.rax    = vmcb->save.rax;
2884         if (npt_enabled)
2885                 hsave->save.cr3    = vmcb->save.cr3;
2886         else
2887                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2888
2889         copy_vmcb_control_area(hsave, vmcb);
2890
2891         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2892                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2893         else
2894                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2895
2896         if (nested_vmcb->control.nested_ctl) {
2897                 kvm_mmu_unload(&svm->vcpu);
2898                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2899                 nested_svm_init_mmu_context(&svm->vcpu);
2900         }
2901
2902         /* Load the nested guest state */
2903         svm->vmcb->save.es = nested_vmcb->save.es;
2904         svm->vmcb->save.cs = nested_vmcb->save.cs;
2905         svm->vmcb->save.ss = nested_vmcb->save.ss;
2906         svm->vmcb->save.ds = nested_vmcb->save.ds;
2907         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2908         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2909         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2910         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2911         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2912         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2913         if (npt_enabled) {
2914                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2915                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2916         } else
2917                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2918
2919         /* Guest paging mode is active - reset mmu */
2920         kvm_mmu_reset_context(&svm->vcpu);
2921
2922         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2923         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2924         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2925         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2926
2927         /* In case we don't even reach vcpu_run, the fields are not updated */
2928         svm->vmcb->save.rax = nested_vmcb->save.rax;
2929         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2930         svm->vmcb->save.rip = nested_vmcb->save.rip;
2931         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2932         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2933         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2934
2935         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2936         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2937
2938         /* cache intercepts */
2939         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2940         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2941         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2942         svm->nested.intercept            = nested_vmcb->control.intercept;
2943
2944         svm_flush_tlb(&svm->vcpu);
2945         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2946         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2947                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2948         else
2949                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2950
2951         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2952                 /* We only want the cr8 intercept bits of the guest */
2953                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2954                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2955         }
2956
2957         /* We don't want to see VMMCALLs from a nested guest */
2958         clr_intercept(svm, INTERCEPT_VMMCALL);
2959
2960         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2961         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2962         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2963         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2964         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2965         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2966
2967         nested_svm_unmap(page);
2968
2969         /* Enter Guest-Mode */
2970         enter_guest_mode(&svm->vcpu);
2971
2972         /*
2973          * Merge guest and host intercepts - must be called  with vcpu in
2974          * guest-mode to take affect here
2975          */
2976         recalc_intercepts(svm);
2977
2978         svm->nested.vmcb = vmcb_gpa;
2979
2980         enable_gif(svm);
2981
2982         mark_all_dirty(svm->vmcb);
2983
2984         return true;
2985 }
2986
2987 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2988 {
2989         to_vmcb->save.fs = from_vmcb->save.fs;
2990         to_vmcb->save.gs = from_vmcb->save.gs;
2991         to_vmcb->save.tr = from_vmcb->save.tr;
2992         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2993         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2994         to_vmcb->save.star = from_vmcb->save.star;
2995         to_vmcb->save.lstar = from_vmcb->save.lstar;
2996         to_vmcb->save.cstar = from_vmcb->save.cstar;
2997         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2998         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2999         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3000         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3001 }
3002
3003 static int vmload_interception(struct vcpu_svm *svm)
3004 {
3005         struct vmcb *nested_vmcb;
3006         struct page *page;
3007
3008         if (nested_svm_check_permissions(svm))
3009                 return 1;
3010
3011         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3012         if (!nested_vmcb)
3013                 return 1;
3014
3015         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3016         skip_emulated_instruction(&svm->vcpu);
3017
3018         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3019         nested_svm_unmap(page);
3020
3021         return 1;
3022 }
3023
3024 static int vmsave_interception(struct vcpu_svm *svm)
3025 {
3026         struct vmcb *nested_vmcb;
3027         struct page *page;
3028
3029         if (nested_svm_check_permissions(svm))
3030                 return 1;
3031
3032         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3033         if (!nested_vmcb)
3034                 return 1;
3035
3036         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3037         skip_emulated_instruction(&svm->vcpu);
3038
3039         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3040         nested_svm_unmap(page);
3041
3042         return 1;
3043 }
3044
3045 static int vmrun_interception(struct vcpu_svm *svm)
3046 {
3047         if (nested_svm_check_permissions(svm))
3048                 return 1;
3049
3050         /* Save rip after vmrun instruction */
3051         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3052
3053         if (!nested_svm_vmrun(svm))
3054                 return 1;
3055
3056         if (!nested_svm_vmrun_msrpm(svm))
3057                 goto failed;
3058
3059         return 1;
3060
3061 failed:
3062
3063         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3064         svm->vmcb->control.exit_code_hi = 0;
3065         svm->vmcb->control.exit_info_1  = 0;
3066         svm->vmcb->control.exit_info_2  = 0;
3067
3068         nested_svm_vmexit(svm);
3069
3070         return 1;
3071 }
3072
3073 static int stgi_interception(struct vcpu_svm *svm)
3074 {
3075         if (nested_svm_check_permissions(svm))
3076                 return 1;
3077
3078         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3079         skip_emulated_instruction(&svm->vcpu);
3080         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3081
3082         enable_gif(svm);
3083
3084         return 1;
3085 }
3086
3087 static int clgi_interception(struct vcpu_svm *svm)
3088 {
3089         if (nested_svm_check_permissions(svm))
3090                 return 1;
3091
3092         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3093         skip_emulated_instruction(&svm->vcpu);
3094
3095         disable_gif(svm);
3096
3097         /* After a CLGI no interrupts should come */
3098         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3099                 svm_clear_vintr(svm);
3100                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3101                 mark_dirty(svm->vmcb, VMCB_INTR);
3102         }
3103
3104         return 1;
3105 }
3106
3107 static int invlpga_interception(struct vcpu_svm *svm)
3108 {
3109         struct kvm_vcpu *vcpu = &svm->vcpu;
3110
3111         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3112                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3113
3114         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3115         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3116
3117         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3118         skip_emulated_instruction(&svm->vcpu);
3119         return 1;
3120 }
3121
3122 static int skinit_interception(struct vcpu_svm *svm)
3123 {
3124         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3125
3126         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3127         return 1;
3128 }
3129
3130 static int wbinvd_interception(struct vcpu_svm *svm)
3131 {
3132         return kvm_emulate_wbinvd(&svm->vcpu);
3133 }
3134
3135 static int xsetbv_interception(struct vcpu_svm *svm)
3136 {
3137         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3138         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3139
3140         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3141                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3142                 skip_emulated_instruction(&svm->vcpu);
3143         }
3144
3145         return 1;
3146 }
3147
3148 static int task_switch_interception(struct vcpu_svm *svm)
3149 {
3150         u16 tss_selector;
3151         int reason;
3152         int int_type = svm->vmcb->control.exit_int_info &
3153                 SVM_EXITINTINFO_TYPE_MASK;
3154         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3155         uint32_t type =
3156                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3157         uint32_t idt_v =
3158                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3159         bool has_error_code = false;
3160         u32 error_code = 0;
3161
3162         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3163
3164         if (svm->vmcb->control.exit_info_2 &
3165             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3166                 reason = TASK_SWITCH_IRET;
3167         else if (svm->vmcb->control.exit_info_2 &
3168                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3169                 reason = TASK_SWITCH_JMP;
3170         else if (idt_v)
3171                 reason = TASK_SWITCH_GATE;
3172         else
3173                 reason = TASK_SWITCH_CALL;
3174
3175         if (reason == TASK_SWITCH_GATE) {
3176                 switch (type) {
3177                 case SVM_EXITINTINFO_TYPE_NMI:
3178                         svm->vcpu.arch.nmi_injected = false;
3179                         break;
3180                 case SVM_EXITINTINFO_TYPE_EXEPT:
3181                         if (svm->vmcb->control.exit_info_2 &
3182                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3183                                 has_error_code = true;
3184                                 error_code =
3185                                         (u32)svm->vmcb->control.exit_info_2;
3186                         }
3187                         kvm_clear_exception_queue(&svm->vcpu);
3188                         break;
3189                 case SVM_EXITINTINFO_TYPE_INTR:
3190                         kvm_clear_interrupt_queue(&svm->vcpu);
3191                         break;
3192                 default:
3193                         break;
3194                 }
3195         }
3196
3197         if (reason != TASK_SWITCH_GATE ||
3198             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3199             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3200              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3201                 skip_emulated_instruction(&svm->vcpu);
3202
3203         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3204                 int_vec = -1;
3205
3206         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3207                                 has_error_code, error_code) == EMULATE_FAIL) {
3208                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3209                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3210                 svm->vcpu.run->internal.ndata = 0;
3211                 return 0;
3212         }
3213         return 1;
3214 }
3215
3216 static int cpuid_interception(struct vcpu_svm *svm)
3217 {
3218         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3219         return kvm_emulate_cpuid(&svm->vcpu);
3220 }
3221
3222 static int iret_interception(struct vcpu_svm *svm)
3223 {
3224         ++svm->vcpu.stat.nmi_window_exits;
3225         clr_intercept(svm, INTERCEPT_IRET);
3226         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3227         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3228         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3229         return 1;
3230 }
3231
3232 static int invlpg_interception(struct vcpu_svm *svm)
3233 {
3234         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3235                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3236
3237         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3238         skip_emulated_instruction(&svm->vcpu);
3239         return 1;
3240 }
3241
3242 static int emulate_on_interception(struct vcpu_svm *svm)
3243 {
3244         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3245 }
3246
3247 static int rdpmc_interception(struct vcpu_svm *svm)
3248 {
3249         int err;
3250
3251         if (!static_cpu_has(X86_FEATURE_NRIPS))
3252                 return emulate_on_interception(svm);
3253
3254         err = kvm_rdpmc(&svm->vcpu);
3255         return kvm_complete_insn_gp(&svm->vcpu, err);
3256 }
3257
3258 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3259                                             unsigned long val)
3260 {
3261         unsigned long cr0 = svm->vcpu.arch.cr0;
3262         bool ret = false;
3263         u64 intercept;
3264
3265         intercept = svm->nested.intercept;
3266
3267         if (!is_guest_mode(&svm->vcpu) ||
3268             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3269                 return false;
3270
3271         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3272         val &= ~SVM_CR0_SELECTIVE_MASK;
3273
3274         if (cr0 ^ val) {
3275                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3276                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3277         }
3278
3279         return ret;
3280 }
3281
3282 #define CR_VALID (1ULL << 63)
3283
3284 static int cr_interception(struct vcpu_svm *svm)
3285 {
3286         int reg, cr;
3287         unsigned long val;
3288         int err;
3289
3290         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3291                 return emulate_on_interception(svm);
3292
3293         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3294                 return emulate_on_interception(svm);
3295
3296         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3297         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3298                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3299         else
3300                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3301
3302         err = 0;
3303         if (cr >= 16) { /* mov to cr */
3304                 cr -= 16;
3305                 val = kvm_register_read(&svm->vcpu, reg);
3306                 switch (cr) {
3307                 case 0:
3308                         if (!check_selective_cr0_intercepted(svm, val))
3309                                 err = kvm_set_cr0(&svm->vcpu, val);
3310                         else
3311                                 return 1;
3312
3313                         break;
3314                 case 3:
3315                         err = kvm_set_cr3(&svm->vcpu, val);
3316                         break;
3317                 case 4:
3318                         err = kvm_set_cr4(&svm->vcpu, val);
3319                         break;
3320                 case 8:
3321                         err = kvm_set_cr8(&svm->vcpu, val);
3322                         break;
3323                 default:
3324                         WARN(1, "unhandled write to CR%d", cr);
3325                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3326                         return 1;
3327                 }
3328         } else { /* mov from cr */
3329                 switch (cr) {
3330                 case 0:
3331                         val = kvm_read_cr0(&svm->vcpu);
3332                         break;
3333                 case 2:
3334                         val = svm->vcpu.arch.cr2;
3335                         break;
3336                 case 3:
3337                         val = kvm_read_cr3(&svm->vcpu);
3338                         break;
3339                 case 4:
3340                         val = kvm_read_cr4(&svm->vcpu);
3341                         break;
3342                 case 8:
3343                         val = kvm_get_cr8(&svm->vcpu);
3344                         break;
3345                 default:
3346                         WARN(1, "unhandled read from CR%d", cr);
3347                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3348                         return 1;
3349                 }
3350                 kvm_register_write(&svm->vcpu, reg, val);
3351         }
3352         return kvm_complete_insn_gp(&svm->vcpu, err);
3353 }
3354
3355 static int dr_interception(struct vcpu_svm *svm)
3356 {
3357         int reg, dr;
3358         unsigned long val;
3359
3360         if (svm->vcpu.guest_debug == 0) {
3361                 /*
3362                  * No more DR vmexits; force a reload of the debug registers
3363                  * and reenter on this instruction.  The next vmexit will
3364                  * retrieve the full state of the debug registers.
3365                  */
3366                 clr_dr_intercepts(svm);
3367                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3368                 return 1;
3369         }
3370
3371         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3372                 return emulate_on_interception(svm);
3373
3374         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3375         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3376
3377         if (dr >= 16) { /* mov to DRn */
3378                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3379                         return 1;
3380                 val = kvm_register_read(&svm->vcpu, reg);
3381                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3382         } else {
3383                 if (!kvm_require_dr(&svm->vcpu, dr))
3384                         return 1;
3385                 kvm_get_dr(&svm->vcpu, dr, &val);
3386                 kvm_register_write(&svm->vcpu, reg, val);
3387         }
3388
3389         skip_emulated_instruction(&svm->vcpu);
3390
3391         return 1;
3392 }
3393
3394 static int cr8_write_interception(struct vcpu_svm *svm)
3395 {
3396         struct kvm_run *kvm_run = svm->vcpu.run;
3397         int r;
3398
3399         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3400         /* instruction emulation calls kvm_set_cr8() */
3401         r = cr_interception(svm);
3402         if (lapic_in_kernel(&svm->vcpu))
3403                 return r;
3404         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3405                 return r;
3406         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3407         return 0;
3408 }
3409
3410 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3411 {
3412         struct vcpu_svm *svm = to_svm(vcpu);
3413
3414         switch (msr_info->index) {
3415         case MSR_IA32_TSC: {
3416                 msr_info->data = svm->vmcb->control.tsc_offset +
3417                         kvm_scale_tsc(vcpu, rdtsc());
3418
3419                 break;
3420         }
3421         case MSR_STAR:
3422                 msr_info->data = svm->vmcb->save.star;
3423                 break;
3424 #ifdef CONFIG_X86_64
3425         case MSR_LSTAR:
3426                 msr_info->data = svm->vmcb->save.lstar;
3427                 break;
3428         case MSR_CSTAR:
3429                 msr_info->data = svm->vmcb->save.cstar;
3430                 break;
3431         case MSR_KERNEL_GS_BASE:
3432                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3433                 break;
3434         case MSR_SYSCALL_MASK:
3435                 msr_info->data = svm->vmcb->save.sfmask;
3436                 break;
3437 #endif
3438         case MSR_IA32_SYSENTER_CS:
3439                 msr_info->data = svm->vmcb->save.sysenter_cs;
3440                 break;
3441         case MSR_IA32_SYSENTER_EIP:
3442                 msr_info->data = svm->sysenter_eip;
3443                 break;
3444         case MSR_IA32_SYSENTER_ESP:
3445                 msr_info->data = svm->sysenter_esp;
3446                 break;
3447         case MSR_TSC_AUX:
3448                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3449                         return 1;
3450                 msr_info->data = svm->tsc_aux;
3451                 break;
3452         /*
3453          * Nobody will change the following 5 values in the VMCB so we can
3454          * safely return them on rdmsr. They will always be 0 until LBRV is
3455          * implemented.
3456          */
3457         case MSR_IA32_DEBUGCTLMSR:
3458                 msr_info->data = svm->vmcb->save.dbgctl;
3459                 break;
3460         case MSR_IA32_LASTBRANCHFROMIP:
3461                 msr_info->data = svm->vmcb->save.br_from;
3462                 break;
3463         case MSR_IA32_LASTBRANCHTOIP:
3464                 msr_info->data = svm->vmcb->save.br_to;
3465                 break;
3466         case MSR_IA32_LASTINTFROMIP:
3467                 msr_info->data = svm->vmcb->save.last_excp_from;
3468                 break;
3469         case MSR_IA32_LASTINTTOIP:
3470                 msr_info->data = svm->vmcb->save.last_excp_to;
3471                 break;
3472         case MSR_VM_HSAVE_PA:
3473                 msr_info->data = svm->nested.hsave_msr;
3474                 break;
3475         case MSR_VM_CR:
3476                 msr_info->data = svm->nested.vm_cr_msr;
3477                 break;
3478         case MSR_IA32_UCODE_REV:
3479                 msr_info->data = 0x01000065;
3480                 break;
3481         case MSR_F15H_IC_CFG: {
3482
3483                 int family, model;
3484
3485                 family = guest_cpuid_family(vcpu);
3486                 model  = guest_cpuid_model(vcpu);
3487
3488                 if (family < 0 || model < 0)
3489                         return kvm_get_msr_common(vcpu, msr_info);
3490
3491                 msr_info->data = 0;
3492
3493                 if (family == 0x15 &&
3494                     (model >= 0x2 && model < 0x20))
3495                         msr_info->data = 0x1E;
3496                 }
3497                 break;
3498         default:
3499                 return kvm_get_msr_common(vcpu, msr_info);
3500         }
3501         return 0;
3502 }
3503
3504 static int rdmsr_interception(struct vcpu_svm *svm)
3505 {
3506         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3507         struct msr_data msr_info;
3508
3509         msr_info.index = ecx;
3510         msr_info.host_initiated = false;
3511         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3512                 trace_kvm_msr_read_ex(ecx);
3513                 kvm_inject_gp(&svm->vcpu, 0);
3514         } else {
3515                 trace_kvm_msr_read(ecx, msr_info.data);
3516
3517                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3518                                    msr_info.data & 0xffffffff);
3519                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3520                                    msr_info.data >> 32);
3521                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3522                 skip_emulated_instruction(&svm->vcpu);
3523         }
3524         return 1;
3525 }
3526
3527 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3528 {
3529         struct vcpu_svm *svm = to_svm(vcpu);
3530         int svm_dis, chg_mask;
3531
3532         if (data & ~SVM_VM_CR_VALID_MASK)
3533                 return 1;
3534
3535         chg_mask = SVM_VM_CR_VALID_MASK;
3536
3537         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3538                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3539
3540         svm->nested.vm_cr_msr &= ~chg_mask;
3541         svm->nested.vm_cr_msr |= (data & chg_mask);
3542
3543         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3544
3545         /* check for svm_disable while efer.svme is set */
3546         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3547                 return 1;
3548
3549         return 0;
3550 }
3551
3552 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3553 {
3554         struct vcpu_svm *svm = to_svm(vcpu);
3555
3556         u32 ecx = msr->index;
3557         u64 data = msr->data;
3558         switch (ecx) {
3559         case MSR_IA32_TSC:
3560                 kvm_write_tsc(vcpu, msr);
3561                 break;
3562         case MSR_STAR:
3563                 svm->vmcb->save.star = data;
3564                 break;
3565 #ifdef CONFIG_X86_64
3566         case MSR_LSTAR:
3567                 svm->vmcb->save.lstar = data;
3568                 break;
3569         case MSR_CSTAR:
3570                 svm->vmcb->save.cstar = data;
3571                 break;
3572         case MSR_KERNEL_GS_BASE:
3573                 svm->vmcb->save.kernel_gs_base = data;
3574                 break;
3575         case MSR_SYSCALL_MASK:
3576                 svm->vmcb->save.sfmask = data;
3577                 break;
3578 #endif
3579         case MSR_IA32_SYSENTER_CS:
3580                 svm->vmcb->save.sysenter_cs = data;
3581                 break;
3582         case MSR_IA32_SYSENTER_EIP:
3583                 svm->sysenter_eip = data;
3584                 svm->vmcb->save.sysenter_eip = data;
3585                 break;
3586         case MSR_IA32_SYSENTER_ESP:
3587                 svm->sysenter_esp = data;
3588                 svm->vmcb->save.sysenter_esp = data;
3589                 break;
3590         case MSR_TSC_AUX:
3591                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3592                         return 1;
3593
3594                 /*
3595                  * This is rare, so we update the MSR here instead of using
3596                  * direct_access_msrs.  Doing that would require a rdmsr in
3597                  * svm_vcpu_put.
3598                  */
3599                 svm->tsc_aux = data;
3600                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3601                 break;
3602         case MSR_IA32_DEBUGCTLMSR:
3603                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3604                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3605                                     __func__, data);
3606                         break;
3607                 }
3608                 if (data & DEBUGCTL_RESERVED_BITS)
3609                         return 1;
3610
3611                 svm->vmcb->save.dbgctl = data;
3612                 mark_dirty(svm->vmcb, VMCB_LBR);
3613                 if (data & (1ULL<<0))
3614                         svm_enable_lbrv(svm);
3615                 else
3616                         svm_disable_lbrv(svm);
3617                 break;
3618         case MSR_VM_HSAVE_PA:
3619                 svm->nested.hsave_msr = data;
3620                 break;
3621         case MSR_VM_CR:
3622                 return svm_set_vm_cr(vcpu, data);
3623         case MSR_VM_IGNNE:
3624                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3625                 break;
3626         case MSR_IA32_APICBASE:
3627                 if (kvm_vcpu_apicv_active(vcpu))
3628                         avic_update_vapic_bar(to_svm(vcpu), data);
3629                 /* Follow through */
3630         default:
3631                 return kvm_set_msr_common(vcpu, msr);
3632         }
3633         return 0;
3634 }
3635
3636 static int wrmsr_interception(struct vcpu_svm *svm)
3637 {
3638         struct msr_data msr;
3639         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3640         u64 data = kvm_read_edx_eax(&svm->vcpu);
3641
3642         msr.data = data;
3643         msr.index = ecx;
3644         msr.host_initiated = false;
3645
3646         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3647         if (kvm_set_msr(&svm->vcpu, &msr)) {
3648                 trace_kvm_msr_write_ex(ecx, data);
3649                 kvm_inject_gp(&svm->vcpu, 0);
3650         } else {
3651                 trace_kvm_msr_write(ecx, data);
3652                 skip_emulated_instruction(&svm->vcpu);
3653         }
3654         return 1;
3655 }
3656
3657 static int msr_interception(struct vcpu_svm *svm)
3658 {
3659         if (svm->vmcb->control.exit_info_1)
3660                 return wrmsr_interception(svm);
3661         else
3662                 return rdmsr_interception(svm);
3663 }
3664
3665 static int interrupt_window_interception(struct vcpu_svm *svm)
3666 {
3667         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3668         svm_clear_vintr(svm);
3669         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3670         mark_dirty(svm->vmcb, VMCB_INTR);
3671         ++svm->vcpu.stat.irq_window_exits;
3672         return 1;
3673 }
3674
3675 static int pause_interception(struct vcpu_svm *svm)
3676 {
3677         kvm_vcpu_on_spin(&(svm->vcpu));
3678         return 1;
3679 }
3680
3681 static int nop_interception(struct vcpu_svm *svm)
3682 {
3683         skip_emulated_instruction(&(svm->vcpu));
3684         return 1;
3685 }
3686
3687 static int monitor_interception(struct vcpu_svm *svm)
3688 {
3689         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3690         return nop_interception(svm);
3691 }
3692
3693 static int mwait_interception(struct vcpu_svm *svm)
3694 {
3695         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3696         return nop_interception(svm);
3697 }
3698
3699 enum avic_ipi_failure_cause {
3700         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3701         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3702         AVIC_IPI_FAILURE_INVALID_TARGET,
3703         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3704 };
3705
3706 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3707 {
3708         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3709         u32 icrl = svm->vmcb->control.exit_info_1;
3710         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3711         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3712         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3713
3714         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3715
3716         switch (id) {
3717         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3718                 /*
3719                  * AVIC hardware handles the generation of
3720                  * IPIs when the specified Message Type is Fixed
3721                  * (also known as fixed delivery mode) and
3722                  * the Trigger Mode is edge-triggered. The hardware
3723                  * also supports self and broadcast delivery modes
3724                  * specified via the Destination Shorthand(DSH)
3725                  * field of the ICRL. Logical and physical APIC ID
3726                  * formats are supported. All other IPI types cause
3727                  * a #VMEXIT, which needs to emulated.
3728                  */
3729                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3730                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3731                 break;
3732         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3733                 int i;
3734                 struct kvm_vcpu *vcpu;
3735                 struct kvm *kvm = svm->vcpu.kvm;
3736                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3737
3738                 /*
3739                  * At this point, we expect that the AVIC HW has already
3740                  * set the appropriate IRR bits on the valid target
3741                  * vcpus. So, we just need to kick the appropriate vcpu.
3742                  */
3743                 kvm_for_each_vcpu(i, vcpu, kvm) {
3744                         bool m = kvm_apic_match_dest(vcpu, apic,
3745                                                      icrl & KVM_APIC_SHORT_MASK,
3746                                                      GET_APIC_DEST_FIELD(icrh),
3747                                                      icrl & KVM_APIC_DEST_MASK);
3748
3749                         if (m && !avic_vcpu_is_running(vcpu))
3750                                 kvm_vcpu_wake_up(vcpu);
3751                 }
3752                 break;
3753         }
3754         case AVIC_IPI_FAILURE_INVALID_TARGET:
3755                 break;
3756         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3757                 WARN_ONCE(1, "Invalid backing page\n");
3758                 break;
3759         default:
3760                 pr_err("Unknown IPI interception\n");
3761         }
3762
3763         return 1;
3764 }
3765
3766 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3767 {
3768         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3769         int index;
3770         u32 *logical_apic_id_table;
3771         int dlid = GET_APIC_LOGICAL_ID(ldr);
3772
3773         if (!dlid)
3774                 return NULL;
3775
3776         if (flat) { /* flat */
3777                 index = ffs(dlid) - 1;
3778                 if (index > 7)
3779                         return NULL;
3780         } else { /* cluster */
3781                 int cluster = (dlid & 0xf0) >> 4;
3782                 int apic = ffs(dlid & 0x0f) - 1;
3783
3784                 if ((apic < 0) || (apic > 7) ||
3785                     (cluster >= 0xf))
3786                         return NULL;
3787                 index = (cluster << 2) + apic;
3788         }
3789
3790         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3791
3792         return &logical_apic_id_table[index];
3793 }
3794
3795 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3796                           bool valid)
3797 {
3798         bool flat;
3799         u32 *entry, new_entry;
3800
3801         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3802         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3803         if (!entry)
3804                 return -EINVAL;
3805
3806         new_entry = READ_ONCE(*entry);
3807         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3808         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3809         if (valid)
3810                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3811         else
3812                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3813         WRITE_ONCE(*entry, new_entry);
3814
3815         return 0;
3816 }
3817
3818 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3819 {
3820         int ret;
3821         struct vcpu_svm *svm = to_svm(vcpu);
3822         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3823
3824         if (!ldr)
3825                 return 1;
3826
3827         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3828         if (ret && svm->ldr_reg) {
3829                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3830                 svm->ldr_reg = 0;
3831         } else {
3832                 svm->ldr_reg = ldr;
3833         }
3834         return ret;
3835 }
3836
3837 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3838 {
3839         u64 *old, *new;
3840         struct vcpu_svm *svm = to_svm(vcpu);
3841         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3842         u32 id = (apic_id_reg >> 24) & 0xff;
3843
3844         if (vcpu->vcpu_id == id)
3845                 return 0;
3846
3847         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3848         new = avic_get_physical_id_entry(vcpu, id);
3849         if (!new || !old)
3850                 return 1;
3851
3852         /* We need to move physical_id_entry to new offset */
3853         *new = *old;
3854         *old = 0ULL;
3855         to_svm(vcpu)->avic_physical_id_cache = new;
3856
3857         /*
3858          * Also update the guest physical APIC ID in the logical
3859          * APIC ID table entry if already setup the LDR.
3860          */
3861         if (svm->ldr_reg)
3862                 avic_handle_ldr_update(vcpu);
3863
3864         return 0;
3865 }
3866
3867 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3868 {
3869         struct vcpu_svm *svm = to_svm(vcpu);
3870         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3871         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3872         u32 mod = (dfr >> 28) & 0xf;
3873
3874         /*
3875          * We assume that all local APICs are using the same type.
3876          * If this changes, we need to flush the AVIC logical
3877          * APID id table.
3878          */
3879         if (vm_data->ldr_mode == mod)
3880                 return 0;
3881
3882         clear_page(page_address(vm_data->avic_logical_id_table_page));
3883         vm_data->ldr_mode = mod;
3884
3885         if (svm->ldr_reg)
3886                 avic_handle_ldr_update(vcpu);
3887         return 0;
3888 }
3889
3890 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3891 {
3892         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3893         u32 offset = svm->vmcb->control.exit_info_1 &
3894                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3895
3896         switch (offset) {
3897         case APIC_ID:
3898                 if (avic_handle_apic_id_update(&svm->vcpu))
3899                         return 0;
3900                 break;
3901         case APIC_LDR:
3902                 if (avic_handle_ldr_update(&svm->vcpu))
3903                         return 0;
3904                 break;
3905         case APIC_DFR:
3906                 avic_handle_dfr_update(&svm->vcpu);
3907                 break;
3908         default:
3909                 break;
3910         }
3911
3912         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3913
3914         return 1;
3915 }
3916
3917 static bool is_avic_unaccelerated_access_trap(u32 offset)
3918 {
3919         bool ret = false;
3920
3921         switch (offset) {
3922         case APIC_ID:
3923         case APIC_EOI:
3924         case APIC_RRR:
3925         case APIC_LDR:
3926         case APIC_DFR:
3927         case APIC_SPIV:
3928         case APIC_ESR:
3929         case APIC_ICR:
3930         case APIC_LVTT:
3931         case APIC_LVTTHMR:
3932         case APIC_LVTPC:
3933         case APIC_LVT0:
3934         case APIC_LVT1:
3935         case APIC_LVTERR:
3936         case APIC_TMICT:
3937         case APIC_TDCR:
3938                 ret = true;
3939                 break;
3940         default:
3941                 break;
3942         }
3943         return ret;
3944 }
3945
3946 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3947 {
3948         int ret = 0;
3949         u32 offset = svm->vmcb->control.exit_info_1 &
3950                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3951         u32 vector = svm->vmcb->control.exit_info_2 &
3952                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3953         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3954                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
3955         bool trap = is_avic_unaccelerated_access_trap(offset);
3956
3957         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3958                                             trap, write, vector);
3959         if (trap) {
3960                 /* Handling Trap */
3961                 WARN_ONCE(!write, "svm: Handling trap read.\n");
3962                 ret = avic_unaccel_trap_write(svm);
3963         } else {
3964                 /* Handling Fault */
3965                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3966         }
3967
3968         return ret;
3969 }
3970
3971 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3972         [SVM_EXIT_READ_CR0]                     = cr_interception,
3973         [SVM_EXIT_READ_CR3]                     = cr_interception,
3974         [SVM_EXIT_READ_CR4]                     = cr_interception,
3975         [SVM_EXIT_READ_CR8]                     = cr_interception,
3976         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3977         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3978         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3979         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3980         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3981         [SVM_EXIT_READ_DR0]                     = dr_interception,
3982         [SVM_EXIT_READ_DR1]                     = dr_interception,
3983         [SVM_EXIT_READ_DR2]                     = dr_interception,
3984         [SVM_EXIT_READ_DR3]                     = dr_interception,
3985         [SVM_EXIT_READ_DR4]                     = dr_interception,
3986         [SVM_EXIT_READ_DR5]                     = dr_interception,
3987         [SVM_EXIT_READ_DR6]                     = dr_interception,
3988         [SVM_EXIT_READ_DR7]                     = dr_interception,
3989         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3990         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3991         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3992         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3993         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3994         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3995         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3996         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3997         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3998         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3999         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4000         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4001         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4002         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4003         [SVM_EXIT_INTR]                         = intr_interception,
4004         [SVM_EXIT_NMI]                          = nmi_interception,
4005         [SVM_EXIT_SMI]                          = nop_on_interception,
4006         [SVM_EXIT_INIT]                         = nop_on_interception,
4007         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4008         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4009         [SVM_EXIT_CPUID]                        = cpuid_interception,
4010         [SVM_EXIT_IRET]                         = iret_interception,
4011         [SVM_EXIT_INVD]                         = emulate_on_interception,
4012         [SVM_EXIT_PAUSE]                        = pause_interception,
4013         [SVM_EXIT_HLT]                          = halt_interception,
4014         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4015         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4016         [SVM_EXIT_IOIO]                         = io_interception,
4017         [SVM_EXIT_MSR]                          = msr_interception,
4018         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4019         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4020         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4021         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4022         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4023         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4024         [SVM_EXIT_STGI]                         = stgi_interception,
4025         [SVM_EXIT_CLGI]                         = clgi_interception,
4026         [SVM_EXIT_SKINIT]                       = skinit_interception,
4027         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4028         [SVM_EXIT_MONITOR]                      = monitor_interception,
4029         [SVM_EXIT_MWAIT]                        = mwait_interception,
4030         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4031         [SVM_EXIT_NPF]                          = pf_interception,
4032         [SVM_EXIT_RSM]                          = emulate_on_interception,
4033         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4034         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4035 };
4036
4037 static void dump_vmcb(struct kvm_vcpu *vcpu)
4038 {
4039         struct vcpu_svm *svm = to_svm(vcpu);
4040         struct vmcb_control_area *control = &svm->vmcb->control;
4041         struct vmcb_save_area *save = &svm->vmcb->save;
4042
4043         pr_err("VMCB Control Area:\n");
4044         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4045         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4046         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4047         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4048         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4049         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4050         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4051         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4052         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4053         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4054         pr_err("%-20s%d\n", "asid:", control->asid);
4055         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4056         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4057         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4058         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4059         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4060         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4061         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4062         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4063         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4064         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4065         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4066         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4067         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4068         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4069         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4070         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4071         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4072         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4073         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4074         pr_err("VMCB State Save Area:\n");
4075         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4076                "es:",
4077                save->es.selector, save->es.attrib,
4078                save->es.limit, save->es.base);
4079         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4080                "cs:",
4081                save->cs.selector, save->cs.attrib,
4082                save->cs.limit, save->cs.base);
4083         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4084                "ss:",
4085                save->ss.selector, save->ss.attrib,
4086                save->ss.limit, save->ss.base);
4087         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4088                "ds:",
4089                save->ds.selector, save->ds.attrib,
4090                save->ds.limit, save->ds.base);
4091         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4092                "fs:",
4093                save->fs.selector, save->fs.attrib,
4094                save->fs.limit, save->fs.base);
4095         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4096                "gs:",
4097                save->gs.selector, save->gs.attrib,
4098                save->gs.limit, save->gs.base);
4099         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4100                "gdtr:",
4101                save->gdtr.selector, save->gdtr.attrib,
4102                save->gdtr.limit, save->gdtr.base);
4103         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4104                "ldtr:",
4105                save->ldtr.selector, save->ldtr.attrib,
4106                save->ldtr.limit, save->ldtr.base);
4107         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4108                "idtr:",
4109                save->idtr.selector, save->idtr.attrib,
4110                save->idtr.limit, save->idtr.base);
4111         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4112                "tr:",
4113                save->tr.selector, save->tr.attrib,
4114                save->tr.limit, save->tr.base);
4115         pr_err("cpl:            %d                efer:         %016llx\n",
4116                 save->cpl, save->efer);
4117         pr_err("%-15s %016llx %-13s %016llx\n",
4118                "cr0:", save->cr0, "cr2:", save->cr2);
4119         pr_err("%-15s %016llx %-13s %016llx\n",
4120                "cr3:", save->cr3, "cr4:", save->cr4);
4121         pr_err("%-15s %016llx %-13s %016llx\n",
4122                "dr6:", save->dr6, "dr7:", save->dr7);
4123         pr_err("%-15s %016llx %-13s %016llx\n",
4124                "rip:", save->rip, "rflags:", save->rflags);
4125         pr_err("%-15s %016llx %-13s %016llx\n",
4126                "rsp:", save->rsp, "rax:", save->rax);
4127         pr_err("%-15s %016llx %-13s %016llx\n",
4128                "star:", save->star, "lstar:", save->lstar);
4129         pr_err("%-15s %016llx %-13s %016llx\n",
4130                "cstar:", save->cstar, "sfmask:", save->sfmask);
4131         pr_err("%-15s %016llx %-13s %016llx\n",
4132                "kernel_gs_base:", save->kernel_gs_base,
4133                "sysenter_cs:", save->sysenter_cs);
4134         pr_err("%-15s %016llx %-13s %016llx\n",
4135                "sysenter_esp:", save->sysenter_esp,
4136                "sysenter_eip:", save->sysenter_eip);
4137         pr_err("%-15s %016llx %-13s %016llx\n",
4138                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4139         pr_err("%-15s %016llx %-13s %016llx\n",
4140                "br_from:", save->br_from, "br_to:", save->br_to);
4141         pr_err("%-15s %016llx %-13s %016llx\n",
4142                "excp_from:", save->last_excp_from,
4143                "excp_to:", save->last_excp_to);
4144 }
4145
4146 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4147 {
4148         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4149
4150         *info1 = control->exit_info_1;
4151         *info2 = control->exit_info_2;
4152 }
4153
4154 static int handle_exit(struct kvm_vcpu *vcpu)
4155 {
4156         struct vcpu_svm *svm = to_svm(vcpu);
4157         struct kvm_run *kvm_run = vcpu->run;
4158         u32 exit_code = svm->vmcb->control.exit_code;
4159
4160         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4161
4162         vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4163
4164         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4165                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4166         if (npt_enabled)
4167                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4168
4169         if (unlikely(svm->nested.exit_required)) {
4170                 nested_svm_vmexit(svm);
4171                 svm->nested.exit_required = false;
4172
4173                 return 1;
4174         }
4175
4176         if (is_guest_mode(vcpu)) {
4177                 int vmexit;
4178
4179                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4180                                         svm->vmcb->control.exit_info_1,
4181                                         svm->vmcb->control.exit_info_2,
4182                                         svm->vmcb->control.exit_int_info,
4183                                         svm->vmcb->control.exit_int_info_err,
4184                                         KVM_ISA_SVM);
4185
4186                 vmexit = nested_svm_exit_special(svm);
4187
4188                 if (vmexit == NESTED_EXIT_CONTINUE)
4189                         vmexit = nested_svm_exit_handled(svm);
4190
4191                 if (vmexit == NESTED_EXIT_DONE)
4192                         return 1;
4193         }
4194
4195         svm_complete_interrupts(svm);
4196
4197         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4198                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4199                 kvm_run->fail_entry.hardware_entry_failure_reason
4200                         = svm->vmcb->control.exit_code;
4201                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4202                 dump_vmcb(vcpu);
4203                 return 0;
4204         }
4205
4206         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4207             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4208             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4209             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4210                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4211                        "exit_code 0x%x\n",
4212                        __func__, svm->vmcb->control.exit_int_info,
4213                        exit_code);
4214
4215         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4216             || !svm_exit_handlers[exit_code]) {
4217                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4218                 kvm_queue_exception(vcpu, UD_VECTOR);
4219                 return 1;
4220         }
4221
4222         return svm_exit_handlers[exit_code](svm);
4223 }
4224
4225 static void reload_tss(struct kvm_vcpu *vcpu)
4226 {
4227         int cpu = raw_smp_processor_id();
4228
4229         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4230         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4231         load_TR_desc();
4232 }
4233
4234 static void pre_svm_run(struct vcpu_svm *svm)
4235 {
4236         int cpu = raw_smp_processor_id();
4237
4238         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4239
4240         /* FIXME: handle wraparound of asid_generation */
4241         if (svm->asid_generation != sd->asid_generation)
4242                 new_asid(svm, sd);
4243 }
4244
4245 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4246 {
4247         struct vcpu_svm *svm = to_svm(vcpu);
4248
4249         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4250         vcpu->arch.hflags |= HF_NMI_MASK;
4251         set_intercept(svm, INTERCEPT_IRET);
4252         ++vcpu->stat.nmi_injections;
4253 }
4254
4255 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4256 {
4257         struct vmcb_control_area *control;
4258
4259         /* The following fields are ignored when AVIC is enabled */
4260         control = &svm->vmcb->control;
4261         control->int_vector = irq;
4262         control->int_ctl &= ~V_INTR_PRIO_MASK;
4263         control->int_ctl |= V_IRQ_MASK |
4264                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4265         mark_dirty(svm->vmcb, VMCB_INTR);
4266 }
4267
4268 static void svm_set_irq(struct kvm_vcpu *vcpu)
4269 {
4270         struct vcpu_svm *svm = to_svm(vcpu);
4271
4272         BUG_ON(!(gif_set(svm)));
4273
4274         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4275         ++vcpu->stat.irq_injections;
4276
4277         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4278                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4279 }
4280
4281 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4282 {
4283         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4284 }
4285
4286 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4287 {
4288         struct vcpu_svm *svm = to_svm(vcpu);
4289
4290         if (svm_nested_virtualize_tpr(vcpu) ||
4291             kvm_vcpu_apicv_active(vcpu))
4292                 return;
4293
4294         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4295
4296         if (irr == -1)
4297                 return;
4298
4299         if (tpr >= irr)
4300                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4301 }
4302
4303 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4304 {
4305         return;
4306 }
4307
4308 static bool svm_get_enable_apicv(void)
4309 {
4310         return avic;
4311 }
4312
4313 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4314 {
4315 }
4316
4317 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4318 {
4319 }
4320
4321 /* Note: Currently only used by Hyper-V. */
4322 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4323 {
4324         struct vcpu_svm *svm = to_svm(vcpu);
4325         struct vmcb *vmcb = svm->vmcb;
4326
4327         if (!avic)
4328                 return;
4329
4330         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4331         mark_dirty(vmcb, VMCB_INTR);
4332 }
4333
4334 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4335 {
4336         return;
4337 }
4338
4339 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4340 {
4341         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4342         smp_mb__after_atomic();
4343
4344         if (avic_vcpu_is_running(vcpu))
4345                 wrmsrl(SVM_AVIC_DOORBELL,
4346                        kvm_cpu_get_apicid(vcpu->cpu));
4347         else
4348                 kvm_vcpu_wake_up(vcpu);
4349 }
4350
4351 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4352 {
4353         unsigned long flags;
4354         struct amd_svm_iommu_ir *cur;
4355
4356         spin_lock_irqsave(&svm->ir_list_lock, flags);
4357         list_for_each_entry(cur, &svm->ir_list, node) {
4358                 if (cur->data != pi->ir_data)
4359                         continue;
4360                 list_del(&cur->node);
4361                 kfree(cur);
4362                 break;
4363         }
4364         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4365 }
4366
4367 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4368 {
4369         int ret = 0;
4370         unsigned long flags;
4371         struct amd_svm_iommu_ir *ir;
4372
4373         /**
4374          * In some cases, the existing irte is updaed and re-set,
4375          * so we need to check here if it's already been * added
4376          * to the ir_list.
4377          */
4378         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4379                 struct kvm *kvm = svm->vcpu.kvm;
4380                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4381                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4382                 struct vcpu_svm *prev_svm;
4383
4384                 if (!prev_vcpu) {
4385                         ret = -EINVAL;
4386                         goto out;
4387                 }
4388
4389                 prev_svm = to_svm(prev_vcpu);
4390                 svm_ir_list_del(prev_svm, pi);
4391         }
4392
4393         /**
4394          * Allocating new amd_iommu_pi_data, which will get
4395          * add to the per-vcpu ir_list.
4396          */
4397         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4398         if (!ir) {
4399                 ret = -ENOMEM;
4400                 goto out;
4401         }
4402         ir->data = pi->ir_data;
4403
4404         spin_lock_irqsave(&svm->ir_list_lock, flags);
4405         list_add(&ir->node, &svm->ir_list);
4406         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4407 out:
4408         return ret;
4409 }
4410
4411 /**
4412  * Note:
4413  * The HW cannot support posting multicast/broadcast
4414  * interrupts to a vCPU. So, we still use legacy interrupt
4415  * remapping for these kind of interrupts.
4416  *
4417  * For lowest-priority interrupts, we only support
4418  * those with single CPU as the destination, e.g. user
4419  * configures the interrupts via /proc/irq or uses
4420  * irqbalance to make the interrupts single-CPU.
4421  */
4422 static int
4423 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4424                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4425 {
4426         struct kvm_lapic_irq irq;
4427         struct kvm_vcpu *vcpu = NULL;
4428
4429         kvm_set_msi_irq(kvm, e, &irq);
4430
4431         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4432                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4433                          __func__, irq.vector);
4434                 return -1;
4435         }
4436
4437         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4438                  irq.vector);
4439         *svm = to_svm(vcpu);
4440         vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4441         vcpu_info->vector = irq.vector;
4442
4443         return 0;
4444 }
4445
4446 /*
4447  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4448  *
4449  * @kvm: kvm
4450  * @host_irq: host irq of the interrupt
4451  * @guest_irq: gsi of the interrupt
4452  * @set: set or unset PI
4453  * returns 0 on success, < 0 on failure
4454  */
4455 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4456                               uint32_t guest_irq, bool set)
4457 {
4458         struct kvm_kernel_irq_routing_entry *e;
4459         struct kvm_irq_routing_table *irq_rt;
4460         int idx, ret = -EINVAL;
4461
4462         if (!kvm_arch_has_assigned_device(kvm) ||
4463             !irq_remapping_cap(IRQ_POSTING_CAP))
4464                 return 0;
4465
4466         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4467                  __func__, host_irq, guest_irq, set);
4468
4469         idx = srcu_read_lock(&kvm->irq_srcu);
4470         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4471         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4472
4473         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4474                 struct vcpu_data vcpu_info;
4475                 struct vcpu_svm *svm = NULL;
4476
4477                 if (e->type != KVM_IRQ_ROUTING_MSI)
4478                         continue;
4479
4480                 /**
4481                  * Here, we setup with legacy mode in the following cases:
4482                  * 1. When cannot target interrupt to a specific vcpu.
4483                  * 2. Unsetting posted interrupt.
4484                  * 3. APIC virtialization is disabled for the vcpu.
4485                  */
4486                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4487                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4488                         struct amd_iommu_pi_data pi;
4489
4490                         /* Try to enable guest_mode in IRTE */
4491                         pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4492                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4493                                                      svm->vcpu.vcpu_id);
4494                         pi.is_guest_mode = true;
4495                         pi.vcpu_data = &vcpu_info;
4496                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4497
4498                         /**
4499                          * Here, we successfully setting up vcpu affinity in
4500                          * IOMMU guest mode. Now, we need to store the posted
4501                          * interrupt information in a per-vcpu ir_list so that
4502                          * we can reference to them directly when we update vcpu
4503                          * scheduling information in IOMMU irte.
4504                          */
4505                         if (!ret && pi.is_guest_mode)
4506                                 svm_ir_list_add(svm, &pi);
4507                 } else {
4508                         /* Use legacy mode in IRTE */
4509                         struct amd_iommu_pi_data pi;
4510
4511                         /**
4512                          * Here, pi is used to:
4513                          * - Tell IOMMU to use legacy mode for this interrupt.
4514                          * - Retrieve ga_tag of prior interrupt remapping data.
4515                          */
4516                         pi.is_guest_mode = false;
4517                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4518
4519                         /**
4520                          * Check if the posted interrupt was previously
4521                          * setup with the guest_mode by checking if the ga_tag
4522                          * was cached. If so, we need to clean up the per-vcpu
4523                          * ir_list.
4524                          */
4525                         if (!ret && pi.prev_ga_tag) {
4526                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4527                                 struct kvm_vcpu *vcpu;
4528
4529                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4530                                 if (vcpu)
4531                                         svm_ir_list_del(to_svm(vcpu), &pi);
4532                         }
4533                 }
4534
4535                 if (!ret && svm) {
4536                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4537                                                  host_irq, e->gsi,
4538                                                  vcpu_info.vector,
4539                                                  vcpu_info.pi_desc_addr, set);
4540                 }
4541
4542                 if (ret < 0) {
4543                         pr_err("%s: failed to update PI IRTE\n", __func__);
4544                         goto out;
4545                 }
4546         }
4547
4548         ret = 0;
4549 out:
4550         srcu_read_unlock(&kvm->irq_srcu, idx);
4551         return ret;
4552 }
4553
4554 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4555 {
4556         struct vcpu_svm *svm = to_svm(vcpu);
4557         struct vmcb *vmcb = svm->vmcb;
4558         int ret;
4559         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4560               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4561         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4562
4563         return ret;
4564 }
4565
4566 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4567 {
4568         struct vcpu_svm *svm = to_svm(vcpu);
4569
4570         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4571 }
4572
4573 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4574 {
4575         struct vcpu_svm *svm = to_svm(vcpu);
4576
4577         if (masked) {
4578                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4579                 set_intercept(svm, INTERCEPT_IRET);
4580         } else {
4581                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4582                 clr_intercept(svm, INTERCEPT_IRET);
4583         }
4584 }
4585
4586 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4587 {
4588         struct vcpu_svm *svm = to_svm(vcpu);
4589         struct vmcb *vmcb = svm->vmcb;
4590         int ret;
4591
4592         if (!gif_set(svm) ||
4593              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4594                 return 0;
4595
4596         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4597
4598         if (is_guest_mode(vcpu))
4599                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4600
4601         return ret;
4602 }
4603
4604 static void enable_irq_window(struct kvm_vcpu *vcpu)
4605 {
4606         struct vcpu_svm *svm = to_svm(vcpu);
4607
4608         if (kvm_vcpu_apicv_active(vcpu))
4609                 return;
4610
4611         /*
4612          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4613          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4614          * get that intercept, this function will be called again though and
4615          * we'll get the vintr intercept.
4616          */
4617         if (gif_set(svm) && nested_svm_intr(svm)) {
4618                 svm_set_vintr(svm);
4619                 svm_inject_irq(svm, 0x0);
4620         }
4621 }
4622
4623 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4624 {
4625         struct vcpu_svm *svm = to_svm(vcpu);
4626
4627         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4628             == HF_NMI_MASK)
4629                 return; /* IRET will cause a vm exit */
4630
4631         /*
4632          * Something prevents NMI from been injected. Single step over possible
4633          * problem (IRET or exception injection or interrupt shadow)
4634          */
4635         svm->nmi_singlestep = true;
4636         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4637 }
4638
4639 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4640 {
4641         return 0;
4642 }
4643
4644 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4645 {
4646         struct vcpu_svm *svm = to_svm(vcpu);
4647
4648         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4649                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4650         else
4651                 svm->asid_generation--;
4652 }
4653
4654 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4655 {
4656 }
4657
4658 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4659 {
4660         struct vcpu_svm *svm = to_svm(vcpu);
4661
4662         if (svm_nested_virtualize_tpr(vcpu))
4663                 return;
4664
4665         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4666                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4667                 kvm_set_cr8(vcpu, cr8);
4668         }
4669 }
4670
4671 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4672 {
4673         struct vcpu_svm *svm = to_svm(vcpu);
4674         u64 cr8;
4675
4676         if (svm_nested_virtualize_tpr(vcpu) ||
4677             kvm_vcpu_apicv_active(vcpu))
4678                 return;
4679
4680         cr8 = kvm_get_cr8(vcpu);
4681         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4682         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4683 }
4684
4685 static void svm_complete_interrupts(struct vcpu_svm *svm)
4686 {
4687         u8 vector;
4688         int type;
4689         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4690         unsigned int3_injected = svm->int3_injected;
4691
4692         svm->int3_injected = 0;
4693
4694         /*
4695          * If we've made progress since setting HF_IRET_MASK, we've
4696          * executed an IRET and can allow NMI injection.
4697          */
4698         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4699             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4700                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4701                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4702         }
4703
4704         svm->vcpu.arch.nmi_injected = false;
4705         kvm_clear_exception_queue(&svm->vcpu);
4706         kvm_clear_interrupt_queue(&svm->vcpu);
4707
4708         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4709                 return;
4710
4711         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4712
4713         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4714         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4715
4716         switch (type) {
4717         case SVM_EXITINTINFO_TYPE_NMI:
4718                 svm->vcpu.arch.nmi_injected = true;
4719                 break;
4720         case SVM_EXITINTINFO_TYPE_EXEPT:
4721                 /*
4722                  * In case of software exceptions, do not reinject the vector,
4723                  * but re-execute the instruction instead. Rewind RIP first
4724                  * if we emulated INT3 before.
4725                  */
4726                 if (kvm_exception_is_soft(vector)) {
4727                         if (vector == BP_VECTOR && int3_injected &&
4728                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4729                                 kvm_rip_write(&svm->vcpu,
4730                                               kvm_rip_read(&svm->vcpu) -
4731                                               int3_injected);
4732                         break;
4733                 }
4734                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4735                         u32 err = svm->vmcb->control.exit_int_info_err;
4736                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4737
4738                 } else
4739                         kvm_requeue_exception(&svm->vcpu, vector);
4740                 break;
4741         case SVM_EXITINTINFO_TYPE_INTR:
4742                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4743                 break;
4744         default:
4745                 break;
4746         }
4747 }
4748
4749 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4750 {
4751         struct vcpu_svm *svm = to_svm(vcpu);
4752         struct vmcb_control_area *control = &svm->vmcb->control;
4753
4754         control->exit_int_info = control->event_inj;
4755         control->exit_int_info_err = control->event_inj_err;
4756         control->event_inj = 0;
4757         svm_complete_interrupts(svm);
4758 }
4759
4760 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4761 {
4762         struct vcpu_svm *svm = to_svm(vcpu);
4763
4764         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4765         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4766         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4767
4768         /*
4769          * A vmexit emulation is required before the vcpu can be executed
4770          * again.
4771          */
4772         if (unlikely(svm->nested.exit_required))
4773                 return;
4774
4775         pre_svm_run(svm);
4776
4777         sync_lapic_to_cr8(vcpu);
4778
4779         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4780
4781         clgi();
4782
4783         local_irq_enable();
4784
4785         asm volatile (
4786                 "push %%" _ASM_BP "; \n\t"
4787                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4788                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4789                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4790                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4791                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4792                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4793 #ifdef CONFIG_X86_64
4794                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4795                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4796                 "mov %c[r10](%[svm]), %%r10 \n\t"
4797                 "mov %c[r11](%[svm]), %%r11 \n\t"
4798                 "mov %c[r12](%[svm]), %%r12 \n\t"
4799                 "mov %c[r13](%[svm]), %%r13 \n\t"
4800                 "mov %c[r14](%[svm]), %%r14 \n\t"
4801                 "mov %c[r15](%[svm]), %%r15 \n\t"
4802 #endif
4803
4804                 /* Enter guest mode */
4805                 "push %%" _ASM_AX " \n\t"
4806                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4807                 __ex(SVM_VMLOAD) "\n\t"
4808                 __ex(SVM_VMRUN) "\n\t"
4809                 __ex(SVM_VMSAVE) "\n\t"
4810                 "pop %%" _ASM_AX " \n\t"
4811
4812                 /* Save guest registers, load host registers */
4813                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4814                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4815                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4816                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4817                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4818                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4819 #ifdef CONFIG_X86_64
4820                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4821                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4822                 "mov %%r10, %c[r10](%[svm]) \n\t"
4823                 "mov %%r11, %c[r11](%[svm]) \n\t"
4824                 "mov %%r12, %c[r12](%[svm]) \n\t"
4825                 "mov %%r13, %c[r13](%[svm]) \n\t"
4826                 "mov %%r14, %c[r14](%[svm]) \n\t"
4827                 "mov %%r15, %c[r15](%[svm]) \n\t"
4828 #endif
4829                 "pop %%" _ASM_BP
4830                 :
4831                 : [svm]"a"(svm),
4832                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4833                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4834                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4835                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4836                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4837                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4838                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4839 #ifdef CONFIG_X86_64
4840                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4841                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4842                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4843                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4844                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4845                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4846                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4847                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4848 #endif
4849                 : "cc", "memory"
4850 #ifdef CONFIG_X86_64
4851                 , "rbx", "rcx", "rdx", "rsi", "rdi"
4852                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4853 #else
4854                 , "ebx", "ecx", "edx", "esi", "edi"
4855 #endif
4856                 );
4857
4858 #ifdef CONFIG_X86_64
4859         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4860 #else
4861         loadsegment(fs, svm->host.fs);
4862 #ifndef CONFIG_X86_32_LAZY_GS
4863         loadsegment(gs, svm->host.gs);
4864 #endif
4865 #endif
4866
4867         reload_tss(vcpu);
4868
4869         local_irq_disable();
4870
4871         vcpu->arch.cr2 = svm->vmcb->save.cr2;
4872         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4873         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4874         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4875
4876         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4877                 kvm_before_handle_nmi(&svm->vcpu);
4878
4879         stgi();
4880
4881         /* Any pending NMI will happen here */
4882
4883         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4884                 kvm_after_handle_nmi(&svm->vcpu);
4885
4886         sync_cr8_to_lapic(vcpu);
4887
4888         svm->next_rip = 0;
4889
4890         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4891
4892         /* if exit due to PF check for async PF */
4893         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4894                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4895
4896         if (npt_enabled) {
4897                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4898                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4899         }
4900
4901         /*
4902          * We need to handle MC intercepts here before the vcpu has a chance to
4903          * change the physical cpu
4904          */
4905         if (unlikely(svm->vmcb->control.exit_code ==
4906                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4907                 svm_handle_mce(svm);
4908
4909         mark_all_clean(svm->vmcb);
4910 }
4911
4912 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4913 {
4914         struct vcpu_svm *svm = to_svm(vcpu);
4915
4916         svm->vmcb->save.cr3 = root;
4917         mark_dirty(svm->vmcb, VMCB_CR);
4918         svm_flush_tlb(vcpu);
4919 }
4920
4921 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4922 {
4923         struct vcpu_svm *svm = to_svm(vcpu);
4924
4925         svm->vmcb->control.nested_cr3 = root;
4926         mark_dirty(svm->vmcb, VMCB_NPT);
4927
4928         /* Also sync guest cr3 here in case we live migrate */
4929         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4930         mark_dirty(svm->vmcb, VMCB_CR);
4931
4932         svm_flush_tlb(vcpu);
4933 }
4934
4935 static int is_disabled(void)
4936 {
4937         u64 vm_cr;
4938
4939         rdmsrl(MSR_VM_CR, vm_cr);
4940         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4941                 return 1;
4942
4943         return 0;
4944 }
4945
4946 static void
4947 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4948 {
4949         /*
4950          * Patch in the VMMCALL instruction:
4951          */
4952         hypercall[0] = 0x0f;
4953         hypercall[1] = 0x01;
4954         hypercall[2] = 0xd9;
4955 }
4956
4957 static void svm_check_processor_compat(void *rtn)
4958 {
4959         *(int *)rtn = 0;
4960 }
4961
4962 static bool svm_cpu_has_accelerated_tpr(void)
4963 {
4964         return false;
4965 }
4966
4967 static bool svm_has_high_real_mode_segbase(void)
4968 {
4969         return true;
4970 }
4971
4972 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4973 {
4974         return 0;
4975 }
4976
4977 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4978 {
4979         struct vcpu_svm *svm = to_svm(vcpu);
4980         struct kvm_cpuid_entry2 *entry;
4981
4982         /* Update nrips enabled cache */
4983         svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4984
4985         if (!kvm_vcpu_apicv_active(vcpu))
4986                 return;
4987
4988         entry = kvm_find_cpuid_entry(vcpu, 1, 0);
4989         if (entry)
4990                 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4991 }
4992
4993 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4994 {
4995         switch (func) {
4996         case 0x1:
4997                 if (avic)
4998                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4999                 break;
5000         case 0x80000001:
5001                 if (nested)
5002                         entry->ecx |= (1 << 2); /* Set SVM bit */
5003                 break;
5004         case 0x8000000A:
5005                 entry->eax = 1; /* SVM revision 1 */
5006                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5007                                    ASID emulation to nested SVM */
5008                 entry->ecx = 0; /* Reserved */
5009                 entry->edx = 0; /* Per default do not support any
5010                                    additional features */
5011
5012                 /* Support next_rip if host supports it */
5013                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5014                         entry->edx |= SVM_FEATURE_NRIP;
5015
5016                 /* Support NPT for the guest if enabled */
5017                 if (npt_enabled)
5018                         entry->edx |= SVM_FEATURE_NPT;
5019
5020                 break;
5021         }
5022 }
5023
5024 static int svm_get_lpage_level(void)
5025 {
5026         return PT_PDPE_LEVEL;
5027 }
5028
5029 static bool svm_rdtscp_supported(void)
5030 {
5031         return boot_cpu_has(X86_FEATURE_RDTSCP);
5032 }
5033
5034 static bool svm_invpcid_supported(void)
5035 {
5036         return false;
5037 }
5038
5039 static bool svm_mpx_supported(void)
5040 {
5041         return false;
5042 }
5043
5044 static bool svm_xsaves_supported(void)
5045 {
5046         return false;
5047 }
5048
5049 static bool svm_has_wbinvd_exit(void)
5050 {
5051         return true;
5052 }
5053
5054 #define PRE_EX(exit)  { .exit_code = (exit), \
5055                         .stage = X86_ICPT_PRE_EXCEPT, }
5056 #define POST_EX(exit) { .exit_code = (exit), \
5057                         .stage = X86_ICPT_POST_EXCEPT, }
5058 #define POST_MEM(exit) { .exit_code = (exit), \
5059                         .stage = X86_ICPT_POST_MEMACCESS, }
5060
5061 static const struct __x86_intercept {
5062         u32 exit_code;
5063         enum x86_intercept_stage stage;
5064 } x86_intercept_map[] = {
5065         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5066         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5067         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5068         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5069         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5070         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5071         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5072         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5073         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5074         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5075         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5076         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5077         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5078         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5079         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5080         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5081         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5082         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5083         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5084         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5085         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5086         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5087         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5088         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5089         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5090         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5091         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5092         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5093         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5094         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5095         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5096         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5097         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5098         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5099         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5100         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5101         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5102         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5103         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5104         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5105         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5106         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5107         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5108         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5109         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5110         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5111 };
5112
5113 #undef PRE_EX
5114 #undef POST_EX
5115 #undef POST_MEM
5116
5117 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5118                                struct x86_instruction_info *info,
5119                                enum x86_intercept_stage stage)
5120 {
5121         struct vcpu_svm *svm = to_svm(vcpu);
5122         int vmexit, ret = X86EMUL_CONTINUE;
5123         struct __x86_intercept icpt_info;
5124         struct vmcb *vmcb = svm->vmcb;
5125
5126         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5127                 goto out;
5128
5129         icpt_info = x86_intercept_map[info->intercept];
5130
5131         if (stage != icpt_info.stage)
5132                 goto out;
5133
5134         switch (icpt_info.exit_code) {
5135         case SVM_EXIT_READ_CR0:
5136                 if (info->intercept == x86_intercept_cr_read)
5137                         icpt_info.exit_code += info->modrm_reg;
5138                 break;
5139         case SVM_EXIT_WRITE_CR0: {
5140                 unsigned long cr0, val;
5141                 u64 intercept;
5142
5143                 if (info->intercept == x86_intercept_cr_write)
5144                         icpt_info.exit_code += info->modrm_reg;
5145
5146                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5147                     info->intercept == x86_intercept_clts)
5148                         break;
5149
5150                 intercept = svm->nested.intercept;
5151
5152                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5153                         break;
5154
5155                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5156                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5157
5158                 if (info->intercept == x86_intercept_lmsw) {
5159                         cr0 &= 0xfUL;
5160                         val &= 0xfUL;
5161                         /* lmsw can't clear PE - catch this here */
5162                         if (cr0 & X86_CR0_PE)
5163                                 val |= X86_CR0_PE;
5164                 }
5165
5166                 if (cr0 ^ val)
5167                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5168
5169                 break;
5170         }
5171         case SVM_EXIT_READ_DR0:
5172         case SVM_EXIT_WRITE_DR0:
5173                 icpt_info.exit_code += info->modrm_reg;
5174                 break;
5175         case SVM_EXIT_MSR:
5176                 if (info->intercept == x86_intercept_wrmsr)
5177                         vmcb->control.exit_info_1 = 1;
5178                 else
5179                         vmcb->control.exit_info_1 = 0;
5180                 break;
5181         case SVM_EXIT_PAUSE:
5182                 /*
5183                  * We get this for NOP only, but pause
5184                  * is rep not, check this here
5185                  */
5186                 if (info->rep_prefix != REPE_PREFIX)
5187                         goto out;
5188         case SVM_EXIT_IOIO: {
5189                 u64 exit_info;
5190                 u32 bytes;
5191
5192                 if (info->intercept == x86_intercept_in ||
5193                     info->intercept == x86_intercept_ins) {
5194                         exit_info = ((info->src_val & 0xffff) << 16) |
5195                                 SVM_IOIO_TYPE_MASK;
5196                         bytes = info->dst_bytes;
5197                 } else {
5198                         exit_info = (info->dst_val & 0xffff) << 16;
5199                         bytes = info->src_bytes;
5200                 }
5201
5202                 if (info->intercept == x86_intercept_outs ||
5203                     info->intercept == x86_intercept_ins)
5204                         exit_info |= SVM_IOIO_STR_MASK;
5205
5206                 if (info->rep_prefix)
5207                         exit_info |= SVM_IOIO_REP_MASK;
5208
5209                 bytes = min(bytes, 4u);
5210
5211                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5212
5213                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5214
5215                 vmcb->control.exit_info_1 = exit_info;
5216                 vmcb->control.exit_info_2 = info->next_rip;
5217
5218                 break;
5219         }
5220         default:
5221                 break;
5222         }
5223
5224         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5225         if (static_cpu_has(X86_FEATURE_NRIPS))
5226                 vmcb->control.next_rip  = info->next_rip;
5227         vmcb->control.exit_code = icpt_info.exit_code;
5228         vmexit = nested_svm_exit_handled(svm);
5229
5230         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5231                                            : X86EMUL_CONTINUE;
5232
5233 out:
5234         return ret;
5235 }
5236
5237 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5238 {
5239         local_irq_enable();
5240         /*
5241          * We must have an instruction with interrupts enabled, so
5242          * the timer interrupt isn't delayed by the interrupt shadow.
5243          */
5244         asm("nop");
5245         local_irq_disable();
5246 }
5247
5248 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5249 {
5250 }
5251
5252 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5253 {
5254         if (avic_handle_apic_id_update(vcpu) != 0)
5255                 return;
5256         if (avic_handle_dfr_update(vcpu) != 0)
5257                 return;
5258         avic_handle_ldr_update(vcpu);
5259 }
5260
5261 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5262 {
5263         /* [63:9] are reserved. */
5264         vcpu->arch.mcg_cap &= 0x1ff;
5265 }
5266
5267 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5268         .cpu_has_kvm_support = has_svm,
5269         .disabled_by_bios = is_disabled,
5270         .hardware_setup = svm_hardware_setup,
5271         .hardware_unsetup = svm_hardware_unsetup,
5272         .check_processor_compatibility = svm_check_processor_compat,
5273         .hardware_enable = svm_hardware_enable,
5274         .hardware_disable = svm_hardware_disable,
5275         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5276         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5277
5278         .vcpu_create = svm_create_vcpu,
5279         .vcpu_free = svm_free_vcpu,
5280         .vcpu_reset = svm_vcpu_reset,
5281
5282         .vm_init = avic_vm_init,
5283         .vm_destroy = avic_vm_destroy,
5284
5285         .prepare_guest_switch = svm_prepare_guest_switch,
5286         .vcpu_load = svm_vcpu_load,
5287         .vcpu_put = svm_vcpu_put,
5288         .vcpu_blocking = svm_vcpu_blocking,
5289         .vcpu_unblocking = svm_vcpu_unblocking,
5290
5291         .update_bp_intercept = update_bp_intercept,
5292         .get_msr = svm_get_msr,
5293         .set_msr = svm_set_msr,
5294         .get_segment_base = svm_get_segment_base,
5295         .get_segment = svm_get_segment,
5296         .set_segment = svm_set_segment,
5297         .get_cpl = svm_get_cpl,
5298         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5299         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5300         .decache_cr3 = svm_decache_cr3,
5301         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5302         .set_cr0 = svm_set_cr0,
5303         .set_cr3 = svm_set_cr3,
5304         .set_cr4 = svm_set_cr4,
5305         .set_efer = svm_set_efer,
5306         .get_idt = svm_get_idt,
5307         .set_idt = svm_set_idt,
5308         .get_gdt = svm_get_gdt,
5309         .set_gdt = svm_set_gdt,
5310         .get_dr6 = svm_get_dr6,
5311         .set_dr6 = svm_set_dr6,
5312         .set_dr7 = svm_set_dr7,
5313         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5314         .cache_reg = svm_cache_reg,
5315         .get_rflags = svm_get_rflags,
5316         .set_rflags = svm_set_rflags,
5317
5318         .get_pkru = svm_get_pkru,
5319
5320         .tlb_flush = svm_flush_tlb,
5321
5322         .run = svm_vcpu_run,
5323         .handle_exit = handle_exit,
5324         .skip_emulated_instruction = skip_emulated_instruction,
5325         .set_interrupt_shadow = svm_set_interrupt_shadow,
5326         .get_interrupt_shadow = svm_get_interrupt_shadow,
5327         .patch_hypercall = svm_patch_hypercall,
5328         .set_irq = svm_set_irq,
5329         .set_nmi = svm_inject_nmi,
5330         .queue_exception = svm_queue_exception,
5331         .cancel_injection = svm_cancel_injection,
5332         .interrupt_allowed = svm_interrupt_allowed,
5333         .nmi_allowed = svm_nmi_allowed,
5334         .get_nmi_mask = svm_get_nmi_mask,
5335         .set_nmi_mask = svm_set_nmi_mask,
5336         .enable_nmi_window = enable_nmi_window,
5337         .enable_irq_window = enable_irq_window,
5338         .update_cr8_intercept = update_cr8_intercept,
5339         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5340         .get_enable_apicv = svm_get_enable_apicv,
5341         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5342         .load_eoi_exitmap = svm_load_eoi_exitmap,
5343         .hwapic_irr_update = svm_hwapic_irr_update,
5344         .hwapic_isr_update = svm_hwapic_isr_update,
5345         .apicv_post_state_restore = avic_post_state_restore,
5346
5347         .set_tss_addr = svm_set_tss_addr,
5348         .get_tdp_level = get_npt_level,
5349         .get_mt_mask = svm_get_mt_mask,
5350
5351         .get_exit_info = svm_get_exit_info,
5352
5353         .get_lpage_level = svm_get_lpage_level,
5354
5355         .cpuid_update = svm_cpuid_update,
5356
5357         .rdtscp_supported = svm_rdtscp_supported,
5358         .invpcid_supported = svm_invpcid_supported,
5359         .mpx_supported = svm_mpx_supported,
5360         .xsaves_supported = svm_xsaves_supported,
5361
5362         .set_supported_cpuid = svm_set_supported_cpuid,
5363
5364         .has_wbinvd_exit = svm_has_wbinvd_exit,
5365
5366         .write_tsc_offset = svm_write_tsc_offset,
5367
5368         .set_tdp_cr3 = set_tdp_cr3,
5369
5370         .check_intercept = svm_check_intercept,
5371         .handle_external_intr = svm_handle_external_intr,
5372
5373         .sched_in = svm_sched_in,
5374
5375         .pmu_ops = &amd_pmu_ops,
5376         .deliver_posted_interrupt = svm_deliver_avic_intr,
5377         .update_pi_irte = svm_update_pi_irte,
5378         .setup_mce = svm_setup_mce,
5379 };
5380
5381 static int __init svm_init(void)
5382 {
5383         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5384                         __alignof__(struct vcpu_svm), THIS_MODULE);
5385 }
5386
5387 static void __exit svm_exit(void)
5388 {
5389         kvm_exit();
5390 }
5391
5392 module_init(svm_init)
5393 module_exit(svm_exit)