2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
46 #include <asm/cmpxchg.h>
49 #include <asm/kvm_page_track.h>
53 * When setting this variable to true it enables Two-Dimensional-Paging
54 * where the hardware walks 2 page tables:
55 * 1. the guest-virtual to guest-physical
56 * 2. while doing 1. it walks guest-physical to host-physical
57 * If the hardware supports that we don't need to do shadow paging.
59 bool tdp_enabled = false;
63 AUDIT_POST_PAGE_FAULT,
74 module_param(dbg, bool, 0644);
76 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
78 #define MMU_WARN_ON(x) WARN_ON(x)
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
82 #define MMU_WARN_ON(x) do { } while (0)
85 #define PTE_PREFETCH_NUM 8
87 #define PT_FIRST_AVAIL_BITS_SHIFT 10
88 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
90 #define PT64_LEVEL_BITS 9
92 #define PT64_LEVEL_SHIFT(level) \
93 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
95 #define PT64_INDEX(address, level)\
96 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
99 #define PT32_LEVEL_BITS 10
101 #define PT32_LEVEL_SHIFT(level) \
102 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
104 #define PT32_LVL_OFFSET_MASK(level) \
105 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
106 * PT32_LEVEL_BITS))) - 1))
108 #define PT32_INDEX(address, level)\
109 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
112 #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
113 #define PT64_DIR_BASE_ADDR_MASK \
114 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
115 #define PT64_LVL_ADDR_MASK(level) \
116 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
117 * PT64_LEVEL_BITS))) - 1))
118 #define PT64_LVL_OFFSET_MASK(level) \
119 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
120 * PT64_LEVEL_BITS))) - 1))
122 #define PT32_BASE_ADDR_MASK PAGE_MASK
123 #define PT32_DIR_BASE_ADDR_MASK \
124 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
125 #define PT32_LVL_ADDR_MASK(level) \
126 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT32_LEVEL_BITS))) - 1))
129 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
130 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
132 #define ACC_EXEC_MASK 1
133 #define ACC_WRITE_MASK PT_WRITABLE_MASK
134 #define ACC_USER_MASK PT_USER_MASK
135 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
137 /* The mask for the R/X bits in EPT PTEs */
138 #define PT64_EPT_READABLE_MASK 0x1ull
139 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
141 #include <trace/events/kvm.h>
143 #define CREATE_TRACE_POINTS
144 #include "mmutrace.h"
146 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
147 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
149 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
151 /* make pte_list_desc fit well in cache line */
152 #define PTE_LIST_EXT 3
155 * Return values of handle_mmio_page_fault and mmu.page_fault:
156 * RET_PF_RETRY: let CPU fault again on the address.
157 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
159 * For handle_mmio_page_fault only:
160 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
168 struct pte_list_desc {
169 u64 *sptes[PTE_LIST_EXT];
170 struct pte_list_desc *more;
173 struct kvm_shadow_walk_iterator {
181 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
182 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
183 shadow_walk_okay(&(_walker)); \
184 shadow_walk_next(&(_walker)))
186 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
187 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
188 shadow_walk_okay(&(_walker)) && \
189 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
190 __shadow_walk_next(&(_walker), spte))
192 static struct kmem_cache *pte_list_desc_cache;
193 static struct kmem_cache *mmu_page_header_cache;
194 static struct percpu_counter kvm_total_used_mmu_pages;
196 static u64 __read_mostly shadow_nx_mask;
197 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
198 static u64 __read_mostly shadow_user_mask;
199 static u64 __read_mostly shadow_accessed_mask;
200 static u64 __read_mostly shadow_dirty_mask;
201 static u64 __read_mostly shadow_mmio_mask;
202 static u64 __read_mostly shadow_mmio_value;
203 static u64 __read_mostly shadow_present_mask;
204 static u64 __read_mostly shadow_me_mask;
207 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
208 * Non-present SPTEs with shadow_acc_track_value set are in place for access
211 static u64 __read_mostly shadow_acc_track_mask;
212 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
215 * The mask/shift to use for saving the original R/X bits when marking the PTE
216 * as not-present for access tracking purposes. We do not save the W bit as the
217 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
218 * restored only when a write is attempted to the page.
220 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
221 PT64_EPT_EXECUTABLE_MASK;
222 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
224 static void mmu_spte_set(u64 *sptep, u64 spte);
226 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value)
228 BUG_ON((mmio_mask & mmio_value) != mmio_value);
229 shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK;
230 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
232 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
234 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
236 return sp->role.ad_disabled;
239 static inline bool spte_ad_enabled(u64 spte)
241 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
242 return !(spte & shadow_acc_track_value);
245 static inline u64 spte_shadow_accessed_mask(u64 spte)
247 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
248 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
251 static inline u64 spte_shadow_dirty_mask(u64 spte)
253 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
254 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
257 static inline bool is_access_track_spte(u64 spte)
259 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
263 * the low bit of the generation number is always presumed to be zero.
264 * This disables mmio caching during memslot updates. The concept is
265 * similar to a seqcount but instead of retrying the access we just punt
266 * and ignore the cache.
268 * spte bits 3-11 are used as bits 1-9 of the generation number,
269 * the bits 52-61 are used as bits 10-19 of the generation number.
271 #define MMIO_SPTE_GEN_LOW_SHIFT 2
272 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
274 #define MMIO_GEN_SHIFT 20
275 #define MMIO_GEN_LOW_SHIFT 10
276 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
277 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
279 static u64 generation_mmio_spte_mask(unsigned int gen)
283 WARN_ON(gen & ~MMIO_GEN_MASK);
285 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
286 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
290 static unsigned int get_mmio_spte_generation(u64 spte)
294 spte &= ~shadow_mmio_mask;
296 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
297 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
301 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
303 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
306 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
309 unsigned int gen = kvm_current_mmio_generation(vcpu);
310 u64 mask = generation_mmio_spte_mask(gen);
312 access &= ACC_WRITE_MASK | ACC_USER_MASK;
313 mask |= shadow_mmio_value | access | gfn << PAGE_SHIFT;
315 trace_mark_mmio_spte(sptep, gfn, access, gen);
316 mmu_spte_set(sptep, mask);
319 static bool is_mmio_spte(u64 spte)
321 return (spte & shadow_mmio_mask) == shadow_mmio_value;
324 static gfn_t get_mmio_spte_gfn(u64 spte)
326 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
327 return (spte & ~mask) >> PAGE_SHIFT;
330 static unsigned get_mmio_spte_access(u64 spte)
332 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
333 return (spte & ~mask) & ~PAGE_MASK;
336 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
337 kvm_pfn_t pfn, unsigned access)
339 if (unlikely(is_noslot_pfn(pfn))) {
340 mark_mmio_spte(vcpu, sptep, gfn, access);
347 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
349 unsigned int kvm_gen, spte_gen;
351 kvm_gen = kvm_current_mmio_generation(vcpu);
352 spte_gen = get_mmio_spte_generation(spte);
354 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
355 return likely(kvm_gen == spte_gen);
359 * Sets the shadow PTE masks used by the MMU.
362 * - Setting either @accessed_mask or @dirty_mask requires setting both
363 * - At least one of @accessed_mask or @acc_track_mask must be set
365 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
366 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
367 u64 acc_track_mask, u64 me_mask)
369 BUG_ON(!dirty_mask != !accessed_mask);
370 BUG_ON(!accessed_mask && !acc_track_mask);
371 BUG_ON(acc_track_mask & shadow_acc_track_value);
373 shadow_user_mask = user_mask;
374 shadow_accessed_mask = accessed_mask;
375 shadow_dirty_mask = dirty_mask;
376 shadow_nx_mask = nx_mask;
377 shadow_x_mask = x_mask;
378 shadow_present_mask = p_mask;
379 shadow_acc_track_mask = acc_track_mask;
380 shadow_me_mask = me_mask;
382 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
384 static void kvm_mmu_clear_all_pte_masks(void)
386 shadow_user_mask = 0;
387 shadow_accessed_mask = 0;
388 shadow_dirty_mask = 0;
391 shadow_mmio_mask = 0;
392 shadow_present_mask = 0;
393 shadow_acc_track_mask = 0;
396 static int is_cpuid_PSE36(void)
401 static int is_nx(struct kvm_vcpu *vcpu)
403 return vcpu->arch.efer & EFER_NX;
406 static int is_shadow_present_pte(u64 pte)
408 return (pte != 0) && !is_mmio_spte(pte);
411 static int is_large_pte(u64 pte)
413 return pte & PT_PAGE_SIZE_MASK;
416 static int is_last_spte(u64 pte, int level)
418 if (level == PT_PAGE_TABLE_LEVEL)
420 if (is_large_pte(pte))
425 static bool is_executable_pte(u64 spte)
427 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
430 static kvm_pfn_t spte_to_pfn(u64 pte)
432 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
435 static gfn_t pse36_gfn_delta(u32 gpte)
437 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
439 return (gpte & PT32_DIR_PSE36_MASK) << shift;
443 static void __set_spte(u64 *sptep, u64 spte)
445 WRITE_ONCE(*sptep, spte);
448 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
450 WRITE_ONCE(*sptep, spte);
453 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
455 return xchg(sptep, spte);
458 static u64 __get_spte_lockless(u64 *sptep)
460 return READ_ONCE(*sptep);
471 static void count_spte_clear(u64 *sptep, u64 spte)
473 struct kvm_mmu_page *sp = page_header(__pa(sptep));
475 if (is_shadow_present_pte(spte))
478 /* Ensure the spte is completely set before we increase the count */
480 sp->clear_spte_count++;
483 static void __set_spte(u64 *sptep, u64 spte)
485 union split_spte *ssptep, sspte;
487 ssptep = (union split_spte *)sptep;
488 sspte = (union split_spte)spte;
490 ssptep->spte_high = sspte.spte_high;
493 * If we map the spte from nonpresent to present, We should store
494 * the high bits firstly, then set present bit, so cpu can not
495 * fetch this spte while we are setting the spte.
499 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
502 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
504 union split_spte *ssptep, sspte;
506 ssptep = (union split_spte *)sptep;
507 sspte = (union split_spte)spte;
509 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
512 * If we map the spte from present to nonpresent, we should clear
513 * present bit firstly to avoid vcpu fetch the old high bits.
517 ssptep->spte_high = sspte.spte_high;
518 count_spte_clear(sptep, spte);
521 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
523 union split_spte *ssptep, sspte, orig;
525 ssptep = (union split_spte *)sptep;
526 sspte = (union split_spte)spte;
528 /* xchg acts as a barrier before the setting of the high bits */
529 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
530 orig.spte_high = ssptep->spte_high;
531 ssptep->spte_high = sspte.spte_high;
532 count_spte_clear(sptep, spte);
538 * The idea using the light way get the spte on x86_32 guest is from
539 * gup_get_pte(arch/x86/mm/gup.c).
541 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
542 * coalesces them and we are running out of the MMU lock. Therefore
543 * we need to protect against in-progress updates of the spte.
545 * Reading the spte while an update is in progress may get the old value
546 * for the high part of the spte. The race is fine for a present->non-present
547 * change (because the high part of the spte is ignored for non-present spte),
548 * but for a present->present change we must reread the spte.
550 * All such changes are done in two steps (present->non-present and
551 * non-present->present), hence it is enough to count the number of
552 * present->non-present updates: if it changed while reading the spte,
553 * we might have hit the race. This is done using clear_spte_count.
555 static u64 __get_spte_lockless(u64 *sptep)
557 struct kvm_mmu_page *sp = page_header(__pa(sptep));
558 union split_spte spte, *orig = (union split_spte *)sptep;
562 count = sp->clear_spte_count;
565 spte.spte_low = orig->spte_low;
568 spte.spte_high = orig->spte_high;
571 if (unlikely(spte.spte_low != orig->spte_low ||
572 count != sp->clear_spte_count))
579 static bool spte_can_locklessly_be_made_writable(u64 spte)
581 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
582 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
585 static bool spte_has_volatile_bits(u64 spte)
587 if (!is_shadow_present_pte(spte))
591 * Always atomically update spte if it can be updated
592 * out of mmu-lock, it can ensure dirty bit is not lost,
593 * also, it can help us to get a stable is_writable_pte()
594 * to ensure tlb flush is not missed.
596 if (spte_can_locklessly_be_made_writable(spte) ||
597 is_access_track_spte(spte))
600 if (spte_ad_enabled(spte)) {
601 if ((spte & shadow_accessed_mask) == 0 ||
602 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
609 static bool is_accessed_spte(u64 spte)
611 u64 accessed_mask = spte_shadow_accessed_mask(spte);
613 return accessed_mask ? spte & accessed_mask
614 : !is_access_track_spte(spte);
617 static bool is_dirty_spte(u64 spte)
619 u64 dirty_mask = spte_shadow_dirty_mask(spte);
621 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
624 /* Rules for using mmu_spte_set:
625 * Set the sptep from nonpresent to present.
626 * Note: the sptep being assigned *must* be either not present
627 * or in a state where the hardware will not attempt to update
630 static void mmu_spte_set(u64 *sptep, u64 new_spte)
632 WARN_ON(is_shadow_present_pte(*sptep));
633 __set_spte(sptep, new_spte);
637 * Update the SPTE (excluding the PFN), but do not track changes in its
638 * accessed/dirty status.
640 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
642 u64 old_spte = *sptep;
644 WARN_ON(!is_shadow_present_pte(new_spte));
646 if (!is_shadow_present_pte(old_spte)) {
647 mmu_spte_set(sptep, new_spte);
651 if (!spte_has_volatile_bits(old_spte))
652 __update_clear_spte_fast(sptep, new_spte);
654 old_spte = __update_clear_spte_slow(sptep, new_spte);
656 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
661 /* Rules for using mmu_spte_update:
662 * Update the state bits, it means the mapped pfn is not changed.
664 * Whenever we overwrite a writable spte with a read-only one we
665 * should flush remote TLBs. Otherwise rmap_write_protect
666 * will find a read-only spte, even though the writable spte
667 * might be cached on a CPU's TLB, the return value indicates this
670 * Returns true if the TLB needs to be flushed
672 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
675 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
677 if (!is_shadow_present_pte(old_spte))
681 * For the spte updated out of mmu-lock is safe, since
682 * we always atomically update it, see the comments in
683 * spte_has_volatile_bits().
685 if (spte_can_locklessly_be_made_writable(old_spte) &&
686 !is_writable_pte(new_spte))
690 * Flush TLB when accessed/dirty states are changed in the page tables,
691 * to guarantee consistency between TLB and page tables.
694 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
696 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
699 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
701 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
708 * Rules for using mmu_spte_clear_track_bits:
709 * It sets the sptep from present to nonpresent, and track the
710 * state bits, it is used to clear the last level sptep.
711 * Returns non-zero if the PTE was previously valid.
713 static int mmu_spte_clear_track_bits(u64 *sptep)
716 u64 old_spte = *sptep;
718 if (!spte_has_volatile_bits(old_spte))
719 __update_clear_spte_fast(sptep, 0ull);
721 old_spte = __update_clear_spte_slow(sptep, 0ull);
723 if (!is_shadow_present_pte(old_spte))
726 pfn = spte_to_pfn(old_spte);
729 * KVM does not hold the refcount of the page used by
730 * kvm mmu, before reclaiming the page, we should
731 * unmap it from mmu first.
733 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
735 if (is_accessed_spte(old_spte))
736 kvm_set_pfn_accessed(pfn);
738 if (is_dirty_spte(old_spte))
739 kvm_set_pfn_dirty(pfn);
745 * Rules for using mmu_spte_clear_no_track:
746 * Directly clear spte without caring the state bits of sptep,
747 * it is used to set the upper level spte.
749 static void mmu_spte_clear_no_track(u64 *sptep)
751 __update_clear_spte_fast(sptep, 0ull);
754 static u64 mmu_spte_get_lockless(u64 *sptep)
756 return __get_spte_lockless(sptep);
759 static u64 mark_spte_for_access_track(u64 spte)
761 if (spte_ad_enabled(spte))
762 return spte & ~shadow_accessed_mask;
764 if (is_access_track_spte(spte))
768 * Making an Access Tracking PTE will result in removal of write access
769 * from the PTE. So, verify that we will be able to restore the write
770 * access in the fast page fault path later on.
772 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
773 !spte_can_locklessly_be_made_writable(spte),
774 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
776 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
777 shadow_acc_track_saved_bits_shift),
778 "kvm: Access Tracking saved bit locations are not zero\n");
780 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
781 shadow_acc_track_saved_bits_shift;
782 spte &= ~shadow_acc_track_mask;
787 /* Restore an acc-track PTE back to a regular PTE */
788 static u64 restore_acc_track_spte(u64 spte)
791 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
792 & shadow_acc_track_saved_bits_mask;
794 WARN_ON_ONCE(spte_ad_enabled(spte));
795 WARN_ON_ONCE(!is_access_track_spte(spte));
797 new_spte &= ~shadow_acc_track_mask;
798 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
799 shadow_acc_track_saved_bits_shift);
800 new_spte |= saved_bits;
805 /* Returns the Accessed status of the PTE and resets it at the same time. */
806 static bool mmu_spte_age(u64 *sptep)
808 u64 spte = mmu_spte_get_lockless(sptep);
810 if (!is_accessed_spte(spte))
813 if (spte_ad_enabled(spte)) {
814 clear_bit((ffs(shadow_accessed_mask) - 1),
815 (unsigned long *)sptep);
818 * Capture the dirty status of the page, so that it doesn't get
819 * lost when the SPTE is marked for access tracking.
821 if (is_writable_pte(spte))
822 kvm_set_pfn_dirty(spte_to_pfn(spte));
824 spte = mark_spte_for_access_track(spte);
825 mmu_spte_update_no_track(sptep, spte);
831 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
834 * Prevent page table teardown by making any free-er wait during
835 * kvm_flush_remote_tlbs() IPI to all active vcpus.
840 * Make sure a following spte read is not reordered ahead of the write
843 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
846 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
849 * Make sure the write to vcpu->mode is not reordered in front of
850 * reads to sptes. If it does, kvm_commit_zap_page() can see us
851 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
853 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
857 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
858 struct kmem_cache *base_cache, int min)
862 if (cache->nobjs >= min)
864 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
865 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
868 cache->objects[cache->nobjs++] = obj;
873 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
878 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
879 struct kmem_cache *cache)
882 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
885 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
890 if (cache->nobjs >= min)
892 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
893 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
896 cache->objects[cache->nobjs++] = page;
901 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
904 free_page((unsigned long)mc->objects[--mc->nobjs]);
907 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
911 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
912 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
915 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
918 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
919 mmu_page_header_cache, 4);
924 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
926 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
927 pte_list_desc_cache);
928 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
929 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
930 mmu_page_header_cache);
933 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
938 p = mc->objects[--mc->nobjs];
942 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
944 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
947 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
949 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
952 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
954 if (!sp->role.direct)
955 return sp->gfns[index];
957 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
960 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
963 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
965 sp->gfns[index] = gfn;
969 * Return the pointer to the large page information for a given gfn,
970 * handling slots that are not large page aligned.
972 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
973 struct kvm_memory_slot *slot,
978 idx = gfn_to_index(gfn, slot->base_gfn, level);
979 return &slot->arch.lpage_info[level - 2][idx];
982 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
983 gfn_t gfn, int count)
985 struct kvm_lpage_info *linfo;
988 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
989 linfo = lpage_info_slot(gfn, slot, i);
990 linfo->disallow_lpage += count;
991 WARN_ON(linfo->disallow_lpage < 0);
995 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
997 update_gfn_disallow_lpage_count(slot, gfn, 1);
1000 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1002 update_gfn_disallow_lpage_count(slot, gfn, -1);
1005 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1007 struct kvm_memslots *slots;
1008 struct kvm_memory_slot *slot;
1011 kvm->arch.indirect_shadow_pages++;
1013 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1014 slot = __gfn_to_memslot(slots, gfn);
1016 /* the non-leaf shadow pages are keeping readonly. */
1017 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1018 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1019 KVM_PAGE_TRACK_WRITE);
1021 kvm_mmu_gfn_disallow_lpage(slot, gfn);
1024 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1026 struct kvm_memslots *slots;
1027 struct kvm_memory_slot *slot;
1030 kvm->arch.indirect_shadow_pages--;
1032 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1033 slot = __gfn_to_memslot(slots, gfn);
1034 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1035 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1036 KVM_PAGE_TRACK_WRITE);
1038 kvm_mmu_gfn_allow_lpage(slot, gfn);
1041 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1042 struct kvm_memory_slot *slot)
1044 struct kvm_lpage_info *linfo;
1047 linfo = lpage_info_slot(gfn, slot, level);
1048 return !!linfo->disallow_lpage;
1054 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1057 struct kvm_memory_slot *slot;
1059 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1060 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1063 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1065 unsigned long page_size;
1068 page_size = kvm_host_page_size(kvm, gfn);
1070 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1071 if (page_size >= KVM_HPAGE_SIZE(i))
1080 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1083 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1085 if (no_dirty_log && slot->dirty_bitmap)
1091 static struct kvm_memory_slot *
1092 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1095 struct kvm_memory_slot *slot;
1097 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1098 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1104 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1105 bool *force_pt_level)
1107 int host_level, level, max_level;
1108 struct kvm_memory_slot *slot;
1110 if (unlikely(*force_pt_level))
1111 return PT_PAGE_TABLE_LEVEL;
1113 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1114 *force_pt_level = !memslot_valid_for_gpte(slot, true);
1115 if (unlikely(*force_pt_level))
1116 return PT_PAGE_TABLE_LEVEL;
1118 host_level = host_mapping_level(vcpu->kvm, large_gfn);
1120 if (host_level == PT_PAGE_TABLE_LEVEL)
1123 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1125 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1126 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1133 * About rmap_head encoding:
1135 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1136 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1137 * pte_list_desc containing more mappings.
1141 * Returns the number of pointers in the rmap chain, not counting the new one.
1143 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1144 struct kvm_rmap_head *rmap_head)
1146 struct pte_list_desc *desc;
1149 if (!rmap_head->val) {
1150 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1151 rmap_head->val = (unsigned long)spte;
1152 } else if (!(rmap_head->val & 1)) {
1153 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1154 desc = mmu_alloc_pte_list_desc(vcpu);
1155 desc->sptes[0] = (u64 *)rmap_head->val;
1156 desc->sptes[1] = spte;
1157 rmap_head->val = (unsigned long)desc | 1;
1160 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1161 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1162 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1164 count += PTE_LIST_EXT;
1166 if (desc->sptes[PTE_LIST_EXT-1]) {
1167 desc->more = mmu_alloc_pte_list_desc(vcpu);
1170 for (i = 0; desc->sptes[i]; ++i)
1172 desc->sptes[i] = spte;
1178 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1179 struct pte_list_desc *desc, int i,
1180 struct pte_list_desc *prev_desc)
1184 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1186 desc->sptes[i] = desc->sptes[j];
1187 desc->sptes[j] = NULL;
1190 if (!prev_desc && !desc->more)
1191 rmap_head->val = (unsigned long)desc->sptes[0];
1194 prev_desc->more = desc->more;
1196 rmap_head->val = (unsigned long)desc->more | 1;
1197 mmu_free_pte_list_desc(desc);
1200 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1202 struct pte_list_desc *desc;
1203 struct pte_list_desc *prev_desc;
1206 if (!rmap_head->val) {
1207 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1209 } else if (!(rmap_head->val & 1)) {
1210 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1211 if ((u64 *)rmap_head->val != spte) {
1212 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1217 rmap_printk("pte_list_remove: %p many->many\n", spte);
1218 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1221 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1222 if (desc->sptes[i] == spte) {
1223 pte_list_desc_remove_entry(rmap_head,
1224 desc, i, prev_desc);
1231 pr_err("pte_list_remove: %p many->many\n", spte);
1236 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1237 struct kvm_memory_slot *slot)
1241 idx = gfn_to_index(gfn, slot->base_gfn, level);
1242 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1245 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1246 struct kvm_mmu_page *sp)
1248 struct kvm_memslots *slots;
1249 struct kvm_memory_slot *slot;
1251 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1252 slot = __gfn_to_memslot(slots, gfn);
1253 return __gfn_to_rmap(gfn, sp->role.level, slot);
1256 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1258 struct kvm_mmu_memory_cache *cache;
1260 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1261 return mmu_memory_cache_free_objects(cache);
1264 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1266 struct kvm_mmu_page *sp;
1267 struct kvm_rmap_head *rmap_head;
1269 sp = page_header(__pa(spte));
1270 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1271 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1272 return pte_list_add(vcpu, spte, rmap_head);
1275 static void rmap_remove(struct kvm *kvm, u64 *spte)
1277 struct kvm_mmu_page *sp;
1279 struct kvm_rmap_head *rmap_head;
1281 sp = page_header(__pa(spte));
1282 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1283 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1284 pte_list_remove(spte, rmap_head);
1288 * Used by the following functions to iterate through the sptes linked by a
1289 * rmap. All fields are private and not assumed to be used outside.
1291 struct rmap_iterator {
1292 /* private fields */
1293 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1294 int pos; /* index of the sptep */
1298 * Iteration must be started by this function. This should also be used after
1299 * removing/dropping sptes from the rmap link because in such cases the
1300 * information in the itererator may not be valid.
1302 * Returns sptep if found, NULL otherwise.
1304 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1305 struct rmap_iterator *iter)
1309 if (!rmap_head->val)
1312 if (!(rmap_head->val & 1)) {
1314 sptep = (u64 *)rmap_head->val;
1318 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1320 sptep = iter->desc->sptes[iter->pos];
1322 BUG_ON(!is_shadow_present_pte(*sptep));
1327 * Must be used with a valid iterator: e.g. after rmap_get_first().
1329 * Returns sptep if found, NULL otherwise.
1331 static u64 *rmap_get_next(struct rmap_iterator *iter)
1336 if (iter->pos < PTE_LIST_EXT - 1) {
1338 sptep = iter->desc->sptes[iter->pos];
1343 iter->desc = iter->desc->more;
1347 /* desc->sptes[0] cannot be NULL */
1348 sptep = iter->desc->sptes[iter->pos];
1355 BUG_ON(!is_shadow_present_pte(*sptep));
1359 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1360 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1361 _spte_; _spte_ = rmap_get_next(_iter_))
1363 static void drop_spte(struct kvm *kvm, u64 *sptep)
1365 if (mmu_spte_clear_track_bits(sptep))
1366 rmap_remove(kvm, sptep);
1370 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1372 if (is_large_pte(*sptep)) {
1373 WARN_ON(page_header(__pa(sptep))->role.level ==
1374 PT_PAGE_TABLE_LEVEL);
1375 drop_spte(kvm, sptep);
1383 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1385 if (__drop_large_spte(vcpu->kvm, sptep))
1386 kvm_flush_remote_tlbs(vcpu->kvm);
1390 * Write-protect on the specified @sptep, @pt_protect indicates whether
1391 * spte write-protection is caused by protecting shadow page table.
1393 * Note: write protection is difference between dirty logging and spte
1395 * - for dirty logging, the spte can be set to writable at anytime if
1396 * its dirty bitmap is properly set.
1397 * - for spte protection, the spte can be writable only after unsync-ing
1400 * Return true if tlb need be flushed.
1402 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1406 if (!is_writable_pte(spte) &&
1407 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1410 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1413 spte &= ~SPTE_MMU_WRITEABLE;
1414 spte = spte & ~PT_WRITABLE_MASK;
1416 return mmu_spte_update(sptep, spte);
1419 static bool __rmap_write_protect(struct kvm *kvm,
1420 struct kvm_rmap_head *rmap_head,
1424 struct rmap_iterator iter;
1427 for_each_rmap_spte(rmap_head, &iter, sptep)
1428 flush |= spte_write_protect(sptep, pt_protect);
1433 static bool spte_clear_dirty(u64 *sptep)
1437 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1439 spte &= ~shadow_dirty_mask;
1441 return mmu_spte_update(sptep, spte);
1444 static bool wrprot_ad_disabled_spte(u64 *sptep)
1446 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1447 (unsigned long *)sptep);
1449 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1451 return was_writable;
1455 * Gets the GFN ready for another round of dirty logging by clearing the
1456 * - D bit on ad-enabled SPTEs, and
1457 * - W bit on ad-disabled SPTEs.
1458 * Returns true iff any D or W bits were cleared.
1460 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1463 struct rmap_iterator iter;
1466 for_each_rmap_spte(rmap_head, &iter, sptep)
1467 if (spte_ad_enabled(*sptep))
1468 flush |= spte_clear_dirty(sptep);
1470 flush |= wrprot_ad_disabled_spte(sptep);
1475 static bool spte_set_dirty(u64 *sptep)
1479 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1481 spte |= shadow_dirty_mask;
1483 return mmu_spte_update(sptep, spte);
1486 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1489 struct rmap_iterator iter;
1492 for_each_rmap_spte(rmap_head, &iter, sptep)
1493 if (spte_ad_enabled(*sptep))
1494 flush |= spte_set_dirty(sptep);
1500 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1501 * @kvm: kvm instance
1502 * @slot: slot to protect
1503 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1504 * @mask: indicates which pages we should protect
1506 * Used when we do not need to care about huge page mappings: e.g. during dirty
1507 * logging we do not have any such mappings.
1509 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1510 struct kvm_memory_slot *slot,
1511 gfn_t gfn_offset, unsigned long mask)
1513 struct kvm_rmap_head *rmap_head;
1516 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1517 PT_PAGE_TABLE_LEVEL, slot);
1518 __rmap_write_protect(kvm, rmap_head, false);
1520 /* clear the first set bit */
1526 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1527 * protect the page if the D-bit isn't supported.
1528 * @kvm: kvm instance
1529 * @slot: slot to clear D-bit
1530 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1531 * @mask: indicates which pages we should clear D-bit
1533 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1535 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1536 struct kvm_memory_slot *slot,
1537 gfn_t gfn_offset, unsigned long mask)
1539 struct kvm_rmap_head *rmap_head;
1542 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1543 PT_PAGE_TABLE_LEVEL, slot);
1544 __rmap_clear_dirty(kvm, rmap_head);
1546 /* clear the first set bit */
1550 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1553 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1556 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1557 * enable dirty logging for them.
1559 * Used when we do not need to care about huge page mappings: e.g. during dirty
1560 * logging we do not have any such mappings.
1562 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1563 struct kvm_memory_slot *slot,
1564 gfn_t gfn_offset, unsigned long mask)
1566 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1567 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1570 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1574 * kvm_arch_write_log_dirty - emulate dirty page logging
1575 * @vcpu: Guest mode vcpu
1577 * Emulate arch specific page modification logging for the
1580 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1582 if (kvm_x86_ops->write_log_dirty)
1583 return kvm_x86_ops->write_log_dirty(vcpu);
1588 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1589 struct kvm_memory_slot *slot, u64 gfn)
1591 struct kvm_rmap_head *rmap_head;
1593 bool write_protected = false;
1595 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1596 rmap_head = __gfn_to_rmap(gfn, i, slot);
1597 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1600 return write_protected;
1603 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1605 struct kvm_memory_slot *slot;
1607 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1608 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1611 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1614 struct rmap_iterator iter;
1617 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1618 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1620 drop_spte(kvm, sptep);
1627 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1628 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1631 return kvm_zap_rmapp(kvm, rmap_head);
1634 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1635 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1639 struct rmap_iterator iter;
1642 pte_t *ptep = (pte_t *)data;
1645 WARN_ON(pte_huge(*ptep));
1646 new_pfn = pte_pfn(*ptep);
1649 for_each_rmap_spte(rmap_head, &iter, sptep) {
1650 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1651 sptep, *sptep, gfn, level);
1655 if (pte_write(*ptep)) {
1656 drop_spte(kvm, sptep);
1659 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1660 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1662 new_spte &= ~PT_WRITABLE_MASK;
1663 new_spte &= ~SPTE_HOST_WRITEABLE;
1665 new_spte = mark_spte_for_access_track(new_spte);
1667 mmu_spte_clear_track_bits(sptep);
1668 mmu_spte_set(sptep, new_spte);
1673 kvm_flush_remote_tlbs(kvm);
1678 struct slot_rmap_walk_iterator {
1680 struct kvm_memory_slot *slot;
1686 /* output fields. */
1688 struct kvm_rmap_head *rmap;
1691 /* private field. */
1692 struct kvm_rmap_head *end_rmap;
1696 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1698 iterator->level = level;
1699 iterator->gfn = iterator->start_gfn;
1700 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1701 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1706 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1707 struct kvm_memory_slot *slot, int start_level,
1708 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1710 iterator->slot = slot;
1711 iterator->start_level = start_level;
1712 iterator->end_level = end_level;
1713 iterator->start_gfn = start_gfn;
1714 iterator->end_gfn = end_gfn;
1716 rmap_walk_init_level(iterator, iterator->start_level);
1719 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1721 return !!iterator->rmap;
1724 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1726 if (++iterator->rmap <= iterator->end_rmap) {
1727 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1731 if (++iterator->level > iterator->end_level) {
1732 iterator->rmap = NULL;
1736 rmap_walk_init_level(iterator, iterator->level);
1739 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1740 _start_gfn, _end_gfn, _iter_) \
1741 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1742 _end_level_, _start_gfn, _end_gfn); \
1743 slot_rmap_walk_okay(_iter_); \
1744 slot_rmap_walk_next(_iter_))
1746 static int kvm_handle_hva_range(struct kvm *kvm,
1747 unsigned long start,
1750 int (*handler)(struct kvm *kvm,
1751 struct kvm_rmap_head *rmap_head,
1752 struct kvm_memory_slot *slot,
1755 unsigned long data))
1757 struct kvm_memslots *slots;
1758 struct kvm_memory_slot *memslot;
1759 struct slot_rmap_walk_iterator iterator;
1763 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1764 slots = __kvm_memslots(kvm, i);
1765 kvm_for_each_memslot(memslot, slots) {
1766 unsigned long hva_start, hva_end;
1767 gfn_t gfn_start, gfn_end;
1769 hva_start = max(start, memslot->userspace_addr);
1770 hva_end = min(end, memslot->userspace_addr +
1771 (memslot->npages << PAGE_SHIFT));
1772 if (hva_start >= hva_end)
1775 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1776 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1778 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1779 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1781 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1782 PT_MAX_HUGEPAGE_LEVEL,
1783 gfn_start, gfn_end - 1,
1785 ret |= handler(kvm, iterator.rmap, memslot,
1786 iterator.gfn, iterator.level, data);
1793 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1795 int (*handler)(struct kvm *kvm,
1796 struct kvm_rmap_head *rmap_head,
1797 struct kvm_memory_slot *slot,
1798 gfn_t gfn, int level,
1799 unsigned long data))
1801 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1804 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1806 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1809 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1811 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1814 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1816 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1819 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1820 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1824 struct rmap_iterator uninitialized_var(iter);
1827 for_each_rmap_spte(rmap_head, &iter, sptep)
1828 young |= mmu_spte_age(sptep);
1830 trace_kvm_age_page(gfn, level, slot, young);
1834 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1835 struct kvm_memory_slot *slot, gfn_t gfn,
1836 int level, unsigned long data)
1839 struct rmap_iterator iter;
1841 for_each_rmap_spte(rmap_head, &iter, sptep)
1842 if (is_accessed_spte(*sptep))
1847 #define RMAP_RECYCLE_THRESHOLD 1000
1849 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1851 struct kvm_rmap_head *rmap_head;
1852 struct kvm_mmu_page *sp;
1854 sp = page_header(__pa(spte));
1856 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1858 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1859 kvm_flush_remote_tlbs(vcpu->kvm);
1862 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1864 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1867 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1869 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1873 static int is_empty_shadow_page(u64 *spt)
1878 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1879 if (is_shadow_present_pte(*pos)) {
1880 printk(KERN_ERR "%s: %p %llx\n", __func__,
1889 * This value is the sum of all of the kvm instances's
1890 * kvm->arch.n_used_mmu_pages values. We need a global,
1891 * aggregate version in order to make the slab shrinker
1894 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1896 kvm->arch.n_used_mmu_pages += nr;
1897 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1900 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1902 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1903 hlist_del(&sp->hash_link);
1904 list_del(&sp->link);
1905 free_page((unsigned long)sp->spt);
1906 if (!sp->role.direct)
1907 free_page((unsigned long)sp->gfns);
1908 kmem_cache_free(mmu_page_header_cache, sp);
1911 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1913 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1916 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1917 struct kvm_mmu_page *sp, u64 *parent_pte)
1922 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1925 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1928 pte_list_remove(parent_pte, &sp->parent_ptes);
1931 static void drop_parent_pte(struct kvm_mmu_page *sp,
1934 mmu_page_remove_parent_pte(sp, parent_pte);
1935 mmu_spte_clear_no_track(parent_pte);
1938 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1940 struct kvm_mmu_page *sp;
1942 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1943 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1945 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1946 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1949 * The active_mmu_pages list is the FIFO list, do not move the
1950 * page until it is zapped. kvm_zap_obsolete_pages depends on
1951 * this feature. See the comments in kvm_zap_obsolete_pages().
1953 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1954 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1958 static void mark_unsync(u64 *spte);
1959 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1962 struct rmap_iterator iter;
1964 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1969 static void mark_unsync(u64 *spte)
1971 struct kvm_mmu_page *sp;
1974 sp = page_header(__pa(spte));
1975 index = spte - sp->spt;
1976 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1978 if (sp->unsync_children++)
1980 kvm_mmu_mark_parents_unsync(sp);
1983 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1984 struct kvm_mmu_page *sp)
1989 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1993 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1994 struct kvm_mmu_page *sp, u64 *spte,
2000 #define KVM_PAGE_ARRAY_NR 16
2002 struct kvm_mmu_pages {
2003 struct mmu_page_and_offset {
2004 struct kvm_mmu_page *sp;
2006 } page[KVM_PAGE_ARRAY_NR];
2010 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2016 for (i=0; i < pvec->nr; i++)
2017 if (pvec->page[i].sp == sp)
2020 pvec->page[pvec->nr].sp = sp;
2021 pvec->page[pvec->nr].idx = idx;
2023 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2026 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2028 --sp->unsync_children;
2029 WARN_ON((int)sp->unsync_children < 0);
2030 __clear_bit(idx, sp->unsync_child_bitmap);
2033 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2034 struct kvm_mmu_pages *pvec)
2036 int i, ret, nr_unsync_leaf = 0;
2038 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2039 struct kvm_mmu_page *child;
2040 u64 ent = sp->spt[i];
2042 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2043 clear_unsync_child_bit(sp, i);
2047 child = page_header(ent & PT64_BASE_ADDR_MASK);
2049 if (child->unsync_children) {
2050 if (mmu_pages_add(pvec, child, i))
2053 ret = __mmu_unsync_walk(child, pvec);
2055 clear_unsync_child_bit(sp, i);
2057 } else if (ret > 0) {
2058 nr_unsync_leaf += ret;
2061 } else if (child->unsync) {
2063 if (mmu_pages_add(pvec, child, i))
2066 clear_unsync_child_bit(sp, i);
2069 return nr_unsync_leaf;
2072 #define INVALID_INDEX (-1)
2074 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2075 struct kvm_mmu_pages *pvec)
2078 if (!sp->unsync_children)
2081 mmu_pages_add(pvec, sp, INVALID_INDEX);
2082 return __mmu_unsync_walk(sp, pvec);
2085 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2087 WARN_ON(!sp->unsync);
2088 trace_kvm_mmu_sync_page(sp);
2090 --kvm->stat.mmu_unsync;
2093 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2094 struct list_head *invalid_list);
2095 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2096 struct list_head *invalid_list);
2099 * NOTE: we should pay more attention on the zapped-obsolete page
2100 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2101 * since it has been deleted from active_mmu_pages but still can be found
2104 * for_each_valid_sp() has skipped that kind of pages.
2106 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2107 hlist_for_each_entry(_sp, \
2108 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2109 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2112 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2113 for_each_valid_sp(_kvm, _sp, _gfn) \
2114 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2116 /* @sp->gfn should be write-protected at the call site */
2117 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2118 struct list_head *invalid_list)
2120 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
2121 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2125 if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
2126 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2133 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2134 struct list_head *invalid_list,
2135 bool remote_flush, bool local_flush)
2137 if (!list_empty(invalid_list)) {
2138 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
2143 kvm_flush_remote_tlbs(vcpu->kvm);
2144 else if (local_flush)
2145 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2148 #ifdef CONFIG_KVM_MMU_AUDIT
2149 #include "mmu_audit.c"
2151 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2152 static void mmu_audit_disable(void) { }
2155 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2157 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2160 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2161 struct list_head *invalid_list)
2163 kvm_unlink_unsync_page(vcpu->kvm, sp);
2164 return __kvm_sync_page(vcpu, sp, invalid_list);
2167 /* @gfn should be write-protected at the call site */
2168 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2169 struct list_head *invalid_list)
2171 struct kvm_mmu_page *s;
2174 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2178 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2179 ret |= kvm_sync_page(vcpu, s, invalid_list);
2185 struct mmu_page_path {
2186 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2187 unsigned int idx[PT64_ROOT_MAX_LEVEL];
2190 #define for_each_sp(pvec, sp, parents, i) \
2191 for (i = mmu_pages_first(&pvec, &parents); \
2192 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2193 i = mmu_pages_next(&pvec, &parents, i))
2195 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2196 struct mmu_page_path *parents,
2201 for (n = i+1; n < pvec->nr; n++) {
2202 struct kvm_mmu_page *sp = pvec->page[n].sp;
2203 unsigned idx = pvec->page[n].idx;
2204 int level = sp->role.level;
2206 parents->idx[level-1] = idx;
2207 if (level == PT_PAGE_TABLE_LEVEL)
2210 parents->parent[level-2] = sp;
2216 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2217 struct mmu_page_path *parents)
2219 struct kvm_mmu_page *sp;
2225 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2227 sp = pvec->page[0].sp;
2228 level = sp->role.level;
2229 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2231 parents->parent[level-2] = sp;
2233 /* Also set up a sentinel. Further entries in pvec are all
2234 * children of sp, so this element is never overwritten.
2236 parents->parent[level-1] = NULL;
2237 return mmu_pages_next(pvec, parents, 0);
2240 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2242 struct kvm_mmu_page *sp;
2243 unsigned int level = 0;
2246 unsigned int idx = parents->idx[level];
2247 sp = parents->parent[level];
2251 WARN_ON(idx == INVALID_INDEX);
2252 clear_unsync_child_bit(sp, idx);
2254 } while (!sp->unsync_children);
2257 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2258 struct kvm_mmu_page *parent)
2261 struct kvm_mmu_page *sp;
2262 struct mmu_page_path parents;
2263 struct kvm_mmu_pages pages;
2264 LIST_HEAD(invalid_list);
2267 while (mmu_unsync_walk(parent, &pages)) {
2268 bool protected = false;
2270 for_each_sp(pages, sp, parents, i)
2271 protected |= rmap_write_protect(vcpu, sp->gfn);
2274 kvm_flush_remote_tlbs(vcpu->kvm);
2278 for_each_sp(pages, sp, parents, i) {
2279 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2280 mmu_pages_clear_parents(&parents);
2282 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2283 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2284 cond_resched_lock(&vcpu->kvm->mmu_lock);
2289 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2292 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2294 atomic_set(&sp->write_flooding_count, 0);
2297 static void clear_sp_write_flooding_count(u64 *spte)
2299 struct kvm_mmu_page *sp = page_header(__pa(spte));
2301 __clear_sp_write_flooding_count(sp);
2304 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2311 union kvm_mmu_page_role role;
2313 struct kvm_mmu_page *sp;
2314 bool need_sync = false;
2317 LIST_HEAD(invalid_list);
2319 role = vcpu->arch.mmu.base_role;
2321 role.direct = direct;
2324 role.access = access;
2325 if (!vcpu->arch.mmu.direct_map
2326 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2327 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2328 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2329 role.quadrant = quadrant;
2331 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2332 if (sp->gfn != gfn) {
2337 if (!need_sync && sp->unsync)
2340 if (sp->role.word != role.word)
2344 /* The page is good, but __kvm_sync_page might still end
2345 * up zapping it. If so, break in order to rebuild it.
2347 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2350 WARN_ON(!list_empty(&invalid_list));
2351 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2354 if (sp->unsync_children)
2355 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2357 __clear_sp_write_flooding_count(sp);
2358 trace_kvm_mmu_get_page(sp, false);
2362 ++vcpu->kvm->stat.mmu_cache_miss;
2364 sp = kvm_mmu_alloc_page(vcpu, direct);
2368 hlist_add_head(&sp->hash_link,
2369 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2372 * we should do write protection before syncing pages
2373 * otherwise the content of the synced shadow page may
2374 * be inconsistent with guest page table.
2376 account_shadowed(vcpu->kvm, sp);
2377 if (level == PT_PAGE_TABLE_LEVEL &&
2378 rmap_write_protect(vcpu, gfn))
2379 kvm_flush_remote_tlbs(vcpu->kvm);
2381 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2382 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2384 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2385 clear_page(sp->spt);
2386 trace_kvm_mmu_get_page(sp, true);
2388 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2390 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2391 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2395 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2396 struct kvm_vcpu *vcpu, u64 addr)
2398 iterator->addr = addr;
2399 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2400 iterator->level = vcpu->arch.mmu.shadow_root_level;
2402 if (iterator->level == PT64_ROOT_4LEVEL &&
2403 vcpu->arch.mmu.root_level < PT64_ROOT_4LEVEL &&
2404 !vcpu->arch.mmu.direct_map)
2407 if (iterator->level == PT32E_ROOT_LEVEL) {
2408 iterator->shadow_addr
2409 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2410 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2412 if (!iterator->shadow_addr)
2413 iterator->level = 0;
2417 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2419 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2422 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2423 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2427 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2430 if (is_last_spte(spte, iterator->level)) {
2431 iterator->level = 0;
2435 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2439 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2441 __shadow_walk_next(iterator, *iterator->sptep);
2444 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2445 struct kvm_mmu_page *sp)
2449 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2451 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2452 shadow_user_mask | shadow_x_mask | shadow_me_mask;
2454 if (sp_ad_disabled(sp))
2455 spte |= shadow_acc_track_value;
2457 spte |= shadow_accessed_mask;
2459 mmu_spte_set(sptep, spte);
2461 mmu_page_add_parent_pte(vcpu, sp, sptep);
2463 if (sp->unsync_children || sp->unsync)
2467 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2468 unsigned direct_access)
2470 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2471 struct kvm_mmu_page *child;
2474 * For the direct sp, if the guest pte's dirty bit
2475 * changed form clean to dirty, it will corrupt the
2476 * sp's access: allow writable in the read-only sp,
2477 * so we should update the spte at this point to get
2478 * a new sp with the correct access.
2480 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2481 if (child->role.access == direct_access)
2484 drop_parent_pte(child, sptep);
2485 kvm_flush_remote_tlbs(vcpu->kvm);
2489 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2493 struct kvm_mmu_page *child;
2496 if (is_shadow_present_pte(pte)) {
2497 if (is_last_spte(pte, sp->role.level)) {
2498 drop_spte(kvm, spte);
2499 if (is_large_pte(pte))
2502 child = page_header(pte & PT64_BASE_ADDR_MASK);
2503 drop_parent_pte(child, spte);
2508 if (is_mmio_spte(pte))
2509 mmu_spte_clear_no_track(spte);
2514 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2515 struct kvm_mmu_page *sp)
2519 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2520 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2523 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2526 struct rmap_iterator iter;
2528 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2529 drop_parent_pte(sp, sptep);
2532 static int mmu_zap_unsync_children(struct kvm *kvm,
2533 struct kvm_mmu_page *parent,
2534 struct list_head *invalid_list)
2537 struct mmu_page_path parents;
2538 struct kvm_mmu_pages pages;
2540 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2543 while (mmu_unsync_walk(parent, &pages)) {
2544 struct kvm_mmu_page *sp;
2546 for_each_sp(pages, sp, parents, i) {
2547 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2548 mmu_pages_clear_parents(&parents);
2556 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2557 struct list_head *invalid_list)
2561 trace_kvm_mmu_prepare_zap_page(sp);
2562 ++kvm->stat.mmu_shadow_zapped;
2563 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2564 kvm_mmu_page_unlink_children(kvm, sp);
2565 kvm_mmu_unlink_parents(kvm, sp);
2567 if (!sp->role.invalid && !sp->role.direct)
2568 unaccount_shadowed(kvm, sp);
2571 kvm_unlink_unsync_page(kvm, sp);
2572 if (!sp->root_count) {
2575 list_move(&sp->link, invalid_list);
2576 kvm_mod_used_mmu_pages(kvm, -1);
2578 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2581 * The obsolete pages can not be used on any vcpus.
2582 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2584 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2585 kvm_reload_remote_mmus(kvm);
2588 sp->role.invalid = 1;
2592 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2593 struct list_head *invalid_list)
2595 struct kvm_mmu_page *sp, *nsp;
2597 if (list_empty(invalid_list))
2601 * We need to make sure everyone sees our modifications to
2602 * the page tables and see changes to vcpu->mode here. The barrier
2603 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2604 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2606 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2607 * guest mode and/or lockless shadow page table walks.
2609 kvm_flush_remote_tlbs(kvm);
2611 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2612 WARN_ON(!sp->role.invalid || sp->root_count);
2613 kvm_mmu_free_page(sp);
2617 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2618 struct list_head *invalid_list)
2620 struct kvm_mmu_page *sp;
2622 if (list_empty(&kvm->arch.active_mmu_pages))
2625 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2626 struct kvm_mmu_page, link);
2627 return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2631 * Changing the number of mmu pages allocated to the vm
2632 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2634 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2636 LIST_HEAD(invalid_list);
2638 spin_lock(&kvm->mmu_lock);
2640 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2641 /* Need to free some mmu pages to achieve the goal. */
2642 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2643 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2646 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2647 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2650 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2652 spin_unlock(&kvm->mmu_lock);
2655 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2657 struct kvm_mmu_page *sp;
2658 LIST_HEAD(invalid_list);
2661 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2663 spin_lock(&kvm->mmu_lock);
2664 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2665 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2668 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2670 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2671 spin_unlock(&kvm->mmu_lock);
2675 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2677 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2679 trace_kvm_mmu_unsync_page(sp);
2680 ++vcpu->kvm->stat.mmu_unsync;
2683 kvm_mmu_mark_parents_unsync(sp);
2686 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2689 struct kvm_mmu_page *sp;
2691 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2694 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2701 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2702 kvm_unsync_page(vcpu, sp);
2708 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2711 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
2713 * Some reserved pages, such as those from NVDIMM
2714 * DAX devices, are not for MMIO, and can be mapped
2715 * with cached memory type for better performance.
2716 * However, the above check misconceives those pages
2717 * as MMIO, and results in KVM mapping them with UC
2718 * memory type, which would hurt the performance.
2719 * Therefore, we check the host memory type in addition
2720 * and only treat UC/UC-/WC pages as MMIO.
2722 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
2727 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2728 unsigned pte_access, int level,
2729 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2730 bool can_unsync, bool host_writable)
2734 struct kvm_mmu_page *sp;
2736 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2739 sp = page_header(__pa(sptep));
2740 if (sp_ad_disabled(sp))
2741 spte |= shadow_acc_track_value;
2744 * For the EPT case, shadow_present_mask is 0 if hardware
2745 * supports exec-only page table entries. In that case,
2746 * ACC_USER_MASK and shadow_user_mask are used to represent
2747 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2749 spte |= shadow_present_mask;
2751 spte |= spte_shadow_accessed_mask(spte);
2753 if (pte_access & ACC_EXEC_MASK)
2754 spte |= shadow_x_mask;
2756 spte |= shadow_nx_mask;
2758 if (pte_access & ACC_USER_MASK)
2759 spte |= shadow_user_mask;
2761 if (level > PT_PAGE_TABLE_LEVEL)
2762 spte |= PT_PAGE_SIZE_MASK;
2764 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2765 kvm_is_mmio_pfn(pfn));
2768 spte |= SPTE_HOST_WRITEABLE;
2770 pte_access &= ~ACC_WRITE_MASK;
2772 if (!kvm_is_mmio_pfn(pfn))
2773 spte |= shadow_me_mask;
2775 spte |= (u64)pfn << PAGE_SHIFT;
2777 if (pte_access & ACC_WRITE_MASK) {
2780 * Other vcpu creates new sp in the window between
2781 * mapping_level() and acquiring mmu-lock. We can
2782 * allow guest to retry the access, the mapping can
2783 * be fixed if guest refault.
2785 if (level > PT_PAGE_TABLE_LEVEL &&
2786 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2789 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2792 * Optimization: for pte sync, if spte was writable the hash
2793 * lookup is unnecessary (and expensive). Write protection
2794 * is responsibility of mmu_get_page / kvm_sync_page.
2795 * Same reasoning can be applied to dirty page accounting.
2797 if (!can_unsync && is_writable_pte(*sptep))
2800 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2801 pgprintk("%s: found shadow page for %llx, marking ro\n",
2804 pte_access &= ~ACC_WRITE_MASK;
2805 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2809 if (pte_access & ACC_WRITE_MASK) {
2810 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2811 spte |= spte_shadow_dirty_mask(spte);
2815 spte = mark_spte_for_access_track(spte);
2818 if (mmu_spte_update(sptep, spte))
2819 kvm_flush_remote_tlbs(vcpu->kvm);
2824 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2825 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2826 bool speculative, bool host_writable)
2828 int was_rmapped = 0;
2830 int ret = RET_PF_RETRY;
2832 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2833 *sptep, write_fault, gfn);
2835 if (is_shadow_present_pte(*sptep)) {
2837 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2838 * the parent of the now unreachable PTE.
2840 if (level > PT_PAGE_TABLE_LEVEL &&
2841 !is_large_pte(*sptep)) {
2842 struct kvm_mmu_page *child;
2845 child = page_header(pte & PT64_BASE_ADDR_MASK);
2846 drop_parent_pte(child, sptep);
2847 kvm_flush_remote_tlbs(vcpu->kvm);
2848 } else if (pfn != spte_to_pfn(*sptep)) {
2849 pgprintk("hfn old %llx new %llx\n",
2850 spte_to_pfn(*sptep), pfn);
2851 drop_spte(vcpu->kvm, sptep);
2852 kvm_flush_remote_tlbs(vcpu->kvm);
2857 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2858 true, host_writable)) {
2860 ret = RET_PF_EMULATE;
2861 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2864 if (unlikely(is_mmio_spte(*sptep)))
2865 ret = RET_PF_EMULATE;
2867 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2868 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2869 is_large_pte(*sptep)? "2MB" : "4kB",
2870 *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
2872 if (!was_rmapped && is_large_pte(*sptep))
2873 ++vcpu->kvm->stat.lpages;
2875 if (is_shadow_present_pte(*sptep)) {
2877 rmap_count = rmap_add(vcpu, sptep, gfn);
2878 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2879 rmap_recycle(vcpu, sptep, gfn);
2883 kvm_release_pfn_clean(pfn);
2888 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2891 struct kvm_memory_slot *slot;
2893 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2895 return KVM_PFN_ERR_FAULT;
2897 return gfn_to_pfn_memslot_atomic(slot, gfn);
2900 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2901 struct kvm_mmu_page *sp,
2902 u64 *start, u64 *end)
2904 struct page *pages[PTE_PREFETCH_NUM];
2905 struct kvm_memory_slot *slot;
2906 unsigned access = sp->role.access;
2910 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2911 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2915 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2919 for (i = 0; i < ret; i++, gfn++, start++)
2920 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2921 page_to_pfn(pages[i]), true, true);
2926 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2927 struct kvm_mmu_page *sp, u64 *sptep)
2929 u64 *spte, *start = NULL;
2932 WARN_ON(!sp->role.direct);
2934 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2937 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2938 if (is_shadow_present_pte(*spte) || spte == sptep) {
2941 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2949 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2951 struct kvm_mmu_page *sp;
2953 sp = page_header(__pa(sptep));
2956 * Without accessed bits, there's no way to distinguish between
2957 * actually accessed translations and prefetched, so disable pte
2958 * prefetch if accessed bits aren't available.
2960 if (sp_ad_disabled(sp))
2963 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2966 __direct_pte_prefetch(vcpu, sp, sptep);
2969 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2970 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2972 struct kvm_shadow_walk_iterator iterator;
2973 struct kvm_mmu_page *sp;
2977 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2980 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2981 if (iterator.level == level) {
2982 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2983 write, level, gfn, pfn, prefault,
2985 direct_pte_prefetch(vcpu, iterator.sptep);
2986 ++vcpu->stat.pf_fixed;
2990 drop_large_spte(vcpu, iterator.sptep);
2991 if (!is_shadow_present_pte(*iterator.sptep)) {
2992 u64 base_addr = iterator.addr;
2994 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2995 pseudo_gfn = base_addr >> PAGE_SHIFT;
2996 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2997 iterator.level - 1, 1, ACC_ALL);
2999 link_shadow_page(vcpu, iterator.sptep, sp);
3005 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3009 clear_siginfo(&info);
3010 info.si_signo = SIGBUS;
3012 info.si_code = BUS_MCEERR_AR;
3013 info.si_addr = (void __user *)address;
3014 info.si_addr_lsb = PAGE_SHIFT;
3016 send_sig_info(SIGBUS, &info, tsk);
3019 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3022 * Do not cache the mmio info caused by writing the readonly gfn
3023 * into the spte otherwise read access on readonly gfn also can
3024 * caused mmio page fault and treat it as mmio access.
3026 if (pfn == KVM_PFN_ERR_RO_FAULT)
3027 return RET_PF_EMULATE;
3029 if (pfn == KVM_PFN_ERR_HWPOISON) {
3030 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3031 return RET_PF_RETRY;
3037 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3038 gfn_t *gfnp, kvm_pfn_t *pfnp,
3041 kvm_pfn_t pfn = *pfnp;
3043 int level = *levelp;
3046 * Check if it's a transparent hugepage. If this would be an
3047 * hugetlbfs page, level wouldn't be set to
3048 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3051 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3052 level == PT_PAGE_TABLE_LEVEL &&
3053 PageTransCompoundMap(pfn_to_page(pfn)) &&
3054 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
3057 * mmu_notifier_retry was successful and we hold the
3058 * mmu_lock here, so the pmd can't become splitting
3059 * from under us, and in turn
3060 * __split_huge_page_refcount() can't run from under
3061 * us and we can safely transfer the refcount from
3062 * PG_tail to PG_head as we switch the pfn to tail to
3065 *levelp = level = PT_DIRECTORY_LEVEL;
3066 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3067 VM_BUG_ON((gfn & mask) != (pfn & mask));
3071 kvm_release_pfn_clean(pfn);
3079 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3080 kvm_pfn_t pfn, unsigned access, int *ret_val)
3082 /* The pfn is invalid, report the error! */
3083 if (unlikely(is_error_pfn(pfn))) {
3084 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3088 if (unlikely(is_noslot_pfn(pfn)))
3089 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3094 static bool page_fault_can_be_fast(u32 error_code)
3097 * Do not fix the mmio spte with invalid generation number which
3098 * need to be updated by slow page fault path.
3100 if (unlikely(error_code & PFERR_RSVD_MASK))
3103 /* See if the page fault is due to an NX violation */
3104 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3105 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3109 * #PF can be fast if:
3110 * 1. The shadow page table entry is not present, which could mean that
3111 * the fault is potentially caused by access tracking (if enabled).
3112 * 2. The shadow page table entry is present and the fault
3113 * is caused by write-protect, that means we just need change the W
3114 * bit of the spte which can be done out of mmu-lock.
3116 * However, if access tracking is disabled we know that a non-present
3117 * page must be a genuine page fault where we have to create a new SPTE.
3118 * So, if access tracking is disabled, we return true only for write
3119 * accesses to a present page.
3122 return shadow_acc_track_mask != 0 ||
3123 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3124 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3128 * Returns true if the SPTE was fixed successfully. Otherwise,
3129 * someone else modified the SPTE from its original value.
3132 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3133 u64 *sptep, u64 old_spte, u64 new_spte)
3137 WARN_ON(!sp->role.direct);
3140 * Theoretically we could also set dirty bit (and flush TLB) here in
3141 * order to eliminate unnecessary PML logging. See comments in
3142 * set_spte. But fast_page_fault is very unlikely to happen with PML
3143 * enabled, so we do not do this. This might result in the same GPA
3144 * to be logged in PML buffer again when the write really happens, and
3145 * eventually to be called by mark_page_dirty twice. But it's also no
3146 * harm. This also avoids the TLB flush needed after setting dirty bit
3147 * so non-PML cases won't be impacted.
3149 * Compare with set_spte where instead shadow_dirty_mask is set.
3151 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3154 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3156 * The gfn of direct spte is stable since it is
3157 * calculated by sp->gfn.
3159 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3160 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3166 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3168 if (fault_err_code & PFERR_FETCH_MASK)
3169 return is_executable_pte(spte);
3171 if (fault_err_code & PFERR_WRITE_MASK)
3172 return is_writable_pte(spte);
3174 /* Fault was on Read access */
3175 return spte & PT_PRESENT_MASK;
3180 * - true: let the vcpu to access on the same address again.
3181 * - false: let the real page fault path to fix it.
3183 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3186 struct kvm_shadow_walk_iterator iterator;
3187 struct kvm_mmu_page *sp;
3188 bool fault_handled = false;
3190 uint retry_count = 0;
3192 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3195 if (!page_fault_can_be_fast(error_code))
3198 walk_shadow_page_lockless_begin(vcpu);
3203 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3204 if (!is_shadow_present_pte(spte) ||
3205 iterator.level < level)
3208 sp = page_header(__pa(iterator.sptep));
3209 if (!is_last_spte(spte, sp->role.level))
3213 * Check whether the memory access that caused the fault would
3214 * still cause it if it were to be performed right now. If not,
3215 * then this is a spurious fault caused by TLB lazily flushed,
3216 * or some other CPU has already fixed the PTE after the
3217 * current CPU took the fault.
3219 * Need not check the access of upper level table entries since
3220 * they are always ACC_ALL.
3222 if (is_access_allowed(error_code, spte)) {
3223 fault_handled = true;
3229 if (is_access_track_spte(spte))
3230 new_spte = restore_acc_track_spte(new_spte);
3233 * Currently, to simplify the code, write-protection can
3234 * be removed in the fast path only if the SPTE was
3235 * write-protected for dirty-logging or access tracking.
3237 if ((error_code & PFERR_WRITE_MASK) &&
3238 spte_can_locklessly_be_made_writable(spte))
3240 new_spte |= PT_WRITABLE_MASK;
3243 * Do not fix write-permission on the large spte. Since
3244 * we only dirty the first page into the dirty-bitmap in
3245 * fast_pf_fix_direct_spte(), other pages are missed
3246 * if its slot has dirty logging enabled.
3248 * Instead, we let the slow page fault path create a
3249 * normal spte to fix the access.
3251 * See the comments in kvm_arch_commit_memory_region().
3253 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3257 /* Verify that the fault can be handled in the fast path */
3258 if (new_spte == spte ||
3259 !is_access_allowed(error_code, new_spte))
3263 * Currently, fast page fault only works for direct mapping
3264 * since the gfn is not stable for indirect shadow page. See
3265 * Documentation/virtual/kvm/locking.txt to get more detail.
3267 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3268 iterator.sptep, spte,
3273 if (++retry_count > 4) {
3274 printk_once(KERN_WARNING
3275 "kvm: Fast #PF retrying more than 4 times.\n");
3281 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3282 spte, fault_handled);
3283 walk_shadow_page_lockless_end(vcpu);
3285 return fault_handled;
3288 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3289 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3290 static int make_mmu_pages_available(struct kvm_vcpu *vcpu);
3292 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3293 gfn_t gfn, bool prefault)
3297 bool force_pt_level = false;
3299 unsigned long mmu_seq;
3300 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3302 level = mapping_level(vcpu, gfn, &force_pt_level);
3303 if (likely(!force_pt_level)) {
3305 * This path builds a PAE pagetable - so we can map
3306 * 2mb pages at maximum. Therefore check if the level
3307 * is larger than that.
3309 if (level > PT_DIRECTORY_LEVEL)
3310 level = PT_DIRECTORY_LEVEL;
3312 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3315 if (fast_page_fault(vcpu, v, level, error_code))
3316 return RET_PF_RETRY;
3318 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3321 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3322 return RET_PF_RETRY;
3324 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3327 spin_lock(&vcpu->kvm->mmu_lock);
3328 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3330 if (make_mmu_pages_available(vcpu) < 0)
3332 if (likely(!force_pt_level))
3333 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3334 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3335 spin_unlock(&vcpu->kvm->mmu_lock);
3340 spin_unlock(&vcpu->kvm->mmu_lock);
3341 kvm_release_pfn_clean(pfn);
3342 return RET_PF_RETRY;
3345 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3346 struct list_head *invalid_list)
3348 struct kvm_mmu_page *sp;
3350 if (!VALID_PAGE(*root_hpa))
3353 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3355 if (!sp->root_count && sp->role.invalid)
3356 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3358 *root_hpa = INVALID_PAGE;
3361 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu)
3364 LIST_HEAD(invalid_list);
3365 struct kvm_mmu *mmu = &vcpu->arch.mmu;
3367 if (!VALID_PAGE(mmu->root_hpa))
3370 spin_lock(&vcpu->kvm->mmu_lock);
3372 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3373 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3374 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa, &invalid_list);
3376 for (i = 0; i < 4; ++i)
3377 if (mmu->pae_root[i] != 0)
3378 mmu_free_root_page(vcpu->kvm, &mmu->pae_root[i],
3380 mmu->root_hpa = INVALID_PAGE;
3383 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3384 spin_unlock(&vcpu->kvm->mmu_lock);
3386 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3388 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3392 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3393 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3400 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3402 struct kvm_mmu_page *sp;
3405 if (vcpu->arch.mmu.shadow_root_level >= PT64_ROOT_4LEVEL) {
3406 spin_lock(&vcpu->kvm->mmu_lock);
3407 if(make_mmu_pages_available(vcpu) < 0) {
3408 spin_unlock(&vcpu->kvm->mmu_lock);
3411 sp = kvm_mmu_get_page(vcpu, 0, 0,
3412 vcpu->arch.mmu.shadow_root_level, 1, ACC_ALL);
3414 spin_unlock(&vcpu->kvm->mmu_lock);
3415 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3416 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3417 for (i = 0; i < 4; ++i) {
3418 hpa_t root = vcpu->arch.mmu.pae_root[i];
3420 MMU_WARN_ON(VALID_PAGE(root));
3421 spin_lock(&vcpu->kvm->mmu_lock);
3422 if (make_mmu_pages_available(vcpu) < 0) {
3423 spin_unlock(&vcpu->kvm->mmu_lock);
3426 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3427 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3428 root = __pa(sp->spt);
3430 spin_unlock(&vcpu->kvm->mmu_lock);
3431 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3433 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3440 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3442 struct kvm_mmu_page *sp;
3447 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3449 if (mmu_check_root(vcpu, root_gfn))
3453 * Do we shadow a long mode page table? If so we need to
3454 * write-protect the guests page table root.
3456 if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) {
3457 hpa_t root = vcpu->arch.mmu.root_hpa;
3459 MMU_WARN_ON(VALID_PAGE(root));
3461 spin_lock(&vcpu->kvm->mmu_lock);
3462 if (make_mmu_pages_available(vcpu) < 0) {
3463 spin_unlock(&vcpu->kvm->mmu_lock);
3466 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
3467 vcpu->arch.mmu.shadow_root_level, 0, ACC_ALL);
3468 root = __pa(sp->spt);
3470 spin_unlock(&vcpu->kvm->mmu_lock);
3471 vcpu->arch.mmu.root_hpa = root;
3476 * We shadow a 32 bit page table. This may be a legacy 2-level
3477 * or a PAE 3-level page table. In either case we need to be aware that
3478 * the shadow page table may be a PAE or a long mode page table.
3480 pm_mask = PT_PRESENT_MASK;
3481 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL)
3482 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3484 for (i = 0; i < 4; ++i) {
3485 hpa_t root = vcpu->arch.mmu.pae_root[i];
3487 MMU_WARN_ON(VALID_PAGE(root));
3488 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3489 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3490 if (!(pdptr & PT_PRESENT_MASK)) {
3491 vcpu->arch.mmu.pae_root[i] = 0;
3494 root_gfn = pdptr >> PAGE_SHIFT;
3495 if (mmu_check_root(vcpu, root_gfn))
3498 spin_lock(&vcpu->kvm->mmu_lock);
3499 if (make_mmu_pages_available(vcpu) < 0) {
3500 spin_unlock(&vcpu->kvm->mmu_lock);
3503 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3505 root = __pa(sp->spt);
3507 spin_unlock(&vcpu->kvm->mmu_lock);
3509 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3511 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3514 * If we shadow a 32 bit page table with a long mode page
3515 * table we enter this path.
3517 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL) {
3518 if (vcpu->arch.mmu.lm_root == NULL) {
3520 * The additional page necessary for this is only
3521 * allocated on demand.
3526 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3527 if (lm_root == NULL)
3530 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3532 vcpu->arch.mmu.lm_root = lm_root;
3535 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3541 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3543 if (vcpu->arch.mmu.direct_map)
3544 return mmu_alloc_direct_roots(vcpu);
3546 return mmu_alloc_shadow_roots(vcpu);
3549 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3552 struct kvm_mmu_page *sp;
3554 if (vcpu->arch.mmu.direct_map)
3557 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3560 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3561 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3562 if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) {
3563 hpa_t root = vcpu->arch.mmu.root_hpa;
3564 sp = page_header(root);
3565 mmu_sync_children(vcpu, sp);
3566 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3569 for (i = 0; i < 4; ++i) {
3570 hpa_t root = vcpu->arch.mmu.pae_root[i];
3572 if (root && VALID_PAGE(root)) {
3573 root &= PT64_BASE_ADDR_MASK;
3574 sp = page_header(root);
3575 mmu_sync_children(vcpu, sp);
3578 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3581 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3583 spin_lock(&vcpu->kvm->mmu_lock);
3584 mmu_sync_roots(vcpu);
3585 spin_unlock(&vcpu->kvm->mmu_lock);
3587 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3589 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3590 u32 access, struct x86_exception *exception)
3593 exception->error_code = 0;
3597 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3599 struct x86_exception *exception)
3602 exception->error_code = 0;
3603 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3607 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3609 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3611 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3612 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3615 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3617 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3620 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3622 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3625 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3628 * A nested guest cannot use the MMIO cache if it is using nested
3629 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3631 if (mmu_is_nested(vcpu))
3635 return vcpu_match_mmio_gpa(vcpu, addr);
3637 return vcpu_match_mmio_gva(vcpu, addr);
3640 /* return true if reserved bit is detected on spte. */
3642 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3644 struct kvm_shadow_walk_iterator iterator;
3645 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3647 bool reserved = false;
3649 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3652 walk_shadow_page_lockless_begin(vcpu);
3654 for (shadow_walk_init(&iterator, vcpu, addr),
3655 leaf = root = iterator.level;
3656 shadow_walk_okay(&iterator);
3657 __shadow_walk_next(&iterator, spte)) {
3658 spte = mmu_spte_get_lockless(iterator.sptep);
3660 sptes[leaf - 1] = spte;
3663 if (!is_shadow_present_pte(spte))
3666 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3670 walk_shadow_page_lockless_end(vcpu);
3673 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3675 while (root > leaf) {
3676 pr_err("------ spte 0x%llx level %d.\n",
3677 sptes[root - 1], root);
3686 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3691 if (mmio_info_in_cache(vcpu, addr, direct))
3692 return RET_PF_EMULATE;
3694 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3695 if (WARN_ON(reserved))
3698 if (is_mmio_spte(spte)) {
3699 gfn_t gfn = get_mmio_spte_gfn(spte);
3700 unsigned access = get_mmio_spte_access(spte);
3702 if (!check_mmio_spte(vcpu, spte))
3703 return RET_PF_INVALID;
3708 trace_handle_mmio_page_fault(addr, gfn, access);
3709 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3710 return RET_PF_EMULATE;
3714 * If the page table is zapped by other cpus, let CPU fault again on
3717 return RET_PF_RETRY;
3720 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3721 u32 error_code, gfn_t gfn)
3723 if (unlikely(error_code & PFERR_RSVD_MASK))
3726 if (!(error_code & PFERR_PRESENT_MASK) ||
3727 !(error_code & PFERR_WRITE_MASK))
3731 * guest is writing the page which is write tracked which can
3732 * not be fixed by page fault handler.
3734 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3740 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3742 struct kvm_shadow_walk_iterator iterator;
3745 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3748 walk_shadow_page_lockless_begin(vcpu);
3749 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3750 clear_sp_write_flooding_count(iterator.sptep);
3751 if (!is_shadow_present_pte(spte))
3754 walk_shadow_page_lockless_end(vcpu);
3757 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3758 u32 error_code, bool prefault)
3760 gfn_t gfn = gva >> PAGE_SHIFT;
3763 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3765 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3766 return RET_PF_EMULATE;
3768 r = mmu_topup_memory_caches(vcpu);
3772 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3775 return nonpaging_map(vcpu, gva & PAGE_MASK,
3776 error_code, gfn, prefault);
3779 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3781 struct kvm_arch_async_pf arch;
3783 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3785 arch.direct_map = vcpu->arch.mmu.direct_map;
3786 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3788 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3791 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
3793 if (unlikely(!lapic_in_kernel(vcpu) ||
3794 kvm_event_needs_reinjection(vcpu) ||
3795 vcpu->arch.exception.pending))
3798 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
3801 return kvm_x86_ops->interrupt_allowed(vcpu);
3804 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3805 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3807 struct kvm_memory_slot *slot;
3811 * Don't expose private memslots to L2.
3813 if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) {
3814 *pfn = KVM_PFN_NOSLOT;
3818 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3820 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3822 return false; /* *pfn has correct page already */
3824 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3825 trace_kvm_try_async_get_page(gva, gfn);
3826 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3827 trace_kvm_async_pf_doublefault(gva, gfn);
3828 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3830 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3834 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3838 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3839 u64 fault_address, char *insn, int insn_len)
3843 switch (vcpu->arch.apf.host_apf_reason) {
3845 trace_kvm_page_fault(fault_address, error_code);
3847 if (kvm_event_needs_reinjection(vcpu))
3848 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3849 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3852 case KVM_PV_REASON_PAGE_NOT_PRESENT:
3853 vcpu->arch.apf.host_apf_reason = 0;
3854 local_irq_disable();
3855 kvm_async_pf_task_wait(fault_address, 0);
3858 case KVM_PV_REASON_PAGE_READY:
3859 vcpu->arch.apf.host_apf_reason = 0;
3860 local_irq_disable();
3861 kvm_async_pf_task_wake(fault_address);
3867 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3870 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3872 int page_num = KVM_PAGES_PER_HPAGE(level);
3874 gfn &= ~(page_num - 1);
3876 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3879 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3885 bool force_pt_level;
3886 gfn_t gfn = gpa >> PAGE_SHIFT;
3887 unsigned long mmu_seq;
3888 int write = error_code & PFERR_WRITE_MASK;
3891 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3893 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3894 return RET_PF_EMULATE;
3896 r = mmu_topup_memory_caches(vcpu);
3900 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3901 PT_DIRECTORY_LEVEL);
3902 level = mapping_level(vcpu, gfn, &force_pt_level);
3903 if (likely(!force_pt_level)) {
3904 if (level > PT_DIRECTORY_LEVEL &&
3905 !check_hugepage_cache_consistency(vcpu, gfn, level))
3906 level = PT_DIRECTORY_LEVEL;
3907 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3910 if (fast_page_fault(vcpu, gpa, level, error_code))
3911 return RET_PF_RETRY;
3913 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3916 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3917 return RET_PF_RETRY;
3919 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3922 spin_lock(&vcpu->kvm->mmu_lock);
3923 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3925 if (make_mmu_pages_available(vcpu) < 0)
3927 if (likely(!force_pt_level))
3928 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3929 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3930 spin_unlock(&vcpu->kvm->mmu_lock);
3935 spin_unlock(&vcpu->kvm->mmu_lock);
3936 kvm_release_pfn_clean(pfn);
3937 return RET_PF_RETRY;
3940 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3941 struct kvm_mmu *context)
3943 context->page_fault = nonpaging_page_fault;
3944 context->gva_to_gpa = nonpaging_gva_to_gpa;
3945 context->sync_page = nonpaging_sync_page;
3946 context->invlpg = nonpaging_invlpg;
3947 context->update_pte = nonpaging_update_pte;
3948 context->root_level = 0;
3949 context->shadow_root_level = PT32E_ROOT_LEVEL;
3950 context->root_hpa = INVALID_PAGE;
3951 context->direct_map = true;
3952 context->nx = false;
3955 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3957 kvm_mmu_free_roots(vcpu);
3960 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3962 return kvm_read_cr3(vcpu);
3965 static void inject_page_fault(struct kvm_vcpu *vcpu,
3966 struct x86_exception *fault)
3968 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3971 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3972 unsigned access, int *nr_present)
3974 if (unlikely(is_mmio_spte(*sptep))) {
3975 if (gfn != get_mmio_spte_gfn(*sptep)) {
3976 mmu_spte_clear_no_track(sptep);
3981 mark_mmio_spte(vcpu, sptep, gfn, access);
3988 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3989 unsigned level, unsigned gpte)
3992 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3993 * If it is clear, there are no large pages at this level, so clear
3994 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3996 gpte &= level - mmu->last_nonleaf_level;
3999 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
4000 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4001 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4003 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
4005 return gpte & PT_PAGE_SIZE_MASK;
4008 #define PTTYPE_EPT 18 /* arbitrary */
4009 #define PTTYPE PTTYPE_EPT
4010 #include "paging_tmpl.h"
4014 #include "paging_tmpl.h"
4018 #include "paging_tmpl.h"
4022 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4023 struct rsvd_bits_validate *rsvd_check,
4024 int maxphyaddr, int level, bool nx, bool gbpages,
4027 u64 exb_bit_rsvd = 0;
4028 u64 gbpages_bit_rsvd = 0;
4029 u64 nonleaf_bit8_rsvd = 0;
4031 rsvd_check->bad_mt_xwr = 0;
4034 exb_bit_rsvd = rsvd_bits(63, 63);
4036 gbpages_bit_rsvd = rsvd_bits(7, 7);
4039 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4040 * leaf entries) on AMD CPUs only.
4043 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4046 case PT32_ROOT_LEVEL:
4047 /* no rsvd bits for 2 level 4K page table entries */
4048 rsvd_check->rsvd_bits_mask[0][1] = 0;
4049 rsvd_check->rsvd_bits_mask[0][0] = 0;
4050 rsvd_check->rsvd_bits_mask[1][0] =
4051 rsvd_check->rsvd_bits_mask[0][0];
4054 rsvd_check->rsvd_bits_mask[1][1] = 0;
4058 if (is_cpuid_PSE36())
4059 /* 36bits PSE 4MB page */
4060 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4062 /* 32 bits PSE 4MB page */
4063 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4065 case PT32E_ROOT_LEVEL:
4066 rsvd_check->rsvd_bits_mask[0][2] =
4067 rsvd_bits(maxphyaddr, 63) |
4068 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4069 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4070 rsvd_bits(maxphyaddr, 62); /* PDE */
4071 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4072 rsvd_bits(maxphyaddr, 62); /* PTE */
4073 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4074 rsvd_bits(maxphyaddr, 62) |
4075 rsvd_bits(13, 20); /* large page */
4076 rsvd_check->rsvd_bits_mask[1][0] =
4077 rsvd_check->rsvd_bits_mask[0][0];
4079 case PT64_ROOT_5LEVEL:
4080 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4081 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4082 rsvd_bits(maxphyaddr, 51);
4083 rsvd_check->rsvd_bits_mask[1][4] =
4084 rsvd_check->rsvd_bits_mask[0][4];
4085 case PT64_ROOT_4LEVEL:
4086 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4087 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4088 rsvd_bits(maxphyaddr, 51);
4089 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4090 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4091 rsvd_bits(maxphyaddr, 51);
4092 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4093 rsvd_bits(maxphyaddr, 51);
4094 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4095 rsvd_bits(maxphyaddr, 51);
4096 rsvd_check->rsvd_bits_mask[1][3] =
4097 rsvd_check->rsvd_bits_mask[0][3];
4098 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4099 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4101 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4102 rsvd_bits(maxphyaddr, 51) |
4103 rsvd_bits(13, 20); /* large page */
4104 rsvd_check->rsvd_bits_mask[1][0] =
4105 rsvd_check->rsvd_bits_mask[0][0];
4110 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4111 struct kvm_mmu *context)
4113 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4114 cpuid_maxphyaddr(vcpu), context->root_level,
4116 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4117 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4121 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4122 int maxphyaddr, bool execonly)
4126 rsvd_check->rsvd_bits_mask[0][4] =
4127 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4128 rsvd_check->rsvd_bits_mask[0][3] =
4129 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4130 rsvd_check->rsvd_bits_mask[0][2] =
4131 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4132 rsvd_check->rsvd_bits_mask[0][1] =
4133 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4134 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4137 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4138 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4139 rsvd_check->rsvd_bits_mask[1][2] =
4140 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4141 rsvd_check->rsvd_bits_mask[1][1] =
4142 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4143 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4145 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4146 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4147 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4148 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4149 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4151 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4152 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4154 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4157 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4158 struct kvm_mmu *context, bool execonly)
4160 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4161 cpuid_maxphyaddr(vcpu), execonly);
4165 * the page table on host is the shadow page table for the page
4166 * table in guest or amd nested guest, its mmu features completely
4167 * follow the features in guest.
4170 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4172 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
4173 struct rsvd_bits_validate *shadow_zero_check;
4177 * Passing "true" to the last argument is okay; it adds a check
4178 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4180 shadow_zero_check = &context->shadow_zero_check;
4181 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4182 boot_cpu_data.x86_phys_bits,
4183 context->shadow_root_level, uses_nx,
4184 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4185 is_pse(vcpu), true);
4187 if (!shadow_me_mask)
4190 for (i = context->shadow_root_level; --i >= 0;) {
4191 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4192 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4196 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4198 static inline bool boot_cpu_is_amd(void)
4200 WARN_ON_ONCE(!tdp_enabled);
4201 return shadow_x_mask == 0;
4205 * the direct page table on host, use as much mmu features as
4206 * possible, however, kvm currently does not do execution-protection.
4209 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4210 struct kvm_mmu *context)
4212 struct rsvd_bits_validate *shadow_zero_check;
4215 shadow_zero_check = &context->shadow_zero_check;
4217 if (boot_cpu_is_amd())
4218 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4219 boot_cpu_data.x86_phys_bits,
4220 context->shadow_root_level, false,
4221 boot_cpu_has(X86_FEATURE_GBPAGES),
4224 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4225 boot_cpu_data.x86_phys_bits,
4228 if (!shadow_me_mask)
4231 for (i = context->shadow_root_level; --i >= 0;) {
4232 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4233 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4238 * as the comments in reset_shadow_zero_bits_mask() except it
4239 * is the shadow page table for intel nested guest.
4242 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4243 struct kvm_mmu *context, bool execonly)
4245 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4246 boot_cpu_data.x86_phys_bits, execonly);
4249 #define BYTE_MASK(access) \
4250 ((1 & (access) ? 2 : 0) | \
4251 (2 & (access) ? 4 : 0) | \
4252 (3 & (access) ? 8 : 0) | \
4253 (4 & (access) ? 16 : 0) | \
4254 (5 & (access) ? 32 : 0) | \
4255 (6 & (access) ? 64 : 0) | \
4256 (7 & (access) ? 128 : 0))
4259 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4260 struct kvm_mmu *mmu, bool ept)
4264 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4265 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4266 const u8 u = BYTE_MASK(ACC_USER_MASK);
4268 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4269 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4270 bool cr0_wp = is_write_protection(vcpu);
4272 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4273 unsigned pfec = byte << 1;
4276 * Each "*f" variable has a 1 bit for each UWX value
4277 * that causes a fault with the given PFEC.
4280 /* Faults from writes to non-writable pages */
4281 u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0;
4282 /* Faults from user mode accesses to supervisor pages */
4283 u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0;
4284 /* Faults from fetches of non-executable pages*/
4285 u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0;
4286 /* Faults from kernel mode fetches of user pages */
4288 /* Faults from kernel mode accesses of user pages */
4292 /* Faults from kernel mode accesses to user pages */
4293 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4295 /* Not really needed: !nx will cause pte.nx to fault */
4299 /* Allow supervisor writes if !cr0.wp */
4301 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4303 /* Disallow supervisor fetches of user code if cr4.smep */
4305 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4308 * SMAP:kernel-mode data accesses from user-mode
4309 * mappings should fault. A fault is considered
4310 * as a SMAP violation if all of the following
4311 * conditions are ture:
4312 * - X86_CR4_SMAP is set in CR4
4313 * - A user page is accessed
4314 * - The access is not a fetch
4315 * - Page fault in kernel mode
4316 * - if CPL = 3 or X86_EFLAGS_AC is clear
4318 * Here, we cover the first three conditions.
4319 * The fourth is computed dynamically in permission_fault();
4320 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4321 * *not* subject to SMAP restrictions.
4324 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4327 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4332 * PKU is an additional mechanism by which the paging controls access to
4333 * user-mode addresses based on the value in the PKRU register. Protection
4334 * key violations are reported through a bit in the page fault error code.
4335 * Unlike other bits of the error code, the PK bit is not known at the
4336 * call site of e.g. gva_to_gpa; it must be computed directly in
4337 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4338 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4340 * In particular the following conditions come from the error code, the
4341 * page tables and the machine state:
4342 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4343 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4344 * - PK is always zero if U=0 in the page tables
4345 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4347 * The PKRU bitmask caches the result of these four conditions. The error
4348 * code (minus the P bit) and the page table's U bit form an index into the
4349 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4350 * with the two bits of the PKRU register corresponding to the protection key.
4351 * For the first three conditions above the bits will be 00, thus masking
4352 * away both AD and WD. For all reads or if the last condition holds, WD
4353 * only will be masked away.
4355 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4366 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4367 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4372 wp = is_write_protection(vcpu);
4374 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4375 unsigned pfec, pkey_bits;
4376 bool check_pkey, check_write, ff, uf, wf, pte_user;
4379 ff = pfec & PFERR_FETCH_MASK;
4380 uf = pfec & PFERR_USER_MASK;
4381 wf = pfec & PFERR_WRITE_MASK;
4383 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4384 pte_user = pfec & PFERR_RSVD_MASK;
4387 * Only need to check the access which is not an
4388 * instruction fetch and is to a user page.
4390 check_pkey = (!ff && pte_user);
4392 * write access is controlled by PKRU if it is a
4393 * user access or CR0.WP = 1.
4395 check_write = check_pkey && wf && (uf || wp);
4397 /* PKRU.AD stops both read and write access. */
4398 pkey_bits = !!check_pkey;
4399 /* PKRU.WD stops write access. */
4400 pkey_bits |= (!!check_write) << 1;
4402 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4406 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4408 unsigned root_level = mmu->root_level;
4410 mmu->last_nonleaf_level = root_level;
4411 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4412 mmu->last_nonleaf_level++;
4415 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4416 struct kvm_mmu *context,
4419 context->nx = is_nx(vcpu);
4420 context->root_level = level;
4422 reset_rsvds_bits_mask(vcpu, context);
4423 update_permission_bitmask(vcpu, context, false);
4424 update_pkru_bitmask(vcpu, context, false);
4425 update_last_nonleaf_level(vcpu, context);
4427 MMU_WARN_ON(!is_pae(vcpu));
4428 context->page_fault = paging64_page_fault;
4429 context->gva_to_gpa = paging64_gva_to_gpa;
4430 context->sync_page = paging64_sync_page;
4431 context->invlpg = paging64_invlpg;
4432 context->update_pte = paging64_update_pte;
4433 context->shadow_root_level = level;
4434 context->root_hpa = INVALID_PAGE;
4435 context->direct_map = false;
4438 static void paging64_init_context(struct kvm_vcpu *vcpu,
4439 struct kvm_mmu *context)
4441 int root_level = is_la57_mode(vcpu) ?
4442 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4444 paging64_init_context_common(vcpu, context, root_level);
4447 static void paging32_init_context(struct kvm_vcpu *vcpu,
4448 struct kvm_mmu *context)
4450 context->nx = false;
4451 context->root_level = PT32_ROOT_LEVEL;
4453 reset_rsvds_bits_mask(vcpu, context);
4454 update_permission_bitmask(vcpu, context, false);
4455 update_pkru_bitmask(vcpu, context, false);
4456 update_last_nonleaf_level(vcpu, context);
4458 context->page_fault = paging32_page_fault;
4459 context->gva_to_gpa = paging32_gva_to_gpa;
4460 context->sync_page = paging32_sync_page;
4461 context->invlpg = paging32_invlpg;
4462 context->update_pte = paging32_update_pte;
4463 context->shadow_root_level = PT32E_ROOT_LEVEL;
4464 context->root_hpa = INVALID_PAGE;
4465 context->direct_map = false;
4468 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4469 struct kvm_mmu *context)
4471 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4474 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4476 struct kvm_mmu *context = &vcpu->arch.mmu;
4478 context->base_role.word = 0;
4479 context->base_role.guest_mode = is_guest_mode(vcpu);
4480 context->base_role.smm = is_smm(vcpu);
4481 context->base_role.ad_disabled = (shadow_accessed_mask == 0);
4482 context->page_fault = tdp_page_fault;
4483 context->sync_page = nonpaging_sync_page;
4484 context->invlpg = nonpaging_invlpg;
4485 context->update_pte = nonpaging_update_pte;
4486 context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu);
4487 context->root_hpa = INVALID_PAGE;
4488 context->direct_map = true;
4489 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4490 context->get_cr3 = get_cr3;
4491 context->get_pdptr = kvm_pdptr_read;
4492 context->inject_page_fault = kvm_inject_page_fault;
4494 if (!is_paging(vcpu)) {
4495 context->nx = false;
4496 context->gva_to_gpa = nonpaging_gva_to_gpa;
4497 context->root_level = 0;
4498 } else if (is_long_mode(vcpu)) {
4499 context->nx = is_nx(vcpu);
4500 context->root_level = is_la57_mode(vcpu) ?
4501 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4502 reset_rsvds_bits_mask(vcpu, context);
4503 context->gva_to_gpa = paging64_gva_to_gpa;
4504 } else if (is_pae(vcpu)) {
4505 context->nx = is_nx(vcpu);
4506 context->root_level = PT32E_ROOT_LEVEL;
4507 reset_rsvds_bits_mask(vcpu, context);
4508 context->gva_to_gpa = paging64_gva_to_gpa;
4510 context->nx = false;
4511 context->root_level = PT32_ROOT_LEVEL;
4512 reset_rsvds_bits_mask(vcpu, context);
4513 context->gva_to_gpa = paging32_gva_to_gpa;
4516 update_permission_bitmask(vcpu, context, false);
4517 update_pkru_bitmask(vcpu, context, false);
4518 update_last_nonleaf_level(vcpu, context);
4519 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4522 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4524 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4525 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4526 struct kvm_mmu *context = &vcpu->arch.mmu;
4528 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4530 if (!is_paging(vcpu))
4531 nonpaging_init_context(vcpu, context);
4532 else if (is_long_mode(vcpu))
4533 paging64_init_context(vcpu, context);
4534 else if (is_pae(vcpu))
4535 paging32E_init_context(vcpu, context);
4537 paging32_init_context(vcpu, context);
4539 context->base_role.nxe = is_nx(vcpu);
4540 context->base_role.cr4_pae = !!is_pae(vcpu);
4541 context->base_role.cr0_wp = is_write_protection(vcpu);
4542 context->base_role.smep_andnot_wp
4543 = smep && !is_write_protection(vcpu);
4544 context->base_role.smap_andnot_wp
4545 = smap && !is_write_protection(vcpu);
4546 context->base_role.guest_mode = is_guest_mode(vcpu);
4547 context->base_role.smm = is_smm(vcpu);
4548 reset_shadow_zero_bits_mask(vcpu, context);
4550 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4552 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4553 bool accessed_dirty)
4555 struct kvm_mmu *context = &vcpu->arch.mmu;
4557 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4559 context->shadow_root_level = PT64_ROOT_4LEVEL;
4562 context->ept_ad = accessed_dirty;
4563 context->page_fault = ept_page_fault;
4564 context->gva_to_gpa = ept_gva_to_gpa;
4565 context->sync_page = ept_sync_page;
4566 context->invlpg = ept_invlpg;
4567 context->update_pte = ept_update_pte;
4568 context->root_level = PT64_ROOT_4LEVEL;
4569 context->root_hpa = INVALID_PAGE;
4570 context->direct_map = false;
4571 context->base_role.ad_disabled = !accessed_dirty;
4572 context->base_role.guest_mode = 1;
4573 update_permission_bitmask(vcpu, context, true);
4574 update_pkru_bitmask(vcpu, context, true);
4575 update_last_nonleaf_level(vcpu, context);
4576 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4577 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4579 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4581 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4583 struct kvm_mmu *context = &vcpu->arch.mmu;
4585 kvm_init_shadow_mmu(vcpu);
4586 context->set_cr3 = kvm_x86_ops->set_cr3;
4587 context->get_cr3 = get_cr3;
4588 context->get_pdptr = kvm_pdptr_read;
4589 context->inject_page_fault = kvm_inject_page_fault;
4592 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4594 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4596 g_context->get_cr3 = get_cr3;
4597 g_context->get_pdptr = kvm_pdptr_read;
4598 g_context->inject_page_fault = kvm_inject_page_fault;
4601 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4602 * L1's nested page tables (e.g. EPT12). The nested translation
4603 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4604 * L2's page tables as the first level of translation and L1's
4605 * nested page tables as the second level of translation. Basically
4606 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4608 if (!is_paging(vcpu)) {
4609 g_context->nx = false;
4610 g_context->root_level = 0;
4611 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4612 } else if (is_long_mode(vcpu)) {
4613 g_context->nx = is_nx(vcpu);
4614 g_context->root_level = is_la57_mode(vcpu) ?
4615 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4616 reset_rsvds_bits_mask(vcpu, g_context);
4617 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4618 } else if (is_pae(vcpu)) {
4619 g_context->nx = is_nx(vcpu);
4620 g_context->root_level = PT32E_ROOT_LEVEL;
4621 reset_rsvds_bits_mask(vcpu, g_context);
4622 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4624 g_context->nx = false;
4625 g_context->root_level = PT32_ROOT_LEVEL;
4626 reset_rsvds_bits_mask(vcpu, g_context);
4627 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4630 update_permission_bitmask(vcpu, g_context, false);
4631 update_pkru_bitmask(vcpu, g_context, false);
4632 update_last_nonleaf_level(vcpu, g_context);
4635 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4637 if (mmu_is_nested(vcpu))
4638 init_kvm_nested_mmu(vcpu);
4639 else if (tdp_enabled)
4640 init_kvm_tdp_mmu(vcpu);
4642 init_kvm_softmmu(vcpu);
4645 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4647 kvm_mmu_unload(vcpu);
4650 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4652 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4656 r = mmu_topup_memory_caches(vcpu);
4659 r = mmu_alloc_roots(vcpu);
4660 kvm_mmu_sync_roots(vcpu);
4663 /* set_cr3() should ensure TLB has been flushed */
4664 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4668 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4670 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4672 kvm_mmu_free_roots(vcpu);
4673 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4675 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4677 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4678 struct kvm_mmu_page *sp, u64 *spte,
4681 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4682 ++vcpu->kvm->stat.mmu_pde_zapped;
4686 ++vcpu->kvm->stat.mmu_pte_updated;
4687 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4690 static bool need_remote_flush(u64 old, u64 new)
4692 if (!is_shadow_present_pte(old))
4694 if (!is_shadow_present_pte(new))
4696 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4698 old ^= shadow_nx_mask;
4699 new ^= shadow_nx_mask;
4700 return (old & ~new & PT64_PERM_MASK) != 0;
4703 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4704 const u8 *new, int *bytes)
4710 * Assume that the pte write on a page table of the same type
4711 * as the current vcpu paging mode since we update the sptes only
4712 * when they have the same mode.
4714 if (is_pae(vcpu) && *bytes == 4) {
4715 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4718 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4721 new = (const u8 *)&gentry;
4726 gentry = *(const u32 *)new;
4729 gentry = *(const u64 *)new;
4740 * If we're seeing too many writes to a page, it may no longer be a page table,
4741 * or we may be forking, in which case it is better to unmap the page.
4743 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4746 * Skip write-flooding detected for the sp whose level is 1, because
4747 * it can become unsync, then the guest page is not write-protected.
4749 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4752 atomic_inc(&sp->write_flooding_count);
4753 return atomic_read(&sp->write_flooding_count) >= 3;
4757 * Misaligned accesses are too much trouble to fix up; also, they usually
4758 * indicate a page is not used as a page table.
4760 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4763 unsigned offset, pte_size, misaligned;
4765 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4766 gpa, bytes, sp->role.word);
4768 offset = offset_in_page(gpa);
4769 pte_size = sp->role.cr4_pae ? 8 : 4;
4772 * Sometimes, the OS only writes the last one bytes to update status
4773 * bits, for example, in linux, andb instruction is used in clear_bit().
4775 if (!(offset & (pte_size - 1)) && bytes == 1)
4778 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4779 misaligned |= bytes < 4;
4784 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4786 unsigned page_offset, quadrant;
4790 page_offset = offset_in_page(gpa);
4791 level = sp->role.level;
4793 if (!sp->role.cr4_pae) {
4794 page_offset <<= 1; /* 32->64 */
4796 * A 32-bit pde maps 4MB while the shadow pdes map
4797 * only 2MB. So we need to double the offset again
4798 * and zap two pdes instead of one.
4800 if (level == PT32_ROOT_LEVEL) {
4801 page_offset &= ~7; /* kill rounding error */
4805 quadrant = page_offset >> PAGE_SHIFT;
4806 page_offset &= ~PAGE_MASK;
4807 if (quadrant != sp->role.quadrant)
4811 spte = &sp->spt[page_offset / sizeof(*spte)];
4815 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4816 const u8 *new, int bytes,
4817 struct kvm_page_track_notifier_node *node)
4819 gfn_t gfn = gpa >> PAGE_SHIFT;
4820 struct kvm_mmu_page *sp;
4821 LIST_HEAD(invalid_list);
4822 u64 entry, gentry, *spte;
4824 bool remote_flush, local_flush;
4825 union kvm_mmu_page_role mask = { };
4830 mask.smep_andnot_wp = 1;
4831 mask.smap_andnot_wp = 1;
4833 mask.guest_mode = 1;
4834 mask.ad_disabled = 1;
4837 * If we don't have indirect shadow pages, it means no page is
4838 * write-protected, so we can exit simply.
4840 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4843 remote_flush = local_flush = false;
4845 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4847 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4850 * No need to care whether allocation memory is successful
4851 * or not since pte prefetch is skiped if it does not have
4852 * enough objects in the cache.
4854 mmu_topup_memory_caches(vcpu);
4856 spin_lock(&vcpu->kvm->mmu_lock);
4857 ++vcpu->kvm->stat.mmu_pte_write;
4858 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4860 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4861 if (detect_write_misaligned(sp, gpa, bytes) ||
4862 detect_write_flooding(sp)) {
4863 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4864 ++vcpu->kvm->stat.mmu_flooded;
4868 spte = get_written_sptes(sp, gpa, &npte);
4875 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4877 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4878 & mask.word) && rmap_can_add(vcpu))
4879 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4880 if (need_remote_flush(entry, *spte))
4881 remote_flush = true;
4885 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4886 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4887 spin_unlock(&vcpu->kvm->mmu_lock);
4890 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4895 if (vcpu->arch.mmu.direct_map)
4898 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4900 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4904 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4906 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
4908 LIST_HEAD(invalid_list);
4910 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4913 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4914 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4917 ++vcpu->kvm->stat.mmu_recycled;
4919 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4921 if (!kvm_mmu_available_pages(vcpu->kvm))
4926 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
4927 void *insn, int insn_len)
4929 int r, emulation_type = EMULTYPE_RETRY;
4930 enum emulation_result er;
4931 bool direct = vcpu->arch.mmu.direct_map;
4933 /* With shadow page tables, fault_address contains a GVA or nGPA. */
4934 if (vcpu->arch.mmu.direct_map) {
4935 vcpu->arch.gpa_available = true;
4936 vcpu->arch.gpa_val = cr2;
4940 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4941 r = handle_mmio_page_fault(vcpu, cr2, direct);
4942 if (r == RET_PF_EMULATE) {
4948 if (r == RET_PF_INVALID) {
4949 r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code),
4951 WARN_ON(r == RET_PF_INVALID);
4954 if (r == RET_PF_RETRY)
4960 * Before emulating the instruction, check if the error code
4961 * was due to a RO violation while translating the guest page.
4962 * This can occur when using nested virtualization with nested
4963 * paging in both guests. If true, we simply unprotect the page
4964 * and resume the guest.
4966 if (vcpu->arch.mmu.direct_map &&
4967 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
4968 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
4972 if (mmio_info_in_cache(vcpu, cr2, direct))
4976 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
4977 * This can happen if a guest gets a page-fault on data access but the HW
4978 * table walker is not able to read the instruction page (e.g instruction
4979 * page is not present in memory). In those cases we simply restart the
4982 if (unlikely(insn && !insn_len))
4985 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4990 case EMULATE_USER_EXIT:
4991 ++vcpu->stat.mmio_exits;
4999 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5001 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5003 vcpu->arch.mmu.invlpg(vcpu, gva);
5004 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5005 ++vcpu->stat.invlpg;
5007 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5009 void kvm_enable_tdp(void)
5013 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
5015 void kvm_disable_tdp(void)
5017 tdp_enabled = false;
5019 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
5021 static void free_mmu_pages(struct kvm_vcpu *vcpu)
5023 free_page((unsigned long)vcpu->arch.mmu.pae_root);
5024 free_page((unsigned long)vcpu->arch.mmu.lm_root);
5027 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
5033 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
5034 * Therefore we need to allocate shadow page tables in the first
5035 * 4GB of memory, which happens to fit the DMA32 zone.
5037 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
5041 vcpu->arch.mmu.pae_root = page_address(page);
5042 for (i = 0; i < 4; ++i)
5043 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
5048 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5050 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
5051 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
5052 vcpu->arch.mmu.translate_gpa = translate_gpa;
5053 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5055 return alloc_mmu_pages(vcpu);
5058 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
5060 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
5065 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5066 struct kvm_memory_slot *slot,
5067 struct kvm_page_track_notifier_node *node)
5069 kvm_mmu_invalidate_zap_all_pages(kvm);
5072 void kvm_mmu_init_vm(struct kvm *kvm)
5074 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5076 node->track_write = kvm_mmu_pte_write;
5077 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5078 kvm_page_track_register_notifier(kvm, node);
5081 void kvm_mmu_uninit_vm(struct kvm *kvm)
5083 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5085 kvm_page_track_unregister_notifier(kvm, node);
5088 /* The return value indicates if tlb flush on all vcpus is needed. */
5089 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5091 /* The caller should hold mmu-lock before calling this function. */
5092 static __always_inline bool
5093 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5094 slot_level_handler fn, int start_level, int end_level,
5095 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5097 struct slot_rmap_walk_iterator iterator;
5100 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5101 end_gfn, &iterator) {
5103 flush |= fn(kvm, iterator.rmap);
5105 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5106 if (flush && lock_flush_tlb) {
5107 kvm_flush_remote_tlbs(kvm);
5110 cond_resched_lock(&kvm->mmu_lock);
5114 if (flush && lock_flush_tlb) {
5115 kvm_flush_remote_tlbs(kvm);
5122 static __always_inline bool
5123 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5124 slot_level_handler fn, int start_level, int end_level,
5125 bool lock_flush_tlb)
5127 return slot_handle_level_range(kvm, memslot, fn, start_level,
5128 end_level, memslot->base_gfn,
5129 memslot->base_gfn + memslot->npages - 1,
5133 static __always_inline bool
5134 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5135 slot_level_handler fn, bool lock_flush_tlb)
5137 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5138 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5141 static __always_inline bool
5142 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5143 slot_level_handler fn, bool lock_flush_tlb)
5145 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5146 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5149 static __always_inline bool
5150 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5151 slot_level_handler fn, bool lock_flush_tlb)
5153 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5154 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5157 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5159 struct kvm_memslots *slots;
5160 struct kvm_memory_slot *memslot;
5163 spin_lock(&kvm->mmu_lock);
5164 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5165 slots = __kvm_memslots(kvm, i);
5166 kvm_for_each_memslot(memslot, slots) {
5169 start = max(gfn_start, memslot->base_gfn);
5170 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5174 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5175 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5176 start, end - 1, true);
5180 spin_unlock(&kvm->mmu_lock);
5183 static bool slot_rmap_write_protect(struct kvm *kvm,
5184 struct kvm_rmap_head *rmap_head)
5186 return __rmap_write_protect(kvm, rmap_head, false);
5189 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5190 struct kvm_memory_slot *memslot)
5194 spin_lock(&kvm->mmu_lock);
5195 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5197 spin_unlock(&kvm->mmu_lock);
5200 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5201 * which do tlb flush out of mmu-lock should be serialized by
5202 * kvm->slots_lock otherwise tlb flush would be missed.
5204 lockdep_assert_held(&kvm->slots_lock);
5207 * We can flush all the TLBs out of the mmu lock without TLB
5208 * corruption since we just change the spte from writable to
5209 * readonly so that we only need to care the case of changing
5210 * spte from present to present (changing the spte from present
5211 * to nonpresent will flush all the TLBs immediately), in other
5212 * words, the only case we care is mmu_spte_update() where we
5213 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5214 * instead of PT_WRITABLE_MASK, that means it does not depend
5215 * on PT_WRITABLE_MASK anymore.
5218 kvm_flush_remote_tlbs(kvm);
5221 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5222 struct kvm_rmap_head *rmap_head)
5225 struct rmap_iterator iter;
5226 int need_tlb_flush = 0;
5228 struct kvm_mmu_page *sp;
5231 for_each_rmap_spte(rmap_head, &iter, sptep) {
5232 sp = page_header(__pa(sptep));
5233 pfn = spte_to_pfn(*sptep);
5236 * We cannot do huge page mapping for indirect shadow pages,
5237 * which are found on the last rmap (level = 1) when not using
5238 * tdp; such shadow pages are synced with the page table in
5239 * the guest, and the guest page table is using 4K page size
5240 * mapping if the indirect sp has level = 1.
5242 if (sp->role.direct &&
5243 !kvm_is_reserved_pfn(pfn) &&
5244 PageTransCompoundMap(pfn_to_page(pfn))) {
5245 drop_spte(kvm, sptep);
5251 return need_tlb_flush;
5254 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5255 const struct kvm_memory_slot *memslot)
5257 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5258 spin_lock(&kvm->mmu_lock);
5259 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5260 kvm_mmu_zap_collapsible_spte, true);
5261 spin_unlock(&kvm->mmu_lock);
5264 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5265 struct kvm_memory_slot *memslot)
5269 spin_lock(&kvm->mmu_lock);
5270 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5271 spin_unlock(&kvm->mmu_lock);
5273 lockdep_assert_held(&kvm->slots_lock);
5276 * It's also safe to flush TLBs out of mmu lock here as currently this
5277 * function is only used for dirty logging, in which case flushing TLB
5278 * out of mmu lock also guarantees no dirty pages will be lost in
5282 kvm_flush_remote_tlbs(kvm);
5284 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5286 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5287 struct kvm_memory_slot *memslot)
5291 spin_lock(&kvm->mmu_lock);
5292 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5294 spin_unlock(&kvm->mmu_lock);
5296 /* see kvm_mmu_slot_remove_write_access */
5297 lockdep_assert_held(&kvm->slots_lock);
5300 kvm_flush_remote_tlbs(kvm);
5302 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5304 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5305 struct kvm_memory_slot *memslot)
5309 spin_lock(&kvm->mmu_lock);
5310 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5311 spin_unlock(&kvm->mmu_lock);
5313 lockdep_assert_held(&kvm->slots_lock);
5315 /* see kvm_mmu_slot_leaf_clear_dirty */
5317 kvm_flush_remote_tlbs(kvm);
5319 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5321 #define BATCH_ZAP_PAGES 10
5322 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5324 struct kvm_mmu_page *sp, *node;
5328 list_for_each_entry_safe_reverse(sp, node,
5329 &kvm->arch.active_mmu_pages, link) {
5333 * No obsolete page exists before new created page since
5334 * active_mmu_pages is the FIFO list.
5336 if (!is_obsolete_sp(kvm, sp))
5340 * Since we are reversely walking the list and the invalid
5341 * list will be moved to the head, skip the invalid page
5342 * can help us to avoid the infinity list walking.
5344 if (sp->role.invalid)
5348 * Need not flush tlb since we only zap the sp with invalid
5349 * generation number.
5351 if (batch >= BATCH_ZAP_PAGES &&
5352 cond_resched_lock(&kvm->mmu_lock)) {
5357 ret = kvm_mmu_prepare_zap_page(kvm, sp,
5358 &kvm->arch.zapped_obsolete_pages);
5366 * Should flush tlb before free page tables since lockless-walking
5367 * may use the pages.
5369 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5373 * Fast invalidate all shadow pages and use lock-break technique
5374 * to zap obsolete pages.
5376 * It's required when memslot is being deleted or VM is being
5377 * destroyed, in these cases, we should ensure that KVM MMU does
5378 * not use any resource of the being-deleted slot or all slots
5379 * after calling the function.
5381 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
5383 spin_lock(&kvm->mmu_lock);
5384 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
5385 kvm->arch.mmu_valid_gen++;
5388 * Notify all vcpus to reload its shadow page table
5389 * and flush TLB. Then all vcpus will switch to new
5390 * shadow page table with the new mmu_valid_gen.
5392 * Note: we should do this under the protection of
5393 * mmu-lock, otherwise, vcpu would purge shadow page
5394 * but miss tlb flush.
5396 kvm_reload_remote_mmus(kvm);
5398 kvm_zap_obsolete_pages(kvm);
5399 spin_unlock(&kvm->mmu_lock);
5402 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5404 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5407 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
5410 * The very rare case: if the generation-number is round,
5411 * zap all shadow pages.
5413 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
5414 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5415 kvm_mmu_invalidate_zap_all_pages(kvm);
5419 static unsigned long
5420 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5423 int nr_to_scan = sc->nr_to_scan;
5424 unsigned long freed = 0;
5426 spin_lock(&kvm_lock);
5428 list_for_each_entry(kvm, &vm_list, vm_list) {
5430 LIST_HEAD(invalid_list);
5433 * Never scan more than sc->nr_to_scan VM instances.
5434 * Will not hit this condition practically since we do not try
5435 * to shrink more than one VM and it is very unlikely to see
5436 * !n_used_mmu_pages so many times.
5441 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5442 * here. We may skip a VM instance errorneosly, but we do not
5443 * want to shrink a VM that only started to populate its MMU
5446 if (!kvm->arch.n_used_mmu_pages &&
5447 !kvm_has_zapped_obsolete_pages(kvm))
5450 idx = srcu_read_lock(&kvm->srcu);
5451 spin_lock(&kvm->mmu_lock);
5453 if (kvm_has_zapped_obsolete_pages(kvm)) {
5454 kvm_mmu_commit_zap_page(kvm,
5455 &kvm->arch.zapped_obsolete_pages);
5459 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5461 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5464 spin_unlock(&kvm->mmu_lock);
5465 srcu_read_unlock(&kvm->srcu, idx);
5468 * unfair on small ones
5469 * per-vm shrinkers cry out
5470 * sadness comes quickly
5472 list_move_tail(&kvm->vm_list, &vm_list);
5476 spin_unlock(&kvm_lock);
5480 static unsigned long
5481 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5483 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5486 static struct shrinker mmu_shrinker = {
5487 .count_objects = mmu_shrink_count,
5488 .scan_objects = mmu_shrink_scan,
5489 .seeks = DEFAULT_SEEKS * 10,
5492 static void mmu_destroy_caches(void)
5494 kmem_cache_destroy(pte_list_desc_cache);
5495 kmem_cache_destroy(mmu_page_header_cache);
5498 int kvm_mmu_module_init(void)
5502 kvm_mmu_clear_all_pte_masks();
5504 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5505 sizeof(struct pte_list_desc),
5506 0, SLAB_ACCOUNT, NULL);
5507 if (!pte_list_desc_cache)
5510 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5511 sizeof(struct kvm_mmu_page),
5512 0, SLAB_ACCOUNT, NULL);
5513 if (!mmu_page_header_cache)
5516 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5519 ret = register_shrinker(&mmu_shrinker);
5526 mmu_destroy_caches();
5531 * Caculate mmu pages needed for kvm.
5533 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5535 unsigned int nr_mmu_pages;
5536 unsigned int nr_pages = 0;
5537 struct kvm_memslots *slots;
5538 struct kvm_memory_slot *memslot;
5541 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5542 slots = __kvm_memslots(kvm, i);
5544 kvm_for_each_memslot(memslot, slots)
5545 nr_pages += memslot->npages;
5548 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5549 nr_mmu_pages = max(nr_mmu_pages,
5550 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5552 return nr_mmu_pages;
5555 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5557 kvm_mmu_unload(vcpu);
5558 free_mmu_pages(vcpu);
5559 mmu_free_memory_caches(vcpu);
5562 void kvm_mmu_module_exit(void)
5564 mmu_destroy_caches();
5565 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5566 unregister_shrinker(&mmu_shrinker);
5567 mmu_audit_disable();