arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  * Copyright 2009 Red Hat, Inc. and/or its affilates.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  * Authors:
  26  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  27  *   Port from Qemu.
  28  */
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/bitops.h>
  32 #include "irq.h"
  33
  34 #include <linux/kvm_host.h>
  35 #include "trace.h"
  36
  37 static void pic_irq_request(struct kvm *kvm, int level);
  38
  39 static void pic_lock(struct kvm_pic *s)
  40         __acquires(&s->lock)
  41 {
  42         raw_spin_lock(&s->lock);
  43 }
  44
  45 static void pic_unlock(struct kvm_pic *s)
  46         __releases(&s->lock)
  47 {
  48         bool wakeup = s->wakeup_needed;
  49         struct kvm_vcpu *vcpu, *found = NULL;
  50         int i;
  51
  52         s->wakeup_needed = false;
  53
  54         raw_spin_unlock(&s->lock);
  55
  56         if (wakeup) {
  57                 kvm_for_each_vcpu(i, vcpu, s->kvm) {
  58                         if (kvm_apic_accept_pic_intr(vcpu)) {
  59                                 found = vcpu;
  60                                 break;
  61                         }
  62                 }
  63
  64                 if (!found)
  65                         found = s->kvm->bsp_vcpu;
  66
  67                 kvm_vcpu_kick(found);
  68         }
  69 }
  70
  71 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  72 {
  73         s->isr &= ~(1 << irq);
  74         s->isr_ack |= (1 << irq);
  75         if (s != &s->pics_state->pics[0])
  76                 irq += 8;
  77         /*
  78          * We are dropping lock while calling ack notifiers since ack
  79          * notifier callbacks for assigned devices call into PIC recursively.
  80          * Other interrupt may be delivered to PIC while lock is dropped but
  81          * it should be safe since PIC state is already updated at this stage.
  82          */
  83         pic_unlock(s->pics_state);
  84         kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
  85         pic_lock(s->pics_state);
  86 }
  87
  88 void kvm_pic_clear_isr_ack(struct kvm *kvm)
  89 {
  90         struct kvm_pic *s = pic_irqchip(kvm);
  91
  92         pic_lock(s);
  93         s->pics[0].isr_ack = 0xff;
  94         s->pics[1].isr_ack = 0xff;
  95         pic_unlock(s);
  96 }
  97
  98 /*
  99  * set irq level. If an edge is detected, then the IRR is set to 1
 100  */
 101 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
 102 {
 103         int mask, ret = 1;
 104         mask = 1 << irq;
 105         if (s->elcr & mask)     /* level triggered */
 106                 if (level) {
 107                         ret = !(s->irr & mask);
 108                         s->irr |= mask;
 109                         s->last_irr |= mask;
 110                 } else {
 111                         s->irr &= ~mask;
 112                         s->last_irr &= ~mask;
 113                 }
 114         else    /* edge triggered */
 115                 if (level) {
 116                         if ((s->last_irr & mask) == 0) {
 117                                 ret = !(s->irr & mask);
 118                                 s->irr |= mask;
 119                         }
 120                         s->last_irr |= mask;
 121                 } else
 122                         s->last_irr &= ~mask;
 123
 124         return (s->imr & mask) ? -1 : ret;
 125 }
 126
 127 /*
 128  * return the highest priority found in mask (highest = smallest
 129  * number). Return 8 if no irq
 130  */
 131 static inline int get_priority(struct kvm_kpic_state *s, int mask)
 132 {
 133         int priority;
 134         if (mask == 0)
 135                 return 8;
 136         priority = 0;
 137         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 138                 priority++;
 139         return priority;
 140 }
 141
 142 /*
 143  * return the pic wanted interrupt. return -1 if none
 144  */
 145 static int pic_get_irq(struct kvm_kpic_state *s)
 146 {
 147         int mask, cur_priority, priority;
 148
 149         mask = s->irr & ~s->imr;
 150         priority = get_priority(s, mask);
 151         if (priority == 8)
 152                 return -1;
 153         /*
 154          * compute current priority. If special fully nested mode on the
 155          * master, the IRQ coming from the slave is not taken into account
 156          * for the priority computation.
 157          */
 158         mask = s->isr;
 159         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 160                 mask &= ~(1 << 2);
 161         cur_priority = get_priority(s, mask);
 162         if (priority < cur_priority)
 163                 /*
 164                  * higher priority found: an irq should be generated
 165                  */
 166                 return (priority + s->priority_add) & 7;
 167         else
 168                 return -1;
 169 }
 170
 171 /*
 172  * raise irq to CPU if necessary. must be called every time the active
 173  * irq may change
 174  */
 175 static void pic_update_irq(struct kvm_pic *s)
 176 {
 177         int irq2, irq;
 178
 179         irq2 = pic_get_irq(&s->pics[1]);
 180         if (irq2 >= 0) {
 181                 /*
 182                  * if irq request by slave pic, signal master PIC
 183                  */
 184                 pic_set_irq1(&s->pics[0], 2, 1);
 185                 pic_set_irq1(&s->pics[0], 2, 0);
 186         }
 187         irq = pic_get_irq(&s->pics[0]);
 188         pic_irq_request(s->kvm, irq >= 0);
 189 }
 190
 191 void kvm_pic_update_irq(struct kvm_pic *s)
 192 {
 193         pic_lock(s);
 194         pic_update_irq(s);
 195         pic_unlock(s);
 196 }
 197
 198 int kvm_pic_set_irq(void *opaque, int irq, int level)
 199 {
 200         struct kvm_pic *s = opaque;
 201         int ret = -1;
 202
 203         pic_lock(s);
 204         if (irq >= 0 && irq < PIC_NUM_PINS) {
 205                 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 206                 pic_update_irq(s);
 207                 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
 208                                       s->pics[irq >> 3].imr, ret == 0);
 209         }
 210         pic_unlock(s);
 211
 212         return ret;
 213 }
 214
 215 /*
 216  * acknowledge interrupt 'irq'
 217  */
 218 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 219 {
 220         s->isr |= 1 << irq;
 221         /*
 222          * We don't clear a level sensitive interrupt here
 223          */
 224         if (!(s->elcr & (1 << irq)))
 225                 s->irr &= ~(1 << irq);
 226
 227         if (s->auto_eoi) {
 228                 if (s->rotate_on_auto_eoi)
 229                         s->priority_add = (irq + 1) & 7;
 230                 pic_clear_isr(s, irq);
 231         }
 232
 233 }
 234
 235 int kvm_pic_read_irq(struct kvm *kvm)
 236 {
 237         int irq, irq2, intno;
 238         struct kvm_pic *s = pic_irqchip(kvm);
 239
 240         pic_lock(s);
 241         irq = pic_get_irq(&s->pics[0]);
 242         if (irq >= 0) {
 243                 pic_intack(&s->pics[0], irq);
 244                 if (irq == 2) {
 245                         irq2 = pic_get_irq(&s->pics[1]);
 246                         if (irq2 >= 0)
 247                                 pic_intack(&s->pics[1], irq2);
 248                         else
 249                                 /*
 250                                  * spurious IRQ on slave controller
 251                                  */
 252                                 irq2 = 7;
 253                         intno = s->pics[1].irq_base + irq2;
 254                         irq = irq2 + 8;
 255                 } else
 256                         intno = s->pics[0].irq_base + irq;
 257         } else {
 258                 /*
 259                  * spurious IRQ on host controller
 260                  */
 261                 irq = 7;
 262                 intno = s->pics[0].irq_base + irq;
 263         }
 264         pic_update_irq(s);
 265         pic_unlock(s);
 266
 267         return intno;
 268 }
 269
 270 void kvm_pic_reset(struct kvm_kpic_state *s)
 271 {
 272         int irq;
 273         struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
 274         u8 irr = s->irr, isr = s->imr;
 275
 276         s->last_irr = 0;
 277         s->irr = 0;
 278         s->imr = 0;
 279         s->isr = 0;
 280         s->isr_ack = 0xff;
 281         s->priority_add = 0;
 282         s->irq_base = 0;
 283         s->read_reg_select = 0;
 284         s->poll = 0;
 285         s->special_mask = 0;
 286         s->init_state = 0;
 287         s->auto_eoi = 0;
 288         s->rotate_on_auto_eoi = 0;
 289         s->special_fully_nested_mode = 0;
 290         s->init4 = 0;
 291
 292         for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
 293                 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
 294                         if (irr & (1 << irq) || isr & (1 << irq)) {
 295                                 pic_clear_isr(s, irq);
 296                         }
 297         }
 298 }
 299
 300 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 301 {
 302         struct kvm_kpic_state *s = opaque;
 303         int priority, cmd, irq;
 304
 305         addr &= 1;
 306         if (addr == 0) {
 307                 if (val & 0x10) {
 308                         kvm_pic_reset(s);       /* init */
 309                         /*
 310                          * deassert a pending interrupt
 311                          */
 312                         pic_irq_request(s->pics_state->kvm, 0);
 313                         s->init_state = 1;
 314                         s->init4 = val & 1;
 315                         if (val & 0x02)
 316                                 printk(KERN_ERR "single mode not supported");
 317                         if (val & 0x08)
 318                                 printk(KERN_ERR
 319                                        "level sensitive irq not supported");
 320                 } else if (val & 0x08) {
 321                         if (val & 0x04)
 322                                 s->poll = 1;
 323                         if (val & 0x02)
 324                                 s->read_reg_select = val & 1;
 325                         if (val & 0x40)
 326                                 s->special_mask = (val >> 5) & 1;
 327                 } else {
 328                         cmd = val >> 5;
 329                         switch (cmd) {
 330                         case 0:
 331                         case 4:
 332                                 s->rotate_on_auto_eoi = cmd >> 2;
 333                                 break;
 334                         case 1: /* end of interrupt */
 335                         case 5:
 336                                 priority = get_priority(s, s->isr);
 337                                 if (priority != 8) {
 338                                         irq = (priority + s->priority_add) & 7;
 339                                         if (cmd == 5)
 340                                                 s->priority_add = (irq + 1) & 7;
 341                                         pic_clear_isr(s, irq);
 342                                         pic_update_irq(s->pics_state);
 343                                 }
 344                                 break;
 345                         case 3:
 346                                 irq = val & 7;
 347                                 pic_clear_isr(s, irq);
 348                                 pic_update_irq(s->pics_state);
 349                                 break;
 350                         case 6:
 351                                 s->priority_add = (val + 1) & 7;
 352                                 pic_update_irq(s->pics_state);
 353                                 break;
 354                         case 7:
 355                                 irq = val & 7;
 356                                 s->priority_add = (irq + 1) & 7;
 357                                 pic_clear_isr(s, irq);
 358                                 pic_update_irq(s->pics_state);
 359                                 break;
 360                         default:
 361                                 break;  /* no operation */
 362                         }
 363                 }
 364         } else
 365                 switch (s->init_state) {
 366                 case 0: { /* normal mode */
 367                         u8 imr_diff = s->imr ^ val,
 368                                 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
 369                         s->imr = val;
 370                         for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
 371                                 if (imr_diff & (1 << irq))
 372                                         kvm_fire_mask_notifiers(
 373                                                 s->pics_state->kvm,
 374                                                 SELECT_PIC(irq + off),
 375                                                 irq + off,
 376                                                 !!(s->imr & (1 << irq)));
 377                         pic_update_irq(s->pics_state);
 378                         break;
 379                 }
 380                 case 1:
 381                         s->irq_base = val & 0xf8;
 382                         s->init_state = 2;
 383                         break;
 384                 case 2:
 385                         if (s->init4)
 386                                 s->init_state = 3;
 387                         else
 388                                 s->init_state = 0;
 389                         break;
 390                 case 3:
 391                         s->special_fully_nested_mode = (val >> 4) & 1;
 392                         s->auto_eoi = (val >> 1) & 1;
 393                         s->init_state = 0;
 394                         break;
 395                 }
 396 }
 397
 398 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 399 {
 400         int ret;
 401
 402         ret = pic_get_irq(s);
 403         if (ret >= 0) {
 404                 if (addr1 >> 7) {
 405                         s->pics_state->pics[0].isr &= ~(1 << 2);
 406                         s->pics_state->pics[0].irr &= ~(1 << 2);
 407                 }
 408                 s->irr &= ~(1 << ret);
 409                 pic_clear_isr(s, ret);
 410                 if (addr1 >> 7 || ret != 2)
 411                         pic_update_irq(s->pics_state);
 412         } else {
 413                 ret = 0x07;
 414                 pic_update_irq(s->pics_state);
 415         }
 416
 417         return ret;
 418 }
 419
 420 static u32 pic_ioport_read(void *opaque, u32 addr1)
 421 {
 422         struct kvm_kpic_state *s = opaque;
 423         unsigned int addr;
 424         int ret;
 425
 426         addr = addr1;
 427         addr &= 1;
 428         if (s->poll) {
 429                 ret = pic_poll_read(s, addr1);
 430                 s->poll = 0;
 431         } else
 432                 if (addr == 0)
 433                         if (s->read_reg_select)
 434                                 ret = s->isr;
 435                         else
 436                                 ret = s->irr;
 437                 else
 438                         ret = s->imr;
 439         return ret;
 440 }
 441
 442 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 443 {
 444         struct kvm_kpic_state *s = opaque;
 445         s->elcr = val & s->elcr_mask;
 446 }
 447
 448 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 449 {
 450         struct kvm_kpic_state *s = opaque;
 451         return s->elcr;
 452 }
 453
 454 static int picdev_in_range(gpa_t addr)
 455 {
 456         switch (addr) {
 457         case 0x20:
 458         case 0x21:
 459         case 0xa0:
 460         case 0xa1:
 461         case 0x4d0:
 462         case 0x4d1:
 463                 return 1;
 464         default:
 465                 return 0;
 466         }
 467 }
 468
 469 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
 470 {
 471         return container_of(dev, struct kvm_pic, dev);
 472 }
 473
 474 static int picdev_write(struct kvm_io_device *this,
 475                          gpa_t addr, int len, const void *val)
 476 {
 477         struct kvm_pic *s = to_pic(this);
 478         unsigned char data = *(unsigned char *)val;
 479         if (!picdev_in_range(addr))
 480                 return -EOPNOTSUPP;
 481
 482         if (len != 1) {
 483                 if (printk_ratelimit())
 484                         printk(KERN_ERR "PIC: non byte write\n");
 485                 return 0;
 486         }
 487         pic_lock(s);
 488         switch (addr) {
 489         case 0x20:
 490         case 0x21:
 491         case 0xa0:
 492         case 0xa1:
 493                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 494                 break;
 495         case 0x4d0:
 496         case 0x4d1:
 497                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 498                 break;
 499         }
 500         pic_unlock(s);
 501         return 0;
 502 }
 503
 504 static int picdev_read(struct kvm_io_device *this,
 505                        gpa_t addr, int len, void *val)
 506 {
 507         struct kvm_pic *s = to_pic(this);
 508         unsigned char data = 0;
 509         if (!picdev_in_range(addr))
 510                 return -EOPNOTSUPP;
 511
 512         if (len != 1) {
 513                 if (printk_ratelimit())
 514                         printk(KERN_ERR "PIC: non byte read\n");
 515                 return 0;
 516         }
 517         pic_lock(s);
 518         switch (addr) {
 519         case 0x20:
 520         case 0x21:
 521         case 0xa0:
 522         case 0xa1:
 523                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 524                 break;
 525         case 0x4d0:
 526         case 0x4d1:
 527                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 528                 break;
 529         }
 530         *(unsigned char *)val = data;
 531         pic_unlock(s);
 532         return 0;
 533 }
 534
 535 /*
 536  * callback when PIC0 irq status changed
 537  */
 538 static void pic_irq_request(struct kvm *kvm, int level)
 539 {
 540         struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
 541         struct kvm_pic *s = pic_irqchip(kvm);
 542         int irq = pic_get_irq(&s->pics[0]);
 543
 544         s->output = level;
 545         if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
 546                 s->pics[0].isr_ack &= ~(1 << irq);
 547                 s->wakeup_needed = true;
 548         }
 549 }
 550
 551 static const struct kvm_io_device_ops picdev_ops = {
 552         .read     = picdev_read,
 553         .write    = picdev_write,
 554 };
 555
 556 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 557 {
 558         struct kvm_pic *s;
 559         int ret;
 560
 561         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 562         if (!s)
 563                 return NULL;
 564         raw_spin_lock_init(&s->lock);
 565         s->kvm = kvm;
 566         s->pics[0].elcr_mask = 0xf8;
 567         s->pics[1].elcr_mask = 0xde;
 568         s->pics[0].pics_state = s;
 569         s->pics[1].pics_state = s;
 570
 571         /*
 572          * Initialize PIO device
 573          */
 574         kvm_iodevice_init(&s->dev, &picdev_ops);
 575         mutex_lock(&kvm->slots_lock);
 576         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
 577         mutex_unlock(&kvm->slots_lock);
 578         if (ret < 0) {
 579                 kfree(s);
 580                 return NULL;
 581         }
 582
 583         return s;
 584 }
 585
 586 void kvm_destroy_pic(struct kvm *kvm)
 587 {
 588         struct kvm_pic *vpic = kvm->arch.vpic;
 589
 590         if (vpic) {
 591                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
 592                 kvm->arch.vpic = NULL;
 593                 kfree(vpic);
 594         }
 595 }