2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
79 #include <asm/qspinlock.h>
80 #include <asm/intel-family.h>
81 #include <asm/cpu_device_id.h>
82 #include <asm/spec-ctrl.h>
84 /* representing HT siblings of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
88 /* representing HT and core siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
90 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
94 /* Per CPU bogomips and other parameters */
95 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
96 EXPORT_PER_CPU_SYMBOL(cpu_info);
98 /* Logical package management. We might want to allocate that dynamically */
99 unsigned int __max_logical_packages __read_mostly;
100 EXPORT_SYMBOL(__max_logical_packages);
101 static unsigned int logical_packages __read_mostly;
103 /* Maximum number of SMT threads on any online core */
104 int __read_mostly __max_smt_threads = 1;
106 /* Flag to indicate if a complete sched domain rebuild is required */
107 bool x86_topology_update;
109 int arch_update_cpu_topology(void)
111 int retval = x86_topology_update;
113 x86_topology_update = false;
117 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
121 spin_lock_irqsave(&rtc_lock, flags);
122 CMOS_WRITE(0xa, 0xf);
123 spin_unlock_irqrestore(&rtc_lock, flags);
124 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
126 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
130 static inline void smpboot_restore_warm_reset_vector(void)
135 * Paranoid: Set warm reset code and vector here back
138 spin_lock_irqsave(&rtc_lock, flags);
140 spin_unlock_irqrestore(&rtc_lock, flags);
142 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
146 * Report back to the Boot Processor during boot time or to the caller processor
149 static void smp_callin(void)
154 * If waken up by an INIT in an 82489DX configuration
155 * cpu_callout_mask guarantees we don't get here before
156 * an INIT_deassert IPI reaches our local APIC, so it is
157 * now safe to touch our local APIC.
159 cpuid = smp_processor_id();
162 * (This works even if the APIC is not enabled.)
164 phys_id = read_apic_id();
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
178 smp_store_cpu_info(cpuid);
181 * The topology information must be up to date before
182 * calibrate_delay() and notify_cpu_starting().
184 set_cpu_sibling_map(raw_smp_processor_id());
188 * Update loops_per_jiffy in cpu_data. Previous call to
189 * smp_store_cpu_info() stored a value that is close but not as
190 * accurate as the value just calculated.
193 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
194 pr_debug("Stack at about %p\n", &cpuid);
198 notify_cpu_starting(cpuid);
201 * Allow the master to continue.
203 cpumask_set_cpu(cpuid, cpu_callin_mask);
206 static int cpu0_logical_apicid;
207 static int enable_start_cpu0;
209 * Activate a secondary processor.
211 static void notrace start_secondary(void *unused)
214 * Don't put *anything* except direct CPU state initialization
215 * before cpu_init(), SMP booting is too fragile that we want to
216 * limit the things done here to the most necessary things.
218 if (boot_cpu_has(X86_FEATURE_PCID))
219 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
222 /* switch away from the initial page table */
223 load_cr3(swapper_pg_dir);
225 * Initialize the CR4 shadow before doing anything that could
233 x86_cpuinit.early_percpu_clock_init();
237 enable_start_cpu0 = 0;
239 /* otherwise gcc will move up smp_processor_id before the cpu_init */
242 * Check TSC synchronization with the boot CPU:
244 check_tsc_sync_target();
246 speculative_store_bypass_ht_init();
249 * Lock vector_lock, set CPU online and bring the vector
250 * allocator online. Online must be set with vector_lock held
251 * to prevent a concurrent irq setup/teardown from seeing a
252 * half valid vector space.
255 set_cpu_online(smp_processor_id(), true);
257 unlock_vector_lock();
258 cpu_set_state_online(smp_processor_id());
259 x86_platform.nmi_init();
261 /* enable local interrupts */
264 /* to prevent fake stack check failure in clock setup */
265 boot_init_stack_canary();
267 x86_cpuinit.setup_percpu_clockev();
270 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
274 * topology_phys_to_logical_pkg - Map a physical package id to a logical
276 * Returns logical package id or -1 if not found
278 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
282 for_each_possible_cpu(cpu) {
283 struct cpuinfo_x86 *c = &cpu_data(cpu);
285 if (c->initialized && c->phys_proc_id == phys_pkg)
286 return c->logical_proc_id;
290 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
293 * topology_update_package_map - Update the physical to logical package map
294 * @pkg: The physical package id as retrieved via CPUID
295 * @cpu: The cpu for which this is updated
297 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
301 /* Already available somewhere? */
302 new = topology_phys_to_logical_pkg(pkg);
306 new = logical_packages++;
308 pr_info("CPU %u Converting physical %u to logical package %u\n",
312 cpu_data(cpu).logical_proc_id = new;
316 void __init smp_store_boot_cpu_info(void)
318 int id = 0; /* CPU 0 */
319 struct cpuinfo_x86 *c = &cpu_data(id);
323 topology_update_package_map(c->phys_proc_id, id);
324 c->initialized = true;
328 * The bootstrap kernel entry code has set these up. Save them for
331 void smp_store_cpu_info(int id)
333 struct cpuinfo_x86 *c = &cpu_data(id);
335 /* Copy boot_cpu_data only on the first bringup */
340 * During boot time, CPU0 has this setup already. Save the info when
341 * bringing up AP or offlined CPU0.
343 identify_secondary_cpu(c);
344 c->initialized = true;
348 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
350 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
352 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
356 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
358 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
360 return !WARN_ONCE(!topology_same_node(c, o),
361 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
362 "[node: %d != %d]. Ignoring dependency.\n",
363 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
366 #define link_mask(mfunc, c1, c2) \
368 cpumask_set_cpu((c1), mfunc(c2)); \
369 cpumask_set_cpu((c2), mfunc(c1)); \
372 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
374 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
375 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
377 if (c->phys_proc_id == o->phys_proc_id &&
378 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
379 if (c->cpu_core_id == o->cpu_core_id)
380 return topology_sane(c, o, "smt");
382 if ((c->cu_id != 0xff) &&
383 (o->cu_id != 0xff) &&
384 (c->cu_id == o->cu_id))
385 return topology_sane(c, o, "smt");
388 } else if (c->phys_proc_id == o->phys_proc_id &&
389 c->cpu_core_id == o->cpu_core_id) {
390 return topology_sane(c, o, "smt");
397 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
399 * These are Intel CPUs that enumerate an LLC that is shared by
400 * multiple NUMA nodes. The LLC on these systems is shared for
401 * off-package data access but private to the NUMA node (half
402 * of the package) for on-package access.
404 * CPUID (the source of the information about the LLC) can only
405 * enumerate the cache as being shared *or* unshared, but not
406 * this particular configuration. The CPU in this case enumerates
407 * the cache to be shared across the entire package (spanning both
411 static const struct x86_cpu_id snc_cpu[] = {
412 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
416 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
418 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
420 /* Do not match if we do not have a valid APICID for cpu: */
421 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
424 /* Do not match if LLC id does not match: */
425 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
429 * Allow the SNC topology without warning. Return of false
430 * means 'c' does not share the LLC of 'o'. This will be
431 * reflected to userspace.
433 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
436 return topology_sane(c, o, "llc");
440 * Unlike the other levels, we do not enforce keeping a
441 * multicore group inside a NUMA node. If this happens, we will
442 * discard the MC level of the topology later.
444 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
446 if (c->phys_proc_id == o->phys_proc_id)
451 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
452 static inline int x86_sched_itmt_flags(void)
454 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
457 #ifdef CONFIG_SCHED_MC
458 static int x86_core_flags(void)
460 return cpu_core_flags() | x86_sched_itmt_flags();
463 #ifdef CONFIG_SCHED_SMT
464 static int x86_smt_flags(void)
466 return cpu_smt_flags() | x86_sched_itmt_flags();
471 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
472 #ifdef CONFIG_SCHED_SMT
473 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
475 #ifdef CONFIG_SCHED_MC
476 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
481 static struct sched_domain_topology_level x86_topology[] = {
482 #ifdef CONFIG_SCHED_SMT
483 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
485 #ifdef CONFIG_SCHED_MC
486 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
488 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
493 * Set if a package/die has multiple NUMA nodes inside.
494 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
495 * Sub-NUMA Clustering have this.
497 static bool x86_has_numa_in_package;
499 void set_cpu_sibling_map(int cpu)
501 bool has_smt = smp_num_siblings > 1;
502 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
503 struct cpuinfo_x86 *c = &cpu_data(cpu);
504 struct cpuinfo_x86 *o;
507 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
510 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
511 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
512 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
517 for_each_cpu(i, cpu_sibling_setup_mask) {
520 if ((i == cpu) || (has_smt && match_smt(c, o)))
521 link_mask(topology_sibling_cpumask, cpu, i);
523 if ((i == cpu) || (has_mp && match_llc(c, o)))
524 link_mask(cpu_llc_shared_mask, cpu, i);
529 * This needs a separate iteration over the cpus because we rely on all
530 * topology_sibling_cpumask links to be set-up.
532 for_each_cpu(i, cpu_sibling_setup_mask) {
535 if ((i == cpu) || (has_mp && match_die(c, o))) {
536 link_mask(topology_core_cpumask, cpu, i);
539 * Does this new cpu bringup a new core?
542 topology_sibling_cpumask(cpu)) == 1) {
544 * for each core in package, increment
545 * the booted_cores for this new cpu
548 topology_sibling_cpumask(i)) == i)
551 * increment the core count for all
552 * the other cpus in this package
555 cpu_data(i).booted_cores++;
556 } else if (i != cpu && !c->booted_cores)
557 c->booted_cores = cpu_data(i).booted_cores;
559 if (match_die(c, o) && !topology_same_node(c, o))
560 x86_has_numa_in_package = true;
563 threads = cpumask_weight(topology_sibling_cpumask(cpu));
564 if (threads > __max_smt_threads)
565 __max_smt_threads = threads;
568 /* maps the cpu to the sched domain representing multi-core */
569 const struct cpumask *cpu_coregroup_mask(int cpu)
571 return cpu_llc_shared_mask(cpu);
574 static void impress_friends(void)
577 unsigned long bogosum = 0;
579 * Allow the user to impress friends.
581 pr_debug("Before bogomips\n");
582 for_each_possible_cpu(cpu)
583 if (cpumask_test_cpu(cpu, cpu_callout_mask))
584 bogosum += cpu_data(cpu).loops_per_jiffy;
585 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
588 (bogosum/(5000/HZ))%100);
590 pr_debug("Before bogocount - setting activated=1\n");
593 void __inquire_remote_apic(int apicid)
595 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
596 const char * const names[] = { "ID", "VERSION", "SPIV" };
600 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
602 for (i = 0; i < ARRAY_SIZE(regs); i++) {
603 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
608 status = safe_apic_wait_icr_idle();
610 pr_cont("a previous APIC delivery may have failed\n");
612 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
617 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
618 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
621 case APIC_ICR_RR_VALID:
622 status = apic_read(APIC_RRR);
623 pr_cont("%08x\n", status);
632 * The Multiprocessor Specification 1.4 (1997) example code suggests
633 * that there should be a 10ms delay between the BSP asserting INIT
634 * and de-asserting INIT, when starting a remote processor.
635 * But that slows boot and resume on modern processors, which include
636 * many cores and don't require that delay.
638 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
639 * Modern processor families are quirked to remove the delay entirely.
641 #define UDELAY_10MS_DEFAULT 10000
643 static unsigned int init_udelay = UINT_MAX;
645 static int __init cpu_init_udelay(char *str)
647 get_option(&str, &init_udelay);
651 early_param("cpu_init_udelay", cpu_init_udelay);
653 static void __init smp_quirk_init_udelay(void)
655 /* if cmdline changed it from default, leave it alone */
656 if (init_udelay != UINT_MAX)
659 /* if modern processor, use no delay */
660 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
661 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
665 /* else, use legacy delay */
666 init_udelay = UDELAY_10MS_DEFAULT;
670 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
671 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
672 * won't ... remember to clear down the APIC, etc later.
675 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
677 unsigned long send_status, accept_status = 0;
681 /* Boot on the stack */
682 /* Kick the second */
683 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
685 pr_debug("Waiting for send to finish...\n");
686 send_status = safe_apic_wait_icr_idle();
689 * Give the other CPU some time to accept the IPI.
692 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
693 maxlvt = lapic_get_maxlvt();
694 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
695 apic_write(APIC_ESR, 0);
696 accept_status = (apic_read(APIC_ESR) & 0xEF);
698 pr_debug("NMI sent\n");
701 pr_err("APIC never delivered???\n");
703 pr_err("APIC delivery error (%lx)\n", accept_status);
705 return (send_status | accept_status);
709 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
711 unsigned long send_status = 0, accept_status = 0;
712 int maxlvt, num_starts, j;
714 maxlvt = lapic_get_maxlvt();
717 * Be paranoid about clearing APIC errors.
719 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
720 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
721 apic_write(APIC_ESR, 0);
725 pr_debug("Asserting INIT\n");
728 * Turn INIT on target chip
733 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
736 pr_debug("Waiting for send to finish...\n");
737 send_status = safe_apic_wait_icr_idle();
741 pr_debug("Deasserting INIT\n");
745 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
747 pr_debug("Waiting for send to finish...\n");
748 send_status = safe_apic_wait_icr_idle();
753 * Should we send STARTUP IPIs ?
755 * Determine this based on the APIC version.
756 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
758 if (APIC_INTEGRATED(boot_cpu_apic_version))
764 * Run STARTUP IPI loop.
766 pr_debug("#startup loops: %d\n", num_starts);
768 for (j = 1; j <= num_starts; j++) {
769 pr_debug("Sending STARTUP #%d\n", j);
770 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
771 apic_write(APIC_ESR, 0);
773 pr_debug("After apic_write\n");
780 /* Boot on the stack */
781 /* Kick the second */
782 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
786 * Give the other CPU some time to accept the IPI.
788 if (init_udelay == 0)
793 pr_debug("Startup point 1\n");
795 pr_debug("Waiting for send to finish...\n");
796 send_status = safe_apic_wait_icr_idle();
799 * Give the other CPU some time to accept the IPI.
801 if (init_udelay == 0)
806 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
807 apic_write(APIC_ESR, 0);
808 accept_status = (apic_read(APIC_ESR) & 0xEF);
809 if (send_status || accept_status)
812 pr_debug("After Startup\n");
815 pr_err("APIC never delivered???\n");
817 pr_err("APIC delivery error (%lx)\n", accept_status);
819 return (send_status | accept_status);
822 /* reduce the number of lines printed when booting a large cpu count system */
823 static void announce_cpu(int cpu, int apicid)
825 static int current_node = -1;
826 int node = early_cpu_to_node(cpu);
827 static int width, node_width;
830 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
833 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
836 printk(KERN_INFO "x86: Booting SMP configuration:\n");
838 if (system_state < SYSTEM_RUNNING) {
839 if (node != current_node) {
840 if (current_node > (-1))
844 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
845 node_width - num_digits(node), " ", node);
848 /* Add padding for the BSP */
850 pr_cont("%*s", width + 1, " ");
852 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
855 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
859 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
863 cpu = smp_processor_id();
864 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
871 * Wake up AP by INIT, INIT, STARTUP sequence.
873 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
874 * boot-strap code which is not a desired behavior for waking up BSP. To
875 * void the boot-strap code, wake up CPU0 by NMI instead.
877 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
878 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
879 * We'll change this code in the future to wake up hard offlined CPU0 if
880 * real platform and request are available.
883 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
884 int *cpu0_nmi_registered)
892 * Wake up AP by INIT, INIT, STARTUP sequence.
895 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
900 * Wake up BSP by nmi.
902 * Register a NMI handler to help wake up CPU0.
904 boot_error = register_nmi_handler(NMI_LOCAL,
905 wakeup_cpu0_nmi, 0, "wake_cpu0");
908 enable_start_cpu0 = 1;
909 *cpu0_nmi_registered = 1;
910 if (apic->dest_logical == APIC_DEST_LOGICAL)
911 id = cpu0_logical_apicid;
914 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
923 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
925 /* Just in case we booted with a single CPU. */
926 alternatives_enable_smp();
928 per_cpu(current_task, cpu) = idle;
931 /* Stack for startup_32 can be just as for start_secondary onwards */
933 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
935 initial_gs = per_cpu_offset(cpu);
940 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
941 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
942 * Returns zero if CPU booted OK, else error code from
943 * ->wakeup_secondary_cpu.
945 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
946 int *cpu0_nmi_registered)
948 volatile u32 *trampoline_status =
949 (volatile u32 *) __va(real_mode_header->trampoline_status);
950 /* start_ip had better be page-aligned! */
951 unsigned long start_ip = real_mode_header->trampoline_start;
953 unsigned long boot_error = 0;
954 unsigned long timeout;
956 idle->thread.sp = (unsigned long)task_pt_regs(idle);
957 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
958 initial_code = (unsigned long)start_secondary;
959 initial_stack = idle->thread.sp;
961 /* Enable the espfix hack for this CPU */
964 /* So we see what's up */
965 announce_cpu(cpu, apicid);
968 * This grunge runs the startup process for
969 * the targeted processor.
972 if (x86_platform.legacy.warm_reset) {
974 pr_debug("Setting warm reset code and vector.\n");
976 smpboot_setup_warm_reset_vector(start_ip);
978 * Be paranoid about clearing APIC errors.
980 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
981 apic_write(APIC_ESR, 0);
987 * AP might wait on cpu_callout_mask in cpu_init() with
988 * cpu_initialized_mask set if previous attempt to online
989 * it timed-out. Clear cpu_initialized_mask so that after
990 * INIT/SIPI it could start with a clean state.
992 cpumask_clear_cpu(cpu, cpu_initialized_mask);
996 * Wake up a CPU in difference cases:
997 * - Use the method in the APIC driver if it's defined
999 * - Use an INIT boot APIC message for APs or NMI for BSP.
1001 if (apic->wakeup_secondary_cpu)
1002 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1004 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1005 cpu0_nmi_registered);
1009 * Wait 10s total for first sign of life from AP
1012 timeout = jiffies + 10*HZ;
1013 while (time_before(jiffies, timeout)) {
1014 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1016 * Tell AP to proceed with initialization
1018 cpumask_set_cpu(cpu, cpu_callout_mask);
1028 * Wait till AP completes initial initialization
1030 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1032 * Allow other tasks to run while we wait for the
1033 * AP to come online. This also gives a chance
1034 * for the MTRR work(triggered by the AP coming online)
1035 * to be completed in the stop machine context.
1041 /* mark "stuck" area as not stuck */
1042 *trampoline_status = 0;
1044 if (x86_platform.legacy.warm_reset) {
1046 * Cleanup possible dangling ends...
1048 smpboot_restore_warm_reset_vector();
1054 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1056 int apicid = apic->cpu_present_to_apicid(cpu);
1057 int cpu0_nmi_registered = 0;
1058 unsigned long flags;
1061 lockdep_assert_irqs_enabled();
1063 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1065 if (apicid == BAD_APICID ||
1066 !physid_isset(apicid, phys_cpu_present_map) ||
1067 !apic->apic_id_valid(apicid)) {
1068 pr_err("%s: bad cpu %d\n", __func__, cpu);
1073 * Already booted CPU?
1075 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1076 pr_debug("do_boot_cpu %d Already started\n", cpu);
1081 * Save current MTRR state in case it was changed since early boot
1082 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1086 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1087 err = cpu_check_up_prepare(cpu);
1088 if (err && err != -EBUSY)
1091 /* the FPU context is blank, nobody can own it */
1092 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1094 common_cpu_up(cpu, tidle);
1096 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1098 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1104 * Check TSC synchronization with the AP (keep irqs disabled
1107 local_irq_save(flags);
1108 check_tsc_sync_source(cpu);
1109 local_irq_restore(flags);
1111 while (!cpu_online(cpu)) {
1113 touch_nmi_watchdog();
1118 * Clean up the nmi handler. Do this after the callin and callout sync
1119 * to avoid impact of possible long unregister time.
1121 if (cpu0_nmi_registered)
1122 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1128 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1130 void arch_disable_smp_support(void)
1132 disable_ioapic_support();
1136 * Fall back to non SMP mode after errors.
1138 * RED-PEN audit/test this more. I bet there is more state messed up here.
1140 static __init void disable_smp(void)
1142 pr_info("SMP disabled\n");
1144 disable_ioapic_support();
1146 init_cpu_present(cpumask_of(0));
1147 init_cpu_possible(cpumask_of(0));
1149 if (smp_found_config)
1150 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1152 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1153 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1154 cpumask_set_cpu(0, topology_core_cpumask(0));
1158 * Various sanity checks.
1160 static void __init smp_sanity_check(void)
1164 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1165 if (def_to_bigsmp && nr_cpu_ids > 8) {
1169 pr_warn("More than 8 CPUs detected - skipping them\n"
1170 "Use CONFIG_X86_BIGSMP\n");
1173 for_each_present_cpu(cpu) {
1175 set_cpu_present(cpu, false);
1180 for_each_possible_cpu(cpu) {
1182 set_cpu_possible(cpu, false);
1190 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1191 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1192 hard_smp_processor_id());
1194 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1198 * Should not be necessary because the MP table should list the boot
1199 * CPU too, but we do it for the sake of robustness anyway.
1201 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1202 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1203 boot_cpu_physical_apicid);
1204 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1209 static void __init smp_cpu_index_default(void)
1212 struct cpuinfo_x86 *c;
1214 for_each_possible_cpu(i) {
1216 /* mark all to hotplug */
1217 c->cpu_index = nr_cpu_ids;
1221 static void __init smp_get_logical_apicid(void)
1224 cpu0_logical_apicid = apic_read(APIC_LDR);
1226 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1230 * Prepare for SMP bootup.
1231 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1232 * for common interface support.
1234 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1238 smp_cpu_index_default();
1241 * Setup boot CPU information
1243 smp_store_boot_cpu_info(); /* Final full version of the data */
1244 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1247 for_each_possible_cpu(i) {
1248 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1249 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1250 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1254 * Set 'default' x86 topology, this matches default_topology() in that
1255 * it has NUMA nodes as a topology level. See also
1256 * native_smp_cpus_done().
1258 * Must be done before set_cpus_sibling_map() is ran.
1260 set_sched_topology(x86_topology);
1262 set_cpu_sibling_map(0);
1266 switch (apic_intr_mode) {
1268 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1271 case APIC_SYMMETRIC_IO_NO_ROUTING:
1273 /* Setup local timer */
1274 x86_init.timers.setup_percpu_clockev();
1276 case APIC_VIRTUAL_WIRE:
1277 case APIC_SYMMETRIC_IO:
1281 /* Setup local timer */
1282 x86_init.timers.setup_percpu_clockev();
1284 smp_get_logical_apicid();
1287 print_cpu_info(&cpu_data(0));
1289 native_pv_lock_init();
1293 set_mtrr_aps_delayed_init();
1295 smp_quirk_init_udelay();
1297 speculative_store_bypass_ht_init();
1300 void arch_enable_nonboot_cpus_begin(void)
1302 set_mtrr_aps_delayed_init();
1305 void arch_enable_nonboot_cpus_end(void)
1311 * Early setup to make printk work.
1313 void __init native_smp_prepare_boot_cpu(void)
1315 int me = smp_processor_id();
1316 switch_to_new_gdt(me);
1317 /* already set me in cpu_online_mask in boot_cpu_init() */
1318 cpumask_set_cpu(me, cpu_callout_mask);
1319 cpu_set_state_online(me);
1322 void __init calculate_max_logical_packages(void)
1327 * Today neither Intel nor AMD support heterogenous systems so
1328 * extrapolate the boot cpu's data to all packages.
1330 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1331 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);
1332 pr_info("Max logical packages: %u\n", __max_logical_packages);
1335 void __init native_smp_cpus_done(unsigned int max_cpus)
1337 pr_debug("Boot done\n");
1339 calculate_max_logical_packages();
1341 if (x86_has_numa_in_package)
1342 set_sched_topology(x86_numa_in_package_topology);
1349 static int __initdata setup_possible_cpus = -1;
1350 static int __init _setup_possible_cpus(char *str)
1352 get_option(&str, &setup_possible_cpus);
1355 early_param("possible_cpus", _setup_possible_cpus);
1359 * cpu_possible_mask should be static, it cannot change as cpu's
1360 * are onlined, or offlined. The reason is per-cpu data-structures
1361 * are allocated by some modules at init time, and dont expect to
1362 * do this dynamically on cpu arrival/departure.
1363 * cpu_present_mask on the other hand can change dynamically.
1364 * In case when cpu_hotplug is not compiled, then we resort to current
1365 * behaviour, which is cpu_possible == cpu_present.
1368 * Three ways to find out the number of additional hotplug CPUs:
1369 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1370 * - The user can overwrite it with possible_cpus=NUM
1371 * - Otherwise don't reserve additional CPUs.
1372 * We do this because additional CPUs waste a lot of memory.
1375 __init void prefill_possible_map(void)
1379 /* No boot processor was found in mptable or ACPI MADT */
1380 if (!num_processors) {
1381 if (boot_cpu_has(X86_FEATURE_APIC)) {
1382 int apicid = boot_cpu_physical_apicid;
1383 int cpu = hard_smp_processor_id();
1385 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1387 /* Make sure boot cpu is enumerated */
1388 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1389 apic->apic_id_valid(apicid))
1390 generic_processor_info(apicid, boot_cpu_apic_version);
1393 if (!num_processors)
1397 i = setup_max_cpus ?: 1;
1398 if (setup_possible_cpus == -1) {
1399 possible = num_processors;
1400 #ifdef CONFIG_HOTPLUG_CPU
1402 possible += disabled_cpus;
1408 possible = setup_possible_cpus;
1410 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1412 /* nr_cpu_ids could be reduced via nr_cpus= */
1413 if (possible > nr_cpu_ids) {
1414 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1415 possible, nr_cpu_ids);
1416 possible = nr_cpu_ids;
1419 #ifdef CONFIG_HOTPLUG_CPU
1420 if (!setup_max_cpus)
1423 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1424 possible, setup_max_cpus);
1428 nr_cpu_ids = possible;
1430 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1431 possible, max_t(int, possible - num_processors, 0));
1433 reset_cpu_possible_mask();
1435 for (i = 0; i < possible; i++)
1436 set_cpu_possible(i, true);
1439 #ifdef CONFIG_HOTPLUG_CPU
1441 /* Recompute SMT state for all CPUs on offline */
1442 static void recompute_smt_state(void)
1444 int max_threads, cpu;
1447 for_each_online_cpu (cpu) {
1448 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1450 if (threads > max_threads)
1451 max_threads = threads;
1453 __max_smt_threads = max_threads;
1456 static void remove_siblinginfo(int cpu)
1459 struct cpuinfo_x86 *c = &cpu_data(cpu);
1461 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1462 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1464 * last thread sibling in this cpu core going down
1466 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1467 cpu_data(sibling).booted_cores--;
1470 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1471 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1472 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1473 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1474 cpumask_clear(cpu_llc_shared_mask(cpu));
1475 cpumask_clear(topology_sibling_cpumask(cpu));
1476 cpumask_clear(topology_core_cpumask(cpu));
1478 c->booted_cores = 0;
1479 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1480 recompute_smt_state();
1483 static void remove_cpu_from_maps(int cpu)
1485 set_cpu_online(cpu, false);
1486 cpumask_clear_cpu(cpu, cpu_callout_mask);
1487 cpumask_clear_cpu(cpu, cpu_callin_mask);
1488 /* was set by cpu_init() */
1489 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1490 numa_remove_cpu(cpu);
1493 void cpu_disable_common(void)
1495 int cpu = smp_processor_id();
1497 remove_siblinginfo(cpu);
1499 /* It's now safe to remove this processor from the online map */
1501 remove_cpu_from_maps(cpu);
1502 unlock_vector_lock();
1507 int native_cpu_disable(void)
1511 ret = lapic_can_unplug_cpu();
1516 cpu_disable_common();
1521 int common_cpu_die(unsigned int cpu)
1525 /* We don't do anything here: idle task is faking death itself. */
1527 /* They ack this in play_dead() by setting CPU_DEAD */
1528 if (cpu_wait_death(cpu, 5)) {
1529 if (system_state == SYSTEM_RUNNING)
1530 pr_info("CPU %u is now offline\n", cpu);
1532 pr_err("CPU %u didn't die...\n", cpu);
1539 void native_cpu_die(unsigned int cpu)
1541 common_cpu_die(cpu);
1544 void play_dead_common(void)
1549 (void)cpu_report_death();
1552 * With physical CPU hotplug, we should halt the cpu
1554 local_irq_disable();
1557 static bool wakeup_cpu0(void)
1559 if (smp_processor_id() == 0 && enable_start_cpu0)
1566 * We need to flush the caches before going to sleep, lest we have
1567 * dirty data in our caches when we come back up.
1569 static inline void mwait_play_dead(void)
1571 unsigned int eax, ebx, ecx, edx;
1572 unsigned int highest_cstate = 0;
1573 unsigned int highest_subcstate = 0;
1577 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1579 if (!this_cpu_has(X86_FEATURE_MWAIT))
1581 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1583 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1586 eax = CPUID_MWAIT_LEAF;
1588 native_cpuid(&eax, &ebx, &ecx, &edx);
1591 * eax will be 0 if EDX enumeration is not valid.
1592 * Initialized below to cstate, sub_cstate value when EDX is valid.
1594 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1597 edx >>= MWAIT_SUBSTATE_SIZE;
1598 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1599 if (edx & MWAIT_SUBSTATE_MASK) {
1601 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1604 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1605 (highest_subcstate - 1);
1609 * This should be a memory location in a cache line which is
1610 * unlikely to be touched by other processors. The actual
1611 * content is immaterial as it is not actually modified in any way.
1613 mwait_ptr = ¤t_thread_info()->flags;
1619 * The CLFLUSH is a workaround for erratum AAI65 for
1620 * the Xeon 7400 series. It's not clear it is actually
1621 * needed, but it should be harmless in either case.
1622 * The WBINVD is insufficient due to the spurious-wakeup
1623 * case where we return around the loop.
1628 __monitor(mwait_ptr, 0, 0);
1632 * If NMI wants to wake up CPU0, start CPU0.
1639 void hlt_play_dead(void)
1641 if (__this_cpu_read(cpu_info.x86) >= 4)
1647 * If NMI wants to wake up CPU0, start CPU0.
1654 void native_play_dead(void)
1657 tboot_shutdown(TB_SHUTDOWN_WFS);
1659 mwait_play_dead(); /* Only returns on failure */
1660 if (cpuidle_play_dead())
1664 #else /* ... !CONFIG_HOTPLUG_CPU */
1665 int native_cpu_disable(void)
1670 void native_cpu_die(unsigned int cpu)
1672 /* We said "no" in __cpu_disable */
1676 void native_play_dead(void)