arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/timer.h>
  37 #include <asm/desc.h>
  38 #include <asm/ldt.h>
  39
  40 #include "perf_event.h"
  41
  42 struct x86_pmu x86_pmu __read_mostly;
  43
  44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  45         .enabled = 1,
  46 };
  47
  48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
  49
  50 u64 __read_mostly hw_cache_event_ids
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54 u64 __read_mostly hw_cache_extra_regs
  55                                 [PERF_COUNT_HW_CACHE_MAX]
  56                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  58
  59 /*
  60  * Propagate event elapsed time into the generic event.
  61  * Can only be executed on the CPU where the event is active.
  62  * Returns the delta events processed.
  63  */
  64 u64 x86_perf_event_update(struct perf_event *event)
  65 {
  66         struct hw_perf_event *hwc = &event->hw;
  67         int shift = 64 - x86_pmu.cntval_bits;
  68         u64 prev_raw_count, new_raw_count;
  69         int idx = hwc->idx;
  70         s64 delta;
  71
  72         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  73                 return 0;
  74
  75         /*
  76          * Careful: an NMI might modify the previous event value.
  77          *
  78          * Our tactic to handle this is to first atomically read and
  79          * exchange a new raw count - then add that new-prev delta
  80          * count to the generic event atomically:
  81          */
  82 again:
  83         prev_raw_count = local64_read(&hwc->prev_count);
  84         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  85
  86         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  87                                         new_raw_count) != prev_raw_count)
  88                 goto again;
  89
  90         /*
  91          * Now we have the new raw value and have updated the prev
  92          * timestamp already. We can now calculate the elapsed delta
  93          * (event-)time and add that to the generic event.
  94          *
  95          * Careful, not all hw sign-extends above the physical width
  96          * of the count.
  97          */
  98         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  99         delta >>= shift;
 100
 101         local64_add(delta, &event->count);
 102         local64_sub(delta, &hwc->period_left);
 103
 104         return new_raw_count;
 105 }
 106
 107 /*
 108  * Find and validate any extra registers to set up.
 109  */
 110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 111 {
 112         struct hw_perf_event_extra *reg;
 113         struct extra_reg *er;
 114
 115         reg = &event->hw.extra_reg;
 116
 117         if (!x86_pmu.extra_regs)
 118                 return 0;
 119
 120         for (er = x86_pmu.extra_regs; er->msr; er++) {
 121                 if (er->event != (config & er->config_mask))
 122                         continue;
 123                 if (event->attr.config1 & ~er->valid_mask)
 124                         return -EINVAL;
 125                 /* Check if the extra msrs can be safely accessed*/
 126                 if (!er->extra_msr_access)
 127                         return -ENXIO;
 128
 129                 reg->idx = er->idx;
 130                 reg->config = event->attr.config1;
 131                 reg->reg = er->msr;
 132                 break;
 133         }
 134         return 0;
 135 }
 136
 137 static atomic_t active_events;
 138 static DEFINE_MUTEX(pmc_reserve_mutex);
 139
 140 #ifdef CONFIG_X86_LOCAL_APIC
 141
 142 static bool reserve_pmc_hardware(void)
 143 {
 144         int i;
 145
 146         for (i = 0; i < x86_pmu.num_counters; i++) {
 147                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 148                         goto perfctr_fail;
 149         }
 150
 151         for (i = 0; i < x86_pmu.num_counters; i++) {
 152                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 153                         goto eventsel_fail;
 154         }
 155
 156         return true;
 157
 158 eventsel_fail:
 159         for (i--; i >= 0; i--)
 160                 release_evntsel_nmi(x86_pmu_config_addr(i));
 161
 162         i = x86_pmu.num_counters;
 163
 164 perfctr_fail:
 165         for (i--; i >= 0; i--)
 166                 release_perfctr_nmi(x86_pmu_event_addr(i));
 167
 168         return false;
 169 }
 170
 171 static void release_pmc_hardware(void)
 172 {
 173         int i;
 174
 175         for (i = 0; i < x86_pmu.num_counters; i++) {
 176                 release_perfctr_nmi(x86_pmu_event_addr(i));
 177                 release_evntsel_nmi(x86_pmu_config_addr(i));
 178         }
 179 }
 180
 181 #else
 182
 183 static bool reserve_pmc_hardware(void) { return true; }
 184 static void release_pmc_hardware(void) {}
 185
 186 #endif
 187
 188 static bool check_hw_exists(void)
 189 {
 190         u64 val, val_fail, val_new= ~0;
 191         int i, reg, reg_fail, ret = 0;
 192         int bios_fail = 0;
 193
 194         /*
 195          * Check to see if the BIOS enabled any of the counters, if so
 196          * complain and bail.
 197          */
 198         for (i = 0; i < x86_pmu.num_counters; i++) {
 199                 reg = x86_pmu_config_addr(i);
 200                 ret = rdmsrl_safe(reg, &val);
 201                 if (ret)
 202                         goto msr_fail;
 203                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 204                         bios_fail = 1;
 205                         val_fail = val;
 206                         reg_fail = reg;
 207                 }
 208         }
 209
 210         if (x86_pmu.num_counters_fixed) {
 211                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 212                 ret = rdmsrl_safe(reg, &val);
 213                 if (ret)
 214                         goto msr_fail;
 215                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 216                         if (val & (0x03 << i*4)) {
 217                                 bios_fail = 1;
 218                                 val_fail = val;
 219                                 reg_fail = reg;
 220                         }
 221                 }
 222         }
 223
 224         /*
 225          * Read the current value, change it and read it back to see if it
 226          * matches, this is needed to detect certain hardware emulators
 227          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 228          */
 229         reg = x86_pmu_event_addr(0);
 230         if (rdmsrl_safe(reg, &val))
 231                 goto msr_fail;
 232         val ^= 0xffffUL;
 233         ret = wrmsrl_safe(reg, val);
 234         ret |= rdmsrl_safe(reg, &val_new);
 235         if (ret || val != val_new)
 236                 goto msr_fail;
 237
 238         /*
 239          * We still allow the PMU driver to operate:
 240          */
 241         if (bios_fail) {
 242                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 243                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 244         }
 245
 246         return true;
 247
 248 msr_fail:
 249         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 250         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
 251                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
 252                 reg, val_new);
 253
 254         return false;
 255 }
 256
 257 static void hw_perf_event_destroy(struct perf_event *event)
 258 {
 259         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 260                 release_pmc_hardware();
 261                 release_ds_buffers();
 262                 mutex_unlock(&pmc_reserve_mutex);
 263         }
 264 }
 265
 266 void hw_perf_lbr_event_destroy(struct perf_event *event)
 267 {
 268         hw_perf_event_destroy(event);
 269
 270         /* undo the lbr/bts event accounting */
 271         x86_del_exclusive(x86_lbr_exclusive_lbr);
 272 }
 273
 274 static inline int x86_pmu_initialized(void)
 275 {
 276         return x86_pmu.handle_irq != NULL;
 277 }
 278
 279 static inline int
 280 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 281 {
 282         struct perf_event_attr *attr = &event->attr;
 283         unsigned int cache_type, cache_op, cache_result;
 284         u64 config, val;
 285
 286         config = attr->config;
 287
 288         cache_type = (config >>  0) & 0xff;
 289         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 290                 return -EINVAL;
 291
 292         cache_op = (config >>  8) & 0xff;
 293         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 294                 return -EINVAL;
 295
 296         cache_result = (config >> 16) & 0xff;
 297         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 298                 return -EINVAL;
 299
 300         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 301
 302         if (val == 0)
 303                 return -ENOENT;
 304
 305         if (val == -1)
 306                 return -EINVAL;
 307
 308         hwc->config |= val;
 309         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 310         return x86_pmu_extra_regs(val, event);
 311 }
 312
 313 /*
 314  * Check if we can create event of a certain type (that no conflicting events
 315  * are present).
 316  */
 317 int x86_add_exclusive(unsigned int what)
 318 {
 319         int ret = -EBUSY, i;
 320
 321         if (atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what]))
 322                 return 0;
 323
 324         mutex_lock(&pmc_reserve_mutex);
 325         for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++)
 326                 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
 327                         goto out;
 328
 329         atomic_inc(&x86_pmu.lbr_exclusive[what]);
 330         ret = 0;
 331
 332 out:
 333         mutex_unlock(&pmc_reserve_mutex);
 334         return ret;
 335 }
 336
 337 void x86_del_exclusive(unsigned int what)
 338 {
 339         atomic_dec(&x86_pmu.lbr_exclusive[what]);
 340 }
 341
 342 int x86_setup_perfctr(struct perf_event *event)
 343 {
 344         struct perf_event_attr *attr = &event->attr;
 345         struct hw_perf_event *hwc = &event->hw;
 346         u64 config;
 347
 348         if (!is_sampling_event(event)) {
 349                 hwc->sample_period = x86_pmu.max_period;
 350                 hwc->last_period = hwc->sample_period;
 351                 local64_set(&hwc->period_left, hwc->sample_period);
 352         }
 353
 354         if (attr->type == PERF_TYPE_RAW)
 355                 return x86_pmu_extra_regs(event->attr.config, event);
 356
 357         if (attr->type == PERF_TYPE_HW_CACHE)
 358                 return set_ext_hw_attr(hwc, event);
 359
 360         if (attr->config >= x86_pmu.max_events)
 361                 return -EINVAL;
 362
 363         /*
 364          * The generic map:
 365          */
 366         config = x86_pmu.event_map(attr->config);
 367
 368         if (config == 0)
 369                 return -ENOENT;
 370
 371         if (config == -1LL)
 372                 return -EINVAL;
 373
 374         /*
 375          * Branch tracing:
 376          */
 377         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 378             !attr->freq && hwc->sample_period == 1) {
 379                 /* BTS is not supported by this architecture. */
 380                 if (!x86_pmu.bts_active)
 381                         return -EOPNOTSUPP;
 382
 383                 /* BTS is currently only allowed for user-mode. */
 384                 if (!attr->exclude_kernel)
 385                         return -EOPNOTSUPP;
 386
 387                 /* disallow bts if conflicting events are present */
 388                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
 389                         return -EBUSY;
 390
 391                 event->destroy = hw_perf_lbr_event_destroy;
 392         }
 393
 394         hwc->config |= config;
 395
 396         return 0;
 397 }
 398
 399 /*
 400  * check that branch_sample_type is compatible with
 401  * settings needed for precise_ip > 1 which implies
 402  * using the LBR to capture ALL taken branches at the
 403  * priv levels of the measurement
 404  */
 405 static inline int precise_br_compat(struct perf_event *event)
 406 {
 407         u64 m = event->attr.branch_sample_type;
 408         u64 b = 0;
 409
 410         /* must capture all branches */
 411         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 412                 return 0;
 413
 414         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 415
 416         if (!event->attr.exclude_user)
 417                 b |= PERF_SAMPLE_BRANCH_USER;
 418
 419         if (!event->attr.exclude_kernel)
 420                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 421
 422         /*
 423          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 424          */
 425
 426         return m == b;
 427 }
 428
 429 int x86_pmu_hw_config(struct perf_event *event)
 430 {
 431         if (event->attr.precise_ip) {
 432                 int precise = 0;
 433
 434                 /* Support for constant skid */
 435                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 436                         precise++;
 437
 438                         /* Support for IP fixup */
 439                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 440                                 precise++;
 441                 }
 442
 443                 if (event->attr.precise_ip > precise)
 444                         return -EOPNOTSUPP;
 445         }
 446         /*
 447          * check that PEBS LBR correction does not conflict with
 448          * whatever the user is asking with attr->branch_sample_type
 449          */
 450         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
 451                 u64 *br_type = &event->attr.branch_sample_type;
 452
 453                 if (has_branch_stack(event)) {
 454                         if (!precise_br_compat(event))
 455                                 return -EOPNOTSUPP;
 456
 457                         /* branch_sample_type is compatible */
 458
 459                 } else {
 460                         /*
 461                          * user did not specify  branch_sample_type
 462                          *
 463                          * For PEBS fixups, we capture all
 464                          * the branches at the priv level of the
 465                          * event.
 466                          */
 467                         *br_type = PERF_SAMPLE_BRANCH_ANY;
 468
 469                         if (!event->attr.exclude_user)
 470                                 *br_type |= PERF_SAMPLE_BRANCH_USER;
 471
 472                         if (!event->attr.exclude_kernel)
 473                                 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 474                 }
 475         }
 476
 477         if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
 478                 event->attach_state |= PERF_ATTACH_TASK_DATA;
 479
 480         /*
 481          * Generate PMC IRQs:
 482          * (keep 'enabled' bit clear for now)
 483          */
 484         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 485
 486         /*
 487          * Count user and OS events unless requested not to
 488          */
 489         if (!event->attr.exclude_user)
 490                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 491         if (!event->attr.exclude_kernel)
 492                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 493
 494         if (event->attr.type == PERF_TYPE_RAW)
 495                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 496
 497         if (event->attr.sample_period && x86_pmu.limit_period) {
 498                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 499                                 event->attr.sample_period)
 500                         return -EINVAL;
 501         }
 502
 503         return x86_setup_perfctr(event);
 504 }
 505
 506 /*
 507  * Setup the hardware configuration for a given attr_type
 508  */
 509 static int __x86_pmu_event_init(struct perf_event *event)
 510 {
 511         int err;
 512
 513         if (!x86_pmu_initialized())
 514                 return -ENODEV;
 515
 516         err = 0;
 517         if (!atomic_inc_not_zero(&active_events)) {
 518                 mutex_lock(&pmc_reserve_mutex);
 519                 if (atomic_read(&active_events) == 0) {
 520                         if (!reserve_pmc_hardware())
 521                                 err = -EBUSY;
 522                         else
 523                                 reserve_ds_buffers();
 524                 }
 525                 if (!err)
 526                         atomic_inc(&active_events);
 527                 mutex_unlock(&pmc_reserve_mutex);
 528         }
 529         if (err)
 530                 return err;
 531
 532         event->destroy = hw_perf_event_destroy;
 533
 534         event->hw.idx = -1;
 535         event->hw.last_cpu = -1;
 536         event->hw.last_tag = ~0ULL;
 537
 538         /* mark unused */
 539         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 540         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 541
 542         return x86_pmu.hw_config(event);
 543 }
 544
 545 void x86_pmu_disable_all(void)
 546 {
 547         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 548         int idx;
 549
 550         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 551                 u64 val;
 552
 553                 if (!test_bit(idx, cpuc->active_mask))
 554                         continue;
 555                 rdmsrl(x86_pmu_config_addr(idx), val);
 556                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 557                         continue;
 558                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 559                 wrmsrl(x86_pmu_config_addr(idx), val);
 560         }
 561 }
 562
 563 static void x86_pmu_disable(struct pmu *pmu)
 564 {
 565         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 566
 567         if (!x86_pmu_initialized())
 568                 return;
 569
 570         if (!cpuc->enabled)
 571                 return;
 572
 573         cpuc->n_added = 0;
 574         cpuc->enabled = 0;
 575         barrier();
 576
 577         x86_pmu.disable_all();
 578 }
 579
 580 void x86_pmu_enable_all(int added)
 581 {
 582         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 583         int idx;
 584
 585         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 586                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 587
 588                 if (!test_bit(idx, cpuc->active_mask))
 589                         continue;
 590
 591                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 592         }
 593 }
 594
 595 static struct pmu pmu;
 596
 597 static inline int is_x86_event(struct perf_event *event)
 598 {
 599         return event->pmu == &pmu;
 600 }
 601
 602 /*
 603  * Event scheduler state:
 604  *
 605  * Assign events iterating over all events and counters, beginning
 606  * with events with least weights first. Keep the current iterator
 607  * state in struct sched_state.
 608  */
 609 struct sched_state {
 610         int     weight;
 611         int     event;          /* event index */
 612         int     counter;        /* counter index */
 613         int     unassigned;     /* number of events to be assigned left */
 614         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 615 };
 616
 617 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 618 #define SCHED_STATES_MAX        2
 619
 620 struct perf_sched {
 621         int                     max_weight;
 622         int                     max_events;
 623         struct event_constraint **constraints;
 624         struct sched_state      state;
 625         int                     saved_states;
 626         struct sched_state      saved[SCHED_STATES_MAX];
 627 };
 628
 629 /*
 630  * Initialize interator that runs through all events and counters.
 631  */
 632 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
 633                             int num, int wmin, int wmax)
 634 {
 635         int idx;
 636
 637         memset(sched, 0, sizeof(*sched));
 638         sched->max_events       = num;
 639         sched->max_weight       = wmax;
 640         sched->constraints      = constraints;
 641
 642         for (idx = 0; idx < num; idx++) {
 643                 if (constraints[idx]->weight == wmin)
 644                         break;
 645         }
 646
 647         sched->state.event      = idx;          /* start with min weight */
 648         sched->state.weight     = wmin;
 649         sched->state.unassigned = num;
 650 }
 651
 652 static void perf_sched_save_state(struct perf_sched *sched)
 653 {
 654         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 655                 return;
 656
 657         sched->saved[sched->saved_states] = sched->state;
 658         sched->saved_states++;
 659 }
 660
 661 static bool perf_sched_restore_state(struct perf_sched *sched)
 662 {
 663         if (!sched->saved_states)
 664                 return false;
 665
 666         sched->saved_states--;
 667         sched->state = sched->saved[sched->saved_states];
 668
 669         /* continue with next counter: */
 670         clear_bit(sched->state.counter++, sched->state.used);
 671
 672         return true;
 673 }
 674
 675 /*
 676  * Select a counter for the current event to schedule. Return true on
 677  * success.
 678  */
 679 static bool __perf_sched_find_counter(struct perf_sched *sched)
 680 {
 681         struct event_constraint *c;
 682         int idx;
 683
 684         if (!sched->state.unassigned)
 685                 return false;
 686
 687         if (sched->state.event >= sched->max_events)
 688                 return false;
 689
 690         c = sched->constraints[sched->state.event];
 691         /* Prefer fixed purpose counters */
 692         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 693                 idx = INTEL_PMC_IDX_FIXED;
 694                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 695                         if (!__test_and_set_bit(idx, sched->state.used))
 696                                 goto done;
 697                 }
 698         }
 699         /* Grab the first unused counter starting with idx */
 700         idx = sched->state.counter;
 701         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 702                 if (!__test_and_set_bit(idx, sched->state.used))
 703                         goto done;
 704         }
 705
 706         return false;
 707
 708 done:
 709         sched->state.counter = idx;
 710
 711         if (c->overlap)
 712                 perf_sched_save_state(sched);
 713
 714         return true;
 715 }
 716
 717 static bool perf_sched_find_counter(struct perf_sched *sched)
 718 {
 719         while (!__perf_sched_find_counter(sched)) {
 720                 if (!perf_sched_restore_state(sched))
 721                         return false;
 722         }
 723
 724         return true;
 725 }
 726
 727 /*
 728  * Go through all unassigned events and find the next one to schedule.
 729  * Take events with the least weight first. Return true on success.
 730  */
 731 static bool perf_sched_next_event(struct perf_sched *sched)
 732 {
 733         struct event_constraint *c;
 734
 735         if (!sched->state.unassigned || !--sched->state.unassigned)
 736                 return false;
 737
 738         do {
 739                 /* next event */
 740                 sched->state.event++;
 741                 if (sched->state.event >= sched->max_events) {
 742                         /* next weight */
 743                         sched->state.event = 0;
 744                         sched->state.weight++;
 745                         if (sched->state.weight > sched->max_weight)
 746                                 return false;
 747                 }
 748                 c = sched->constraints[sched->state.event];
 749         } while (c->weight != sched->state.weight);
 750
 751         sched->state.counter = 0;       /* start with first counter */
 752
 753         return true;
 754 }
 755
 756 /*
 757  * Assign a counter for each event.
 758  */
 759 int perf_assign_events(struct event_constraint **constraints, int n,
 760                         int wmin, int wmax, int *assign)
 761 {
 762         struct perf_sched sched;
 763
 764         perf_sched_init(&sched, constraints, n, wmin, wmax);
 765
 766         do {
 767                 if (!perf_sched_find_counter(&sched))
 768                         break;  /* failed */
 769                 if (assign)
 770                         assign[sched.state.event] = sched.state.counter;
 771         } while (perf_sched_next_event(&sched));
 772
 773         return sched.state.unassigned;
 774 }
 775 EXPORT_SYMBOL_GPL(perf_assign_events);
 776
 777 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 778 {
 779         struct event_constraint *c;
 780         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 781         struct perf_event *e;
 782         int i, wmin, wmax, unsched = 0;
 783         struct hw_perf_event *hwc;
 784
 785         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 786
 787         if (x86_pmu.start_scheduling)
 788                 x86_pmu.start_scheduling(cpuc);
 789
 790         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 791                 cpuc->event_constraint[i] = NULL;
 792                 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
 793                 cpuc->event_constraint[i] = c;
 794
 795                 wmin = min(wmin, c->weight);
 796                 wmax = max(wmax, c->weight);
 797         }
 798
 799         /*
 800          * fastpath, try to reuse previous register
 801          */
 802         for (i = 0; i < n; i++) {
 803                 hwc = &cpuc->event_list[i]->hw;
 804                 c = cpuc->event_constraint[i];
 805
 806                 /* never assigned */
 807                 if (hwc->idx == -1)
 808                         break;
 809
 810                 /* constraint still honored */
 811                 if (!test_bit(hwc->idx, c->idxmsk))
 812                         break;
 813
 814                 /* not already used */
 815                 if (test_bit(hwc->idx, used_mask))
 816                         break;
 817
 818                 __set_bit(hwc->idx, used_mask);
 819                 if (assign)
 820                         assign[i] = hwc->idx;
 821         }
 822
 823         /* slow path */
 824         if (i != n) {
 825                 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
 826                                              wmax, assign);
 827         }
 828
 829         /*
 830          * In case of success (unsched = 0), mark events as committed,
 831          * so we do not put_constraint() in case new events are added
 832          * and fail to be scheduled
 833          *
 834          * We invoke the lower level commit callback to lock the resource
 835          *
 836          * We do not need to do all of this in case we are called to
 837          * validate an event group (assign == NULL)
 838          */
 839         if (!unsched && assign) {
 840                 for (i = 0; i < n; i++) {
 841                         e = cpuc->event_list[i];
 842                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 843                         if (x86_pmu.commit_scheduling)
 844                                 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
 845                 }
 846         }
 847
 848         if (!assign || unsched) {
 849
 850                 for (i = 0; i < n; i++) {
 851                         e = cpuc->event_list[i];
 852                         /*
 853                          * do not put_constraint() on comitted events,
 854                          * because they are good to go
 855                          */
 856                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 857                                 continue;
 858
 859                         /*
 860                          * release events that failed scheduling
 861                          */
 862                         if (x86_pmu.put_event_constraints)
 863                                 x86_pmu.put_event_constraints(cpuc, e);
 864                 }
 865         }
 866
 867         if (x86_pmu.stop_scheduling)
 868                 x86_pmu.stop_scheduling(cpuc);
 869
 870         return unsched ? -EINVAL : 0;
 871 }
 872
 873 /*
 874  * dogrp: true if must collect siblings events (group)
 875  * returns total number of events and error code
 876  */
 877 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 878 {
 879         struct perf_event *event;
 880         int n, max_count;
 881
 882         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 883
 884         /* current number of events already accepted */
 885         n = cpuc->n_events;
 886
 887         if (is_x86_event(leader)) {
 888                 if (n >= max_count)
 889                         return -EINVAL;
 890                 cpuc->event_list[n] = leader;
 891                 n++;
 892         }
 893         if (!dogrp)
 894                 return n;
 895
 896         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 897                 if (!is_x86_event(event) ||
 898                     event->state <= PERF_EVENT_STATE_OFF)
 899                         continue;
 900
 901                 if (n >= max_count)
 902                         return -EINVAL;
 903
 904                 cpuc->event_list[n] = event;
 905                 n++;
 906         }
 907         return n;
 908 }
 909
 910 static inline void x86_assign_hw_event(struct perf_event *event,
 911                                 struct cpu_hw_events *cpuc, int i)
 912 {
 913         struct hw_perf_event *hwc = &event->hw;
 914
 915         hwc->idx = cpuc->assign[i];
 916         hwc->last_cpu = smp_processor_id();
 917         hwc->last_tag = ++cpuc->tags[i];
 918
 919         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 920                 hwc->config_base = 0;
 921                 hwc->event_base = 0;
 922         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 923                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 924                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 925                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 926         } else {
 927                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 928                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 929                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 930         }
 931 }
 932
 933 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 934                                         struct cpu_hw_events *cpuc,
 935                                         int i)
 936 {
 937         return hwc->idx == cpuc->assign[i] &&
 938                 hwc->last_cpu == smp_processor_id() &&
 939                 hwc->last_tag == cpuc->tags[i];
 940 }
 941
 942 static void x86_pmu_start(struct perf_event *event, int flags);
 943
 944 static void x86_pmu_enable(struct pmu *pmu)
 945 {
 946         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 947         struct perf_event *event;
 948         struct hw_perf_event *hwc;
 949         int i, added = cpuc->n_added;
 950
 951         if (!x86_pmu_initialized())
 952                 return;
 953
 954         if (cpuc->enabled)
 955                 return;
 956
 957         if (cpuc->n_added) {
 958                 int n_running = cpuc->n_events - cpuc->n_added;
 959                 /*
 960                  * apply assignment obtained either from
 961                  * hw_perf_group_sched_in() or x86_pmu_enable()
 962                  *
 963                  * step1: save events moving to new counters
 964                  */
 965                 for (i = 0; i < n_running; i++) {
 966                         event = cpuc->event_list[i];
 967                         hwc = &event->hw;
 968
 969                         /*
 970                          * we can avoid reprogramming counter if:
 971                          * - assigned same counter as last time
 972                          * - running on same CPU as last time
 973                          * - no other event has used the counter since
 974                          */
 975                         if (hwc->idx == -1 ||
 976                             match_prev_assignment(hwc, cpuc, i))
 977                                 continue;
 978
 979                         /*
 980                          * Ensure we don't accidentally enable a stopped
 981                          * counter simply because we rescheduled.
 982                          */
 983                         if (hwc->state & PERF_HES_STOPPED)
 984                                 hwc->state |= PERF_HES_ARCH;
 985
 986                         x86_pmu_stop(event, PERF_EF_UPDATE);
 987                 }
 988
 989                 /*
 990                  * step2: reprogram moved events into new counters
 991                  */
 992                 for (i = 0; i < cpuc->n_events; i++) {
 993                         event = cpuc->event_list[i];
 994                         hwc = &event->hw;
 995
 996                         if (!match_prev_assignment(hwc, cpuc, i))
 997                                 x86_assign_hw_event(event, cpuc, i);
 998                         else if (i < n_running)
 999                                 continue;
1000
1001                         if (hwc->state & PERF_HES_ARCH)
1002                                 continue;
1003
1004                         x86_pmu_start(event, PERF_EF_RELOAD);
1005                 }
1006                 cpuc->n_added = 0;
1007                 perf_events_lapic_init();
1008         }
1009
1010         cpuc->enabled = 1;
1011         barrier();
1012
1013         x86_pmu.enable_all(added);
1014 }
1015
1016 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1017
1018 /*
1019  * Set the next IRQ period, based on the hwc->period_left value.
1020  * To be called with the event disabled in hw:
1021  */
1022 int x86_perf_event_set_period(struct perf_event *event)
1023 {
1024         struct hw_perf_event *hwc = &event->hw;
1025         s64 left = local64_read(&hwc->period_left);
1026         s64 period = hwc->sample_period;
1027         int ret = 0, idx = hwc->idx;
1028
1029         if (idx == INTEL_PMC_IDX_FIXED_BTS)
1030                 return 0;
1031
1032         /*
1033          * If we are way outside a reasonable range then just skip forward:
1034          */
1035         if (unlikely(left <= -period)) {
1036                 left = period;
1037                 local64_set(&hwc->period_left, left);
1038                 hwc->last_period = period;
1039                 ret = 1;
1040         }
1041
1042         if (unlikely(left <= 0)) {
1043                 left += period;
1044                 local64_set(&hwc->period_left, left);
1045                 hwc->last_period = period;
1046                 ret = 1;
1047         }
1048         /*
1049          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1050          */
1051         if (unlikely(left < 2))
1052                 left = 2;
1053
1054         if (left > x86_pmu.max_period)
1055                 left = x86_pmu.max_period;
1056
1057         if (x86_pmu.limit_period)
1058                 left = x86_pmu.limit_period(event, left);
1059
1060         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1061
1062         /*
1063          * The hw event starts counting from this event offset,
1064          * mark it to be able to extra future deltas:
1065          */
1066         local64_set(&hwc->prev_count, (u64)-left);
1067
1068         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1069
1070         /*
1071          * Due to erratum on certan cpu we need
1072          * a second write to be sure the register
1073          * is updated properly
1074          */
1075         if (x86_pmu.perfctr_second_write) {
1076                 wrmsrl(hwc->event_base,
1077                         (u64)(-left) & x86_pmu.cntval_mask);
1078         }
1079
1080         perf_event_update_userpage(event);
1081
1082         return ret;
1083 }
1084
1085 void x86_pmu_enable_event(struct perf_event *event)
1086 {
1087         if (__this_cpu_read(cpu_hw_events.enabled))
1088                 __x86_pmu_enable_event(&event->hw,
1089                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1090 }
1091
1092 /*
1093  * Add a single event to the PMU.
1094  *
1095  * The event is added to the group of enabled events
1096  * but only if it can be scehduled with existing events.
1097  */
1098 static int x86_pmu_add(struct perf_event *event, int flags)
1099 {
1100         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1101         struct hw_perf_event *hwc;
1102         int assign[X86_PMC_IDX_MAX];
1103         int n, n0, ret;
1104
1105         hwc = &event->hw;
1106
1107         n0 = cpuc->n_events;
1108         ret = n = collect_events(cpuc, event, false);
1109         if (ret < 0)
1110                 goto out;
1111
1112         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1113         if (!(flags & PERF_EF_START))
1114                 hwc->state |= PERF_HES_ARCH;
1115
1116         /*
1117          * If group events scheduling transaction was started,
1118          * skip the schedulability test here, it will be performed
1119          * at commit time (->commit_txn) as a whole.
1120          */
1121         if (cpuc->group_flag & PERF_EVENT_TXN)
1122                 goto done_collect;
1123
1124         ret = x86_pmu.schedule_events(cpuc, n, assign);
1125         if (ret)
1126                 goto out;
1127         /*
1128          * copy new assignment, now we know it is possible
1129          * will be used by hw_perf_enable()
1130          */
1131         memcpy(cpuc->assign, assign, n*sizeof(int));
1132
1133 done_collect:
1134         /*
1135          * Commit the collect_events() state. See x86_pmu_del() and
1136          * x86_pmu_*_txn().
1137          */
1138         cpuc->n_events = n;
1139         cpuc->n_added += n - n0;
1140         cpuc->n_txn += n - n0;
1141
1142         ret = 0;
1143 out:
1144         return ret;
1145 }
1146
1147 static void x86_pmu_start(struct perf_event *event, int flags)
1148 {
1149         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1150         int idx = event->hw.idx;
1151
1152         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1153                 return;
1154
1155         if (WARN_ON_ONCE(idx == -1))
1156                 return;
1157
1158         if (flags & PERF_EF_RELOAD) {
1159                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1160                 x86_perf_event_set_period(event);
1161         }
1162
1163         event->hw.state = 0;
1164
1165         cpuc->events[idx] = event;
1166         __set_bit(idx, cpuc->active_mask);
1167         __set_bit(idx, cpuc->running);
1168         x86_pmu.enable(event);
1169         perf_event_update_userpage(event);
1170 }
1171
1172 void perf_event_print_debug(void)
1173 {
1174         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1175         u64 pebs, debugctl;
1176         struct cpu_hw_events *cpuc;
1177         unsigned long flags;
1178         int cpu, idx;
1179
1180         if (!x86_pmu.num_counters)
1181                 return;
1182
1183         local_irq_save(flags);
1184
1185         cpu = smp_processor_id();
1186         cpuc = &per_cpu(cpu_hw_events, cpu);
1187
1188         if (x86_pmu.version >= 2) {
1189                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1190                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1191                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1192                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1193
1194                 pr_info("\n");
1195                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1196                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1197                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1198                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1199                 if (x86_pmu.pebs_constraints) {
1200                         rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1201                         pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1202                 }
1203                 if (x86_pmu.lbr_nr) {
1204                         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1205                         pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1206                 }
1207         }
1208         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1209
1210         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1211                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1212                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1213
1214                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1215
1216                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1217                         cpu, idx, pmc_ctrl);
1218                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1219                         cpu, idx, pmc_count);
1220                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1221                         cpu, idx, prev_left);
1222         }
1223         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1224                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1225
1226                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1227                         cpu, idx, pmc_count);
1228         }
1229         local_irq_restore(flags);
1230 }
1231
1232 void x86_pmu_stop(struct perf_event *event, int flags)
1233 {
1234         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1235         struct hw_perf_event *hwc = &event->hw;
1236
1237         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1238                 x86_pmu.disable(event);
1239                 cpuc->events[hwc->idx] = NULL;
1240                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1241                 hwc->state |= PERF_HES_STOPPED;
1242         }
1243
1244         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1245                 /*
1246                  * Drain the remaining delta count out of a event
1247                  * that we are disabling:
1248                  */
1249                 x86_perf_event_update(event);
1250                 hwc->state |= PERF_HES_UPTODATE;
1251         }
1252 }
1253
1254 static void x86_pmu_del(struct perf_event *event, int flags)
1255 {
1256         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1257         int i;
1258
1259         /*
1260          * event is descheduled
1261          */
1262         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1263
1264         /*
1265          * If we're called during a txn, we don't need to do anything.
1266          * The events never got scheduled and ->cancel_txn will truncate
1267          * the event_list.
1268          *
1269          * XXX assumes any ->del() called during a TXN will only be on
1270          * an event added during that same TXN.
1271          */
1272         if (cpuc->group_flag & PERF_EVENT_TXN)
1273                 return;
1274
1275         /*
1276          * Not a TXN, therefore cleanup properly.
1277          */
1278         x86_pmu_stop(event, PERF_EF_UPDATE);
1279
1280         for (i = 0; i < cpuc->n_events; i++) {
1281                 if (event == cpuc->event_list[i])
1282                         break;
1283         }
1284
1285         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1286                 return;
1287
1288         /* If we have a newly added event; make sure to decrease n_added. */
1289         if (i >= cpuc->n_events - cpuc->n_added)
1290                 --cpuc->n_added;
1291
1292         if (x86_pmu.put_event_constraints)
1293                 x86_pmu.put_event_constraints(cpuc, event);
1294
1295         /* Delete the array entry. */
1296         while (++i < cpuc->n_events) {
1297                 cpuc->event_list[i-1] = cpuc->event_list[i];
1298                 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1299         }
1300         --cpuc->n_events;
1301
1302         perf_event_update_userpage(event);
1303 }
1304
1305 int x86_pmu_handle_irq(struct pt_regs *regs)
1306 {
1307         struct perf_sample_data data;
1308         struct cpu_hw_events *cpuc;
1309         struct perf_event *event;
1310         int idx, handled = 0;
1311         u64 val;
1312
1313         cpuc = this_cpu_ptr(&cpu_hw_events);
1314
1315         /*
1316          * Some chipsets need to unmask the LVTPC in a particular spot
1317          * inside the nmi handler.  As a result, the unmasking was pushed
1318          * into all the nmi handlers.
1319          *
1320          * This generic handler doesn't seem to have any issues where the
1321          * unmasking occurs so it was left at the top.
1322          */
1323         apic_write(APIC_LVTPC, APIC_DM_NMI);
1324
1325         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1326                 if (!test_bit(idx, cpuc->active_mask)) {
1327                         /*
1328                          * Though we deactivated the counter some cpus
1329                          * might still deliver spurious interrupts still
1330                          * in flight. Catch them:
1331                          */
1332                         if (__test_and_clear_bit(idx, cpuc->running))
1333                                 handled++;
1334                         continue;
1335                 }
1336
1337                 event = cpuc->events[idx];
1338
1339                 val = x86_perf_event_update(event);
1340                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1341                         continue;
1342
1343                 /*
1344                  * event overflow
1345                  */
1346                 handled++;
1347                 perf_sample_data_init(&data, 0, event->hw.last_period);
1348
1349                 if (!x86_perf_event_set_period(event))
1350                         continue;
1351
1352                 if (perf_event_overflow(event, &data, regs))
1353                         x86_pmu_stop(event, 0);
1354         }
1355
1356         if (handled)
1357                 inc_irq_stat(apic_perf_irqs);
1358
1359         return handled;
1360 }
1361
1362 void perf_events_lapic_init(void)
1363 {
1364         if (!x86_pmu.apic || !x86_pmu_initialized())
1365                 return;
1366
1367         /*
1368          * Always use NMI for PMU
1369          */
1370         apic_write(APIC_LVTPC, APIC_DM_NMI);
1371 }
1372
1373 static int
1374 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1375 {
1376         u64 start_clock;
1377         u64 finish_clock;
1378         int ret;
1379
1380         if (!atomic_read(&active_events))
1381                 return NMI_DONE;
1382
1383         start_clock = sched_clock();
1384         ret = x86_pmu.handle_irq(regs);
1385         finish_clock = sched_clock();
1386
1387         perf_sample_event_took(finish_clock - start_clock);
1388
1389         return ret;
1390 }
1391 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1392
1393 struct event_constraint emptyconstraint;
1394 struct event_constraint unconstrained;
1395
1396 static int
1397 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1398 {
1399         unsigned int cpu = (long)hcpu;
1400         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1401         int i, ret = NOTIFY_OK;
1402
1403         switch (action & ~CPU_TASKS_FROZEN) {
1404         case CPU_UP_PREPARE:
1405                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1406                         cpuc->kfree_on_online[i] = NULL;
1407                 if (x86_pmu.cpu_prepare)
1408                         ret = x86_pmu.cpu_prepare(cpu);
1409                 break;
1410
1411         case CPU_STARTING:
1412                 if (x86_pmu.cpu_starting)
1413                         x86_pmu.cpu_starting(cpu);
1414                 break;
1415
1416         case CPU_ONLINE:
1417                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1418                         kfree(cpuc->kfree_on_online[i]);
1419                         cpuc->kfree_on_online[i] = NULL;
1420                 }
1421                 break;
1422
1423         case CPU_DYING:
1424                 if (x86_pmu.cpu_dying)
1425                         x86_pmu.cpu_dying(cpu);
1426                 break;
1427
1428         case CPU_UP_CANCELED:
1429         case CPU_DEAD:
1430                 if (x86_pmu.cpu_dead)
1431                         x86_pmu.cpu_dead(cpu);
1432                 break;
1433
1434         default:
1435                 break;
1436         }
1437
1438         return ret;
1439 }
1440
1441 static void __init pmu_check_apic(void)
1442 {
1443         if (cpu_has_apic)
1444                 return;
1445
1446         x86_pmu.apic = 0;
1447         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1448         pr_info("no hardware sampling interrupt available.\n");
1449
1450         /*
1451          * If we have a PMU initialized but no APIC
1452          * interrupts, we cannot sample hardware
1453          * events (user-space has to fall back and
1454          * sample via a hrtimer based software event):
1455          */
1456         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1457
1458 }
1459
1460 static struct attribute_group x86_pmu_format_group = {
1461         .name = "format",
1462         .attrs = NULL,
1463 };
1464
1465 /*
1466  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1467  * out of events_attr attributes.
1468  */
1469 static void __init filter_events(struct attribute **attrs)
1470 {
1471         struct device_attribute *d;
1472         struct perf_pmu_events_attr *pmu_attr;
1473         int i, j;
1474
1475         for (i = 0; attrs[i]; i++) {
1476                 d = (struct device_attribute *)attrs[i];
1477                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1478                 /* str trumps id */
1479                 if (pmu_attr->event_str)
1480                         continue;
1481                 if (x86_pmu.event_map(i))
1482                         continue;
1483
1484                 for (j = i; attrs[j]; j++)
1485                         attrs[j] = attrs[j + 1];
1486
1487                 /* Check the shifted attr. */
1488                 i--;
1489         }
1490 }
1491
1492 /* Merge two pointer arrays */
1493 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1494 {
1495         struct attribute **new;
1496         int j, i;
1497
1498         for (j = 0; a[j]; j++)
1499                 ;
1500         for (i = 0; b[i]; i++)
1501                 j++;
1502         j++;
1503
1504         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1505         if (!new)
1506                 return NULL;
1507
1508         j = 0;
1509         for (i = 0; a[i]; i++)
1510                 new[j++] = a[i];
1511         for (i = 0; b[i]; i++)
1512                 new[j++] = b[i];
1513         new[j] = NULL;
1514
1515         return new;
1516 }
1517
1518 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1519                           char *page)
1520 {
1521         struct perf_pmu_events_attr *pmu_attr = \
1522                 container_of(attr, struct perf_pmu_events_attr, attr);
1523         u64 config = x86_pmu.event_map(pmu_attr->id);
1524
1525         /* string trumps id */
1526         if (pmu_attr->event_str)
1527                 return sprintf(page, "%s", pmu_attr->event_str);
1528
1529         return x86_pmu.events_sysfs_show(page, config);
1530 }
1531
1532 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1533 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1534 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1535 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1536 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1537 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1538 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1539 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1540 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1541 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1542
1543 static struct attribute *empty_attrs;
1544
1545 static struct attribute *events_attr[] = {
1546         EVENT_PTR(CPU_CYCLES),
1547         EVENT_PTR(INSTRUCTIONS),
1548         EVENT_PTR(CACHE_REFERENCES),
1549         EVENT_PTR(CACHE_MISSES),
1550         EVENT_PTR(BRANCH_INSTRUCTIONS),
1551         EVENT_PTR(BRANCH_MISSES),
1552         EVENT_PTR(BUS_CYCLES),
1553         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1554         EVENT_PTR(STALLED_CYCLES_BACKEND),
1555         EVENT_PTR(REF_CPU_CYCLES),
1556         NULL,
1557 };
1558
1559 static struct attribute_group x86_pmu_events_group = {
1560         .name = "events",
1561         .attrs = events_attr,
1562 };
1563
1564 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1565 {
1566         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1567         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1568         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1569         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1570         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1571         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1572         ssize_t ret;
1573
1574         /*
1575         * We have whole page size to spend and just little data
1576         * to write, so we can safely use sprintf.
1577         */
1578         ret = sprintf(page, "event=0x%02llx", event);
1579
1580         if (umask)
1581                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1582
1583         if (edge)
1584                 ret += sprintf(page + ret, ",edge");
1585
1586         if (pc)
1587                 ret += sprintf(page + ret, ",pc");
1588
1589         if (any)
1590                 ret += sprintf(page + ret, ",any");
1591
1592         if (inv)
1593                 ret += sprintf(page + ret, ",inv");
1594
1595         if (cmask)
1596                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1597
1598         ret += sprintf(page + ret, "\n");
1599
1600         return ret;
1601 }
1602
1603 static int __init init_hw_perf_events(void)
1604 {
1605         struct x86_pmu_quirk *quirk;
1606         int err;
1607
1608         pr_info("Performance Events: ");
1609
1610         switch (boot_cpu_data.x86_vendor) {
1611         case X86_VENDOR_INTEL:
1612                 err = intel_pmu_init();
1613                 break;
1614         case X86_VENDOR_AMD:
1615                 err = amd_pmu_init();
1616                 break;
1617         default:
1618                 err = -ENOTSUPP;
1619         }
1620         if (err != 0) {
1621                 pr_cont("no PMU driver, software events only.\n");
1622                 return 0;
1623         }
1624
1625         pmu_check_apic();
1626
1627         /* sanity check that the hardware exists or is emulated */
1628         if (!check_hw_exists())
1629                 return 0;
1630
1631         pr_cont("%s PMU driver.\n", x86_pmu.name);
1632
1633         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1634
1635         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1636                 quirk->func();
1637
1638         if (!x86_pmu.intel_ctrl)
1639                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1640
1641         perf_events_lapic_init();
1642         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1643
1644         unconstrained = (struct event_constraint)
1645                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1646                                    0, x86_pmu.num_counters, 0, 0);
1647
1648         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1649
1650         if (x86_pmu.event_attrs)
1651                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1652
1653         if (!x86_pmu.events_sysfs_show)
1654                 x86_pmu_events_group.attrs = &empty_attrs;
1655         else
1656                 filter_events(x86_pmu_events_group.attrs);
1657
1658         if (x86_pmu.cpu_events) {
1659                 struct attribute **tmp;
1660
1661                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1662                 if (!WARN_ON(!tmp))
1663                         x86_pmu_events_group.attrs = tmp;
1664         }
1665
1666         pr_info("... version:                %d\n",     x86_pmu.version);
1667         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1668         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1669         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1670         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1671         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1672         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1673
1674         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1675         perf_cpu_notifier(x86_pmu_notifier);
1676
1677         return 0;
1678 }
1679 early_initcall(init_hw_perf_events);
1680
1681 static inline void x86_pmu_read(struct perf_event *event)
1682 {
1683         x86_perf_event_update(event);
1684 }
1685
1686 /*
1687  * Start group events scheduling transaction
1688  * Set the flag to make pmu::enable() not perform the
1689  * schedulability test, it will be performed at commit time
1690  */
1691 static void x86_pmu_start_txn(struct pmu *pmu)
1692 {
1693         perf_pmu_disable(pmu);
1694         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1695         __this_cpu_write(cpu_hw_events.n_txn, 0);
1696 }
1697
1698 /*
1699  * Stop group events scheduling transaction
1700  * Clear the flag and pmu::enable() will perform the
1701  * schedulability test.
1702  */
1703 static void x86_pmu_cancel_txn(struct pmu *pmu)
1704 {
1705         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1706         /*
1707          * Truncate collected array by the number of events added in this
1708          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1709          */
1710         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1711         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1712         perf_pmu_enable(pmu);
1713 }
1714
1715 /*
1716  * Commit group events scheduling transaction
1717  * Perform the group schedulability test as a whole
1718  * Return 0 if success
1719  *
1720  * Does not cancel the transaction on failure; expects the caller to do this.
1721  */
1722 static int x86_pmu_commit_txn(struct pmu *pmu)
1723 {
1724         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1725         int assign[X86_PMC_IDX_MAX];
1726         int n, ret;
1727
1728         n = cpuc->n_events;
1729
1730         if (!x86_pmu_initialized())
1731                 return -EAGAIN;
1732
1733         ret = x86_pmu.schedule_events(cpuc, n, assign);
1734         if (ret)
1735                 return ret;
1736
1737         /*
1738          * copy new assignment, now we know it is possible
1739          * will be used by hw_perf_enable()
1740          */
1741         memcpy(cpuc->assign, assign, n*sizeof(int));
1742
1743         cpuc->group_flag &= ~PERF_EVENT_TXN;
1744         perf_pmu_enable(pmu);
1745         return 0;
1746 }
1747 /*
1748  * a fake_cpuc is used to validate event groups. Due to
1749  * the extra reg logic, we need to also allocate a fake
1750  * per_core and per_cpu structure. Otherwise, group events
1751  * using extra reg may conflict without the kernel being
1752  * able to catch this when the last event gets added to
1753  * the group.
1754  */
1755 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1756 {
1757         kfree(cpuc->shared_regs);
1758         kfree(cpuc);
1759 }
1760
1761 static struct cpu_hw_events *allocate_fake_cpuc(void)
1762 {
1763         struct cpu_hw_events *cpuc;
1764         int cpu = raw_smp_processor_id();
1765
1766         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1767         if (!cpuc)
1768                 return ERR_PTR(-ENOMEM);
1769
1770         /* only needed, if we have extra_regs */
1771         if (x86_pmu.extra_regs) {
1772                 cpuc->shared_regs = allocate_shared_regs(cpu);
1773                 if (!cpuc->shared_regs)
1774                         goto error;
1775         }
1776         cpuc->is_fake = 1;
1777         return cpuc;
1778 error:
1779         free_fake_cpuc(cpuc);
1780         return ERR_PTR(-ENOMEM);
1781 }
1782
1783 /*
1784  * validate that we can schedule this event
1785  */
1786 static int validate_event(struct perf_event *event)
1787 {
1788         struct cpu_hw_events *fake_cpuc;
1789         struct event_constraint *c;
1790         int ret = 0;
1791
1792         fake_cpuc = allocate_fake_cpuc();
1793         if (IS_ERR(fake_cpuc))
1794                 return PTR_ERR(fake_cpuc);
1795
1796         c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1797
1798         if (!c || !c->weight)
1799                 ret = -EINVAL;
1800
1801         if (x86_pmu.put_event_constraints)
1802                 x86_pmu.put_event_constraints(fake_cpuc, event);
1803
1804         free_fake_cpuc(fake_cpuc);
1805
1806         return ret;
1807 }
1808
1809 /*
1810  * validate a single event group
1811  *
1812  * validation include:
1813  *      - check events are compatible which each other
1814  *      - events do not compete for the same counter
1815  *      - number of events <= number of counters
1816  *
1817  * validation ensures the group can be loaded onto the
1818  * PMU if it was the only group available.
1819  */
1820 static int validate_group(struct perf_event *event)
1821 {
1822         struct perf_event *leader = event->group_leader;
1823         struct cpu_hw_events *fake_cpuc;
1824         int ret = -EINVAL, n;
1825
1826         fake_cpuc = allocate_fake_cpuc();
1827         if (IS_ERR(fake_cpuc))
1828                 return PTR_ERR(fake_cpuc);
1829         /*
1830          * the event is not yet connected with its
1831          * siblings therefore we must first collect
1832          * existing siblings, then add the new event
1833          * before we can simulate the scheduling
1834          */
1835         n = collect_events(fake_cpuc, leader, true);
1836         if (n < 0)
1837                 goto out;
1838
1839         fake_cpuc->n_events = n;
1840         n = collect_events(fake_cpuc, event, false);
1841         if (n < 0)
1842                 goto out;
1843
1844         fake_cpuc->n_events = n;
1845
1846         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1847
1848 out:
1849         free_fake_cpuc(fake_cpuc);
1850         return ret;
1851 }
1852
1853 static int x86_pmu_event_init(struct perf_event *event)
1854 {
1855         struct pmu *tmp;
1856         int err;
1857
1858         switch (event->attr.type) {
1859         case PERF_TYPE_RAW:
1860         case PERF_TYPE_HARDWARE:
1861         case PERF_TYPE_HW_CACHE:
1862                 break;
1863
1864         default:
1865                 return -ENOENT;
1866         }
1867
1868         err = __x86_pmu_event_init(event);
1869         if (!err) {
1870                 /*
1871                  * we temporarily connect event to its pmu
1872                  * such that validate_group() can classify
1873                  * it as an x86 event using is_x86_event()
1874                  */
1875                 tmp = event->pmu;
1876                 event->pmu = &pmu;
1877
1878                 if (event->group_leader != event)
1879                         err = validate_group(event);
1880                 else
1881                         err = validate_event(event);
1882
1883                 event->pmu = tmp;
1884         }
1885         if (err) {
1886                 if (event->destroy)
1887                         event->destroy(event);
1888         }
1889
1890         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
1891                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
1892
1893         return err;
1894 }
1895
1896 static void refresh_pce(void *ignored)
1897 {
1898         if (current->mm)
1899                 load_mm_cr4(current->mm);
1900 }
1901
1902 static void x86_pmu_event_mapped(struct perf_event *event)
1903 {
1904         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1905                 return;
1906
1907         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
1908                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1909 }
1910
1911 static void x86_pmu_event_unmapped(struct perf_event *event)
1912 {
1913         if (!current->mm)
1914                 return;
1915
1916         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1917                 return;
1918
1919         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
1920                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1921 }
1922
1923 static int x86_pmu_event_idx(struct perf_event *event)
1924 {
1925         int idx = event->hw.idx;
1926
1927         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1928                 return 0;
1929
1930         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1931                 idx -= INTEL_PMC_IDX_FIXED;
1932                 idx |= 1 << 30;
1933         }
1934
1935         return idx + 1;
1936 }
1937
1938 static ssize_t get_attr_rdpmc(struct device *cdev,
1939                               struct device_attribute *attr,
1940                               char *buf)
1941 {
1942         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1943 }
1944
1945 static ssize_t set_attr_rdpmc(struct device *cdev,
1946                               struct device_attribute *attr,
1947                               const char *buf, size_t count)
1948 {
1949         unsigned long val;
1950         ssize_t ret;
1951
1952         ret = kstrtoul(buf, 0, &val);
1953         if (ret)
1954                 return ret;
1955
1956         if (val > 2)
1957                 return -EINVAL;
1958
1959         if (x86_pmu.attr_rdpmc_broken)
1960                 return -ENOTSUPP;
1961
1962         if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
1963                 /*
1964                  * Changing into or out of always available, aka
1965                  * perf-event-bypassing mode.  This path is extremely slow,
1966                  * but only root can trigger it, so it's okay.
1967                  */
1968                 if (val == 2)
1969                         static_key_slow_inc(&rdpmc_always_available);
1970                 else
1971                         static_key_slow_dec(&rdpmc_always_available);
1972                 on_each_cpu(refresh_pce, NULL, 1);
1973         }
1974
1975         x86_pmu.attr_rdpmc = val;
1976
1977         return count;
1978 }
1979
1980 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1981
1982 static struct attribute *x86_pmu_attrs[] = {
1983         &dev_attr_rdpmc.attr,
1984         NULL,
1985 };
1986
1987 static struct attribute_group x86_pmu_attr_group = {
1988         .attrs = x86_pmu_attrs,
1989 };
1990
1991 static const struct attribute_group *x86_pmu_attr_groups[] = {
1992         &x86_pmu_attr_group,
1993         &x86_pmu_format_group,
1994         &x86_pmu_events_group,
1995         NULL,
1996 };
1997
1998 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
1999 {
2000         if (x86_pmu.sched_task)
2001                 x86_pmu.sched_task(ctx, sched_in);
2002 }
2003
2004 void perf_check_microcode(void)
2005 {
2006         if (x86_pmu.check_microcode)
2007                 x86_pmu.check_microcode();
2008 }
2009 EXPORT_SYMBOL_GPL(perf_check_microcode);
2010
2011 static struct pmu pmu = {
2012         .pmu_enable             = x86_pmu_enable,
2013         .pmu_disable            = x86_pmu_disable,
2014
2015         .attr_groups            = x86_pmu_attr_groups,
2016
2017         .event_init             = x86_pmu_event_init,
2018
2019         .event_mapped           = x86_pmu_event_mapped,
2020         .event_unmapped         = x86_pmu_event_unmapped,
2021
2022         .add                    = x86_pmu_add,
2023         .del                    = x86_pmu_del,
2024         .start                  = x86_pmu_start,
2025         .stop                   = x86_pmu_stop,
2026         .read                   = x86_pmu_read,
2027
2028         .start_txn              = x86_pmu_start_txn,
2029         .cancel_txn             = x86_pmu_cancel_txn,
2030         .commit_txn             = x86_pmu_commit_txn,
2031
2032         .event_idx              = x86_pmu_event_idx,
2033         .sched_task             = x86_pmu_sched_task,
2034         .task_ctx_size          = sizeof(struct x86_perf_task_context),
2035 };
2036
2037 void arch_perf_update_userpage(struct perf_event *event,
2038                                struct perf_event_mmap_page *userpg, u64 now)
2039 {
2040         struct cyc2ns_data *data;
2041
2042         userpg->cap_user_time = 0;
2043         userpg->cap_user_time_zero = 0;
2044         userpg->cap_user_rdpmc =
2045                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2046         userpg->pmc_width = x86_pmu.cntval_bits;
2047
2048         if (!sched_clock_stable())
2049                 return;
2050
2051         data = cyc2ns_read_begin();
2052
2053         /*
2054          * Internal timekeeping for enabled/running/stopped times
2055          * is always in the local_clock domain.
2056          */
2057         userpg->cap_user_time = 1;
2058         userpg->time_mult = data->cyc2ns_mul;
2059         userpg->time_shift = data->cyc2ns_shift;
2060         userpg->time_offset = data->cyc2ns_offset - now;
2061
2062         /*
2063          * cap_user_time_zero doesn't make sense when we're using a different
2064          * time base for the records.
2065          */
2066         if (event->clock == &local_clock) {
2067                 userpg->cap_user_time_zero = 1;
2068                 userpg->time_zero = data->cyc2ns_offset;
2069         }
2070
2071         cyc2ns_read_end(data);
2072 }
2073
2074 /*
2075  * callchain support
2076  */
2077
2078 static int backtrace_stack(void *data, char *name)
2079 {
2080         return 0;
2081 }
2082
2083 static void backtrace_address(void *data, unsigned long addr, int reliable)
2084 {
2085         struct perf_callchain_entry *entry = data;
2086
2087         perf_callchain_store(entry, addr);
2088 }
2089
2090 static const struct stacktrace_ops backtrace_ops = {
2091         .stack                  = backtrace_stack,
2092         .address                = backtrace_address,
2093         .walk_stack             = print_context_stack_bp,
2094 };
2095
2096 void
2097 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2098 {
2099         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2100                 /* TODO: We don't support guest os callchain now */
2101                 return;
2102         }
2103
2104         perf_callchain_store(entry, regs->ip);
2105
2106         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2107 }
2108
2109 static inline int
2110 valid_user_frame(const void __user *fp, unsigned long size)
2111 {
2112         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2113 }
2114
2115 static unsigned long get_segment_base(unsigned int segment)
2116 {
2117         struct desc_struct *desc;
2118         int idx = segment >> 3;
2119
2120         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2121                 if (idx > LDT_ENTRIES)
2122                         return 0;
2123
2124                 if (idx > current->active_mm->context.size)
2125                         return 0;
2126
2127                 desc = current->active_mm->context.ldt;
2128         } else {
2129                 if (idx > GDT_ENTRIES)
2130                         return 0;
2131
2132                 desc = raw_cpu_ptr(gdt_page.gdt);
2133         }
2134
2135         return get_desc_base(desc + idx);
2136 }
2137
2138 #ifdef CONFIG_COMPAT
2139
2140 #include <asm/compat.h>
2141
2142 static inline int
2143 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2144 {
2145         /* 32-bit process in 64-bit kernel. */
2146         unsigned long ss_base, cs_base;
2147         struct stack_frame_ia32 frame;
2148         const void __user *fp;
2149
2150         if (!test_thread_flag(TIF_IA32))
2151                 return 0;
2152
2153         cs_base = get_segment_base(regs->cs);
2154         ss_base = get_segment_base(regs->ss);
2155
2156         fp = compat_ptr(ss_base + regs->bp);
2157         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2158                 unsigned long bytes;
2159                 frame.next_frame     = 0;
2160                 frame.return_address = 0;
2161
2162                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2163                 if (bytes != 0)
2164                         break;
2165
2166                 if (!valid_user_frame(fp, sizeof(frame)))
2167                         break;
2168
2169                 perf_callchain_store(entry, cs_base + frame.return_address);
2170                 fp = compat_ptr(ss_base + frame.next_frame);
2171         }
2172         return 1;
2173 }
2174 #else
2175 static inline int
2176 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2177 {
2178     return 0;
2179 }
2180 #endif
2181
2182 void
2183 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2184 {
2185         struct stack_frame frame;
2186         const void __user *fp;
2187
2188         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2189                 /* TODO: We don't support guest os callchain now */
2190                 return;
2191         }
2192
2193         /*
2194          * We don't know what to do with VM86 stacks.. ignore them for now.
2195          */
2196         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2197                 return;
2198
2199         fp = (void __user *)regs->bp;
2200
2201         perf_callchain_store(entry, regs->ip);
2202
2203         if (!current->mm)
2204                 return;
2205
2206         if (perf_callchain_user32(regs, entry))
2207                 return;
2208
2209         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2210                 unsigned long bytes;
2211                 frame.next_frame             = NULL;
2212                 frame.return_address = 0;
2213
2214                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2215                 if (bytes != 0)
2216                         break;
2217
2218                 if (!valid_user_frame(fp, sizeof(frame)))
2219                         break;
2220
2221                 perf_callchain_store(entry, frame.return_address);
2222                 fp = frame.next_frame;
2223         }
2224 }
2225
2226 /*
2227  * Deal with code segment offsets for the various execution modes:
2228  *
2229  *   VM86 - the good olde 16 bit days, where the linear address is
2230  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2231  *
2232  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2233  *          to figure out what the 32bit base address is.
2234  *
2235  *    X32 - has TIF_X32 set, but is running in x86_64
2236  *
2237  * X86_64 - CS,DS,SS,ES are all zero based.
2238  */
2239 static unsigned long code_segment_base(struct pt_regs *regs)
2240 {
2241         /*
2242          * For IA32 we look at the GDT/LDT segment base to convert the
2243          * effective IP to a linear address.
2244          */
2245
2246 #ifdef CONFIG_X86_32
2247         /*
2248          * If we are in VM86 mode, add the segment offset to convert to a
2249          * linear address.
2250          */
2251         if (regs->flags & X86_VM_MASK)
2252                 return 0x10 * regs->cs;
2253
2254         if (user_mode(regs) && regs->cs != __USER_CS)
2255                 return get_segment_base(regs->cs);
2256 #else
2257         if (user_mode(regs) && !user_64bit_mode(regs) &&
2258             regs->cs != __USER32_CS)
2259                 return get_segment_base(regs->cs);
2260 #endif
2261         return 0;
2262 }
2263
2264 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2265 {
2266         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2267                 return perf_guest_cbs->get_guest_ip();
2268
2269         return regs->ip + code_segment_base(regs);
2270 }
2271
2272 unsigned long perf_misc_flags(struct pt_regs *regs)
2273 {
2274         int misc = 0;
2275
2276         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2277                 if (perf_guest_cbs->is_user_mode())
2278                         misc |= PERF_RECORD_MISC_GUEST_USER;
2279                 else
2280                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2281         } else {
2282                 if (user_mode(regs))
2283                         misc |= PERF_RECORD_MISC_USER;
2284                 else
2285                         misc |= PERF_RECORD_MISC_KERNEL;
2286         }
2287
2288         if (regs->flags & PERF_EFLAGS_EXACT)
2289                 misc |= PERF_RECORD_MISC_EXACT_IP;
2290
2291         return misc;
2292 }
2293
2294 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2295 {
2296         cap->version            = x86_pmu.version;
2297         cap->num_counters_gp    = x86_pmu.num_counters;
2298         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2299         cap->bit_width_gp       = x86_pmu.cntval_bits;
2300         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2301         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2302         cap->events_mask_len    = x86_pmu.events_mask_len;
2303 }
2304 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);