arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         int type = in_nmi() ? KM_NMI : KM_IRQ0;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page, type);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map, type);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 #define MAX_LBR_ENTRIES         16
  98
  99 struct cpu_hw_events {
 100         /*
 101          * Generic x86 PMC bits
 102          */
 103         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 104         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     n_txn;
 110         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 111         u64                     tags[X86_PMC_IDX_MAX];
 112         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 113
 114         unsigned int            group_flag;
 115
 116         /*
 117          * Intel DebugStore bits
 118          */
 119         struct debug_store      *ds;
 120         u64                     pebs_enabled;
 121
 122         /*
 123          * Intel LBR bits
 124          */
 125         int                             lbr_users;
 126         void                            *lbr_context;
 127         struct perf_branch_stack        lbr_stack;
 128         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 129
 130         /*
 131          * AMD specific bits
 132          */
 133         struct amd_nb           *amd_nb;
 134 };
 135
 136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 137         { .idxmsk64 = (n) },            \
 138         .code = (c),                    \
 139         .cmask = (m),                   \
 140         .weight = (w),                  \
 141 }
 142
 143 #define EVENT_CONSTRAINT(c, n, m)       \
 144         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 145
 146 /*
 147  * Constraint on the Event code.
 148  */
 149 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 150         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 151
 152 /*
 153  * Constraint on the Event code + UMask + fixed-mask
 154  *
 155  * filter mask to validate fixed counter events.
 156  * the following filters disqualify for fixed counters:
 157  *  - inv
 158  *  - edge
 159  *  - cnt-mask
 160  *  The other filters are supported by fixed counters.
 161  *  The any-thread option is supported starting with v3.
 162  */
 163 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 164         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 165
 166 /*
 167  * Constraint on the Event code + UMask
 168  */
 169 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 170         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 171
 172 #define EVENT_CONSTRAINT_END            \
 173         EVENT_CONSTRAINT(0, 0, 0)
 174
 175 #define for_each_event_constraint(e, c) \
 176         for ((e) = (c); (e)->weight; (e)++)
 177
 178 union perf_capabilities {
 179         struct {
 180                 u64     lbr_format    : 6;
 181                 u64     pebs_trap     : 1;
 182                 u64     pebs_arch_reg : 1;
 183                 u64     pebs_format   : 4;
 184                 u64     smm_freeze    : 1;
 185         };
 186         u64     capabilities;
 187 };
 188
 189 /*
 190  * struct x86_pmu - generic x86 pmu
 191  */
 192 struct x86_pmu {
 193         /*
 194          * Generic x86 PMC bits
 195          */
 196         const char      *name;
 197         int             version;
 198         int             (*handle_irq)(struct pt_regs *);
 199         void            (*disable_all)(void);
 200         void            (*enable_all)(int added);
 201         void            (*enable)(struct perf_event *);
 202         void            (*disable)(struct perf_event *);
 203         int             (*hw_config)(struct perf_event *event);
 204         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 205         unsigned        eventsel;
 206         unsigned        perfctr;
 207         u64             (*event_map)(int);
 208         int             max_events;
 209         int             num_counters;
 210         int             num_counters_fixed;
 211         int             cntval_bits;
 212         u64             cntval_mask;
 213         int             apic;
 214         u64             max_period;
 215         struct event_constraint *
 216                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218
 219         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 220                                                  struct perf_event *event);
 221         struct event_constraint *event_constraints;
 222         void            (*quirks)(void);
 223
 224         int             (*cpu_prepare)(int cpu);
 225         void            (*cpu_starting)(int cpu);
 226         void            (*cpu_dying)(int cpu);
 227         void            (*cpu_dead)(int cpu);
 228
 229         /*
 230          * Intel Arch Perfmon v2+
 231          */
 232         u64                     intel_ctrl;
 233         union perf_capabilities intel_cap;
 234
 235         /*
 236          * Intel DebugStore bits
 237          */
 238         int             bts, pebs;
 239         int             pebs_record_size;
 240         void            (*drain_pebs)(struct pt_regs *regs);
 241         struct event_constraint *pebs_constraints;
 242
 243         /*
 244          * Intel LBR
 245          */
 246         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 247         int             lbr_nr;                    /* hardware stack size */
 248 };
 249
 250 static struct x86_pmu x86_pmu __read_mostly;
 251
 252 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 253         .enabled = 1,
 254 };
 255
 256 static int x86_perf_event_set_period(struct perf_event *event);
 257
 258 /*
 259  * Generalized hw caching related hw_event table, filled
 260  * in on a per model basis. A value of 0 means
 261  * 'not supported', -1 means 'hw_event makes no sense on
 262  * this CPU', any other value means the raw hw_event
 263  * ID.
 264  */
 265
 266 #define C(x) PERF_COUNT_HW_CACHE_##x
 267
 268 static u64 __read_mostly hw_cache_event_ids
 269                                 [PERF_COUNT_HW_CACHE_MAX]
 270                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 271                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 272
 273 /*
 274  * Propagate event elapsed time into the generic event.
 275  * Can only be executed on the CPU where the event is active.
 276  * Returns the delta events processed.
 277  */
 278 static u64
 279 x86_perf_event_update(struct perf_event *event)
 280 {
 281         struct hw_perf_event *hwc = &event->hw;
 282         int shift = 64 - x86_pmu.cntval_bits;
 283         u64 prev_raw_count, new_raw_count;
 284         int idx = hwc->idx;
 285         s64 delta;
 286
 287         if (idx == X86_PMC_IDX_FIXED_BTS)
 288                 return 0;
 289
 290         /*
 291          * Careful: an NMI might modify the previous event value.
 292          *
 293          * Our tactic to handle this is to first atomically read and
 294          * exchange a new raw count - then add that new-prev delta
 295          * count to the generic event atomically:
 296          */
 297 again:
 298         prev_raw_count = atomic64_read(&hwc->prev_count);
 299         rdmsrl(hwc->event_base + idx, new_raw_count);
 300
 301         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 302                                         new_raw_count) != prev_raw_count)
 303                 goto again;
 304
 305         /*
 306          * Now we have the new raw value and have updated the prev
 307          * timestamp already. We can now calculate the elapsed delta
 308          * (event-)time and add that to the generic event.
 309          *
 310          * Careful, not all hw sign-extends above the physical width
 311          * of the count.
 312          */
 313         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 314         delta >>= shift;
 315
 316         atomic64_add(delta, &event->count);
 317         atomic64_sub(delta, &hwc->period_left);
 318
 319         return new_raw_count;
 320 }
 321
 322 static atomic_t active_events;
 323 static DEFINE_MUTEX(pmc_reserve_mutex);
 324
 325 #ifdef CONFIG_X86_LOCAL_APIC
 326
 327 static bool reserve_pmc_hardware(void)
 328 {
 329         int i;
 330
 331         if (nmi_watchdog == NMI_LOCAL_APIC)
 332                 disable_lapic_nmi_watchdog();
 333
 334         for (i = 0; i < x86_pmu.num_counters; i++) {
 335                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 336                         goto perfctr_fail;
 337         }
 338
 339         for (i = 0; i < x86_pmu.num_counters; i++) {
 340                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 341                         goto eventsel_fail;
 342         }
 343
 344         return true;
 345
 346 eventsel_fail:
 347         for (i--; i >= 0; i--)
 348                 release_evntsel_nmi(x86_pmu.eventsel + i);
 349
 350         i = x86_pmu.num_counters;
 351
 352 perfctr_fail:
 353         for (i--; i >= 0; i--)
 354                 release_perfctr_nmi(x86_pmu.perfctr + i);
 355
 356         if (nmi_watchdog == NMI_LOCAL_APIC)
 357                 enable_lapic_nmi_watchdog();
 358
 359         return false;
 360 }
 361
 362 static void release_pmc_hardware(void)
 363 {
 364         int i;
 365
 366         for (i = 0; i < x86_pmu.num_counters; i++) {
 367                 release_perfctr_nmi(x86_pmu.perfctr + i);
 368                 release_evntsel_nmi(x86_pmu.eventsel + i);
 369         }
 370
 371         if (nmi_watchdog == NMI_LOCAL_APIC)
 372                 enable_lapic_nmi_watchdog();
 373 }
 374
 375 #else
 376
 377 static bool reserve_pmc_hardware(void) { return true; }
 378 static void release_pmc_hardware(void) {}
 379
 380 #endif
 381
 382 static int reserve_ds_buffers(void);
 383 static void release_ds_buffers(void);
 384
 385 static void hw_perf_event_destroy(struct perf_event *event)
 386 {
 387         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 388                 release_pmc_hardware();
 389                 release_ds_buffers();
 390                 mutex_unlock(&pmc_reserve_mutex);
 391         }
 392 }
 393
 394 static inline int x86_pmu_initialized(void)
 395 {
 396         return x86_pmu.handle_irq != NULL;
 397 }
 398
 399 static inline int
 400 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 401 {
 402         unsigned int cache_type, cache_op, cache_result;
 403         u64 config, val;
 404
 405         config = attr->config;
 406
 407         cache_type = (config >>  0) & 0xff;
 408         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 409                 return -EINVAL;
 410
 411         cache_op = (config >>  8) & 0xff;
 412         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 413                 return -EINVAL;
 414
 415         cache_result = (config >> 16) & 0xff;
 416         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 417                 return -EINVAL;
 418
 419         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 420
 421         if (val == 0)
 422                 return -ENOENT;
 423
 424         if (val == -1)
 425                 return -EINVAL;
 426
 427         hwc->config |= val;
 428
 429         return 0;
 430 }
 431
 432 static int x86_setup_perfctr(struct perf_event *event)
 433 {
 434         struct perf_event_attr *attr = &event->attr;
 435         struct hw_perf_event *hwc = &event->hw;
 436         u64 config;
 437
 438         if (!hwc->sample_period) {
 439                 hwc->sample_period = x86_pmu.max_period;
 440                 hwc->last_period = hwc->sample_period;
 441                 atomic64_set(&hwc->period_left, hwc->sample_period);
 442         } else {
 443                 /*
 444                  * If we have a PMU initialized but no APIC
 445                  * interrupts, we cannot sample hardware
 446                  * events (user-space has to fall back and
 447                  * sample via a hrtimer based software event):
 448                  */
 449                 if (!x86_pmu.apic)
 450                         return -EOPNOTSUPP;
 451         }
 452
 453         if (attr->type == PERF_TYPE_RAW)
 454                 return 0;
 455
 456         if (attr->type == PERF_TYPE_HW_CACHE)
 457                 return set_ext_hw_attr(hwc, attr);
 458
 459         if (attr->config >= x86_pmu.max_events)
 460                 return -EINVAL;
 461
 462         /*
 463          * The generic map:
 464          */
 465         config = x86_pmu.event_map(attr->config);
 466
 467         if (config == 0)
 468                 return -ENOENT;
 469
 470         if (config == -1LL)
 471                 return -EINVAL;
 472
 473         /*
 474          * Branch tracing:
 475          */
 476         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 477             (hwc->sample_period == 1)) {
 478                 /* BTS is not supported by this architecture. */
 479                 if (!x86_pmu.bts)
 480                         return -EOPNOTSUPP;
 481
 482                 /* BTS is currently only allowed for user-mode. */
 483                 if (!attr->exclude_kernel)
 484                         return -EOPNOTSUPP;
 485         }
 486
 487         hwc->config |= config;
 488
 489         return 0;
 490 }
 491
 492 static int x86_pmu_hw_config(struct perf_event *event)
 493 {
 494         if (event->attr.precise_ip) {
 495                 int precise = 0;
 496
 497                 /* Support for constant skid */
 498                 if (x86_pmu.pebs)
 499                         precise++;
 500
 501                 /* Support for IP fixup */
 502                 if (x86_pmu.lbr_nr)
 503                         precise++;
 504
 505                 if (event->attr.precise_ip > precise)
 506                         return -EOPNOTSUPP;
 507         }
 508
 509         /*
 510          * Generate PMC IRQs:
 511          * (keep 'enabled' bit clear for now)
 512          */
 513         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 514
 515         /*
 516          * Count user and OS events unless requested not to
 517          */
 518         if (!event->attr.exclude_user)
 519                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 520         if (!event->attr.exclude_kernel)
 521                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 522
 523         if (event->attr.type == PERF_TYPE_RAW)
 524                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 525
 526         return x86_setup_perfctr(event);
 527 }
 528
 529 /*
 530  * Setup the hardware configuration for a given attr_type
 531  */
 532 static int __hw_perf_event_init(struct perf_event *event)
 533 {
 534         int err;
 535
 536         if (!x86_pmu_initialized())
 537                 return -ENODEV;
 538
 539         err = 0;
 540         if (!atomic_inc_not_zero(&active_events)) {
 541                 mutex_lock(&pmc_reserve_mutex);
 542                 if (atomic_read(&active_events) == 0) {
 543                         if (!reserve_pmc_hardware())
 544                                 err = -EBUSY;
 545                         else {
 546                                 err = reserve_ds_buffers();
 547                                 if (err)
 548                                         release_pmc_hardware();
 549                         }
 550                 }
 551                 if (!err)
 552                         atomic_inc(&active_events);
 553                 mutex_unlock(&pmc_reserve_mutex);
 554         }
 555         if (err)
 556                 return err;
 557
 558         event->destroy = hw_perf_event_destroy;
 559
 560         event->hw.idx = -1;
 561         event->hw.last_cpu = -1;
 562         event->hw.last_tag = ~0ULL;
 563
 564         return x86_pmu.hw_config(event);
 565 }
 566
 567 static void x86_pmu_disable_all(void)
 568 {
 569         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 570         int idx;
 571
 572         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 573                 u64 val;
 574
 575                 if (!test_bit(idx, cpuc->active_mask))
 576                         continue;
 577                 rdmsrl(x86_pmu.eventsel + idx, val);
 578                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 579                         continue;
 580                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 581                 wrmsrl(x86_pmu.eventsel + idx, val);
 582         }
 583 }
 584
 585 void hw_perf_disable(void)
 586 {
 587         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 588
 589         if (!x86_pmu_initialized())
 590                 return;
 591
 592         if (!cpuc->enabled)
 593                 return;
 594
 595         cpuc->n_added = 0;
 596         cpuc->enabled = 0;
 597         barrier();
 598
 599         x86_pmu.disable_all();
 600 }
 601
 602 static void x86_pmu_enable_all(int added)
 603 {
 604         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 605         int idx;
 606
 607         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 608                 struct perf_event *event = cpuc->events[idx];
 609                 u64 val;
 610
 611                 if (!test_bit(idx, cpuc->active_mask))
 612                         continue;
 613
 614                 val = event->hw.config;
 615                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 616                 wrmsrl(x86_pmu.eventsel + idx, val);
 617         }
 618 }
 619
 620 static const struct pmu pmu;
 621
 622 static inline int is_x86_event(struct perf_event *event)
 623 {
 624         return event->pmu == &pmu;
 625 }
 626
 627 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 628 {
 629         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 630         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 631         int i, j, w, wmax, num = 0;
 632         struct hw_perf_event *hwc;
 633
 634         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 635
 636         for (i = 0; i < n; i++) {
 637                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 638                 constraints[i] = c;
 639         }
 640
 641         /*
 642          * fastpath, try to reuse previous register
 643          */
 644         for (i = 0; i < n; i++) {
 645                 hwc = &cpuc->event_list[i]->hw;
 646                 c = constraints[i];
 647
 648                 /* never assigned */
 649                 if (hwc->idx == -1)
 650                         break;
 651
 652                 /* constraint still honored */
 653                 if (!test_bit(hwc->idx, c->idxmsk))
 654                         break;
 655
 656                 /* not already used */
 657                 if (test_bit(hwc->idx, used_mask))
 658                         break;
 659
 660                 __set_bit(hwc->idx, used_mask);
 661                 if (assign)
 662                         assign[i] = hwc->idx;
 663         }
 664         if (i == n)
 665                 goto done;
 666
 667         /*
 668          * begin slow path
 669          */
 670
 671         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 672
 673         /*
 674          * weight = number of possible counters
 675          *
 676          * 1    = most constrained, only works on one counter
 677          * wmax = least constrained, works on any counter
 678          *
 679          * assign events to counters starting with most
 680          * constrained events.
 681          */
 682         wmax = x86_pmu.num_counters;
 683
 684         /*
 685          * when fixed event counters are present,
 686          * wmax is incremented by 1 to account
 687          * for one more choice
 688          */
 689         if (x86_pmu.num_counters_fixed)
 690                 wmax++;
 691
 692         for (w = 1, num = n; num && w <= wmax; w++) {
 693                 /* for each event */
 694                 for (i = 0; num && i < n; i++) {
 695                         c = constraints[i];
 696                         hwc = &cpuc->event_list[i]->hw;
 697
 698                         if (c->weight != w)
 699                                 continue;
 700
 701                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 702                                 if (!test_bit(j, used_mask))
 703                                         break;
 704                         }
 705
 706                         if (j == X86_PMC_IDX_MAX)
 707                                 break;
 708
 709                         __set_bit(j, used_mask);
 710
 711                         if (assign)
 712                                 assign[i] = j;
 713                         num--;
 714                 }
 715         }
 716 done:
 717         /*
 718          * scheduling failed or is just a simulation,
 719          * free resources if necessary
 720          */
 721         if (!assign || num) {
 722                 for (i = 0; i < n; i++) {
 723                         if (x86_pmu.put_event_constraints)
 724                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 725                 }
 726         }
 727         return num ? -ENOSPC : 0;
 728 }
 729
 730 /*
 731  * dogrp: true if must collect siblings events (group)
 732  * returns total number of events and error code
 733  */
 734 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 735 {
 736         struct perf_event *event;
 737         int n, max_count;
 738
 739         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 740
 741         /* current number of events already accepted */
 742         n = cpuc->n_events;
 743
 744         if (is_x86_event(leader)) {
 745                 if (n >= max_count)
 746                         return -ENOSPC;
 747                 cpuc->event_list[n] = leader;
 748                 n++;
 749         }
 750         if (!dogrp)
 751                 return n;
 752
 753         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 754                 if (!is_x86_event(event) ||
 755                     event->state <= PERF_EVENT_STATE_OFF)
 756                         continue;
 757
 758                 if (n >= max_count)
 759                         return -ENOSPC;
 760
 761                 cpuc->event_list[n] = event;
 762                 n++;
 763         }
 764         return n;
 765 }
 766
 767 static inline void x86_assign_hw_event(struct perf_event *event,
 768                                 struct cpu_hw_events *cpuc, int i)
 769 {
 770         struct hw_perf_event *hwc = &event->hw;
 771
 772         hwc->idx = cpuc->assign[i];
 773         hwc->last_cpu = smp_processor_id();
 774         hwc->last_tag = ++cpuc->tags[i];
 775
 776         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 777                 hwc->config_base = 0;
 778                 hwc->event_base = 0;
 779         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 780                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 781                 /*
 782                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 783                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 784                  */
 785                 hwc->event_base =
 786                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 787         } else {
 788                 hwc->config_base = x86_pmu.eventsel;
 789                 hwc->event_base  = x86_pmu.perfctr;
 790         }
 791 }
 792
 793 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 794                                         struct cpu_hw_events *cpuc,
 795                                         int i)
 796 {
 797         return hwc->idx == cpuc->assign[i] &&
 798                 hwc->last_cpu == smp_processor_id() &&
 799                 hwc->last_tag == cpuc->tags[i];
 800 }
 801
 802 static int x86_pmu_start(struct perf_event *event);
 803 static void x86_pmu_stop(struct perf_event *event);
 804
 805 void hw_perf_enable(void)
 806 {
 807         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 808         struct perf_event *event;
 809         struct hw_perf_event *hwc;
 810         int i, added = cpuc->n_added;
 811
 812         if (!x86_pmu_initialized())
 813                 return;
 814
 815         if (cpuc->enabled)
 816                 return;
 817
 818         if (cpuc->n_added) {
 819                 int n_running = cpuc->n_events - cpuc->n_added;
 820                 /*
 821                  * apply assignment obtained either from
 822                  * hw_perf_group_sched_in() or x86_pmu_enable()
 823                  *
 824                  * step1: save events moving to new counters
 825                  * step2: reprogram moved events into new counters
 826                  */
 827                 for (i = 0; i < n_running; i++) {
 828                         event = cpuc->event_list[i];
 829                         hwc = &event->hw;
 830
 831                         /*
 832                          * we can avoid reprogramming counter if:
 833                          * - assigned same counter as last time
 834                          * - running on same CPU as last time
 835                          * - no other event has used the counter since
 836                          */
 837                         if (hwc->idx == -1 ||
 838                             match_prev_assignment(hwc, cpuc, i))
 839                                 continue;
 840
 841                         x86_pmu_stop(event);
 842                 }
 843
 844                 for (i = 0; i < cpuc->n_events; i++) {
 845                         event = cpuc->event_list[i];
 846                         hwc = &event->hw;
 847
 848                         if (!match_prev_assignment(hwc, cpuc, i))
 849                                 x86_assign_hw_event(event, cpuc, i);
 850                         else if (i < n_running)
 851                                 continue;
 852
 853                         x86_pmu_start(event);
 854                 }
 855                 cpuc->n_added = 0;
 856                 perf_events_lapic_init();
 857         }
 858
 859         cpuc->enabled = 1;
 860         barrier();
 861
 862         x86_pmu.enable_all(added);
 863 }
 864
 865 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 866                                           u64 enable_mask)
 867 {
 868         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
 869 }
 870
 871 static inline void x86_pmu_disable_event(struct perf_event *event)
 872 {
 873         struct hw_perf_event *hwc = &event->hw;
 874
 875         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 876 }
 877
 878 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 879
 880 /*
 881  * Set the next IRQ period, based on the hwc->period_left value.
 882  * To be called with the event disabled in hw:
 883  */
 884 static int
 885 x86_perf_event_set_period(struct perf_event *event)
 886 {
 887         struct hw_perf_event *hwc = &event->hw;
 888         s64 left = atomic64_read(&hwc->period_left);
 889         s64 period = hwc->sample_period;
 890         int ret = 0, idx = hwc->idx;
 891
 892         if (idx == X86_PMC_IDX_FIXED_BTS)
 893                 return 0;
 894
 895         /*
 896          * If we are way outside a reasonable range then just skip forward:
 897          */
 898         if (unlikely(left <= -period)) {
 899                 left = period;
 900                 atomic64_set(&hwc->period_left, left);
 901                 hwc->last_period = period;
 902                 ret = 1;
 903         }
 904
 905         if (unlikely(left <= 0)) {
 906                 left += period;
 907                 atomic64_set(&hwc->period_left, left);
 908                 hwc->last_period = period;
 909                 ret = 1;
 910         }
 911         /*
 912          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 913          */
 914         if (unlikely(left < 2))
 915                 left = 2;
 916
 917         if (left > x86_pmu.max_period)
 918                 left = x86_pmu.max_period;
 919
 920         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 921
 922         /*
 923          * The hw event starts counting from this event offset,
 924          * mark it to be able to extra future deltas:
 925          */
 926         atomic64_set(&hwc->prev_count, (u64)-left);
 927
 928         wrmsrl(hwc->event_base + idx,
 929                         (u64)(-left) & x86_pmu.cntval_mask);
 930
 931         perf_event_update_userpage(event);
 932
 933         return ret;
 934 }
 935
 936 static void x86_pmu_enable_event(struct perf_event *event)
 937 {
 938         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 939         if (cpuc->enabled)
 940                 __x86_pmu_enable_event(&event->hw,
 941                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 942 }
 943
 944 /*
 945  * activate a single event
 946  *
 947  * The event is added to the group of enabled events
 948  * but only if it can be scehduled with existing events.
 949  *
 950  * Called with PMU disabled. If successful and return value 1,
 951  * then guaranteed to call perf_enable() and hw_perf_enable()
 952  */
 953 static int x86_pmu_enable(struct perf_event *event)
 954 {
 955         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 956         struct hw_perf_event *hwc;
 957         int assign[X86_PMC_IDX_MAX];
 958         int n, n0, ret;
 959
 960         hwc = &event->hw;
 961
 962         n0 = cpuc->n_events;
 963         n = collect_events(cpuc, event, false);
 964         if (n < 0)
 965                 return n;
 966
 967         /*
 968          * If group events scheduling transaction was started,
 969          * skip the schedulability test here, it will be peformed
 970          * at commit time(->commit_txn) as a whole
 971          */
 972         if (cpuc->group_flag & PERF_EVENT_TXN_STARTED)
 973                 goto out;
 974
 975         ret = x86_pmu.schedule_events(cpuc, n, assign);
 976         if (ret)
 977                 return ret;
 978         /*
 979          * copy new assignment, now we know it is possible
 980          * will be used by hw_perf_enable()
 981          */
 982         memcpy(cpuc->assign, assign, n*sizeof(int));
 983
 984 out:
 985         cpuc->n_events = n;
 986         cpuc->n_added += n - n0;
 987         cpuc->n_txn += n - n0;
 988
 989         return 0;
 990 }
 991
 992 static int x86_pmu_start(struct perf_event *event)
 993 {
 994         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 995         int idx = event->hw.idx;
 996
 997         if (idx == -1)
 998                 return -EAGAIN;
 999
1000         x86_perf_event_set_period(event);
1001         cpuc->events[idx] = event;
1002         __set_bit(idx, cpuc->active_mask);
1003         x86_pmu.enable(event);
1004         perf_event_update_userpage(event);
1005
1006         return 0;
1007 }
1008
1009 static void x86_pmu_unthrottle(struct perf_event *event)
1010 {
1011         int ret = x86_pmu_start(event);
1012         WARN_ON_ONCE(ret);
1013 }
1014
1015 void perf_event_print_debug(void)
1016 {
1017         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1018         u64 pebs;
1019         struct cpu_hw_events *cpuc;
1020         unsigned long flags;
1021         int cpu, idx;
1022
1023         if (!x86_pmu.num_counters)
1024                 return;
1025
1026         local_irq_save(flags);
1027
1028         cpu = smp_processor_id();
1029         cpuc = &per_cpu(cpu_hw_events, cpu);
1030
1031         if (x86_pmu.version >= 2) {
1032                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1033                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1034                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1035                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1036                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1037
1038                 pr_info("\n");
1039                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1040                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1041                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1042                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1043                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1044         }
1045         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1046
1047         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1048                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1049                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1050
1051                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1052
1053                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1054                         cpu, idx, pmc_ctrl);
1055                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1056                         cpu, idx, pmc_count);
1057                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1058                         cpu, idx, prev_left);
1059         }
1060         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1061                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1062
1063                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1064                         cpu, idx, pmc_count);
1065         }
1066         local_irq_restore(flags);
1067 }
1068
1069 static void x86_pmu_stop(struct perf_event *event)
1070 {
1071         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1072         struct hw_perf_event *hwc = &event->hw;
1073         int idx = hwc->idx;
1074
1075         if (!__test_and_clear_bit(idx, cpuc->active_mask))
1076                 return;
1077
1078         x86_pmu.disable(event);
1079
1080         /*
1081          * Drain the remaining delta count out of a event
1082          * that we are disabling:
1083          */
1084         x86_perf_event_update(event);
1085
1086         cpuc->events[idx] = NULL;
1087 }
1088
1089 static void x86_pmu_disable(struct perf_event *event)
1090 {
1091         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1092         int i;
1093
1094         /*
1095          * If we're called during a txn, we don't need to do anything.
1096          * The events never got scheduled and ->cancel_txn will truncate
1097          * the event_list.
1098          */
1099         if (cpuc->group_flag & PERF_EVENT_TXN_STARTED)
1100                 return;
1101
1102         x86_pmu_stop(event);
1103
1104         for (i = 0; i < cpuc->n_events; i++) {
1105                 if (event == cpuc->event_list[i]) {
1106
1107                         if (x86_pmu.put_event_constraints)
1108                                 x86_pmu.put_event_constraints(cpuc, event);
1109
1110                         while (++i < cpuc->n_events)
1111                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1112
1113                         --cpuc->n_events;
1114                         break;
1115                 }
1116         }
1117         perf_event_update_userpage(event);
1118 }
1119
1120 static int x86_pmu_handle_irq(struct pt_regs *regs)
1121 {
1122         struct perf_sample_data data;
1123         struct cpu_hw_events *cpuc;
1124         struct perf_event *event;
1125         struct hw_perf_event *hwc;
1126         int idx, handled = 0;
1127         u64 val;
1128
1129         perf_sample_data_init(&data, 0);
1130
1131         cpuc = &__get_cpu_var(cpu_hw_events);
1132
1133         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1134                 if (!test_bit(idx, cpuc->active_mask))
1135                         continue;
1136
1137                 event = cpuc->events[idx];
1138                 hwc = &event->hw;
1139
1140                 val = x86_perf_event_update(event);
1141                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1142                         continue;
1143
1144                 /*
1145                  * event overflow
1146                  */
1147                 handled         = 1;
1148                 data.period     = event->hw.last_period;
1149
1150                 if (!x86_perf_event_set_period(event))
1151                         continue;
1152
1153                 if (perf_event_overflow(event, 1, &data, regs))
1154                         x86_pmu_stop(event);
1155         }
1156
1157         if (handled)
1158                 inc_irq_stat(apic_perf_irqs);
1159
1160         return handled;
1161 }
1162
1163 void smp_perf_pending_interrupt(struct pt_regs *regs)
1164 {
1165         irq_enter();
1166         ack_APIC_irq();
1167         inc_irq_stat(apic_pending_irqs);
1168         perf_event_do_pending();
1169         irq_exit();
1170 }
1171
1172 void set_perf_event_pending(void)
1173 {
1174 #ifdef CONFIG_X86_LOCAL_APIC
1175         if (!x86_pmu.apic || !x86_pmu_initialized())
1176                 return;
1177
1178         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1179 #endif
1180 }
1181
1182 void perf_events_lapic_init(void)
1183 {
1184         if (!x86_pmu.apic || !x86_pmu_initialized())
1185                 return;
1186
1187         /*
1188          * Always use NMI for PMU
1189          */
1190         apic_write(APIC_LVTPC, APIC_DM_NMI);
1191 }
1192
1193 static int __kprobes
1194 perf_event_nmi_handler(struct notifier_block *self,
1195                          unsigned long cmd, void *__args)
1196 {
1197         struct die_args *args = __args;
1198         struct pt_regs *regs;
1199
1200         if (!atomic_read(&active_events))
1201                 return NOTIFY_DONE;
1202
1203         switch (cmd) {
1204         case DIE_NMI:
1205         case DIE_NMI_IPI:
1206                 break;
1207
1208         default:
1209                 return NOTIFY_DONE;
1210         }
1211
1212         regs = args->regs;
1213
1214         apic_write(APIC_LVTPC, APIC_DM_NMI);
1215         /*
1216          * Can't rely on the handled return value to say it was our NMI, two
1217          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1218          *
1219          * If the first NMI handles both, the latter will be empty and daze
1220          * the CPU.
1221          */
1222         x86_pmu.handle_irq(regs);
1223
1224         return NOTIFY_STOP;
1225 }
1226
1227 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1228         .notifier_call          = perf_event_nmi_handler,
1229         .next                   = NULL,
1230         .priority               = 1
1231 };
1232
1233 static struct event_constraint unconstrained;
1234 static struct event_constraint emptyconstraint;
1235
1236 static struct event_constraint *
1237 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1238 {
1239         struct event_constraint *c;
1240
1241         if (x86_pmu.event_constraints) {
1242                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1243                         if ((event->hw.config & c->cmask) == c->code)
1244                                 return c;
1245                 }
1246         }
1247
1248         return &unconstrained;
1249 }
1250
1251 #include "perf_event_amd.c"
1252 #include "perf_event_p6.c"
1253 #include "perf_event_p4.c"
1254 #include "perf_event_intel_lbr.c"
1255 #include "perf_event_intel_ds.c"
1256 #include "perf_event_intel.c"
1257
1258 static int __cpuinit
1259 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1260 {
1261         unsigned int cpu = (long)hcpu;
1262         int ret = NOTIFY_OK;
1263
1264         switch (action & ~CPU_TASKS_FROZEN) {
1265         case CPU_UP_PREPARE:
1266                 if (x86_pmu.cpu_prepare)
1267                         ret = x86_pmu.cpu_prepare(cpu);
1268                 break;
1269
1270         case CPU_STARTING:
1271                 if (x86_pmu.cpu_starting)
1272                         x86_pmu.cpu_starting(cpu);
1273                 break;
1274
1275         case CPU_DYING:
1276                 if (x86_pmu.cpu_dying)
1277                         x86_pmu.cpu_dying(cpu);
1278                 break;
1279
1280         case CPU_UP_CANCELED:
1281         case CPU_DEAD:
1282                 if (x86_pmu.cpu_dead)
1283                         x86_pmu.cpu_dead(cpu);
1284                 break;
1285
1286         default:
1287                 break;
1288         }
1289
1290         return ret;
1291 }
1292
1293 static void __init pmu_check_apic(void)
1294 {
1295         if (cpu_has_apic)
1296                 return;
1297
1298         x86_pmu.apic = 0;
1299         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1300         pr_info("no hardware sampling interrupt available.\n");
1301 }
1302
1303 void __init init_hw_perf_events(void)
1304 {
1305         struct event_constraint *c;
1306         int err;
1307
1308         pr_info("Performance Events: ");
1309
1310         switch (boot_cpu_data.x86_vendor) {
1311         case X86_VENDOR_INTEL:
1312                 err = intel_pmu_init();
1313                 break;
1314         case X86_VENDOR_AMD:
1315                 err = amd_pmu_init();
1316                 break;
1317         default:
1318                 return;
1319         }
1320         if (err != 0) {
1321                 pr_cont("no PMU driver, software events only.\n");
1322                 return;
1323         }
1324
1325         pmu_check_apic();
1326
1327         pr_cont("%s PMU driver.\n", x86_pmu.name);
1328
1329         if (x86_pmu.quirks)
1330                 x86_pmu.quirks();
1331
1332         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1333                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1334                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1335                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1336         }
1337         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1338         perf_max_events = x86_pmu.num_counters;
1339
1340         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1341                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1342                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1343                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1344         }
1345
1346         x86_pmu.intel_ctrl |=
1347                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1348
1349         perf_events_lapic_init();
1350         register_die_notifier(&perf_event_nmi_notifier);
1351
1352         unconstrained = (struct event_constraint)
1353                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1354                                    0, x86_pmu.num_counters);
1355
1356         if (x86_pmu.event_constraints) {
1357                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1358                         if (c->cmask != X86_RAW_EVENT_MASK)
1359                                 continue;
1360
1361                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1362                         c->weight += x86_pmu.num_counters;
1363                 }
1364         }
1365
1366         pr_info("... version:                %d\n",     x86_pmu.version);
1367         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1368         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1369         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1370         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1371         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1372         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1373
1374         perf_cpu_notifier(x86_pmu_notifier);
1375 }
1376
1377 static inline void x86_pmu_read(struct perf_event *event)
1378 {
1379         x86_perf_event_update(event);
1380 }
1381
1382 /*
1383  * Start group events scheduling transaction
1384  * Set the flag to make pmu::enable() not perform the
1385  * schedulability test, it will be performed at commit time
1386  */
1387 static void x86_pmu_start_txn(const struct pmu *pmu)
1388 {
1389         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1390
1391         cpuc->group_flag |= PERF_EVENT_TXN_STARTED;
1392         cpuc->n_txn = 0;
1393 }
1394
1395 /*
1396  * Stop group events scheduling transaction
1397  * Clear the flag and pmu::enable() will perform the
1398  * schedulability test.
1399  */
1400 static void x86_pmu_cancel_txn(const struct pmu *pmu)
1401 {
1402         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1403
1404         cpuc->group_flag &= ~PERF_EVENT_TXN_STARTED;
1405         /*
1406          * Truncate the collected events.
1407          */
1408         cpuc->n_added -= cpuc->n_txn;
1409         cpuc->n_events -= cpuc->n_txn;
1410 }
1411
1412 /*
1413  * Commit group events scheduling transaction
1414  * Perform the group schedulability test as a whole
1415  * Return 0 if success
1416  */
1417 static int x86_pmu_commit_txn(const struct pmu *pmu)
1418 {
1419         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1420         int assign[X86_PMC_IDX_MAX];
1421         int n, ret;
1422
1423         n = cpuc->n_events;
1424
1425         if (!x86_pmu_initialized())
1426                 return -EAGAIN;
1427
1428         ret = x86_pmu.schedule_events(cpuc, n, assign);
1429         if (ret)
1430                 return ret;
1431
1432         /*
1433          * copy new assignment, now we know it is possible
1434          * will be used by hw_perf_enable()
1435          */
1436         memcpy(cpuc->assign, assign, n*sizeof(int));
1437
1438         /*
1439          * Clear out the txn count so that ->cancel_txn() which gets
1440          * run after ->commit_txn() doesn't undo things.
1441          */
1442         cpuc->n_txn = 0;
1443
1444         return 0;
1445 }
1446
1447 static const struct pmu pmu = {
1448         .enable         = x86_pmu_enable,
1449         .disable        = x86_pmu_disable,
1450         .start          = x86_pmu_start,
1451         .stop           = x86_pmu_stop,
1452         .read           = x86_pmu_read,
1453         .unthrottle     = x86_pmu_unthrottle,
1454         .start_txn      = x86_pmu_start_txn,
1455         .cancel_txn     = x86_pmu_cancel_txn,
1456         .commit_txn     = x86_pmu_commit_txn,
1457 };
1458
1459 /*
1460  * validate that we can schedule this event
1461  */
1462 static int validate_event(struct perf_event *event)
1463 {
1464         struct cpu_hw_events *fake_cpuc;
1465         struct event_constraint *c;
1466         int ret = 0;
1467
1468         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1469         if (!fake_cpuc)
1470                 return -ENOMEM;
1471
1472         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1473
1474         if (!c || !c->weight)
1475                 ret = -ENOSPC;
1476
1477         if (x86_pmu.put_event_constraints)
1478                 x86_pmu.put_event_constraints(fake_cpuc, event);
1479
1480         kfree(fake_cpuc);
1481
1482         return ret;
1483 }
1484
1485 /*
1486  * validate a single event group
1487  *
1488  * validation include:
1489  *      - check events are compatible which each other
1490  *      - events do not compete for the same counter
1491  *      - number of events <= number of counters
1492  *
1493  * validation ensures the group can be loaded onto the
1494  * PMU if it was the only group available.
1495  */
1496 static int validate_group(struct perf_event *event)
1497 {
1498         struct perf_event *leader = event->group_leader;
1499         struct cpu_hw_events *fake_cpuc;
1500         int ret, n;
1501
1502         ret = -ENOMEM;
1503         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1504         if (!fake_cpuc)
1505                 goto out;
1506
1507         /*
1508          * the event is not yet connected with its
1509          * siblings therefore we must first collect
1510          * existing siblings, then add the new event
1511          * before we can simulate the scheduling
1512          */
1513         ret = -ENOSPC;
1514         n = collect_events(fake_cpuc, leader, true);
1515         if (n < 0)
1516                 goto out_free;
1517
1518         fake_cpuc->n_events = n;
1519         n = collect_events(fake_cpuc, event, false);
1520         if (n < 0)
1521                 goto out_free;
1522
1523         fake_cpuc->n_events = n;
1524
1525         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1526
1527 out_free:
1528         kfree(fake_cpuc);
1529 out:
1530         return ret;
1531 }
1532
1533 const struct pmu *hw_perf_event_init(struct perf_event *event)
1534 {
1535         const struct pmu *tmp;
1536         int err;
1537
1538         err = __hw_perf_event_init(event);
1539         if (!err) {
1540                 /*
1541                  * we temporarily connect event to its pmu
1542                  * such that validate_group() can classify
1543                  * it as an x86 event using is_x86_event()
1544                  */
1545                 tmp = event->pmu;
1546                 event->pmu = &pmu;
1547
1548                 if (event->group_leader != event)
1549                         err = validate_group(event);
1550                 else
1551                         err = validate_event(event);
1552
1553                 event->pmu = tmp;
1554         }
1555         if (err) {
1556                 if (event->destroy)
1557                         event->destroy(event);
1558                 return ERR_PTR(err);
1559         }
1560
1561         return &pmu;
1562 }
1563
1564 /*
1565  * callchain support
1566  */
1567
1568 static inline
1569 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1570 {
1571         if (entry->nr < PERF_MAX_STACK_DEPTH)
1572                 entry->ip[entry->nr++] = ip;
1573 }
1574
1575 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1576 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1577
1578
1579 static void
1580 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1581 {
1582         /* Ignore warnings */
1583 }
1584
1585 static void backtrace_warning(void *data, char *msg)
1586 {
1587         /* Ignore warnings */
1588 }
1589
1590 static int backtrace_stack(void *data, char *name)
1591 {
1592         return 0;
1593 }
1594
1595 static void backtrace_address(void *data, unsigned long addr, int reliable)
1596 {
1597         struct perf_callchain_entry *entry = data;
1598
1599         callchain_store(entry, addr);
1600 }
1601
1602 static const struct stacktrace_ops backtrace_ops = {
1603         .warning                = backtrace_warning,
1604         .warning_symbol         = backtrace_warning_symbol,
1605         .stack                  = backtrace_stack,
1606         .address                = backtrace_address,
1607         .walk_stack             = print_context_stack_bp,
1608 };
1609
1610 #include "../dumpstack.h"
1611
1612 static void
1613 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1614 {
1615         callchain_store(entry, PERF_CONTEXT_KERNEL);
1616         callchain_store(entry, regs->ip);
1617
1618         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1619 }
1620
1621 #ifdef CONFIG_COMPAT
1622 static inline int
1623 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1624 {
1625         /* 32-bit process in 64-bit kernel. */
1626         struct stack_frame_ia32 frame;
1627         const void __user *fp;
1628
1629         if (!test_thread_flag(TIF_IA32))
1630                 return 0;
1631
1632         fp = compat_ptr(regs->bp);
1633         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1634                 unsigned long bytes;
1635                 frame.next_frame     = 0;
1636                 frame.return_address = 0;
1637
1638                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1639                 if (bytes != sizeof(frame))
1640                         break;
1641
1642                 if (fp < compat_ptr(regs->sp))
1643                         break;
1644
1645                 callchain_store(entry, frame.return_address);
1646                 fp = compat_ptr(frame.next_frame);
1647         }
1648         return 1;
1649 }
1650 #else
1651 static inline int
1652 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1653 {
1654     return 0;
1655 }
1656 #endif
1657
1658 static void
1659 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1660 {
1661         struct stack_frame frame;
1662         const void __user *fp;
1663
1664         if (!user_mode(regs))
1665                 regs = task_pt_regs(current);
1666
1667         fp = (void __user *)regs->bp;
1668
1669         callchain_store(entry, PERF_CONTEXT_USER);
1670         callchain_store(entry, regs->ip);
1671
1672         if (perf_callchain_user32(regs, entry))
1673                 return;
1674
1675         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1676                 unsigned long bytes;
1677                 frame.next_frame             = NULL;
1678                 frame.return_address = 0;
1679
1680                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1681                 if (bytes != sizeof(frame))
1682                         break;
1683
1684                 if ((unsigned long)fp < regs->sp)
1685                         break;
1686
1687                 callchain_store(entry, frame.return_address);
1688                 fp = frame.next_frame;
1689         }
1690 }
1691
1692 static void
1693 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1694 {
1695         int is_user;
1696
1697         if (!regs)
1698                 return;
1699
1700         is_user = user_mode(regs);
1701
1702         if (is_user && current->state != TASK_RUNNING)
1703                 return;
1704
1705         if (!is_user)
1706                 perf_callchain_kernel(regs, entry);
1707
1708         if (current->mm)
1709                 perf_callchain_user(regs, entry);
1710 }
1711
1712 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1713 {
1714         struct perf_callchain_entry *entry;
1715
1716         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1717                 /* TODO: We don't support guest os callchain now */
1718                 return NULL;
1719         }
1720
1721         if (in_nmi())
1722                 entry = &__get_cpu_var(pmc_nmi_entry);
1723         else
1724                 entry = &__get_cpu_var(pmc_irq_entry);
1725
1726         entry->nr = 0;
1727
1728         perf_do_callchain(regs, entry);
1729
1730         return entry;
1731 }
1732
1733 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1734 {
1735         regs->ip = ip;
1736         /*
1737          * perf_arch_fetch_caller_regs adds another call, we need to increment
1738          * the skip level
1739          */
1740         regs->bp = rewind_frame_pointer(skip + 1);
1741         regs->cs = __KERNEL_CS;
1742         /*
1743          * We abuse bit 3 to pass exact information, see perf_misc_flags
1744          * and the comment with PERF_EFLAGS_EXACT.
1745          */
1746         regs->flags = 0;
1747 }
1748
1749 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1750 {
1751         unsigned long ip;
1752
1753         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1754                 ip = perf_guest_cbs->get_guest_ip();
1755         else
1756                 ip = instruction_pointer(regs);
1757
1758         return ip;
1759 }
1760
1761 unsigned long perf_misc_flags(struct pt_regs *regs)
1762 {
1763         int misc = 0;
1764
1765         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1766                 if (perf_guest_cbs->is_user_mode())
1767                         misc |= PERF_RECORD_MISC_GUEST_USER;
1768                 else
1769                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1770         } else {
1771                 if (user_mode(regs))
1772                         misc |= PERF_RECORD_MISC_USER;
1773                 else
1774                         misc |= PERF_RECORD_MISC_KERNEL;
1775         }
1776
1777         if (regs->flags & PERF_EFLAGS_EXACT)
1778                 misc |= PERF_RECORD_MISC_EXACT_IP;
1779
1780         return misc;
1781 }