arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/vmx.h>
  26 #include <asm/paravirt.h>
  27 #include <asm/alternative.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/set_memory.h>
  30 #include <asm/intel-family.h>
  31 #include <asm/e820/api.h>
  32 #include <asm/hypervisor.h>
  33
  34 static void __init spectre_v2_select_mitigation(void);
  35 static void __init ssb_select_mitigation(void);
  36 static void __init l1tf_select_mitigation(void);
  37
  38 /*
  39  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  40  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  41  */
  42 u64 __ro_after_init x86_spec_ctrl_base;
  43 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  44
  45 /*
  46  * The vendor and possibly platform specific bits which can be modified in
  47  * x86_spec_ctrl_base.
  48  */
  49 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  50
  51 /*
  52  * AMD specific MSR info for Speculative Store Bypass control.
  53  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  54  */
  55 u64 __ro_after_init x86_amd_ls_cfg_base;
  56 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  57
  58 void __init check_bugs(void)
  59 {
  60         identify_boot_cpu();
  61
  62         /*
  63          * identify_boot_cpu() initialized SMT support information, let the
  64          * core code know.
  65          */
  66         cpu_smt_check_topology_early();
  67
  68         if (!IS_ENABLED(CONFIG_SMP)) {
  69                 pr_info("CPU: ");
  70                 print_cpu_info(&boot_cpu_data);
  71         }
  72
  73         /*
  74          * Read the SPEC_CTRL MSR to account for reserved bits which may
  75          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  76          * init code as it is not enumerated and depends on the family.
  77          */
  78         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  79                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  80
  81         /* Allow STIBP in MSR_SPEC_CTRL if supported */
  82         if (boot_cpu_has(X86_FEATURE_STIBP))
  83                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
  84
  85         /* Select the proper spectre mitigation before patching alternatives */
  86         spectre_v2_select_mitigation();
  87
  88         /*
  89          * Select proper mitigation for any exposure to the Speculative Store
  90          * Bypass vulnerability.
  91          */
  92         ssb_select_mitigation();
  93
  94         l1tf_select_mitigation();
  95
  96 #ifdef CONFIG_X86_32
  97         /*
  98          * Check whether we are able to run this kernel safely on SMP.
  99          *
 100          * - i386 is no longer supported.
 101          * - In order to run on anything without a TSC, we need to be
 102          *   compiled for a i486.
 103          */
 104         if (boot_cpu_data.x86 < 4)
 105                 panic("Kernel requires i486+ for 'invlpg' and other features");
 106
 107         init_utsname()->machine[1] =
 108                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 109         alternative_instructions();
 110
 111         fpu__init_check_bugs();
 112 #else /* CONFIG_X86_64 */
 113         alternative_instructions();
 114
 115         /*
 116          * Make sure the first 2MB area is not mapped by huge pages
 117          * There are typically fixed size MTRRs in there and overlapping
 118          * MTRRs into large pages causes slow downs.
 119          *
 120          * Right now we don't do that with gbpages because there seems
 121          * very little benefit for that case.
 122          */
 123         if (!direct_gbpages)
 124                 set_memory_4k((unsigned long)__va(0), 1);
 125 #endif
 126 }
 127
 128 /* The kernel command line selection */
 129 enum spectre_v2_mitigation_cmd {
 130         SPECTRE_V2_CMD_NONE,
 131         SPECTRE_V2_CMD_AUTO,
 132         SPECTRE_V2_CMD_FORCE,
 133         SPECTRE_V2_CMD_RETPOLINE,
 134         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 135         SPECTRE_V2_CMD_RETPOLINE_AMD,
 136 };
 137
 138 static const char *spectre_v2_strings[] = {
 139         [SPECTRE_V2_NONE]                       = "Vulnerable",
 140         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 141         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 142         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 143         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 144         [SPECTRE_V2_IBRS_ENHANCED]              = "Mitigation: Enhanced IBRS",
 145 };
 146
 147 #undef pr_fmt
 148 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 149
 150 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 151         SPECTRE_V2_NONE;
 152
 153 void
 154 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 155 {
 156         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 157         struct thread_info *ti = current_thread_info();
 158
 159         /* Is MSR_SPEC_CTRL implemented ? */
 160         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 161                 /*
 162                  * Restrict guest_spec_ctrl to supported values. Clear the
 163                  * modifiable bits in the host base value and or the
 164                  * modifiable bits from the guest value.
 165                  */
 166                 guestval = hostval & ~x86_spec_ctrl_mask;
 167                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 168
 169                 /* SSBD controlled in MSR_SPEC_CTRL */
 170                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 171                     static_cpu_has(X86_FEATURE_AMD_SSBD))
 172                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 173
 174                 if (hostval != guestval) {
 175                         msrval = setguest ? guestval : hostval;
 176                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 177                 }
 178         }
 179
 180         /*
 181          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 182          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 183          */
 184         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 185             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 186                 return;
 187
 188         /*
 189          * If the host has SSBD mitigation enabled, force it in the host's
 190          * virtual MSR value. If its not permanently enabled, evaluate
 191          * current's TIF_SSBD thread flag.
 192          */
 193         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 194                 hostval = SPEC_CTRL_SSBD;
 195         else
 196                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 197
 198         /* Sanitize the guest value */
 199         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 200
 201         if (hostval != guestval) {
 202                 unsigned long tif;
 203
 204                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 205                                  ssbd_spec_ctrl_to_tif(hostval);
 206
 207                 speculative_store_bypass_update(tif);
 208         }
 209 }
 210 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 211
 212 static void x86_amd_ssb_disable(void)
 213 {
 214         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 215
 216         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 217                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 218         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 219                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 220 }
 221
 222 #ifdef RETPOLINE
 223 static bool spectre_v2_bad_module;
 224
 225 bool retpoline_module_ok(bool has_retpoline)
 226 {
 227         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 228                 return true;
 229
 230         pr_err("System may be vulnerable to spectre v2\n");
 231         spectre_v2_bad_module = true;
 232         return false;
 233 }
 234
 235 static inline const char *spectre_v2_module_string(void)
 236 {
 237         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 238 }
 239 #else
 240 static inline const char *spectre_v2_module_string(void) { return ""; }
 241 #endif
 242
 243 static void __init spec2_print_if_insecure(const char *reason)
 244 {
 245         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 246                 pr_info("%s selected on command line.\n", reason);
 247 }
 248
 249 static void __init spec2_print_if_secure(const char *reason)
 250 {
 251         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 252                 pr_info("%s selected on command line.\n", reason);
 253 }
 254
 255 static inline bool retp_compiler(void)
 256 {
 257         return __is_defined(RETPOLINE);
 258 }
 259
 260 static inline bool match_option(const char *arg, int arglen, const char *opt)
 261 {
 262         int len = strlen(opt);
 263
 264         return len == arglen && !strncmp(arg, opt, len);
 265 }
 266
 267 static const struct {
 268         const char *option;
 269         enum spectre_v2_mitigation_cmd cmd;
 270         bool secure;
 271 } mitigation_options[] = {
 272         { "off",               SPECTRE_V2_CMD_NONE,              false },
 273         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 274         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 275         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 276         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 277         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 278 };
 279
 280 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 281 {
 282         char arg[20];
 283         int ret, i;
 284         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 285
 286         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 287                 return SPECTRE_V2_CMD_NONE;
 288         else {
 289                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 290                 if (ret < 0)
 291                         return SPECTRE_V2_CMD_AUTO;
 292
 293                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 294                         if (!match_option(arg, ret, mitigation_options[i].option))
 295                                 continue;
 296                         cmd = mitigation_options[i].cmd;
 297                         break;
 298                 }
 299
 300                 if (i >= ARRAY_SIZE(mitigation_options)) {
 301                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 302                         return SPECTRE_V2_CMD_AUTO;
 303                 }
 304         }
 305
 306         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 307              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 308              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 309             !IS_ENABLED(CONFIG_RETPOLINE)) {
 310                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 311                 return SPECTRE_V2_CMD_AUTO;
 312         }
 313
 314         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 315             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
 316             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 317                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 318                 return SPECTRE_V2_CMD_AUTO;
 319         }
 320
 321         if (mitigation_options[i].secure)
 322                 spec2_print_if_secure(mitigation_options[i].option);
 323         else
 324                 spec2_print_if_insecure(mitigation_options[i].option);
 325
 326         return cmd;
 327 }
 328
 329 static void __init spectre_v2_select_mitigation(void)
 330 {
 331         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 332         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 333
 334         /*
 335          * If the CPU is not affected and the command line mode is NONE or AUTO
 336          * then nothing to do.
 337          */
 338         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 339             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 340                 return;
 341
 342         switch (cmd) {
 343         case SPECTRE_V2_CMD_NONE:
 344                 return;
 345
 346         case SPECTRE_V2_CMD_FORCE:
 347         case SPECTRE_V2_CMD_AUTO:
 348                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
 349                         mode = SPECTRE_V2_IBRS_ENHANCED;
 350                         /* Force it so VMEXIT will restore correctly */
 351                         x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
 352                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 353                         goto specv2_set_mode;
 354                 }
 355                 if (IS_ENABLED(CONFIG_RETPOLINE))
 356                         goto retpoline_auto;
 357                 break;
 358         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 359                 if (IS_ENABLED(CONFIG_RETPOLINE))
 360                         goto retpoline_amd;
 361                 break;
 362         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 363                 if (IS_ENABLED(CONFIG_RETPOLINE))
 364                         goto retpoline_generic;
 365                 break;
 366         case SPECTRE_V2_CMD_RETPOLINE:
 367                 if (IS_ENABLED(CONFIG_RETPOLINE))
 368                         goto retpoline_auto;
 369                 break;
 370         }
 371         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 372         return;
 373
 374 retpoline_auto:
 375         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
 376             boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
 377         retpoline_amd:
 378                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 379                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 380                         goto retpoline_generic;
 381                 }
 382                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 383                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 384                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 385                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 386         } else {
 387         retpoline_generic:
 388                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 389                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 390                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 391         }
 392
 393 specv2_set_mode:
 394         spectre_v2_enabled = mode;
 395         pr_info("%s\n", spectre_v2_strings[mode]);
 396
 397         /*
 398          * If spectre v2 protection has been enabled, unconditionally fill
 399          * RSB during a context switch; this protects against two independent
 400          * issues:
 401          *
 402          *      - RSB underflow (and switch to BTB) on Skylake+
 403          *      - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
 404          */
 405         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 406         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
 407
 408         /* Initialize Indirect Branch Prediction Barrier if supported */
 409         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 410                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 411                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 412         }
 413
 414         /*
 415          * Retpoline means the kernel is safe because it has no indirect
 416          * branches. Enhanced IBRS protects firmware too, so, enable restricted
 417          * speculation around firmware calls only when Enhanced IBRS isn't
 418          * supported.
 419          *
 420          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
 421          * the user might select retpoline on the kernel command line and if
 422          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
 423          * enable IBRS around firmware calls.
 424          */
 425         if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
 426                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 427                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 428         }
 429 }
 430
 431 #undef pr_fmt
 432 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 433
 434 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 435
 436 /* The kernel command line selection */
 437 enum ssb_mitigation_cmd {
 438         SPEC_STORE_BYPASS_CMD_NONE,
 439         SPEC_STORE_BYPASS_CMD_AUTO,
 440         SPEC_STORE_BYPASS_CMD_ON,
 441         SPEC_STORE_BYPASS_CMD_PRCTL,
 442         SPEC_STORE_BYPASS_CMD_SECCOMP,
 443 };
 444
 445 static const char *ssb_strings[] = {
 446         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 447         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 448         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 449         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 450 };
 451
 452 static const struct {
 453         const char *option;
 454         enum ssb_mitigation_cmd cmd;
 455 } ssb_mitigation_options[] = {
 456         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 457         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 458         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 459         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 460         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 461 };
 462
 463 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 464 {
 465         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 466         char arg[20];
 467         int ret, i;
 468
 469         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 470                 return SPEC_STORE_BYPASS_CMD_NONE;
 471         } else {
 472                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 473                                           arg, sizeof(arg));
 474                 if (ret < 0)
 475                         return SPEC_STORE_BYPASS_CMD_AUTO;
 476
 477                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 478                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 479                                 continue;
 480
 481                         cmd = ssb_mitigation_options[i].cmd;
 482                         break;
 483                 }
 484
 485                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 486                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 487                         return SPEC_STORE_BYPASS_CMD_AUTO;
 488                 }
 489         }
 490
 491         return cmd;
 492 }
 493
 494 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 495 {
 496         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 497         enum ssb_mitigation_cmd cmd;
 498
 499         if (!boot_cpu_has(X86_FEATURE_SSBD))
 500                 return mode;
 501
 502         cmd = ssb_parse_cmdline();
 503         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 504             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 505              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 506                 return mode;
 507
 508         switch (cmd) {
 509         case SPEC_STORE_BYPASS_CMD_AUTO:
 510         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 511                 /*
 512                  * Choose prctl+seccomp as the default mode if seccomp is
 513                  * enabled.
 514                  */
 515                 if (IS_ENABLED(CONFIG_SECCOMP))
 516                         mode = SPEC_STORE_BYPASS_SECCOMP;
 517                 else
 518                         mode = SPEC_STORE_BYPASS_PRCTL;
 519                 break;
 520         case SPEC_STORE_BYPASS_CMD_ON:
 521                 mode = SPEC_STORE_BYPASS_DISABLE;
 522                 break;
 523         case SPEC_STORE_BYPASS_CMD_PRCTL:
 524                 mode = SPEC_STORE_BYPASS_PRCTL;
 525                 break;
 526         case SPEC_STORE_BYPASS_CMD_NONE:
 527                 break;
 528         }
 529
 530         /*
 531          * We have three CPU feature flags that are in play here:
 532          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 533          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 534          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 535          */
 536         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 537                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 538                 /*
 539                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
 540                  * use a completely different MSR and bit dependent on family.
 541                  */
 542                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
 543                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
 544                         x86_amd_ssb_disable();
 545                 } else {
 546                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 547                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 548                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 549                 }
 550         }
 551
 552         return mode;
 553 }
 554
 555 static void ssb_select_mitigation(void)
 556 {
 557         ssb_mode = __ssb_select_mitigation();
 558
 559         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 560                 pr_info("%s\n", ssb_strings[ssb_mode]);
 561 }
 562
 563 #undef pr_fmt
 564 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 565
 566 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 567 {
 568         bool update;
 569
 570         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 571             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 572                 return -ENXIO;
 573
 574         switch (ctrl) {
 575         case PR_SPEC_ENABLE:
 576                 /* If speculation is force disabled, enable is not allowed */
 577                 if (task_spec_ssb_force_disable(task))
 578                         return -EPERM;
 579                 task_clear_spec_ssb_disable(task);
 580                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 581                 break;
 582         case PR_SPEC_DISABLE:
 583                 task_set_spec_ssb_disable(task);
 584                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 585                 break;
 586         case PR_SPEC_FORCE_DISABLE:
 587                 task_set_spec_ssb_disable(task);
 588                 task_set_spec_ssb_force_disable(task);
 589                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 590                 break;
 591         default:
 592                 return -ERANGE;
 593         }
 594
 595         /*
 596          * If being set on non-current task, delay setting the CPU
 597          * mitigation until it is next scheduled.
 598          */
 599         if (task == current && update)
 600                 speculative_store_bypass_update_current();
 601
 602         return 0;
 603 }
 604
 605 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 606                              unsigned long ctrl)
 607 {
 608         switch (which) {
 609         case PR_SPEC_STORE_BYPASS:
 610                 return ssb_prctl_set(task, ctrl);
 611         default:
 612                 return -ENODEV;
 613         }
 614 }
 615
 616 #ifdef CONFIG_SECCOMP
 617 void arch_seccomp_spec_mitigate(struct task_struct *task)
 618 {
 619         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 620                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 621 }
 622 #endif
 623
 624 static int ssb_prctl_get(struct task_struct *task)
 625 {
 626         switch (ssb_mode) {
 627         case SPEC_STORE_BYPASS_DISABLE:
 628                 return PR_SPEC_DISABLE;
 629         case SPEC_STORE_BYPASS_SECCOMP:
 630         case SPEC_STORE_BYPASS_PRCTL:
 631                 if (task_spec_ssb_force_disable(task))
 632                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 633                 if (task_spec_ssb_disable(task))
 634                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 635                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 636         default:
 637                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 638                         return PR_SPEC_ENABLE;
 639                 return PR_SPEC_NOT_AFFECTED;
 640         }
 641 }
 642
 643 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 644 {
 645         switch (which) {
 646         case PR_SPEC_STORE_BYPASS:
 647                 return ssb_prctl_get(task);
 648         default:
 649                 return -ENODEV;
 650         }
 651 }
 652
 653 void x86_spec_ctrl_setup_ap(void)
 654 {
 655         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 656                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 657
 658         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 659                 x86_amd_ssb_disable();
 660 }
 661
 662 #undef pr_fmt
 663 #define pr_fmt(fmt)     "L1TF: " fmt
 664
 665 /* Default mitigation for L1TF-affected CPUs */
 666 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
 667 #if IS_ENABLED(CONFIG_KVM_INTEL)
 668 EXPORT_SYMBOL_GPL(l1tf_mitigation);
 669 #endif
 670 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
 671 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
 672
 673 /*
 674  * These CPUs all support 44bits physical address space internally in the
 675  * cache but CPUID can report a smaller number of physical address bits.
 676  *
 677  * The L1TF mitigation uses the top most address bit for the inversion of
 678  * non present PTEs. When the installed memory reaches into the top most
 679  * address bit due to memory holes, which has been observed on machines
 680  * which report 36bits physical address bits and have 32G RAM installed,
 681  * then the mitigation range check in l1tf_select_mitigation() triggers.
 682  * This is a false positive because the mitigation is still possible due to
 683  * the fact that the cache uses 44bit internally. Use the cache bits
 684  * instead of the reported physical bits and adjust them on the affected
 685  * machines to 44bit if the reported bits are less than 44.
 686  */
 687 static void override_cache_bits(struct cpuinfo_x86 *c)
 688 {
 689         if (c->x86 != 6)
 690                 return;
 691
 692         switch (c->x86_model) {
 693         case INTEL_FAM6_NEHALEM:
 694         case INTEL_FAM6_WESTMERE:
 695         case INTEL_FAM6_SANDYBRIDGE:
 696         case INTEL_FAM6_IVYBRIDGE:
 697         case INTEL_FAM6_HASWELL_CORE:
 698         case INTEL_FAM6_HASWELL_ULT:
 699         case INTEL_FAM6_HASWELL_GT3E:
 700         case INTEL_FAM6_BROADWELL_CORE:
 701         case INTEL_FAM6_BROADWELL_GT3E:
 702         case INTEL_FAM6_SKYLAKE_MOBILE:
 703         case INTEL_FAM6_SKYLAKE_DESKTOP:
 704         case INTEL_FAM6_KABYLAKE_MOBILE:
 705         case INTEL_FAM6_KABYLAKE_DESKTOP:
 706                 if (c->x86_cache_bits < 44)
 707                         c->x86_cache_bits = 44;
 708                 break;
 709         }
 710 }
 711
 712 static void __init l1tf_select_mitigation(void)
 713 {
 714         u64 half_pa;
 715
 716         if (!boot_cpu_has_bug(X86_BUG_L1TF))
 717                 return;
 718
 719         override_cache_bits(&boot_cpu_data);
 720
 721         switch (l1tf_mitigation) {
 722         case L1TF_MITIGATION_OFF:
 723         case L1TF_MITIGATION_FLUSH_NOWARN:
 724         case L1TF_MITIGATION_FLUSH:
 725                 break;
 726         case L1TF_MITIGATION_FLUSH_NOSMT:
 727         case L1TF_MITIGATION_FULL:
 728                 cpu_smt_disable(false);
 729                 break;
 730         case L1TF_MITIGATION_FULL_FORCE:
 731                 cpu_smt_disable(true);
 732                 break;
 733         }
 734
 735 #if CONFIG_PGTABLE_LEVELS == 2
 736         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
 737         return;
 738 #endif
 739
 740         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
 741         if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
 742                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
 743                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
 744                                 half_pa);
 745                 pr_info("However, doing so will make a part of your RAM unusable.\n");
 746                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
 747                 return;
 748         }
 749
 750         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
 751 }
 752
 753 static int __init l1tf_cmdline(char *str)
 754 {
 755         if (!boot_cpu_has_bug(X86_BUG_L1TF))
 756                 return 0;
 757
 758         if (!str)
 759                 return -EINVAL;
 760
 761         if (!strcmp(str, "off"))
 762                 l1tf_mitigation = L1TF_MITIGATION_OFF;
 763         else if (!strcmp(str, "flush,nowarn"))
 764                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
 765         else if (!strcmp(str, "flush"))
 766                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
 767         else if (!strcmp(str, "flush,nosmt"))
 768                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
 769         else if (!strcmp(str, "full"))
 770                 l1tf_mitigation = L1TF_MITIGATION_FULL;
 771         else if (!strcmp(str, "full,force"))
 772                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
 773
 774         return 0;
 775 }
 776 early_param("l1tf", l1tf_cmdline);
 777
 778 #undef pr_fmt
 779
 780 #ifdef CONFIG_SYSFS
 781
 782 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
 783
 784 #if IS_ENABLED(CONFIG_KVM_INTEL)
 785 static const char *l1tf_vmx_states[] = {
 786         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
 787         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
 788         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
 789         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
 790         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
 791         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
 792 };
 793
 794 static ssize_t l1tf_show_state(char *buf)
 795 {
 796         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
 797                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
 798
 799         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
 800             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
 801              cpu_smt_control == CPU_SMT_ENABLED))
 802                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
 803                                l1tf_vmx_states[l1tf_vmx_mitigation]);
 804
 805         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
 806                        l1tf_vmx_states[l1tf_vmx_mitigation],
 807                        cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled");
 808 }
 809 #else
 810 static ssize_t l1tf_show_state(char *buf)
 811 {
 812         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
 813 }
 814 #endif
 815
 816 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 817                                char *buf, unsigned int bug)
 818 {
 819         if (!boot_cpu_has_bug(bug))
 820                 return sprintf(buf, "Not affected\n");
 821
 822         switch (bug) {
 823         case X86_BUG_CPU_MELTDOWN:
 824                 if (boot_cpu_has(X86_FEATURE_PTI))
 825                         return sprintf(buf, "Mitigation: PTI\n");
 826
 827                 if (hypervisor_is_type(X86_HYPER_XEN_PV))
 828                         return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
 829
 830                 break;
 831
 832         case X86_BUG_SPECTRE_V1:
 833                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 834
 835         case X86_BUG_SPECTRE_V2:
 836                 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 837                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 838                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 839                                spectre_v2_module_string());
 840
 841         case X86_BUG_SPEC_STORE_BYPASS:
 842                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 843
 844         case X86_BUG_L1TF:
 845                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
 846                         return l1tf_show_state(buf);
 847                 break;
 848         default:
 849                 break;
 850         }
 851
 852         return sprintf(buf, "Vulnerable\n");
 853 }
 854
 855 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 856 {
 857         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 858 }
 859
 860 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 861 {
 862         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 863 }
 864
 865 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 866 {
 867         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 868 }
 869
 870 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 871 {
 872         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 873 }
 874
 875 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
 876 {
 877         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
 878 }
 879 #endif