2 * Support of MSI, HPET and DMAR interrupts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Convert to hierarchical irqdomain
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/interrupt.h>
15 #include <linux/pci.h>
16 #include <linux/dmar.h>
17 #include <linux/hpet.h>
18 #include <linux/msi.h>
19 #include <asm/irqdomain.h>
20 #include <asm/msidef.h>
22 #include <asm/hw_irq.h>
24 #include <asm/irq_remapping.h>
26 static struct irq_domain *msi_default_domain;
28 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
30 struct irq_cfg *cfg = irqd_cfg(data);
32 msg->address_hi = MSI_ADDR_BASE_HI;
35 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
39 ((apic->irq_dest_mode == 0) ?
40 MSI_ADDR_DEST_MODE_PHYSICAL :
41 MSI_ADDR_DEST_MODE_LOGICAL) |
42 ((apic->irq_delivery_mode != dest_LowestPrio) ?
43 MSI_ADDR_REDIRECTION_CPU :
44 MSI_ADDR_REDIRECTION_LOWPRI) |
45 MSI_ADDR_DEST_ID(cfg->dest_apicid);
48 MSI_DATA_TRIGGER_EDGE |
49 MSI_DATA_LEVEL_ASSERT |
50 ((apic->irq_delivery_mode != dest_LowestPrio) ?
51 MSI_DATA_DELIVERY_FIXED :
52 MSI_DATA_DELIVERY_LOWPRI) |
53 MSI_DATA_VECTOR(cfg->vector);
57 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
58 * which implement the MSI or MSI-X Capability Structure.
60 static struct irq_chip pci_msi_controller = {
62 .irq_unmask = pci_msi_unmask_irq,
63 .irq_mask = pci_msi_mask_irq,
64 .irq_ack = irq_chip_ack_parent,
65 .irq_retrigger = irq_chip_retrigger_hierarchy,
66 .irq_compose_msi_msg = irq_msi_compose_msg,
67 .flags = IRQCHIP_SKIP_SET_WAKE,
70 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
72 struct irq_domain *domain;
73 struct irq_alloc_info info;
75 init_irq_alloc_info(&info, NULL);
76 info.type = X86_IRQ_ALLOC_TYPE_MSI;
79 domain = irq_remapping_get_irq_domain(&info);
81 domain = msi_default_domain;
85 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
88 void native_teardown_msi_irq(unsigned int irq)
90 irq_domain_free_irqs(irq, 1);
93 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
94 msi_alloc_info_t *arg)
96 return arg->msi_hwirq;
99 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
100 msi_alloc_info_t *arg)
102 struct pci_dev *pdev = to_pci_dev(dev);
103 struct msi_desc *desc = first_pci_msi_entry(pdev);
105 init_irq_alloc_info(arg, NULL);
107 if (desc->msi_attrib.is_msix) {
108 arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
110 arg->type = X86_IRQ_ALLOC_TYPE_MSI;
111 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
116 EXPORT_SYMBOL_GPL(pci_msi_prepare);
118 void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
120 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
122 EXPORT_SYMBOL_GPL(pci_msi_set_desc);
124 static struct msi_domain_ops pci_msi_domain_ops = {
125 .get_hwirq = pci_msi_get_hwirq,
126 .msi_prepare = pci_msi_prepare,
127 .set_desc = pci_msi_set_desc,
130 static struct msi_domain_info pci_msi_domain_info = {
131 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
133 .ops = &pci_msi_domain_ops,
134 .chip = &pci_msi_controller,
135 .handler = handle_edge_irq,
136 .handler_name = "edge",
139 void __init arch_init_msi_domain(struct irq_domain *parent)
141 struct fwnode_handle *fn;
146 fn = irq_domain_alloc_named_fwnode("PCI-MSI");
149 pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
151 irq_domain_free_fwnode(fn);
153 if (!msi_default_domain)
154 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
157 #ifdef CONFIG_IRQ_REMAP
158 static struct irq_chip pci_msi_ir_controller = {
159 .name = "IR-PCI-MSI",
160 .irq_unmask = pci_msi_unmask_irq,
161 .irq_mask = pci_msi_mask_irq,
162 .irq_ack = irq_chip_ack_parent,
163 .irq_retrigger = irq_chip_retrigger_hierarchy,
164 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
165 .flags = IRQCHIP_SKIP_SET_WAKE,
168 static struct msi_domain_info pci_msi_ir_domain_info = {
169 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
170 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
171 .ops = &pci_msi_domain_ops,
172 .chip = &pci_msi_ir_controller,
173 .handler = handle_edge_irq,
174 .handler_name = "edge",
177 struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
178 const char *name, int id)
180 struct fwnode_handle *fn;
181 struct irq_domain *d;
183 fn = irq_domain_alloc_named_id_fwnode(name, id);
186 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
187 irq_domain_free_fwnode(fn);
192 #ifdef CONFIG_DMAR_TABLE
193 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
195 dmar_msi_write(data->irq, msg);
198 static struct irq_chip dmar_msi_controller = {
200 .irq_unmask = dmar_msi_unmask,
201 .irq_mask = dmar_msi_mask,
202 .irq_ack = irq_chip_ack_parent,
203 .irq_set_affinity = msi_domain_set_affinity,
204 .irq_retrigger = irq_chip_retrigger_hierarchy,
205 .irq_compose_msi_msg = irq_msi_compose_msg,
206 .irq_write_msi_msg = dmar_msi_write_msg,
207 .flags = IRQCHIP_SKIP_SET_WAKE,
210 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
211 msi_alloc_info_t *arg)
216 static int dmar_msi_init(struct irq_domain *domain,
217 struct msi_domain_info *info, unsigned int virq,
218 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
220 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
221 handle_edge_irq, arg->dmar_data, "edge");
226 static struct msi_domain_ops dmar_msi_domain_ops = {
227 .get_hwirq = dmar_msi_get_hwirq,
228 .msi_init = dmar_msi_init,
231 static struct msi_domain_info dmar_msi_domain_info = {
232 .ops = &dmar_msi_domain_ops,
233 .chip = &dmar_msi_controller,
236 static struct irq_domain *dmar_get_irq_domain(void)
238 static struct irq_domain *dmar_domain;
239 static DEFINE_MUTEX(dmar_lock);
240 struct fwnode_handle *fn;
242 mutex_lock(&dmar_lock);
246 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
248 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
250 irq_domain_free_fwnode(fn);
253 mutex_unlock(&dmar_lock);
257 int dmar_alloc_hwirq(int id, int node, void *arg)
259 struct irq_domain *domain = dmar_get_irq_domain();
260 struct irq_alloc_info info;
265 init_irq_alloc_info(&info, NULL);
266 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
268 info.dmar_data = arg;
270 return irq_domain_alloc_irqs(domain, 1, node, &info);
273 void dmar_free_hwirq(int irq)
275 irq_domain_free_irqs(irq, 1);
280 * MSI message composition
282 #ifdef CONFIG_HPET_TIMER
283 static inline int hpet_dev_id(struct irq_domain *domain)
285 struct msi_domain_info *info = msi_get_domain_info(domain);
287 return (int)(long)info->data;
290 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
292 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
295 static struct irq_chip hpet_msi_controller __ro_after_init = {
297 .irq_unmask = hpet_msi_unmask,
298 .irq_mask = hpet_msi_mask,
299 .irq_ack = irq_chip_ack_parent,
300 .irq_set_affinity = msi_domain_set_affinity,
301 .irq_retrigger = irq_chip_retrigger_hierarchy,
302 .irq_compose_msi_msg = irq_msi_compose_msg,
303 .irq_write_msi_msg = hpet_msi_write_msg,
304 .flags = IRQCHIP_SKIP_SET_WAKE,
307 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
308 msi_alloc_info_t *arg)
310 return arg->hpet_index;
313 static int hpet_msi_init(struct irq_domain *domain,
314 struct msi_domain_info *info, unsigned int virq,
315 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
317 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
318 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
319 handle_edge_irq, arg->hpet_data, "edge");
324 static void hpet_msi_free(struct irq_domain *domain,
325 struct msi_domain_info *info, unsigned int virq)
327 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
330 static struct msi_domain_ops hpet_msi_domain_ops = {
331 .get_hwirq = hpet_msi_get_hwirq,
332 .msi_init = hpet_msi_init,
333 .msi_free = hpet_msi_free,
336 static struct msi_domain_info hpet_msi_domain_info = {
337 .ops = &hpet_msi_domain_ops,
338 .chip = &hpet_msi_controller,
341 struct irq_domain *hpet_create_irq_domain(int hpet_id)
343 struct msi_domain_info *domain_info;
344 struct irq_domain *parent, *d;
345 struct irq_alloc_info info;
346 struct fwnode_handle *fn;
348 if (x86_vector_domain == NULL)
351 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
355 *domain_info = hpet_msi_domain_info;
356 domain_info->data = (void *)(long)hpet_id;
358 init_irq_alloc_info(&info, NULL);
359 info.type = X86_IRQ_ALLOC_TYPE_HPET;
360 info.hpet_id = hpet_id;
361 parent = irq_remapping_get_ir_irq_domain(&info);
363 parent = x86_vector_domain;
365 hpet_msi_controller.name = "IR-HPET-MSI";
367 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
374 d = msi_create_irq_domain(fn, domain_info, parent);
375 irq_domain_free_fwnode(fn);
379 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
382 struct irq_alloc_info info;
384 init_irq_alloc_info(&info, NULL);
385 info.type = X86_IRQ_ALLOC_TYPE_HPET;
386 info.hpet_data = dev;
387 info.hpet_id = hpet_dev_id(domain);
388 info.hpet_index = dev_num;
390 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);