arch/x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13
  14 /*
  15  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  16  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  17  */
  18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  19 #define HYPERV_CPUID_INTERFACE                  0x40000001
  20 #define HYPERV_CPUID_VERSION                    0x40000002
  21 #define HYPERV_CPUID_FEATURES                   0x40000003
  22 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  23 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  24 #define HYPERV_CPUID_NESTED_FEATURES            0x4000000A
  25
  26 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  27 #define HYPERV_CPUID_MIN                        0x40000005
  28 #define HYPERV_CPUID_MAX                        0x4000ffff
  29
  30 /*
  31  * Feature identification. EAX indicates which features are available
  32  * to the partition based upon the current partition privileges.
  33  */
  34
  35 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
  36 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         (1 << 0)
  37 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
  38 #define HV_MSR_TIME_REF_COUNT_AVAILABLE         (1 << 1)
  39 /* Partition reference TSC MSR is available */
  40 #define HV_MSR_REFERENCE_TSC_AVAILABLE          (1 << 9)
  41 /* Partition Guest IDLE MSR is available */
  42 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE         (1 << 10)
  43
  44 /* A partition's reference time stamp counter (TSC) page */
  45 #define HV_X64_MSR_REFERENCE_TSC                0x40000021
  46
  47 /*
  48  * There is a single feature flag that signifies if the partition has access
  49  * to MSRs with local APIC and TSC frequencies.
  50  */
  51 #define HV_X64_ACCESS_FREQUENCY_MSRS            (1 << 11)
  52
  53 /* AccessReenlightenmentControls privilege */
  54 #define HV_X64_ACCESS_REENLIGHTENMENT           BIT(13)
  55
  56 /*
  57  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
  58  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
  59  */
  60 #define HV_X64_MSR_SYNIC_AVAILABLE              (1 << 2)
  61 /*
  62  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
  63  * HV_X64_MSR_STIMER3_COUNT) available
  64  */
  65 #define HV_MSR_SYNTIMER_AVAILABLE               (1 << 3)
  66 /*
  67  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
  68  * are available
  69  */
  70 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        (1 << 4)
  71 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
  72 #define HV_X64_MSR_HYPERCALL_AVAILABLE          (1 << 5)
  73 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
  74 #define HV_X64_MSR_VP_INDEX_AVAILABLE           (1 << 6)
  75 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
  76 #define HV_X64_MSR_RESET_AVAILABLE              (1 << 7)
  77  /*
  78   * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  79   * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  80   * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  81   */
  82 #define HV_X64_MSR_STAT_PAGES_AVAILABLE         (1 << 8)
  83
  84 /* Frequency MSRs available */
  85 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE     (1 << 8)
  86
  87 /* Crash MSR available */
  88 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
  89
  90 /* stimer Direct Mode is available */
  91 #define HV_STIMER_DIRECT_MODE_AVAILABLE         (1 << 19)
  92
  93 /*
  94  * Feature identification: EBX indicates which flags were specified at
  95  * partition creation. The format is the same as the partition creation
  96  * flag structure defined in section Partition Creation Flags.
  97  */
  98 #define HV_X64_CREATE_PARTITIONS                (1 << 0)
  99 #define HV_X64_ACCESS_PARTITION_ID              (1 << 1)
 100 #define HV_X64_ACCESS_MEMORY_POOL               (1 << 2)
 101 #define HV_X64_ADJUST_MESSAGE_BUFFERS           (1 << 3)
 102 #define HV_X64_POST_MESSAGES                    (1 << 4)
 103 #define HV_X64_SIGNAL_EVENTS                    (1 << 5)
 104 #define HV_X64_CREATE_PORT                      (1 << 6)
 105 #define HV_X64_CONNECT_PORT                     (1 << 7)
 106 #define HV_X64_ACCESS_STATS                     (1 << 8)
 107 #define HV_X64_DEBUGGING                        (1 << 11)
 108 #define HV_X64_CPU_POWER_MANAGEMENT             (1 << 12)
 109 #define HV_X64_CONFIGURE_PROFILER               (1 << 13)
 110
 111 /*
 112  * Feature identification. EDX indicates which miscellaneous features
 113  * are available to the partition.
 114  */
 115 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
 116 #define HV_X64_MWAIT_AVAILABLE                          (1 << 0)
 117 /* Guest debugging support is available */
 118 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                (1 << 1)
 119 /* Performance Monitor support is available*/
 120 #define HV_X64_PERF_MONITOR_AVAILABLE                   (1 << 2)
 121 /* Support for physical CPU dynamic partitioning events is available*/
 122 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       (1 << 3)
 123 /*
 124  * Support for passing hypercall input parameter block via XMM
 125  * registers is available
 126  */
 127 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           (1 << 4)
 128 /* Support for a virtual guest idle state is available */
 129 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               (1 << 5)
 130 /* Guest crash data handler available */
 131 #define HV_X64_GUEST_CRASH_MSR_AVAILABLE                (1 << 10)
 132
 133 /*
 134  * Implementation recommendations. Indicates which behaviors the hypervisor
 135  * recommends the OS implement for optimal performance.
 136  */
 137  /*
 138   * Recommend using hypercall for address space switches rather
 139   * than MOV to CR3 instruction
 140   */
 141 #define HV_X64_AS_SWITCH_RECOMMENDED            (1 << 0)
 142 /* Recommend using hypercall for local TLB flushes rather
 143  * than INVLPG or MOV to CR3 instructions */
 144 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED      (1 << 1)
 145 /*
 146  * Recommend using hypercall for remote TLB flushes rather
 147  * than inter-processor interrupts
 148  */
 149 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED     (1 << 2)
 150 /*
 151  * Recommend using MSRs for accessing APIC registers
 152  * EOI, ICR and TPR rather than their memory-mapped counterparts
 153  */
 154 #define HV_X64_APIC_ACCESS_RECOMMENDED          (1 << 3)
 155 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
 156 #define HV_X64_SYSTEM_RESET_RECOMMENDED         (1 << 4)
 157 /*
 158  * Recommend using relaxed timing for this partition. If used,
 159  * the VM should disable any watchdog timeouts that rely on the
 160  * timely delivery of external interrupts
 161  */
 162 #define HV_X64_RELAXED_TIMING_RECOMMENDED       (1 << 5)
 163
 164 /*
 165  * Recommend not using Auto End-Of-Interrupt feature
 166  */
 167 #define HV_DEPRECATING_AEOI_RECOMMENDED         (1 << 9)
 168
 169 /*
 170  * Recommend using cluster IPI hypercalls.
 171  */
 172 #define HV_X64_CLUSTER_IPI_RECOMMENDED         (1 << 10)
 173
 174 /* Recommend using the newer ExProcessorMasks interface */
 175 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED   (1 << 11)
 176
 177 /* Recommend using enlightened VMCS */
 178 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED    (1 << 14)
 179
 180 /*
 181  * Crash notification flags.
 182  */
 183 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG   BIT_ULL(62)
 184 #define HV_CRASH_CTL_CRASH_NOTIFY       BIT_ULL(63)
 185
 186 /* MSR used to identify the guest OS. */
 187 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 188
 189 /* MSR used to setup pages used to communicate with the hypervisor. */
 190 #define HV_X64_MSR_HYPERCALL                    0x40000001
 191
 192 /* MSR used to provide vcpu index */
 193 #define HV_X64_MSR_VP_INDEX                     0x40000002
 194
 195 /* MSR used to reset the guest OS. */
 196 #define HV_X64_MSR_RESET                        0x40000003
 197
 198 /* MSR used to provide vcpu runtime in 100ns units */
 199 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 200
 201 /* MSR used to read the per-partition time reference counter */
 202 #define HV_X64_MSR_TIME_REF_COUNT               0x40000020
 203
 204 /* MSR used to retrieve the TSC frequency */
 205 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 206
 207 /* MSR used to retrieve the local APIC timer frequency */
 208 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 209
 210 /* Define the virtual APIC registers */
 211 #define HV_X64_MSR_EOI                          0x40000070
 212 #define HV_X64_MSR_ICR                          0x40000071
 213 #define HV_X64_MSR_TPR                          0x40000072
 214 #define HV_X64_MSR_VP_ASSIST_PAGE               0x40000073
 215
 216 /* Define synthetic interrupt controller model specific registers. */
 217 #define HV_X64_MSR_SCONTROL                     0x40000080
 218 #define HV_X64_MSR_SVERSION                     0x40000081
 219 #define HV_X64_MSR_SIEFP                        0x40000082
 220 #define HV_X64_MSR_SIMP                         0x40000083
 221 #define HV_X64_MSR_EOM                          0x40000084
 222 #define HV_X64_MSR_SINT0                        0x40000090
 223 #define HV_X64_MSR_SINT1                        0x40000091
 224 #define HV_X64_MSR_SINT2                        0x40000092
 225 #define HV_X64_MSR_SINT3                        0x40000093
 226 #define HV_X64_MSR_SINT4                        0x40000094
 227 #define HV_X64_MSR_SINT5                        0x40000095
 228 #define HV_X64_MSR_SINT6                        0x40000096
 229 #define HV_X64_MSR_SINT7                        0x40000097
 230 #define HV_X64_MSR_SINT8                        0x40000098
 231 #define HV_X64_MSR_SINT9                        0x40000099
 232 #define HV_X64_MSR_SINT10                       0x4000009A
 233 #define HV_X64_MSR_SINT11                       0x4000009B
 234 #define HV_X64_MSR_SINT12                       0x4000009C
 235 #define HV_X64_MSR_SINT13                       0x4000009D
 236 #define HV_X64_MSR_SINT14                       0x4000009E
 237 #define HV_X64_MSR_SINT15                       0x4000009F
 238
 239 /*
 240  * Synthetic Timer MSRs. Four timers per vcpu.
 241  */
 242 #define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
 243 #define HV_X64_MSR_STIMER0_COUNT                0x400000B1
 244 #define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
 245 #define HV_X64_MSR_STIMER1_COUNT                0x400000B3
 246 #define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
 247 #define HV_X64_MSR_STIMER2_COUNT                0x400000B5
 248 #define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
 249 #define HV_X64_MSR_STIMER3_COUNT                0x400000B7
 250
 251 /* Hyper-V guest idle MSR */
 252 #define HV_X64_MSR_GUEST_IDLE                   0x400000F0
 253
 254 /* Hyper-V guest crash notification MSR's */
 255 #define HV_X64_MSR_CRASH_P0                     0x40000100
 256 #define HV_X64_MSR_CRASH_P1                     0x40000101
 257 #define HV_X64_MSR_CRASH_P2                     0x40000102
 258 #define HV_X64_MSR_CRASH_P3                     0x40000103
 259 #define HV_X64_MSR_CRASH_P4                     0x40000104
 260 #define HV_X64_MSR_CRASH_CTL                    0x40000105
 261 #define HV_X64_MSR_CRASH_CTL_NOTIFY             (1ULL << 63)
 262 #define HV_X64_MSR_CRASH_PARAMS         \
 263                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 264
 265 /*
 266  * Declare the MSR used to setup pages used to communicate with the hypervisor.
 267  */
 268 union hv_x64_msr_hypercall_contents {
 269         u64 as_uint64;
 270         struct {
 271                 u64 enable:1;
 272                 u64 reserved:11;
 273                 u64 guest_physical_address:52;
 274         };
 275 };
 276
 277 /*
 278  * TSC page layout.
 279  */
 280 struct ms_hyperv_tsc_page {
 281         volatile u32 tsc_sequence;
 282         u32 reserved1;
 283         volatile u64 tsc_scale;
 284         volatile s64 tsc_offset;
 285         u64 reserved2[509];
 286 };
 287
 288 /*
 289  * The guest OS needs to register the guest ID with the hypervisor.
 290  * The guest ID is a 64 bit entity and the structure of this ID is
 291  * specified in the Hyper-V specification:
 292  *
 293  * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx
 294  *
 295  * While the current guideline does not specify how Linux guest ID(s)
 296  * need to be generated, our plan is to publish the guidelines for
 297  * Linux and other guest operating systems that currently are hosted
 298  * on Hyper-V. The implementation here conforms to this yet
 299  * unpublished guidelines.
 300  *
 301  *
 302  * Bit(s)
 303  * 63 - Indicates if the OS is Open Source or not; 1 is Open Source
 304  * 62:56 - Os Type; Linux is 0x100
 305  * 55:48 - Distro specific identification
 306  * 47:16 - Linux kernel version number
 307  * 15:0  - Distro specific identification
 308  *
 309  *
 310  */
 311
 312 #define HV_LINUX_VENDOR_ID              0x8100
 313
 314 /* TSC emulation after migration */
 315 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 316
 317 /* Nested features (CPUID 0x4000000A) EAX */
 318 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH       BIT(18)
 319 #define HV_X64_NESTED_MSR_BITMAP                BIT(19)
 320
 321 struct hv_reenlightenment_control {
 322         __u64 vector:8;
 323         __u64 reserved1:8;
 324         __u64 enabled:1;
 325         __u64 reserved2:15;
 326         __u64 target_vp:32;
 327 };
 328
 329 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 330 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 331
 332 struct hv_tsc_emulation_control {
 333         __u64 enabled:1;
 334         __u64 reserved:63;
 335 };
 336
 337 struct hv_tsc_emulation_status {
 338         __u64 inprogress:1;
 339         __u64 reserved:63;
 340 };
 341
 342 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 343 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 344 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 345                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 346
 347 #define HV_IPI_LOW_VECTOR       0x10
 348 #define HV_IPI_HIGH_VECTOR      0xff
 349
 350 /* Declare the various hypercall operations. */
 351 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE      0x0002
 352 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST       0x0003
 353 #define HVCALL_NOTIFY_LONG_SPIN_WAIT            0x0008
 354 #define HVCALL_SEND_IPI                         0x000b
 355 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
 356 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
 357 #define HVCALL_SEND_IPI_EX                      0x0015
 358 #define HVCALL_POST_MESSAGE                     0x005c
 359 #define HVCALL_SIGNAL_EVENT                     0x005d
 360 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
 361
 362 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE        0x00000001
 363 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
 364 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK  \
 365                 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 366
 367 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */
 368 #define HV_X64_ENLIGHTENED_VMCS_VERSION         0xff
 369
 370 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 371 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 372
 373 #define HV_PROCESSOR_POWER_STATE_C0             0
 374 #define HV_PROCESSOR_POWER_STATE_C1             1
 375 #define HV_PROCESSOR_POWER_STATE_C2             2
 376 #define HV_PROCESSOR_POWER_STATE_C3             3
 377
 378 #define HV_FLUSH_ALL_PROCESSORS                 BIT(0)
 379 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES     BIT(1)
 380 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY       BIT(2)
 381 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT      BIT(3)
 382
 383 enum HV_GENERIC_SET_FORMAT {
 384         HV_GENERIC_SET_SPARSE_4K,
 385         HV_GENERIC_SET_ALL,
 386 };
 387
 388 #define HV_HYPERCALL_RESULT_MASK        GENMASK_ULL(15, 0)
 389 #define HV_HYPERCALL_FAST_BIT           BIT(16)
 390 #define HV_HYPERCALL_VARHEAD_OFFSET     17
 391 #define HV_HYPERCALL_REP_COMP_OFFSET    32
 392 #define HV_HYPERCALL_REP_COMP_MASK      GENMASK_ULL(43, 32)
 393 #define HV_HYPERCALL_REP_START_OFFSET   48
 394 #define HV_HYPERCALL_REP_START_MASK     GENMASK_ULL(59, 48)
 395
 396 /* hypercall status code */
 397 #define HV_STATUS_SUCCESS                       0
 398 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
 399 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
 400 #define HV_STATUS_INVALID_ALIGNMENT             4
 401 #define HV_STATUS_INVALID_PARAMETER             5
 402 #define HV_STATUS_INSUFFICIENT_MEMORY           11
 403 #define HV_STATUS_INVALID_PORT_ID               17
 404 #define HV_STATUS_INVALID_CONNECTION_ID         18
 405 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 406
 407 typedef struct _HV_REFERENCE_TSC_PAGE {
 408         __u32 tsc_sequence;
 409         __u32 res1;
 410         __u64 tsc_scale;
 411         __s64 tsc_offset;
 412 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
 413
 414 /* Define the number of synthetic interrupt sources. */
 415 #define HV_SYNIC_SINT_COUNT             (16)
 416 /* Define the expected SynIC version. */
 417 #define HV_SYNIC_VERSION_1              (0x1)
 418 /* Valid SynIC vectors are 16-255. */
 419 #define HV_SYNIC_FIRST_VALID_VECTOR     (16)
 420
 421 #define HV_SYNIC_CONTROL_ENABLE         (1ULL << 0)
 422 #define HV_SYNIC_SIMP_ENABLE            (1ULL << 0)
 423 #define HV_SYNIC_SIEFP_ENABLE           (1ULL << 0)
 424 #define HV_SYNIC_SINT_MASKED            (1ULL << 16)
 425 #define HV_SYNIC_SINT_AUTO_EOI          (1ULL << 17)
 426 #define HV_SYNIC_SINT_VECTOR_MASK       (0xFF)
 427
 428 #define HV_SYNIC_STIMER_COUNT           (4)
 429
 430 /* Define synthetic interrupt controller message constants. */
 431 #define HV_MESSAGE_SIZE                 (256)
 432 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT   (240)
 433 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT  (30)
 434
 435 /* Define hypervisor message types. */
 436 enum hv_message_type {
 437         HVMSG_NONE                      = 0x00000000,
 438
 439         /* Memory access messages. */
 440         HVMSG_UNMAPPED_GPA              = 0x80000000,
 441         HVMSG_GPA_INTERCEPT             = 0x80000001,
 442
 443         /* Timer notification messages. */
 444         HVMSG_TIMER_EXPIRED                     = 0x80000010,
 445
 446         /* Error messages. */
 447         HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
 448         HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
 449         HVMSG_UNSUPPORTED_FEATURE               = 0x80000022,
 450
 451         /* Trace buffer complete messages. */
 452         HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
 453
 454         /* Platform-specific processor intercept messages. */
 455         HVMSG_X64_IOPORT_INTERCEPT              = 0x80010000,
 456         HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
 457         HVMSG_X64_CPUID_INTERCEPT               = 0x80010002,
 458         HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
 459         HVMSG_X64_APIC_EOI                      = 0x80010004,
 460         HVMSG_X64_LEGACY_FP_ERROR               = 0x80010005
 461 };
 462
 463 /* Define synthetic interrupt controller message flags. */
 464 union hv_message_flags {
 465         __u8 asu8;
 466         struct {
 467                 __u8 msg_pending:1;
 468                 __u8 reserved:7;
 469         };
 470 };
 471
 472 /* Define port identifier type. */
 473 union hv_port_id {
 474         __u32 asu32;
 475         struct {
 476                 __u32 id:24;
 477                 __u32 reserved:8;
 478         } u;
 479 };
 480
 481 /* Define synthetic interrupt controller message header. */
 482 struct hv_message_header {
 483         __u32 message_type;
 484         __u8 payload_size;
 485         union hv_message_flags message_flags;
 486         __u8 reserved[2];
 487         union {
 488                 __u64 sender;
 489                 union hv_port_id port;
 490         };
 491 };
 492
 493 /* Define synthetic interrupt controller message format. */
 494 struct hv_message {
 495         struct hv_message_header header;
 496         union {
 497                 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
 498         } u;
 499 };
 500
 501 /* Define the synthetic interrupt message page layout. */
 502 struct hv_message_page {
 503         struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
 504 };
 505
 506 /* Define timer message payload structure. */
 507 struct hv_timer_message_payload {
 508         __u32 timer_index;
 509         __u32 reserved;
 510         __u64 expiration_time;  /* When the timer expired */
 511         __u64 delivery_time;    /* When the message was delivered */
 512 };
 513
 514 /* Define virtual processor assist page structure. */
 515 struct hv_vp_assist_page {
 516         __u32 apic_assist;
 517         __u32 reserved;
 518         __u64 vtl_control[2];
 519         __u64 nested_enlightenments_control[2];
 520         __u32 enlighten_vmentry;
 521         __u64 current_nested_vmcs;
 522 };
 523
 524 struct hv_enlightened_vmcs {
 525         u32 revision_id;
 526         u32 abort;
 527
 528         u16 host_es_selector;
 529         u16 host_cs_selector;
 530         u16 host_ss_selector;
 531         u16 host_ds_selector;
 532         u16 host_fs_selector;
 533         u16 host_gs_selector;
 534         u16 host_tr_selector;
 535
 536         u64 host_ia32_pat;
 537         u64 host_ia32_efer;
 538
 539         u64 host_cr0;
 540         u64 host_cr3;
 541         u64 host_cr4;
 542
 543         u64 host_ia32_sysenter_esp;
 544         u64 host_ia32_sysenter_eip;
 545         u64 host_rip;
 546         u32 host_ia32_sysenter_cs;
 547
 548         u32 pin_based_vm_exec_control;
 549         u32 vm_exit_controls;
 550         u32 secondary_vm_exec_control;
 551
 552         u64 io_bitmap_a;
 553         u64 io_bitmap_b;
 554         u64 msr_bitmap;
 555
 556         u16 guest_es_selector;
 557         u16 guest_cs_selector;
 558         u16 guest_ss_selector;
 559         u16 guest_ds_selector;
 560         u16 guest_fs_selector;
 561         u16 guest_gs_selector;
 562         u16 guest_ldtr_selector;
 563         u16 guest_tr_selector;
 564
 565         u32 guest_es_limit;
 566         u32 guest_cs_limit;
 567         u32 guest_ss_limit;
 568         u32 guest_ds_limit;
 569         u32 guest_fs_limit;
 570         u32 guest_gs_limit;
 571         u32 guest_ldtr_limit;
 572         u32 guest_tr_limit;
 573         u32 guest_gdtr_limit;
 574         u32 guest_idtr_limit;
 575
 576         u32 guest_es_ar_bytes;
 577         u32 guest_cs_ar_bytes;
 578         u32 guest_ss_ar_bytes;
 579         u32 guest_ds_ar_bytes;
 580         u32 guest_fs_ar_bytes;
 581         u32 guest_gs_ar_bytes;
 582         u32 guest_ldtr_ar_bytes;
 583         u32 guest_tr_ar_bytes;
 584
 585         u64 guest_es_base;
 586         u64 guest_cs_base;
 587         u64 guest_ss_base;
 588         u64 guest_ds_base;
 589         u64 guest_fs_base;
 590         u64 guest_gs_base;
 591         u64 guest_ldtr_base;
 592         u64 guest_tr_base;
 593         u64 guest_gdtr_base;
 594         u64 guest_idtr_base;
 595
 596         u64 padding64_1[3];
 597
 598         u64 vm_exit_msr_store_addr;
 599         u64 vm_exit_msr_load_addr;
 600         u64 vm_entry_msr_load_addr;
 601
 602         u64 cr3_target_value0;
 603         u64 cr3_target_value1;
 604         u64 cr3_target_value2;
 605         u64 cr3_target_value3;
 606
 607         u32 page_fault_error_code_mask;
 608         u32 page_fault_error_code_match;
 609
 610         u32 cr3_target_count;
 611         u32 vm_exit_msr_store_count;
 612         u32 vm_exit_msr_load_count;
 613         u32 vm_entry_msr_load_count;
 614
 615         u64 tsc_offset;
 616         u64 virtual_apic_page_addr;
 617         u64 vmcs_link_pointer;
 618
 619         u64 guest_ia32_debugctl;
 620         u64 guest_ia32_pat;
 621         u64 guest_ia32_efer;
 622
 623         u64 guest_pdptr0;
 624         u64 guest_pdptr1;
 625         u64 guest_pdptr2;
 626         u64 guest_pdptr3;
 627
 628         u64 guest_pending_dbg_exceptions;
 629         u64 guest_sysenter_esp;
 630         u64 guest_sysenter_eip;
 631
 632         u32 guest_activity_state;
 633         u32 guest_sysenter_cs;
 634
 635         u64 cr0_guest_host_mask;
 636         u64 cr4_guest_host_mask;
 637         u64 cr0_read_shadow;
 638         u64 cr4_read_shadow;
 639         u64 guest_cr0;
 640         u64 guest_cr3;
 641         u64 guest_cr4;
 642         u64 guest_dr7;
 643
 644         u64 host_fs_base;
 645         u64 host_gs_base;
 646         u64 host_tr_base;
 647         u64 host_gdtr_base;
 648         u64 host_idtr_base;
 649         u64 host_rsp;
 650
 651         u64 ept_pointer;
 652
 653         u16 virtual_processor_id;
 654         u16 padding16[3];
 655
 656         u64 padding64_2[5];
 657         u64 guest_physical_address;
 658
 659         u32 vm_instruction_error;
 660         u32 vm_exit_reason;
 661         u32 vm_exit_intr_info;
 662         u32 vm_exit_intr_error_code;
 663         u32 idt_vectoring_info_field;
 664         u32 idt_vectoring_error_code;
 665         u32 vm_exit_instruction_len;
 666         u32 vmx_instruction_info;
 667
 668         u64 exit_qualification;
 669         u64 exit_io_instruction_ecx;
 670         u64 exit_io_instruction_esi;
 671         u64 exit_io_instruction_edi;
 672         u64 exit_io_instruction_eip;
 673
 674         u64 guest_linear_address;
 675         u64 guest_rsp;
 676         u64 guest_rflags;
 677
 678         u32 guest_interruptibility_info;
 679         u32 cpu_based_vm_exec_control;
 680         u32 exception_bitmap;
 681         u32 vm_entry_controls;
 682         u32 vm_entry_intr_info_field;
 683         u32 vm_entry_exception_error_code;
 684         u32 vm_entry_instruction_len;
 685         u32 tpr_threshold;
 686
 687         u64 guest_rip;
 688
 689         u32 hv_clean_fields;
 690         u32 hv_padding_32;
 691         u32 hv_synthetic_controls;
 692         struct {
 693                 u32 nested_flush_hypercall:1;
 694                 u32 msr_bitmap:1;
 695                 u32 reserved:30;
 696         } hv_enlightenments_control;
 697         u32 hv_vp_id;
 698
 699         u64 hv_vm_id;
 700         u64 partition_assist_page;
 701         u64 padding64_4[4];
 702         u64 guest_bndcfgs;
 703         u64 padding64_5[7];
 704         u64 xss_exit_bitmap;
 705         u64 padding64_6[7];
 706 };
 707
 708 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE                     0
 709 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP                BIT(0)
 710 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP               BIT(1)
 711 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2             BIT(2)
 712 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1             BIT(3)
 713 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC             BIT(4)
 714 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT            BIT(5)
 715 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY            BIT(6)
 716 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN            BIT(7)
 717 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR                     BIT(8)
 718 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT             BIT(9)
 719 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC              BIT(10)
 720 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1               BIT(11)
 721 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2               BIT(12)
 722 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER             BIT(13)
 723 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1                BIT(14)
 724 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL    BIT(15)
 725
 726 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL                      0xFFFF
 727
 728 #define HV_STIMER_ENABLE                (1ULL << 0)
 729 #define HV_STIMER_PERIODIC              (1ULL << 1)
 730 #define HV_STIMER_LAZY                  (1ULL << 2)
 731 #define HV_STIMER_AUTOENABLE            (1ULL << 3)
 732 #define HV_STIMER_SINT(config)          (__u8)(((config) >> 16) & 0x0F)
 733
 734 struct hv_vpset {
 735         u64 format;
 736         u64 valid_bank_mask;
 737         u64 bank_contents[];
 738 };
 739
 740 /* HvCallSendSyntheticClusterIpi hypercall */
 741 struct hv_send_ipi {
 742         u32 vector;
 743         u32 reserved;
 744         u64 cpu_mask;
 745 };
 746
 747 /* HvCallSendSyntheticClusterIpiEx hypercall */
 748 struct hv_send_ipi_ex {
 749         u32 vector;
 750         u32 reserved;
 751         struct hv_vpset vp_set;
 752 };
 753
 754 /* HvFlushGuestPhysicalAddressSpace hypercalls */
 755 struct hv_guest_mapping_flush {
 756         u64 address_space;
 757         u64 flags;
 758 };
 759
 760 /* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */
 761 struct hv_tlb_flush {
 762         u64 address_space;
 763         u64 flags;
 764         u64 processor_mask;
 765         u64 gva_list[];
 766 };
 767
 768 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */
 769 struct hv_tlb_flush_ex {
 770         u64 address_space;
 771         u64 flags;
 772         struct hv_vpset hv_vp_set;
 773         u64 gva_list[];
 774 };
 775
 776 #endif