4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com>
8 * Based on SH7785 Setup
10 * Copyright (C) 2007 Paul Mundt
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
16 #include <linux/platform_device.h>
17 #include <linux/init.h>
18 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/sh_timer.h>
24 #include <linux/sh_intc.h>
25 #include <cpu/dma-register.h>
26 #include <asm/mmzone.h>
27 #include <asm/dmaengine.h>
29 static struct plat_sci_port scif0_platform_data = {
30 .mapbase = 0xffea0000,
31 .flags = UPF_BOOT_AUTOCONF,
33 .irqs = { 40, 41, 43, 42 },
36 static struct platform_device scif0_device = {
40 .platform_data = &scif0_platform_data,
45 * The rest of these all have multiplexed IRQs
47 static struct plat_sci_port scif1_platform_data = {
48 .mapbase = 0xffeb0000,
49 .flags = UPF_BOOT_AUTOCONF,
51 .irqs = { 44, 44, 44, 44 },
54 static struct platform_device scif1_device = {
58 .platform_data = &scif1_platform_data,
62 static struct plat_sci_port scif2_platform_data = {
63 .mapbase = 0xffec0000,
64 .flags = UPF_BOOT_AUTOCONF,
66 .irqs = { 50, 50, 50, 50 },
69 static struct platform_device scif2_device = {
73 .platform_data = &scif2_platform_data,
77 static struct plat_sci_port scif3_platform_data = {
78 .mapbase = 0xffed0000,
79 .flags = UPF_BOOT_AUTOCONF,
81 .irqs = { 51, 51, 51, 51 },
84 static struct platform_device scif3_device = {
88 .platform_data = &scif3_platform_data,
92 static struct plat_sci_port scif4_platform_data = {
93 .mapbase = 0xffee0000,
94 .flags = UPF_BOOT_AUTOCONF,
96 .irqs = { 52, 52, 52, 52 },
99 static struct platform_device scif4_device = {
103 .platform_data = &scif4_platform_data,
107 static struct plat_sci_port scif5_platform_data = {
108 .mapbase = 0xffef0000,
109 .flags = UPF_BOOT_AUTOCONF,
111 .irqs = { 53, 53, 53, 53 },
114 static struct platform_device scif5_device = {
118 .platform_data = &scif5_platform_data,
122 static struct sh_timer_config tmu0_platform_data = {
123 .channel_offset = 0x04,
125 .clockevent_rating = 200,
128 static struct resource tmu0_resources[] = {
132 .flags = IORESOURCE_MEM,
136 .flags = IORESOURCE_IRQ,
140 static struct platform_device tmu0_device = {
144 .platform_data = &tmu0_platform_data,
146 .resource = tmu0_resources,
147 .num_resources = ARRAY_SIZE(tmu0_resources),
150 static struct sh_timer_config tmu1_platform_data = {
151 .channel_offset = 0x10,
153 .clocksource_rating = 200,
156 static struct resource tmu1_resources[] = {
160 .flags = IORESOURCE_MEM,
164 .flags = IORESOURCE_IRQ,
168 static struct platform_device tmu1_device = {
172 .platform_data = &tmu1_platform_data,
174 .resource = tmu1_resources,
175 .num_resources = ARRAY_SIZE(tmu1_resources),
178 static struct sh_timer_config tmu2_platform_data = {
179 .channel_offset = 0x1c,
183 static struct resource tmu2_resources[] = {
187 .flags = IORESOURCE_MEM,
191 .flags = IORESOURCE_IRQ,
195 static struct platform_device tmu2_device = {
199 .platform_data = &tmu2_platform_data,
201 .resource = tmu2_resources,
202 .num_resources = ARRAY_SIZE(tmu2_resources),
205 static struct sh_timer_config tmu3_platform_data = {
206 .channel_offset = 0x04,
210 static struct resource tmu3_resources[] = {
214 .flags = IORESOURCE_MEM,
218 .flags = IORESOURCE_IRQ,
222 static struct platform_device tmu3_device = {
226 .platform_data = &tmu3_platform_data,
228 .resource = tmu3_resources,
229 .num_resources = ARRAY_SIZE(tmu3_resources),
232 static struct sh_timer_config tmu4_platform_data = {
233 .channel_offset = 0x10,
237 static struct resource tmu4_resources[] = {
241 .flags = IORESOURCE_MEM,
245 .flags = IORESOURCE_IRQ,
249 static struct platform_device tmu4_device = {
253 .platform_data = &tmu4_platform_data,
255 .resource = tmu4_resources,
256 .num_resources = ARRAY_SIZE(tmu4_resources),
259 static struct sh_timer_config tmu5_platform_data = {
260 .channel_offset = 0x1c,
264 static struct resource tmu5_resources[] = {
268 .flags = IORESOURCE_MEM,
272 .flags = IORESOURCE_IRQ,
276 static struct platform_device tmu5_device = {
280 .platform_data = &tmu5_platform_data,
282 .resource = tmu5_resources,
283 .num_resources = ARRAY_SIZE(tmu5_resources),
286 static struct sh_timer_config tmu6_platform_data = {
287 .channel_offset = 0x04,
291 static struct resource tmu6_resources[] = {
295 .flags = IORESOURCE_MEM,
299 .flags = IORESOURCE_IRQ,
303 static struct platform_device tmu6_device = {
307 .platform_data = &tmu6_platform_data,
309 .resource = tmu6_resources,
310 .num_resources = ARRAY_SIZE(tmu6_resources),
313 static struct sh_timer_config tmu7_platform_data = {
314 .channel_offset = 0x10,
318 static struct resource tmu7_resources[] = {
322 .flags = IORESOURCE_MEM,
326 .flags = IORESOURCE_IRQ,
330 static struct platform_device tmu7_device = {
334 .platform_data = &tmu7_platform_data,
336 .resource = tmu7_resources,
337 .num_resources = ARRAY_SIZE(tmu7_resources),
340 static struct sh_timer_config tmu8_platform_data = {
341 .channel_offset = 0x1c,
345 static struct resource tmu8_resources[] = {
349 .flags = IORESOURCE_MEM,
353 .flags = IORESOURCE_IRQ,
357 static struct platform_device tmu8_device = {
361 .platform_data = &tmu8_platform_data,
363 .resource = tmu8_resources,
364 .num_resources = ARRAY_SIZE(tmu8_resources),
367 static struct sh_timer_config tmu9_platform_data = {
368 .channel_offset = 0x04,
372 static struct resource tmu9_resources[] = {
376 .flags = IORESOURCE_MEM,
380 .flags = IORESOURCE_IRQ,
384 static struct platform_device tmu9_device = {
388 .platform_data = &tmu9_platform_data,
390 .resource = tmu9_resources,
391 .num_resources = ARRAY_SIZE(tmu9_resources),
394 static struct sh_timer_config tmu10_platform_data = {
395 .channel_offset = 0x10,
399 static struct resource tmu10_resources[] = {
403 .flags = IORESOURCE_MEM,
407 .flags = IORESOURCE_IRQ,
411 static struct platform_device tmu10_device = {
415 .platform_data = &tmu10_platform_data,
417 .resource = tmu10_resources,
418 .num_resources = ARRAY_SIZE(tmu10_resources),
421 static struct sh_timer_config tmu11_platform_data = {
422 .channel_offset = 0x1c,
426 static struct resource tmu11_resources[] = {
430 .flags = IORESOURCE_MEM,
434 .flags = IORESOURCE_IRQ,
438 static struct platform_device tmu11_device = {
442 .platform_data = &tmu11_platform_data,
444 .resource = tmu11_resources,
445 .num_resources = ARRAY_SIZE(tmu11_resources),
448 static const struct sh_dmae_channel dmac0_channels[] = {
476 static const unsigned int ts_shift[] = TS_SHIFT;
478 static struct sh_dmae_pdata dma0_platform_data = {
479 .channel = dmac0_channels,
480 .channel_num = ARRAY_SIZE(dmac0_channels),
481 .ts_low_shift = CHCR_TS_LOW_SHIFT,
482 .ts_low_mask = CHCR_TS_LOW_MASK,
483 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
484 .ts_high_mask = CHCR_TS_HIGH_MASK,
485 .ts_shift = ts_shift,
486 .ts_shift_num = ARRAY_SIZE(ts_shift),
487 .dmaor_init = DMAOR_INIT,
490 /* Resource order important! */
491 static struct resource dmac0_resources[] = {
493 /* Channel registers and DMAOR */
496 .flags = IORESOURCE_MEM,
501 .flags = IORESOURCE_MEM,
504 .start = evt2irq(0x5c0),
505 .end = evt2irq(0x5c0),
506 .flags = IORESOURCE_IRQ,
508 /* IRQ for channels 0-5 */
509 .start = evt2irq(0x500),
510 .end = evt2irq(0x5a0),
511 .flags = IORESOURCE_IRQ,
515 static struct platform_device dma0_device = {
516 .name = "sh-dma-engine",
518 .resource = dmac0_resources,
519 .num_resources = ARRAY_SIZE(dmac0_resources),
521 .platform_data = &dma0_platform_data,
525 static struct resource usb_ohci_resources[] = {
529 .flags = IORESOURCE_MEM,
534 .flags = IORESOURCE_IRQ,
538 static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
539 static struct platform_device usb_ohci_device = {
543 .dma_mask = &usb_ohci_dma_mask,
544 .coherent_dma_mask = DMA_BIT_MASK(32),
546 .num_resources = ARRAY_SIZE(usb_ohci_resources),
547 .resource = usb_ohci_resources,
550 static struct platform_device *sh7786_early_devices[] __initdata = {
571 static struct platform_device *sh7786_devices[] __initdata = {
577 * Please call this function if your platform board
578 * use external clock for USB
580 #define USBCTL0 0xffe70858
581 #define CLOCK_MODE_MASK 0xffffff7f
582 #define EXT_CLOCK_MODE 0x00000080
584 void __init sh7786_usb_use_exclock(void)
586 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
587 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
590 #define USBINITREG1 0xffe70094
591 #define USBINITREG2 0xffe7009c
592 #define USBINITVAL1 0x00ff0040
593 #define USBINITVAL2 0x00000001
595 #define USBPCTL1 0xffe70804
596 #define USBST 0xffe70808
597 #define PHY_ENB 0x00000001
598 #define PLL_ENB 0x00000002
599 #define PHY_RST 0x00000004
600 #define ACT_PLL_STATUS 0xc0000000
602 static void __init sh7786_usb_setup(void)
607 * USB initial settings
609 * The following settings are necessary
610 * for using the USB modules.
612 * see "USB Inital Settings" for detail
614 __raw_writel(USBINITVAL1, USBINITREG1);
615 __raw_writel(USBINITVAL2, USBINITREG2);
618 * Set the PHY and PLL enable bit
620 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
622 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
623 /* Set the PHY RST bit */
624 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
625 printk(KERN_INFO "sh7786 usb setup done\n");
632 static int __init sh7786_devices_setup(void)
638 ret = platform_add_devices(sh7786_early_devices,
639 ARRAY_SIZE(sh7786_early_devices));
640 if (unlikely(ret != 0))
643 return platform_add_devices(sh7786_devices,
644 ARRAY_SIZE(sh7786_devices));
646 arch_initcall(sh7786_devices_setup);
648 void __init plat_early_device_setup(void)
650 early_platform_add_devices(sh7786_early_devices,
651 ARRAY_SIZE(sh7786_early_devices));
657 /* interrupt sources */
659 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
660 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
661 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
662 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
664 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
665 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
666 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
667 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
669 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
671 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
672 TMU1_0, TMU1_1, TMU1_2,
673 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
675 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
677 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
680 SCIF2, SCIF3, SCIF4, SCIF5,
682 PCIeC0_0, PCIeC0_1, PCIeC0_2,
683 PCIeC1_0, PCIeC1_1, PCIeC1_2,
687 SSI0, SSI1, SSI2, SSI3,
688 PCIeC2_0, PCIeC2_1, PCIeC2_2,
694 INTICI0, INTICI1, INTICI2, INTICI3,
695 INTICI4, INTICI5, INTICI6, INTICI7,
698 static struct intc_vect vectors[] __initdata = {
699 INTC_VECT(WDT, 0x3e0),
700 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
701 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
702 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
703 INTC_VECT(TMU1_2, 0x4c0),
704 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
705 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
706 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
707 INTC_VECT(DMAC0_6, 0x5c0),
708 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
709 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
710 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
711 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
712 INTC_VECT(HPB_2, 0x6e0),
713 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
714 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
715 INTC_VECT(SCIF1, 0x780),
716 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
717 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
718 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
719 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
720 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
721 INTC_VECT(PCIeC0_2, 0xb20),
722 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
723 INTC_VECT(PCIeC1_2, 0xb80),
724 INTC_VECT(USB, 0xba0),
725 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
726 INTC_VECT(DU, 0xd00),
727 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
728 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
729 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
730 INTC_VECT(PCIeC2_2, 0xde0),
731 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
732 INTC_VECT(FLCTL, 0xe40),
733 INTC_VECT(HSPI, 0xe80),
734 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
735 INTC_VECT(Thermal, 0xee0),
736 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
737 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
738 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
739 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
742 #define CnINTMSK0 0xfe410030
743 #define CnINTMSK1 0xfe410040
744 #define CnINTMSKCLR0 0xfe410050
745 #define CnINTMSKCLR1 0xfe410060
746 #define CnINT2MSKR0 0xfe410a20
747 #define CnINT2MSKR1 0xfe410a24
748 #define CnINT2MSKR2 0xfe410a28
749 #define CnINT2MSKR3 0xfe410a2c
750 #define CnINT2MSKCR0 0xfe410a30
751 #define CnINT2MSKCR1 0xfe410a34
752 #define CnINT2MSKCR2 0xfe410a38
753 #define CnINT2MSKCR3 0xfe410a3c
754 #define INTMSK2 0xfe410068
755 #define INTMSKCLR2 0xfe41006c
757 #define INTDISTCR0 0xfe4100b0
758 #define INTDISTCR1 0xfe4100b4
759 #define INTACK 0xfe4100b8
760 #define INTACKCLR 0xfe4100bc
761 #define INT2DISTCR0 0xfe410900
762 #define INT2DISTCR1 0xfe410904
763 #define INT2DISTCR2 0xfe410908
764 #define INT2DISTCR3 0xfe41090c
766 static struct intc_mask_reg mask_registers[] __initdata = {
767 { CnINTMSK0, CnINTMSKCLR0, 32,
768 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
769 INTC_SMP_BALANCING(INTDISTCR0) },
770 { INTMSK2, INTMSKCLR2, 32,
771 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
772 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
773 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
774 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
775 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
776 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
777 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
778 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
779 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
780 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
781 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
782 INTC_SMP_BALANCING(INT2DISTCR0) },
783 { CnINT2MSKR1, CnINT2MSKCR1, 32,
784 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
785 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
787 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
789 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
791 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
792 { CnINT2MSKR2, CnINT2MSKCR2, 32,
793 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
795 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
796 PCIeC0_0, PCIeC0_1, PCIeC0_2,
797 PCIeC1_0, PCIeC1_1, PCIeC1_2,
798 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
799 { CnINT2MSKR3, CnINT2MSKCR3, 32,
802 DU, SSI0, SSI1, SSI2, SSI3,
803 PCIeC2_0, PCIeC2_1, PCIeC2_2,
806 HSPI, GPIO0, GPIO1, Thermal,
807 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
810 static struct intc_prio_reg prio_registers[] __initdata = {
811 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
812 IRQ4, IRQ5, IRQ6, IRQ7 } },
813 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
814 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
816 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
818 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
819 DMAC0_2, DMAC0_3 } },
820 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
822 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
823 DMAC1_1, DMAC1_2 } },
824 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
826 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
827 SCIF0_2, SCIF0_3 } },
828 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
829 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
830 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
832 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
833 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
834 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
835 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
836 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
837 PCIeC1_0, PCIeC1_1 } },
838 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
839 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
840 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
841 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
842 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
843 PCIeC2_1, PCIeC2_2 } },
844 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
845 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
847 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
848 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
849 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
850 { INTICI7, INTICI6, INTICI5, INTICI4,
851 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
854 static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
855 mask_registers, prio_registers, NULL);
857 /* Support for external interrupt pins in IRQ mode */
859 static struct intc_vect vectors_irq0123[] __initdata = {
860 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
861 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
864 static struct intc_vect vectors_irq4567[] __initdata = {
865 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
866 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
869 static struct intc_sense_reg sense_registers[] __initdata = {
870 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
871 IRQ4, IRQ5, IRQ6, IRQ7 } },
874 static struct intc_mask_reg ack_registers[] __initdata = {
875 { 0xfe410024, 0, 32, /* INTREQ */
876 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
879 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
880 vectors_irq0123, NULL, mask_registers,
881 prio_registers, sense_registers, ack_registers);
883 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
884 vectors_irq4567, NULL, mask_registers,
885 prio_registers, sense_registers, ack_registers);
887 /* External interrupt pins in IRL mode */
889 static struct intc_vect vectors_irl0123[] __initdata = {
890 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
891 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
892 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
893 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
894 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
895 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
896 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
897 INTC_VECT(IRL0_HHHL, 0x3c0),
900 static struct intc_vect vectors_irl4567[] __initdata = {
901 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
902 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
903 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
904 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
905 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
906 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
907 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
908 INTC_VECT(IRL4_HHHL, 0xac0),
911 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
912 NULL, mask_registers, NULL, NULL);
914 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
915 NULL, mask_registers, NULL, NULL);
917 #define INTC_ICR0 0xfe410000
918 #define INTC_INTMSK0 CnINTMSK0
919 #define INTC_INTMSK1 CnINTMSK1
920 #define INTC_INTMSK2 INTMSK2
921 #define INTC_INTMSKCLR1 CnINTMSKCLR1
922 #define INTC_INTMSKCLR2 INTMSKCLR2
923 #define INTC_USERIMASK 0xfe411000
925 #ifdef CONFIG_INTC_BALANCING
926 unsigned int irq_lookup(unsigned int irq)
928 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
931 void irq_finish(unsigned int irq)
933 __raw_writel(irq2evt(irq), INTACKCLR);
937 void __init plat_irq_setup(void)
939 /* disable IRQ3-0 + IRQ7-4 */
940 __raw_writel(0xff000000, INTC_INTMSK0);
942 /* disable IRL3-0 + IRL7-4 */
943 __raw_writel(0xc0000000, INTC_INTMSK1);
944 __raw_writel(0xfffefffe, INTC_INTMSK2);
946 /* select IRL mode for IRL3-0 + IRL7-4 */
947 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
949 register_intc_controller(&intc_desc);
950 register_intc_userimask(INTC_USERIMASK);
953 void __init plat_irq_setup_pins(int mode)
956 case IRQ_MODE_IRQ7654:
957 /* select IRQ mode for IRL7-4 */
958 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
959 register_intc_controller(&intc_desc_irq4567);
961 case IRQ_MODE_IRQ3210:
962 /* select IRQ mode for IRL3-0 */
963 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
964 register_intc_controller(&intc_desc_irq0123);
966 case IRQ_MODE_IRL7654:
967 /* enable IRL7-4 but don't provide any masking */
968 __raw_writel(0x40000000, INTC_INTMSKCLR1);
969 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
971 case IRQ_MODE_IRL3210:
972 /* enable IRL0-3 but don't provide any masking */
973 __raw_writel(0x80000000, INTC_INTMSKCLR1);
974 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
976 case IRQ_MODE_IRL7654_MASK:
977 /* enable IRL7-4 and mask using cpu intc controller */
978 __raw_writel(0x40000000, INTC_INTMSKCLR1);
979 register_intc_controller(&intc_desc_irl4567);
981 case IRQ_MODE_IRL3210_MASK:
982 /* enable IRL0-3 and mask using cpu intc controller */
983 __raw_writel(0x80000000, INTC_INTMSKCLR1);
984 register_intc_controller(&intc_desc_irl0123);
991 void __init plat_mem_setup(void)