arch/sh/kernel/cpu/sh4a/setup-sh7723.c

   1 /*
   2  * SH7723 Setup
   3  *
   4  *  Copyright (C) 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/mm.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/uio_driver.h>
  16 #include <asm/clock.h>
  17 #include <asm/mmzone.h>
  18
  19 static struct uio_info vpu_platform_data = {
  20         .name = "VPU5",
  21         .version = "0",
  22         .irq = 60,
  23 };
  24
  25 static struct resource vpu_resources[] = {
  26         [0] = {
  27                 .name   = "VPU",
  28                 .start  = 0xfe900000,
  29                 .end    = 0xfe902807,
  30                 .flags  = IORESOURCE_MEM,
  31         },
  32         [1] = {
  33                 /* place holder for contiguous memory */
  34         },
  35 };
  36
  37 static struct platform_device vpu_device = {
  38         .name           = "uio_pdrv_genirq",
  39         .id             = 0,
  40         .dev = {
  41                 .platform_data  = &vpu_platform_data,
  42         },
  43         .resource       = vpu_resources,
  44         .num_resources  = ARRAY_SIZE(vpu_resources),
  45 };
  46
  47 static struct uio_info veu0_platform_data = {
  48         .name = "VEU2H",
  49         .version = "0",
  50         .irq = 54,
  51 };
  52
  53 static struct resource veu0_resources[] = {
  54         [0] = {
  55                 .name   = "VEU2H0",
  56                 .start  = 0xfe920000,
  57                 .end    = 0xfe92027b,
  58                 .flags  = IORESOURCE_MEM,
  59         },
  60         [1] = {
  61                 /* place holder for contiguous memory */
  62         },
  63 };
  64
  65 static struct platform_device veu0_device = {
  66         .name           = "uio_pdrv_genirq",
  67         .id             = 1,
  68         .dev = {
  69                 .platform_data  = &veu0_platform_data,
  70         },
  71         .resource       = veu0_resources,
  72         .num_resources  = ARRAY_SIZE(veu0_resources),
  73 };
  74
  75 static struct uio_info veu1_platform_data = {
  76         .name = "VEU2H",
  77         .version = "0",
  78         .irq = 27,
  79 };
  80
  81 static struct resource veu1_resources[] = {
  82         [0] = {
  83                 .name   = "VEU2H1",
  84                 .start  = 0xfe924000,
  85                 .end    = 0xfe92427b,
  86                 .flags  = IORESOURCE_MEM,
  87         },
  88         [1] = {
  89                 /* place holder for contiguous memory */
  90         },
  91 };
  92
  93 static struct platform_device veu1_device = {
  94         .name           = "uio_pdrv_genirq",
  95         .id             = 2,
  96         .dev = {
  97                 .platform_data  = &veu1_platform_data,
  98         },
  99         .resource       = veu1_resources,
 100         .num_resources  = ARRAY_SIZE(veu1_resources),
 101 };
 102
 103 static struct plat_sci_port sci_platform_data[] = {
 104         {
 105                 .mapbase        = 0xffe00000,
 106                 .flags          = UPF_BOOT_AUTOCONF,
 107                 .type           = PORT_SCIF,
 108                 .irqs           = { 80, 80, 80, 80 },
 109         },{
 110                 .mapbase        = 0xffe10000,
 111                 .flags          = UPF_BOOT_AUTOCONF,
 112                 .type           = PORT_SCIF,
 113                 .irqs           = { 81, 81, 81, 81 },
 114         },{
 115                 .mapbase        = 0xffe20000,
 116                 .flags          = UPF_BOOT_AUTOCONF,
 117                 .type           = PORT_SCIF,
 118                 .irqs           = { 82, 82, 82, 82 },
 119         },{
 120                 .mapbase        = 0xa4e30000,
 121                 .flags          = UPF_BOOT_AUTOCONF,
 122                 .type           = PORT_SCIFA,
 123                 .irqs           = { 56, 56, 56, 56 },
 124         },{
 125                 .mapbase        = 0xa4e40000,
 126                 .flags          = UPF_BOOT_AUTOCONF,
 127                 .type           = PORT_SCIFA,
 128                 .irqs           = { 88, 88, 88, 88 },
 129         },{
 130                 .mapbase        = 0xa4e50000,
 131                 .flags          = UPF_BOOT_AUTOCONF,
 132                 .type           = PORT_SCIFA,
 133                 .irqs           = { 109, 109, 109, 109 },
 134         }, {
 135                 .flags = 0,
 136         }
 137 };
 138
 139 static struct platform_device sci_device = {
 140         .name           = "sh-sci",
 141         .id             = -1,
 142         .dev            = {
 143                 .platform_data  = sci_platform_data,
 144         },
 145 };
 146
 147 static struct resource rtc_resources[] = {
 148         [0] = {
 149                 .start  = 0xa465fec0,
 150                 .end    = 0xa465fec0 + 0x58 - 1,
 151                 .flags  = IORESOURCE_IO,
 152         },
 153         [1] = {
 154                 /* Period IRQ */
 155                 .start  = 69,
 156                 .flags  = IORESOURCE_IRQ,
 157         },
 158         [2] = {
 159                 /* Carry IRQ */
 160                 .start  = 70,
 161                 .flags  = IORESOURCE_IRQ,
 162         },
 163         [3] = {
 164                 /* Alarm IRQ */
 165                 .start  = 68,
 166                 .flags  = IORESOURCE_IRQ,
 167         },
 168 };
 169
 170 static struct platform_device rtc_device = {
 171         .name           = "sh-rtc",
 172         .id             = -1,
 173         .num_resources  = ARRAY_SIZE(rtc_resources),
 174         .resource       = rtc_resources,
 175 };
 176
 177 static struct resource sh7723_usb_host_resources[] = {
 178         [0] = {
 179                 .name   = "r8a66597_hcd",
 180                 .start  = 0xa4d80000,
 181                 .end    = 0xa4d800ff,
 182                 .flags  = IORESOURCE_MEM,
 183         },
 184         [1] = {
 185                 .start  = 65,
 186                 .end    = 65,
 187                 .flags  = IORESOURCE_IRQ,
 188         },
 189 };
 190
 191 static struct platform_device sh7723_usb_host_device = {
 192         .name           = "r8a66597_hcd",
 193         .id             = 0,
 194         .dev = {
 195                 .dma_mask               = NULL,         /*  not use dma */
 196                 .coherent_dma_mask      = 0xffffffff,
 197         },
 198         .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
 199         .resource       = sh7723_usb_host_resources,
 200 };
 201
 202 static struct resource iic_resources[] = {
 203         [0] = {
 204                 .name   = "IIC",
 205                 .start  = 0x04470000,
 206                 .end    = 0x04470017,
 207                 .flags  = IORESOURCE_MEM,
 208         },
 209         [1] = {
 210                 .start  = 96,
 211                 .end    = 99,
 212                 .flags  = IORESOURCE_IRQ,
 213        },
 214 };
 215
 216 static struct platform_device iic_device = {
 217         .name           = "i2c-sh_mobile",
 218         .id             = 0, /* "i2c0" clock */
 219         .num_resources  = ARRAY_SIZE(iic_resources),
 220         .resource       = iic_resources,
 221 };
 222
 223 static struct platform_device *sh7723_devices[] __initdata = {
 224         &sci_device,
 225         &rtc_device,
 226         &iic_device,
 227         &sh7723_usb_host_device,
 228         &vpu_device,
 229         &veu0_device,
 230         &veu1_device,
 231 };
 232
 233 static int __init sh7723_devices_setup(void)
 234 {
 235         clk_always_enable("meram0"); /* MERAM */
 236         clk_always_enable("rtc0"); /* RTC */
 237         clk_always_enable("veu1"); /* VEU2H1 */
 238         clk_always_enable("veu0"); /* VEU2H0 */
 239         clk_always_enable("vpu0"); /* VPU */
 240
 241         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 242         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 243         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 244
 245         return platform_add_devices(sh7723_devices,
 246                                     ARRAY_SIZE(sh7723_devices));
 247 }
 248 __initcall(sh7723_devices_setup);
 249
 250 enum {
 251         UNUSED=0,
 252
 253         /* interrupt sources */
 254         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 255         HUDI,
 256         DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
 257         _2DG_TRI,_2DG_INI,_2DG_CEI,
 258         DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
 259         VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
 260         SCIFA_SCIFA0,
 261         VPU_VPUI,
 262         TPU_TPUI,
 263         ADC_ADI,
 264         USB_USI0,
 265         RTC_ATI,RTC_PRI,RTC_CUI,
 266         DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
 267         DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
 268         KEYSC_KEYI,
 269         SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
 270         MSIOF_MSIOFI0,MSIOF_MSIOFI1,
 271         SCIFA_SCIFA1,
 272         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
 273         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
 274         SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
 275         CMT_CMTI,
 276         TSIF_TSIFI,
 277         SIU_SIUI,
 278         SCIFA_SCIFA2,
 279         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
 280         IRDA_IRDAI,
 281         ATAPI_ATAPII,
 282         SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
 283         VEU2H1_VEU2HI,
 284         LCDC_LCDCI,
 285         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
 286
 287         /* interrupt groups */
 288         DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
 289         SDHI1, RTC, DMAC1B, SDHI0,
 290 };
 291
 292 static struct intc_vect vectors[] __initdata = {
 293         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 294         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 295         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 296         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 297
 298         INTC_VECT(DMAC1A_DEI0,0x700),
 299         INTC_VECT(DMAC1A_DEI1,0x720),
 300         INTC_VECT(DMAC1A_DEI2,0x740),
 301         INTC_VECT(DMAC1A_DEI3,0x760),
 302
 303         INTC_VECT(_2DG_TRI, 0x780),
 304         INTC_VECT(_2DG_INI, 0x7A0),
 305         INTC_VECT(_2DG_CEI, 0x7C0),
 306
 307         INTC_VECT(DMAC0A_DEI0,0x800),
 308         INTC_VECT(DMAC0A_DEI1,0x820),
 309         INTC_VECT(DMAC0A_DEI2,0x840),
 310         INTC_VECT(DMAC0A_DEI3,0x860),
 311
 312         INTC_VECT(VIO_CEUI,0x880),
 313         INTC_VECT(VIO_BEUI,0x8A0),
 314         INTC_VECT(VIO_VEU2HI,0x8C0),
 315         INTC_VECT(VIO_VOUI,0x8E0),
 316
 317         INTC_VECT(SCIFA_SCIFA0,0x900),
 318         INTC_VECT(VPU_VPUI,0x980),
 319         INTC_VECT(TPU_TPUI,0x9A0),
 320         INTC_VECT(ADC_ADI,0x9E0),
 321         INTC_VECT(USB_USI0,0xA20),
 322
 323         INTC_VECT(RTC_ATI,0xA80),
 324         INTC_VECT(RTC_PRI,0xAA0),
 325         INTC_VECT(RTC_CUI,0xAC0),
 326
 327         INTC_VECT(DMAC1B_DEI4,0xB00),
 328         INTC_VECT(DMAC1B_DEI5,0xB20),
 329         INTC_VECT(DMAC1B_DADERR,0xB40),
 330
 331         INTC_VECT(DMAC0B_DEI4,0xB80),
 332         INTC_VECT(DMAC0B_DEI5,0xBA0),
 333         INTC_VECT(DMAC0B_DADERR,0xBC0),
 334
 335         INTC_VECT(KEYSC_KEYI,0xBE0),
 336         INTC_VECT(SCIF_SCIF0,0xC00),
 337         INTC_VECT(SCIF_SCIF1,0xC20),
 338         INTC_VECT(SCIF_SCIF2,0xC40),
 339         INTC_VECT(MSIOF_MSIOFI0,0xC80),
 340         INTC_VECT(MSIOF_MSIOFI1,0xCA0),
 341         INTC_VECT(SCIFA_SCIFA1,0xD00),
 342
 343         INTC_VECT(FLCTL_FLSTEI,0xD80),
 344         INTC_VECT(FLCTL_FLTENDI,0xDA0),
 345         INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
 346         INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
 347
 348         INTC_VECT(I2C_ALI,0xE00),
 349         INTC_VECT(I2C_TACKI,0xE20),
 350         INTC_VECT(I2C_WAITI,0xE40),
 351         INTC_VECT(I2C_DTEI,0xE60),
 352
 353         INTC_VECT(SDHI0_SDHII0,0xE80),
 354         INTC_VECT(SDHI0_SDHII1,0xEA0),
 355         INTC_VECT(SDHI0_SDHII2,0xEC0),
 356
 357         INTC_VECT(CMT_CMTI,0xF00),
 358         INTC_VECT(TSIF_TSIFI,0xF20),
 359         INTC_VECT(SIU_SIUI,0xF80),
 360         INTC_VECT(SCIFA_SCIFA2,0xFA0),
 361
 362         INTC_VECT(TMU0_TUNI0,0x400),
 363         INTC_VECT(TMU0_TUNI1,0x420),
 364         INTC_VECT(TMU0_TUNI2,0x440),
 365
 366         INTC_VECT(IRDA_IRDAI,0x480),
 367         INTC_VECT(ATAPI_ATAPII,0x4A0),
 368
 369         INTC_VECT(SDHI1_SDHII0,0x4E0),
 370         INTC_VECT(SDHI1_SDHII1,0x500),
 371         INTC_VECT(SDHI1_SDHII2,0x520),
 372
 373         INTC_VECT(VEU2H1_VEU2HI,0x560),
 374         INTC_VECT(LCDC_LCDCI,0x580),
 375
 376         INTC_VECT(TMU1_TUNI0,0x920),
 377         INTC_VECT(TMU1_TUNI1,0x940),
 378         INTC_VECT(TMU1_TUNI2,0x960),
 379
 380 };
 381
 382 static struct intc_group groups[] __initdata = {
 383         INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
 384         INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
 385         INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
 386         INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
 387         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
 388         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
 389         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
 390         INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
 391         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
 392         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
 393         INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
 394 };
 395
 396 static struct intc_mask_reg mask_registers[] __initdata = {
 397         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 398           { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
 399         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 400           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
 401         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 402           { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
 403         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 404           { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
 405         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 406           { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
 407         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 408           { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
 409         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 410           { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
 411         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 412           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 413             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
 414         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 415           { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
 416         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 417           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
 418         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 419           { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
 420         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 421           { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
 422         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
 423           { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
 424         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 425           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 426 };
 427
 428 static struct intc_prio_reg prio_registers[] __initdata = {
 429         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
 430         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
 431         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
 432         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 433         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
 434         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
 435         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
 436         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
 437         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
 438         { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
 439         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
 440         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
 441         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 442           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 443 };
 444
 445 static struct intc_sense_reg sense_registers[] __initdata = {
 446         { 0xa414001c, 16, 2, /* ICR1 */
 447           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 448 };
 449
 450 static struct intc_mask_reg ack_registers[] __initdata = {
 451         { 0xa4140024, 0, 8, /* INTREQ00 */
 452           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 453 };
 454
 455 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
 456                              mask_registers, prio_registers, sense_registers,
 457                              ack_registers);
 458
 459 void __init plat_irq_setup(void)
 460 {
 461         register_intc_controller(&intc_desc);
 462 }