2 * SMP initialisation and IPI support
3 * Based on arch/arm64/kernel/smp.c
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2015 Regents of the University of California
7 * Copyright (C) 2017 SiFive
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/interrupt.h>
23 #include <linux/smp.h>
24 #include <linux/sched.h>
25 #include <linux/seq_file.h>
26 #include <linux/delay.h>
29 #include <asm/tlbflush.h>
30 #include <asm/cacheflush.h>
32 enum ipi_message_type {
39 /* A collection of single bit ipi messages. */
41 unsigned long stats[IPI_MAX] ____cacheline_aligned;
42 unsigned long bits ____cacheline_aligned;
43 } ipi_data[NR_CPUS] __cacheline_aligned;
45 int riscv_hartid_to_cpuid(int hartid)
49 for (i = 0; i < NR_CPUS; i++)
50 if (cpuid_to_hartid_map(i) == hartid)
53 pr_err("Couldn't find cpu id for hartid [%d]\n", hartid);
58 void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out)
63 cpumask_set_cpu(cpuid_to_hartid_map(cpu), out);
66 int setup_profiling_timer(unsigned int multiplier)
71 static void ipi_stop(void)
73 set_cpu_online(smp_processor_id(), false);
78 void riscv_software_interrupt(void)
80 unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits;
81 unsigned long *stats = ipi_data[smp_processor_id()].stats;
83 /* Clear pending IPI */
84 csr_clear(sip, SIE_SSIE);
89 /* Order bit clearing and data access. */
92 ops = xchg(pending_ipis, 0);
96 if (ops & (1 << IPI_RESCHEDULE)) {
97 stats[IPI_RESCHEDULE]++;
101 if (ops & (1 << IPI_CALL_FUNC)) {
102 stats[IPI_CALL_FUNC]++;
103 generic_smp_call_function_interrupt();
106 if (ops & (1 << IPI_CPU_STOP)) {
107 stats[IPI_CPU_STOP]++;
111 BUG_ON((ops >> IPI_MAX) != 0);
113 /* Order data access and bit testing. */
119 send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation)
122 struct cpumask hartid_mask;
124 cpumask_clear(&hartid_mask);
126 for_each_cpu(cpuid, to_whom) {
127 set_bit(operation, &ipi_data[cpuid].bits);
128 hartid = cpuid_to_hartid_map(cpuid);
129 cpumask_set_cpu(hartid, &hartid_mask);
132 sbi_send_ipi(cpumask_bits(&hartid_mask));
135 static const char * const ipi_names[] = {
136 [IPI_RESCHEDULE] = "Rescheduling interrupts",
137 [IPI_CALL_FUNC] = "Function call interrupts",
138 [IPI_CPU_STOP] = "CPU stop interrupts",
141 void show_ipi_stats(struct seq_file *p, int prec)
145 for (i = 0; i < IPI_MAX; i++) {
146 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
147 prec >= 4 ? " " : "");
148 for_each_online_cpu(cpu)
149 seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]);
150 seq_printf(p, " %s\n", ipi_names[i]);
154 void arch_send_call_function_ipi_mask(struct cpumask *mask)
156 send_ipi_message(mask, IPI_CALL_FUNC);
159 void arch_send_call_function_single_ipi(int cpu)
161 send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
164 void smp_send_stop(void)
166 unsigned long timeout;
168 if (num_online_cpus() > 1) {
171 cpumask_copy(&mask, cpu_online_mask);
172 cpumask_clear_cpu(smp_processor_id(), &mask);
174 if (system_state <= SYSTEM_RUNNING)
175 pr_crit("SMP: stopping secondary CPUs\n");
176 send_ipi_message(&mask, IPI_CPU_STOP);
179 /* Wait up to one second for other CPUs to stop */
180 timeout = USEC_PER_SEC;
181 while (num_online_cpus() > 1 && timeout--)
184 if (num_online_cpus() > 1)
185 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
186 cpumask_pr_args(cpu_online_mask));
189 void smp_send_reschedule(int cpu)
191 send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
195 * Performs an icache flush for the given MM context. RISC-V has no direct
196 * mechanism for instruction cache shoot downs, so instead we send an IPI that
197 * informs the remote harts they need to flush their local instruction caches.
198 * To avoid pathologically slow behavior in a common case (a bunch of
199 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
200 * IPIs for harts that are not currently executing a MM context and instead
201 * schedule a deferred local instruction cache flush to be performed before
202 * execution resumes on each hart.
204 void flush_icache_mm(struct mm_struct *mm, bool local)
207 cpumask_t others, hmask, *mask;
211 /* Mark every hart's icache as needing a flush for this MM. */
212 mask = &mm->context.icache_stale_mask;
213 cpumask_setall(mask);
214 /* Flush this hart's I$ now, and mark it as flushed. */
215 cpu = smp_processor_id();
216 cpumask_clear_cpu(cpu, mask);
217 local_flush_icache_all();
220 * Flush the I$ of other harts concurrently executing, and mark them as
223 cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
224 local |= cpumask_empty(&others);
225 if (mm != current->active_mm || !local) {
226 cpumask_clear(&hmask);
227 riscv_cpuid_to_hartid_mask(&others, &hmask);
228 sbi_remote_fence_i(hmask.bits);
231 * It's assumed that at least one strongly ordered operation is
232 * performed on this hart between setting a hart's cpumask bit
233 * and scheduling this MM context on that hart. Sending an SBI
234 * remote message will do this, but in the case where no
235 * messages are sent we still need to order this hart's writes
236 * with flush_icache_deferred().