arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2018-2019 SiFive, Inc */
   3
   4 #include "fu540-c000.dtsi"
   5
   6 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
   7 #define RTCCLK_FREQ             1000000
   8
   9 / {
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12         model = "SiFive HiFive Unleashed A00";
  13         compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
  14
  15         chosen {
  16         };
  17
  18         cpus {
  19                 timebase-frequency = <RTCCLK_FREQ>;
  20         };
  21
  22         memory@80000000 {
  23                 device_type = "memory";
  24                 reg = <0x0 0x80000000 0x2 0x00000000>;
  25         };
  26
  27         soc {
  28         };
  29
  30         hfclk: hfclk {
  31                 #clock-cells = <0>;
  32                 compatible = "fixed-clock";
  33                 clock-frequency = <33333333>;
  34                 clock-output-names = "hfclk";
  35         };
  36
  37         rtcclk: rtcclk {
  38                 #clock-cells = <0>;
  39                 compatible = "fixed-clock";
  40                 clock-frequency = <RTCCLK_FREQ>;
  41                 clock-output-names = "rtcclk";
  42         };
  43 };
  44
  45 &uart0 {
  46         status = "okay";
  47 };
  48
  49 &uart1 {
  50         status = "okay";
  51 };
  52
  53 &i2c0 {
  54         status = "okay";
  55 };
  56
  57 &qspi0 {
  58         status = "okay";
  59         flash@0 {
  60                 compatible = "issi,is25wp256", "jedec,spi-nor";
  61                 reg = <0>;
  62                 spi-max-frequency = <50000000>;
  63                 m25p,fast-read;
  64                 spi-tx-bus-width = <4>;
  65                 spi-rx-bus-width = <4>;
  66         };
  67 };
  68
  69 &qspi2 {
  70         status = "okay";
  71         mmc@0 {
  72                 compatible = "mmc-spi-slot";
  73                 reg = <0>;
  74                 spi-max-frequency = <20000000>;
  75                 voltage-ranges = <3300 3300>;
  76                 disable-wp;
  77         };
  78 };
  79
  80 &eth0 {
  81         status = "okay";
  82         phy-mode = "gmii";
  83         phy-handle = <&phy0>;
  84         phy0: ethernet-phy@0 {
  85                 reg = <0>;
  86         };
  87 };