2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
34 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) udbg_printf(fmt)
42 unsigned long pci_probe_only = 1;
43 unsigned long pci_assign_all_buses = 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask;
51 EXPORT_SYMBOL(io_page_mask);
53 #ifdef CONFIG_PPC_MULTIPLATFORM
54 static void fixup_resource(struct resource *res, struct pci_dev *dev);
55 static void do_bus_setup(struct pci_bus *bus);
58 unsigned int pcibios_assign_all_busses(void)
60 return pci_assign_all_buses;
63 /* pci_io_base -- the base address from which io bars are offsets.
64 * This is the lowest I/O base address (so bar values are always positive),
65 * and it *must* be the start of ISA space if an ISA bus exists because
66 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
67 * page is mapped and isa_io_limit prevents access to it.
69 unsigned long isa_io_base; /* NULL if no ISA bus */
70 EXPORT_SYMBOL(isa_io_base);
71 unsigned long pci_io_base;
72 EXPORT_SYMBOL(pci_io_base);
74 void iSeries_pcibios_init(void);
78 struct dma_mapping_ops pci_dma_ops;
79 EXPORT_SYMBOL(pci_dma_ops);
81 int global_phb_number; /* Global phb counter */
83 /* Cached ISA bridge dev. */
84 struct pci_dev *ppc64_isabridge_dev = NULL;
86 static void fixup_broken_pcnet32(struct pci_dev* dev)
88 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
89 dev->vendor = PCI_VENDOR_ID_AMD;
90 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
93 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
95 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
98 unsigned long offset = 0;
99 struct pci_controller *hose = pci_bus_to_host(dev->bus);
104 if (res->flags & IORESOURCE_IO)
105 offset = (unsigned long)hose->io_base_virt - pci_io_base;
107 if (res->flags & IORESOURCE_MEM)
108 offset = hose->pci_mem_offset;
110 region->start = res->start - offset;
111 region->end = res->end - offset;
114 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
115 struct pci_bus_region *region)
117 unsigned long offset = 0;
118 struct pci_controller *hose = pci_bus_to_host(dev->bus);
123 if (res->flags & IORESOURCE_IO)
124 offset = (unsigned long)hose->io_base_virt - pci_io_base;
126 if (res->flags & IORESOURCE_MEM)
127 offset = hose->pci_mem_offset;
129 res->start = region->start + offset;
130 res->end = region->end + offset;
133 #ifdef CONFIG_HOTPLUG
134 EXPORT_SYMBOL(pcibios_resource_to_bus);
135 EXPORT_SYMBOL(pcibios_bus_to_resource);
139 * We need to avoid collisions with `mirrored' VGA ports
140 * and other strange ISA hardware, so we always want the
141 * addresses to be allocated in the 0x000-0x0ff region
144 * Why? Because some silly external IO cards only decode
145 * the low 10 bits of the IO address. The 0x00-0xff region
146 * is reserved for motherboard devices that decode all 16
147 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
148 * but we want to try to avoid allocating at 0x2900-0x2bff
149 * which might have be mirrored at 0x0100-0x03ff..
151 void pcibios_align_resource(void *data, struct resource *res,
152 unsigned long size, unsigned long align)
154 struct pci_dev *dev = data;
155 struct pci_controller *hose = pci_bus_to_host(dev->bus);
156 unsigned long start = res->start;
157 unsigned long alignto;
159 if (res->flags & IORESOURCE_IO) {
160 unsigned long offset = (unsigned long)hose->io_base_virt -
162 /* Make sure we start at our min on all hoses */
163 if (start - offset < PCIBIOS_MIN_IO)
164 start = PCIBIOS_MIN_IO + offset;
167 * Put everything into 0x00-0xff region modulo 0x400
170 start = (start + 0x3ff) & ~0x3ff;
172 } else if (res->flags & IORESOURCE_MEM) {
173 /* Make sure we start at our min on all hoses */
174 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
175 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
177 /* Align to multiple of size of minimum base. */
178 alignto = max(0x1000UL, align);
179 start = ALIGN(start, alignto);
185 static DEFINE_SPINLOCK(hose_spinlock);
188 * pci_controller(phb) initialized common variables.
190 void __devinit pci_setup_pci_controller(struct pci_controller *hose)
192 memset(hose, 0, sizeof(struct pci_controller));
194 spin_lock(&hose_spinlock);
195 hose->global_number = global_phb_number++;
196 list_add_tail(&hose->list_node, &hose_list);
197 spin_unlock(&hose_spinlock);
200 static void __init pcibios_claim_one_bus(struct pci_bus *b)
203 struct pci_bus *child_bus;
205 list_for_each_entry(dev, &b->devices, bus_list) {
208 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
209 struct resource *r = &dev->resource[i];
211 if (r->parent || !r->start || !r->flags)
213 pci_claim_resource(dev, i);
217 list_for_each_entry(child_bus, &b->children, node)
218 pcibios_claim_one_bus(child_bus);
221 #ifndef CONFIG_PPC_ISERIES
222 static void __init pcibios_claim_of_setup(void)
226 list_for_each_entry(b, &pci_root_buses, node)
227 pcibios_claim_one_bus(b);
231 #ifdef CONFIG_PPC_MULTIPLATFORM
232 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
237 prop = (u32 *) get_property(np, name, &len);
238 if (prop && len >= 4)
243 static unsigned int pci_parse_of_flags(u32 addr0)
245 unsigned int flags = 0;
247 if (addr0 & 0x02000000) {
248 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
249 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
250 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
251 if (addr0 & 0x40000000)
252 flags |= IORESOURCE_PREFETCH
253 | PCI_BASE_ADDRESS_MEM_PREFETCH;
254 } else if (addr0 & 0x01000000)
255 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
259 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
261 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
265 struct resource *res;
269 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
272 for (; proplen >= 20; proplen -= 20, addrs += 5) {
273 flags = pci_parse_of_flags(addrs[0]);
276 base = GET_64BIT(addrs, 1);
277 size = GET_64BIT(addrs, 3);
281 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
282 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
283 } else if (i == dev->rom_base_reg) {
284 res = &dev->resource[PCI_ROM_RESOURCE];
285 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
287 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
291 res->end = base + size - 1;
293 res->name = pci_name(dev);
294 fixup_resource(res, dev);
298 static struct pci_dev *of_create_pci_dev(struct device_node *node,
299 struct pci_bus *bus, int devfn)
304 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
307 type = get_property(node, "device_type", NULL);
311 memset(dev, 0, sizeof(struct pci_dev));
314 dev->dev.parent = bus->bridge;
315 dev->dev.bus = &pci_bus_type;
317 dev->multifunction = 0; /* maybe a lie? */
319 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
320 dev->device = get_int_prop(node, "device-id", 0xffff);
321 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
322 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
324 dev->cfg_size = 256; /*pci_cfg_space_size(dev);*/
326 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
327 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
328 dev->class = get_int_prop(node, "class-code", 0);
330 dev->current_state = 4; /* unknown power state */
332 if (!strcmp(type, "pci")) {
333 /* a PCI-PCI bridge */
334 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
335 dev->rom_base_reg = PCI_ROM_ADDRESS1;
336 } else if (!strcmp(type, "cardbus")) {
337 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
339 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
340 dev->rom_base_reg = PCI_ROM_ADDRESS;
342 if (node->n_intrs > 0) {
343 dev->irq = node->intrs[0].line;
344 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
349 pci_parse_of_addrs(node, dev);
351 pci_device_add(dev, bus);
353 /* XXX pci_scan_msi_device(dev); */
358 static void of_scan_pci_bridge(struct device_node *node, struct pci_dev *dev);
360 static void __devinit of_scan_bus(struct device_node *node,
363 struct device_node *child = NULL;
368 while ((child = of_get_next_child(node, child)) != NULL) {
369 reg = (u32 *) get_property(child, "reg", ®len);
370 if (reg == NULL || reglen < 20)
372 devfn = (reg[0] >> 8) & 0xff;
373 /* create a new pci_dev for this device */
374 dev = of_create_pci_dev(child, bus, devfn);
377 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
378 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
379 of_scan_pci_bridge(child, dev);
385 static void __devinit of_scan_pci_bridge(struct device_node *node,
389 u32 *busrange, *ranges;
391 struct resource *res;
395 /* parse bus-range property */
396 busrange = (u32 *) get_property(node, "bus-range", &len);
397 if (busrange == NULL || len != 8) {
398 printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n",
402 ranges = (u32 *) get_property(node, "ranges", &len);
403 if (ranges == NULL) {
404 printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n",
409 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
411 printk(KERN_ERR "Failed to create pci bus for %s\n",
416 bus->primary = dev->bus->number;
417 bus->subordinate = busrange[1];
421 /* parse ranges property */
422 /* PCI #address-cells == 3 and #size-cells == 2 always */
423 res = &dev->resource[PCI_BRIDGE_RESOURCES];
424 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
426 bus->resource[i] = res;
430 for (; len >= 32; len -= 32, ranges += 8) {
431 flags = pci_parse_of_flags(ranges[0]);
432 size = GET_64BIT(ranges, 6);
433 if (flags == 0 || size == 0)
435 if (flags & IORESOURCE_IO) {
436 res = bus->resource[0];
438 printk(KERN_ERR "PCI: ignoring extra I/O range"
439 " for bridge %s\n", node->full_name);
443 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
444 printk(KERN_ERR "PCI: too many memory ranges"
445 " for bridge %s\n", node->full_name);
448 res = bus->resource[i];
451 res->start = GET_64BIT(ranges, 1);
452 res->end = res->start + size - 1;
454 fixup_resource(res, dev);
456 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
459 mode = PCI_PROBE_NORMAL;
460 if (ppc_md.pci_probe_mode)
461 mode = ppc_md.pci_probe_mode(bus);
462 if (mode == PCI_PROBE_DEVTREE)
463 of_scan_bus(node, bus);
464 else if (mode == PCI_PROBE_NORMAL)
465 pci_scan_child_bus(bus);
467 #endif /* CONFIG_PPC_MULTIPLATFORM */
469 static void __devinit scan_phb(struct pci_controller *hose)
472 struct device_node *node = hose->arch_data;
474 struct resource *res;
476 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
478 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
479 hose->global_number);
482 bus->secondary = hose->first_busno;
485 bus->resource[0] = res = &hose->io_resource;
486 if (res->flags && request_resource(&ioport_resource, res))
487 printk(KERN_ERR "Failed to request PCI IO region "
488 "on PCI domain %04x\n", hose->global_number);
490 for (i = 0; i < 3; ++i) {
491 res = &hose->mem_resources[i];
492 bus->resource[i+1] = res;
493 if (res->flags && request_resource(&iomem_resource, res))
494 printk(KERN_ERR "Failed to request PCI memory region "
495 "on PCI domain %04x\n", hose->global_number);
498 mode = PCI_PROBE_NORMAL;
499 #ifdef CONFIG_PPC_MULTIPLATFORM
500 if (ppc_md.pci_probe_mode)
501 mode = ppc_md.pci_probe_mode(bus);
502 if (mode == PCI_PROBE_DEVTREE) {
503 bus->subordinate = hose->last_busno;
504 of_scan_bus(node, bus);
506 #endif /* CONFIG_PPC_MULTIPLATFORM */
507 if (mode == PCI_PROBE_NORMAL)
508 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
509 pci_bus_add_devices(bus);
512 static int __init pcibios_init(void)
514 struct pci_controller *hose, *tmp;
516 /* For now, override phys_mem_access_prot. If we need it,
517 * later, we may move that initialization to each ppc_md
519 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
521 #ifdef CONFIG_PPC_ISERIES
522 iSeries_pcibios_init();
525 printk("PCI: Probing PCI hardware\n");
527 /* Scan all of the recorded PCI controllers. */
528 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
531 #ifndef CONFIG_PPC_ISERIES
533 pcibios_claim_of_setup();
535 /* FIXME: `else' will be removed when
536 pci_assign_unassigned_resources() is able to work
537 correctly with [partially] allocated PCI tree. */
538 pci_assign_unassigned_resources();
539 #endif /* !CONFIG_PPC_ISERIES */
541 /* Call machine dependent final fixup */
542 if (ppc_md.pcibios_fixup)
543 ppc_md.pcibios_fixup();
545 /* Cache the location of the ISA bridge (if we have one) */
546 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
547 if (ppc64_isabridge_dev != NULL)
548 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
550 printk("PCI: Probing PCI hardware done\n");
555 subsys_initcall(pcibios_init);
557 char __init *pcibios_setup(char *str)
562 int pcibios_enable_device(struct pci_dev *dev, int mask)
567 pci_read_config_word(dev, PCI_COMMAND, &cmd);
570 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
571 struct resource *res = &dev->resource[i];
573 /* Only set up the requested stuff */
574 if (!(mask & (1<<i)))
577 if (res->flags & IORESOURCE_IO)
578 cmd |= PCI_COMMAND_IO;
579 if (res->flags & IORESOURCE_MEM)
580 cmd |= PCI_COMMAND_MEMORY;
584 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
586 /* Enable the appropriate bits in the PCI command register. */
587 pci_write_config_word(dev, PCI_COMMAND, cmd);
593 * Return the domain number for this bus.
595 int pci_domain_nr(struct pci_bus *bus)
597 #ifdef CONFIG_PPC_ISERIES
600 struct pci_controller *hose = pci_bus_to_host(bus);
602 return hose->global_number;
606 EXPORT_SYMBOL(pci_domain_nr);
608 /* Decide whether to display the domain number in /proc */
609 int pci_proc_domain(struct pci_bus *bus)
611 #ifdef CONFIG_PPC_ISERIES
614 struct pci_controller *hose = pci_bus_to_host(bus);
620 * Platform support for /proc/bus/pci/X/Y mmap()s,
621 * modelled on the sparc64 implementation by Dave Miller.
626 * Adjust vm_pgoff of VMA such that it is the physical page offset
627 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
629 * Basically, the user finds the base address for his device which he wishes
630 * to mmap. They read the 32-bit value from the config space base register,
631 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
632 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
634 * Returns negative error code on failure, zero on success.
636 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
637 unsigned long *offset,
638 enum pci_mmap_state mmap_state)
640 struct pci_controller *hose = pci_bus_to_host(dev->bus);
641 unsigned long io_offset = 0;
645 return NULL; /* should never happen */
647 /* If memory, add on the PCI bridge address offset */
648 if (mmap_state == pci_mmap_mem) {
649 *offset += hose->pci_mem_offset;
650 res_bit = IORESOURCE_MEM;
652 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
653 *offset += io_offset;
654 res_bit = IORESOURCE_IO;
658 * Check that the offset requested corresponds to one of the
659 * resources of the device.
661 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
662 struct resource *rp = &dev->resource[i];
663 int flags = rp->flags;
665 /* treat ROM as memory (should be already) */
666 if (i == PCI_ROM_RESOURCE)
667 flags |= IORESOURCE_MEM;
669 /* Active and same type? */
670 if ((flags & res_bit) == 0)
673 /* In the range of this resource? */
674 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
677 /* found it! construct the final physical address */
678 if (mmap_state == pci_mmap_io)
679 *offset += hose->io_base_phys - io_offset;
687 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
690 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
692 enum pci_mmap_state mmap_state,
695 unsigned long prot = pgprot_val(protection);
697 /* Write combine is always 0 on non-memory space mappings. On
698 * memory space, if the user didn't pass 1, we check for a
699 * "prefetchable" resource. This is a bit hackish, but we use
700 * this to workaround the inability of /sysfs to provide a write
703 if (mmap_state != pci_mmap_mem)
705 else if (write_combine == 0) {
706 if (rp->flags & IORESOURCE_PREFETCH)
710 /* XXX would be nice to have a way to ask for write-through */
711 prot |= _PAGE_NO_CACHE;
713 prot &= ~_PAGE_GUARDED;
715 prot |= _PAGE_GUARDED;
717 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
720 return __pgprot(prot);
724 * This one is used by /dev/mem and fbdev who have no clue about the
725 * PCI device, it tries to find the PCI device first and calls the
728 pgprot_t pci_phys_mem_access_prot(struct file *file,
733 struct pci_dev *pdev = NULL;
734 struct resource *found = NULL;
735 unsigned long prot = pgprot_val(protection);
736 unsigned long offset = pfn << PAGE_SHIFT;
739 if (page_is_ram(pfn))
740 return __pgprot(prot);
742 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
744 for_each_pci_dev(pdev) {
745 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
746 struct resource *rp = &pdev->resource[i];
747 int flags = rp->flags;
749 /* Active and same type? */
750 if ((flags & IORESOURCE_MEM) == 0)
752 /* In the range of this resource? */
753 if (offset < (rp->start & PAGE_MASK) ||
763 if (found->flags & IORESOURCE_PREFETCH)
764 prot &= ~_PAGE_GUARDED;
768 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
770 return __pgprot(prot);
775 * Perform the actual remap of the pages for a PCI device mapping, as
776 * appropriate for this architecture. The region in the process to map
777 * is described by vm_start and vm_end members of VMA, the base physical
778 * address is found in vm_pgoff.
779 * The pci device structure is provided so that architectures may make mapping
780 * decisions on a per-device or per-bus basis.
782 * Returns a negative error code on failure, zero on success.
784 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
785 enum pci_mmap_state mmap_state,
788 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
792 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
796 vma->vm_pgoff = offset >> PAGE_SHIFT;
797 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
798 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
800 mmap_state, write_combine);
802 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
803 vma->vm_end - vma->vm_start, vma->vm_page_prot);
808 #ifdef CONFIG_PPC_MULTIPLATFORM
809 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
811 struct pci_dev *pdev;
812 struct device_node *np;
814 pdev = to_pci_dev (dev);
815 np = pci_device_to_OF_node(pdev);
816 if (np == NULL || np->full_name == NULL)
818 return sprintf(buf, "%s", np->full_name);
820 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
821 #endif /* CONFIG_PPC_MULTIPLATFORM */
823 void pcibios_add_platform_entries(struct pci_dev *pdev)
825 #ifdef CONFIG_PPC_MULTIPLATFORM
826 device_create_file(&pdev->dev, &dev_attr_devspec);
827 #endif /* CONFIG_PPC_MULTIPLATFORM */
830 #ifdef CONFIG_PPC_MULTIPLATFORM
832 #define ISA_SPACE_MASK 0x1
833 #define ISA_SPACE_IO 0x1
835 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
836 unsigned long phb_io_base_phys,
837 void __iomem * phb_io_base_virt)
839 struct isa_range *range;
840 unsigned long pci_addr;
841 unsigned int isa_addr;
845 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
846 if (range == NULL || (rlen < sizeof(struct isa_range))) {
847 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
849 __ioremap_explicit(phb_io_base_phys,
850 (unsigned long)phb_io_base_virt,
851 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
855 /* From "ISA Binding to 1275"
856 * The ranges property is laid out as an array of elements,
857 * each of which comprises:
858 * cells 0 - 1: an ISA address
859 * cells 2 - 4: a PCI address
860 * (size depending on dev->n_addr_cells)
861 * cell 5: the size of the range
863 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
864 isa_addr = range->isa_addr.a_lo;
865 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
866 range->pci_addr.a_lo;
868 /* Assume these are both zero */
869 if ((pci_addr != 0) || (isa_addr != 0)) {
870 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
875 size = PAGE_ALIGN(range->size);
877 __ioremap_explicit(phb_io_base_phys,
878 (unsigned long) phb_io_base_virt,
879 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
883 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
884 struct device_node *dev, int prim)
886 unsigned int *ranges, pci_space;
890 struct resource *res;
891 int np, na = prom_n_addr_cells(dev);
892 unsigned long pci_addr, cpu_phys_addr;
896 /* From "PCI Binding to 1275"
897 * The ranges property is laid out as an array of elements,
898 * each of which comprises:
899 * cells 0 - 2: a PCI address
900 * cells 3 or 3+4: a CPU physical address
901 * (size depending on dev->n_addr_cells)
902 * cells 4+5 or 5+6: the size of the range
905 hose->io_base_phys = 0;
906 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
907 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
909 pci_space = ranges[0];
910 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
912 cpu_phys_addr = ranges[3];
914 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
916 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
921 /* Now consume following elements while they are contiguous */
922 while (rlen >= np * sizeof(unsigned int)) {
923 unsigned long addr, phys;
925 if (ranges[0] != pci_space)
927 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
930 phys = (phys << 32) | ranges[4];
931 if (addr != pci_addr + size ||
932 phys != cpu_phys_addr + size)
935 size += ((unsigned long)ranges[na+3] << 32)
938 rlen -= np * sizeof(unsigned int);
941 switch ((pci_space >> 24) & 0x3) {
942 case 1: /* I/O space */
943 hose->io_base_phys = cpu_phys_addr;
944 hose->pci_io_size = size;
946 res = &hose->io_resource;
947 res->flags = IORESOURCE_IO;
948 res->start = pci_addr;
949 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
950 res->start, res->start + size - 1);
952 case 2: /* memory space */
954 while (memno < 3 && hose->mem_resources[memno].flags)
958 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
960 res = &hose->mem_resources[memno];
961 res->flags = IORESOURCE_MEM;
962 res->start = cpu_phys_addr;
963 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
964 res->start, res->start + size - 1);
969 res->name = dev->full_name;
970 res->end = res->start + size - 1;
978 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
980 unsigned long size = hose->pci_io_size;
981 unsigned long io_virt_offset;
982 struct resource *res;
983 struct device_node *isa_dn;
985 hose->io_base_virt = reserve_phb_iospace(size);
986 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
987 hose->global_number, hose->io_base_phys,
988 (unsigned long) hose->io_base_virt);
991 pci_io_base = (unsigned long)hose->io_base_virt;
992 isa_dn = of_find_node_by_type(NULL, "isa");
994 isa_io_base = pci_io_base;
995 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1003 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1004 res = &hose->io_resource;
1005 res->start += io_virt_offset;
1006 res->end += io_virt_offset;
1009 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1012 unsigned long size = hose->pci_io_size;
1013 unsigned long io_virt_offset;
1014 struct resource *res;
1016 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1017 _PAGE_NO_CACHE | _PAGE_GUARDED);
1018 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1019 hose->global_number, hose->io_base_phys,
1020 (unsigned long) hose->io_base_virt);
1023 pci_io_base = (unsigned long)hose->io_base_virt;
1025 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1026 res = &hose->io_resource;
1027 res->start += io_virt_offset;
1028 res->end += io_virt_offset;
1032 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1033 unsigned long *start_virt, unsigned long *size)
1035 struct pci_controller *hose = pci_bus_to_host(bus);
1036 struct pci_bus_region region;
1037 struct resource *res;
1040 res = bus->resource[0];
1041 pcibios_resource_to_bus(bus->self, ®ion, res);
1042 *start_phys = hose->io_base_phys + region.start;
1043 *start_virt = (unsigned long) hose->io_base_virt +
1045 if (region.end > region.start)
1046 *size = region.end - region.start + 1;
1048 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1049 __FUNCTION__, region.start, region.end);
1055 res = &hose->io_resource;
1056 *start_phys = hose->io_base_phys;
1057 *start_virt = (unsigned long) hose->io_base_virt;
1058 if (res->end > res->start)
1059 *size = res->end - res->start + 1;
1061 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1062 __FUNCTION__, res->start, res->end);
1070 int unmap_bus_range(struct pci_bus *bus)
1072 unsigned long start_phys;
1073 unsigned long start_virt;
1077 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1081 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1083 if (iounmap_explicit((void __iomem *) start_virt, size))
1088 EXPORT_SYMBOL(unmap_bus_range);
1090 int remap_bus_range(struct pci_bus *bus)
1092 unsigned long start_phys;
1093 unsigned long start_virt;
1097 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1102 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1104 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1105 if (__ioremap_explicit(start_phys, start_virt, size,
1106 _PAGE_NO_CACHE | _PAGE_GUARDED))
1111 EXPORT_SYMBOL(remap_bus_range);
1113 void phbs_remap_io(void)
1115 struct pci_controller *hose, *tmp;
1117 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1118 remap_bus_range(hose->bus);
1122 * ppc64 can have multifunction devices that do not respond to function 0.
1123 * In this case we must scan all functions.
1124 * XXX this can go now, we use the OF device tree in all the
1125 * cases that caused problems. -- paulus
1127 int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
1132 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1134 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1135 unsigned long start, end, mask, offset;
1137 if (res->flags & IORESOURCE_IO) {
1138 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1140 start = res->start += offset;
1141 end = res->end += offset;
1143 /* Need to allow IO access to pages that are in the
1145 if (start < MAX_ISA_PORT) {
1146 if (end > MAX_ISA_PORT)
1149 start >>= PAGE_SHIFT;
1152 /* get the range of pages for the map */
1153 mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1);
1154 io_page_mask |= mask;
1156 } else if (res->flags & IORESOURCE_MEM) {
1157 res->start += hose->pci_mem_offset;
1158 res->end += hose->pci_mem_offset;
1162 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1163 struct pci_bus *bus)
1165 /* Update device resources. */
1168 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1169 if (dev->resource[i].flags)
1170 fixup_resource(&dev->resource[i], dev);
1172 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1174 static void __devinit do_bus_setup(struct pci_bus *bus)
1176 struct pci_dev *dev;
1178 ppc_md.iommu_bus_setup(bus);
1180 list_for_each_entry(dev, &bus->devices, bus_list)
1181 ppc_md.iommu_dev_setup(dev);
1183 if (ppc_md.irq_bus_setup)
1184 ppc_md.irq_bus_setup(bus);
1187 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1189 struct pci_dev *dev = bus->self;
1191 if (dev && pci_probe_only &&
1192 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1193 /* This is a subordinate bridge */
1195 pci_read_bridge_bases(bus);
1196 pcibios_fixup_device_resources(dev, bus);
1201 if (!pci_probe_only)
1204 list_for_each_entry(dev, &bus->devices, bus_list)
1205 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1206 pcibios_fixup_device_resources(dev, bus);
1208 EXPORT_SYMBOL(pcibios_fixup_bus);
1211 * Reads the interrupt pin to determine if interrupt is use by card.
1212 * If the interrupt is used, then gets the interrupt line from the
1213 * openfirmware and sets it in the pci_dev and pci_config line.
1215 int pci_read_irq_line(struct pci_dev *pci_dev)
1218 struct device_node *node;
1220 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
1224 node = pci_device_to_OF_node(pci_dev);
1228 if (node->n_intrs == 0)
1231 pci_dev->irq = node->intrs[0].line;
1233 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
1237 EXPORT_SYMBOL(pci_read_irq_line);
1239 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1240 const struct resource *rsrc,
1241 u64 *start, u64 *end)
1243 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1244 unsigned long offset = 0;
1249 if (rsrc->flags & IORESOURCE_IO)
1250 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1253 *start = rsrc->start + offset;
1254 *end = rsrc->end + offset;
1257 #endif /* CONFIG_PPC_MULTIPLATFORM */
1260 #define IOBASE_BRIDGE_NUMBER 0
1261 #define IOBASE_MEMORY 1
1263 #define IOBASE_ISA_IO 3
1264 #define IOBASE_ISA_MEM 4
1266 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1267 unsigned long in_devfn)
1269 struct pci_controller* hose;
1270 struct list_head *ln;
1271 struct pci_bus *bus = NULL;
1272 struct device_node *hose_node;
1274 /* Argh ! Please forgive me for that hack, but that's the
1275 * simplest way to get existing XFree to not lockup on some
1276 * G5 machines... So when something asks for bus 0 io base
1277 * (bus 0 is HT root), we return the AGP one instead.
1279 #ifdef CONFIG_PPC_PMAC
1280 if (systemcfg->platform == PLATFORM_POWERMAC &&
1281 machine_is_compatible("MacRISC4"))
1284 #endif /* CONFIG_PPC_PMAC */
1286 /* That syscall isn't quite compatible with PCI domains, but it's
1287 * used on pre-domains setup. We return the first match
1290 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1291 bus = pci_bus_b(ln);
1292 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1296 if (bus == NULL || bus->sysdata == NULL)
1299 hose_node = (struct device_node *)bus->sysdata;
1300 hose = PCI_DN(hose_node)->phb;
1303 case IOBASE_BRIDGE_NUMBER:
1304 return (long)hose->first_busno;
1306 return (long)hose->pci_mem_offset;
1308 return (long)hose->io_base_phys;
1310 return (long)isa_io_base;
1311 case IOBASE_ISA_MEM: