arch/powerpc/sysdev/cpm1.c

   1 /*
   2  * General Purpose functions for the global management of the
   3  * Communication Processor Module.
   4  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
   5  *
   6  * In addition to the individual control of the communication
   7  * channels, there are a few functions that globally affect the
   8  * communication processor.
   9  *
  10  * Buffer descriptors must be allocated from the dual ported memory
  11  * space.  The allocator for that is here.  When the communication
  12  * process is reset, we reclaim the memory available.  There is
  13  * currently no deallocator for this memory.
  14  * The amount of space available is platform dependent.  On the
  15  * MBX, the EPPC software loads additional microcode into the
  16  * communication processor, and uses some of the DP ram for this
  17  * purpose.  Current, the first 512 bytes and the last 256 bytes of
  18  * memory are used.  Right now I am conservative and only use the
  19  * memory that can never be used for microcode.  If there are
  20  * applications that require more DP ram, we can expand the boundaries
  21  * but then we have to be careful of any downloaded microcode.
  22  */
  23 #include <linux/errno.h>
  24 #include <linux/sched.h>
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/param.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/module.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/slab.h>
  35 #include <asm/page.h>
  36 #include <asm/pgtable.h>
  37 #include <asm/8xx_immap.h>
  38 #include <asm/cpm1.h>
  39 #include <asm/io.h>
  40 #include <asm/tlbflush.h>
  41 #include <asm/rheap.h>
  42 #include <asm/prom.h>
  43 #include <asm/cpm.h>
  44
  45 #include <asm/fs_pd.h>
  46
  47 #ifdef CONFIG_8xx_GPIO
  48 #include <linux/of_gpio.h>
  49 #endif
  50
  51 #define CPM_MAP_SIZE    (0x4000)
  52
  53 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
  54 immap_t __iomem *mpc8xx_immr;
  55 static cpic8xx_t __iomem *cpic_reg;
  56
  57 static struct irq_domain *cpm_pic_host;
  58
  59 static void cpm_mask_irq(struct irq_data *d)
  60 {
  61         unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  62
  63         clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  64 }
  65
  66 static void cpm_unmask_irq(struct irq_data *d)
  67 {
  68         unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  69
  70         setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  71 }
  72
  73 static void cpm_end_irq(struct irq_data *d)
  74 {
  75         unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  76
  77         out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
  78 }
  79
  80 static struct irq_chip cpm_pic = {
  81         .name = "CPM PIC",
  82         .irq_mask = cpm_mask_irq,
  83         .irq_unmask = cpm_unmask_irq,
  84         .irq_eoi = cpm_end_irq,
  85 };
  86
  87 int cpm_get_irq(void)
  88 {
  89         int cpm_vec;
  90
  91         /* Get the vector by setting the ACK bit and then reading
  92          * the register.
  93          */
  94         out_be16(&cpic_reg->cpic_civr, 1);
  95         cpm_vec = in_be16(&cpic_reg->cpic_civr);
  96         cpm_vec >>= 11;
  97
  98         return irq_linear_revmap(cpm_pic_host, cpm_vec);
  99 }
 100
 101 static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
 102                           irq_hw_number_t hw)
 103 {
 104         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
 105
 106         irq_set_status_flags(virq, IRQ_LEVEL);
 107         irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
 108         return 0;
 109 }
 110
 111 /* The CPM can generate the error interrupt when there is a race condition
 112  * between generating and masking interrupts.  All we have to do is ACK it
 113  * and return.  This is a no-op function so we don't need any special
 114  * tests in the interrupt handler.
 115  */
 116 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
 117 {
 118         return IRQ_HANDLED;
 119 }
 120
 121 static struct irqaction cpm_error_irqaction = {
 122         .handler = cpm_error_interrupt,
 123         .flags = IRQF_NO_THREAD,
 124         .name = "error",
 125 };
 126
 127 static const struct irq_domain_ops cpm_pic_host_ops = {
 128         .map = cpm_pic_host_map,
 129 };
 130
 131 unsigned int cpm_pic_init(void)
 132 {
 133         struct device_node *np = NULL;
 134         struct resource res;
 135         unsigned int sirq = 0, hwirq, eirq;
 136         int ret;
 137
 138         pr_debug("cpm_pic_init\n");
 139
 140         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
 141         if (np == NULL)
 142                 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
 143         if (np == NULL) {
 144                 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
 145                 return sirq;
 146         }
 147
 148         ret = of_address_to_resource(np, 0, &res);
 149         if (ret)
 150                 goto end;
 151
 152         cpic_reg = ioremap(res.start, resource_size(&res));
 153         if (cpic_reg == NULL)
 154                 goto end;
 155
 156         sirq = irq_of_parse_and_map(np, 0);
 157         if (!sirq)
 158                 goto end;
 159
 160         /* Initialize the CPM interrupt controller. */
 161         hwirq = (unsigned int)virq_to_hw(sirq);
 162         out_be32(&cpic_reg->cpic_cicr,
 163             (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
 164                 ((hwirq/2) << 13) | CICR_HP_MASK);
 165
 166         out_be32(&cpic_reg->cpic_cimr, 0);
 167
 168         cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
 169         if (cpm_pic_host == NULL) {
 170                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
 171                 sirq = 0;
 172                 goto end;
 173         }
 174
 175         /* Install our own error handler. */
 176         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
 177         if (np == NULL)
 178                 np = of_find_node_by_type(NULL, "cpm");
 179         if (np == NULL) {
 180                 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
 181                 goto end;
 182         }
 183
 184         eirq = irq_of_parse_and_map(np, 0);
 185         if (!eirq)
 186                 goto end;
 187
 188         if (setup_irq(eirq, &cpm_error_irqaction))
 189                 printk(KERN_ERR "Could not allocate CPM error IRQ!");
 190
 191         setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
 192
 193 end:
 194         of_node_put(np);
 195         return sirq;
 196 }
 197
 198 void __init cpm_reset(void)
 199 {
 200         sysconf8xx_t __iomem *siu_conf;
 201
 202         mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
 203         if (!mpc8xx_immr) {
 204                 printk(KERN_CRIT "Could not map IMMR\n");
 205                 return;
 206         }
 207
 208         cpmp = &mpc8xx_immr->im_cpm;
 209
 210 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
 211         /* Perform a reset.
 212         */
 213         out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
 214
 215         /* Wait for it.
 216         */
 217         while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
 218 #endif
 219
 220 #ifdef CONFIG_UCODE_PATCH
 221         cpm_load_patch(cpmp);
 222 #endif
 223
 224         /* Set SDMA Bus Request priority 5.
 225          * On 860T, this also enables FEC priority 6.  I am not sure
 226          * this is what we really want for some applications, but the
 227          * manual recommends it.
 228          * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 229          */
 230         siu_conf = immr_map(im_siu_conf);
 231         if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
 232                 out_be32(&siu_conf->sc_sdcr, 0x40);
 233         else
 234                 out_be32(&siu_conf->sc_sdcr, 1);
 235         immr_unmap(siu_conf);
 236 }
 237
 238 static DEFINE_SPINLOCK(cmd_lock);
 239
 240 #define MAX_CR_CMD_LOOPS        10000
 241
 242 int cpm_command(u32 command, u8 opcode)
 243 {
 244         int i, ret;
 245         unsigned long flags;
 246
 247         if (command & 0xffffff0f)
 248                 return -EINVAL;
 249
 250         spin_lock_irqsave(&cmd_lock, flags);
 251
 252         ret = 0;
 253         out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
 254         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
 255                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
 256                         goto out;
 257
 258         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
 259         ret = -EIO;
 260 out:
 261         spin_unlock_irqrestore(&cmd_lock, flags);
 262         return ret;
 263 }
 264 EXPORT_SYMBOL(cpm_command);
 265
 266 /* Set a baud rate generator.  This needs lots of work.  There are
 267  * four BRGs, any of which can be wired to any channel.
 268  * The internal baud rate clock is the system clock divided by 16.
 269  * This assumes the baudrate is 16x oversampled by the uart.
 270  */
 271 #define BRG_INT_CLK             (get_brgfreq())
 272 #define BRG_UART_CLK            (BRG_INT_CLK/16)
 273 #define BRG_UART_CLK_DIV16      (BRG_UART_CLK/16)
 274
 275 void
 276 cpm_setbrg(uint brg, uint rate)
 277 {
 278         u32 __iomem *bp;
 279
 280         /* This is good enough to get SMCs running.....
 281         */
 282         bp = &cpmp->cp_brgc1;
 283         bp += brg;
 284         /* The BRG has a 12-bit counter.  For really slow baud rates (or
 285          * really fast processors), we may have to further divide by 16.
 286          */
 287         if (((BRG_UART_CLK / rate) - 1) < 4096)
 288                 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 289         else
 290                 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
 291                               CPM_BRG_EN | CPM_BRG_DIV16);
 292 }
 293
 294 struct cpm_ioport16 {
 295         __be16 dir, par, odr_sor, dat, intr;
 296         __be16 res[3];
 297 };
 298
 299 struct cpm_ioport32b {
 300         __be32 dir, par, odr, dat;
 301 };
 302
 303 struct cpm_ioport32e {
 304         __be32 dir, par, sor, odr, dat;
 305 };
 306
 307 static void cpm1_set_pin32(int port, int pin, int flags)
 308 {
 309         struct cpm_ioport32e __iomem *iop;
 310         pin = 1 << (31 - pin);
 311
 312         if (port == CPM_PORTB)
 313                 iop = (struct cpm_ioport32e __iomem *)
 314                       &mpc8xx_immr->im_cpm.cp_pbdir;
 315         else
 316                 iop = (struct cpm_ioport32e __iomem *)
 317                       &mpc8xx_immr->im_cpm.cp_pedir;
 318
 319         if (flags & CPM_PIN_OUTPUT)
 320                 setbits32(&iop->dir, pin);
 321         else
 322                 clrbits32(&iop->dir, pin);
 323
 324         if (!(flags & CPM_PIN_GPIO))
 325                 setbits32(&iop->par, pin);
 326         else
 327                 clrbits32(&iop->par, pin);
 328
 329         if (port == CPM_PORTB) {
 330                 if (flags & CPM_PIN_OPENDRAIN)
 331                         setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 332                 else
 333                         clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 334         }
 335
 336         if (port == CPM_PORTE) {
 337                 if (flags & CPM_PIN_SECONDARY)
 338                         setbits32(&iop->sor, pin);
 339                 else
 340                         clrbits32(&iop->sor, pin);
 341
 342                 if (flags & CPM_PIN_OPENDRAIN)
 343                         setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 344                 else
 345                         clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 346         }
 347 }
 348
 349 static void cpm1_set_pin16(int port, int pin, int flags)
 350 {
 351         struct cpm_ioport16 __iomem *iop =
 352                 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
 353
 354         pin = 1 << (15 - pin);
 355
 356         if (port != 0)
 357                 iop += port - 1;
 358
 359         if (flags & CPM_PIN_OUTPUT)
 360                 setbits16(&iop->dir, pin);
 361         else
 362                 clrbits16(&iop->dir, pin);
 363
 364         if (!(flags & CPM_PIN_GPIO))
 365                 setbits16(&iop->par, pin);
 366         else
 367                 clrbits16(&iop->par, pin);
 368
 369         if (port == CPM_PORTA) {
 370                 if (flags & CPM_PIN_OPENDRAIN)
 371                         setbits16(&iop->odr_sor, pin);
 372                 else
 373                         clrbits16(&iop->odr_sor, pin);
 374         }
 375         if (port == CPM_PORTC) {
 376                 if (flags & CPM_PIN_SECONDARY)
 377                         setbits16(&iop->odr_sor, pin);
 378                 else
 379                         clrbits16(&iop->odr_sor, pin);
 380                 if (flags & CPM_PIN_FALLEDGE)
 381                         setbits16(&iop->intr, pin);
 382                 else
 383                         clrbits16(&iop->intr, pin);
 384         }
 385 }
 386
 387 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
 388 {
 389         if (port == CPM_PORTB || port == CPM_PORTE)
 390                 cpm1_set_pin32(port, pin, flags);
 391         else
 392                 cpm1_set_pin16(port, pin, flags);
 393 }
 394
 395 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 396 {
 397         int shift;
 398         int i, bits = 0;
 399         u32 __iomem *reg;
 400         u32 mask = 7;
 401
 402         u8 clk_map[][3] = {
 403                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 404                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 405                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 406                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 407                 {CPM_CLK_SCC1, CPM_CLK1, 4},
 408                 {CPM_CLK_SCC1, CPM_CLK2, 5},
 409                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 410                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 411
 412                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 413                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 414                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 415                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 416                 {CPM_CLK_SCC2, CPM_CLK1, 4},
 417                 {CPM_CLK_SCC2, CPM_CLK2, 5},
 418                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 419                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 420
 421                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 422                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 423                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 424                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 425                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 426                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 427                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 428                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 429
 430                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 431                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 432                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 433                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 434                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 435                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 436                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 437                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 438
 439                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 440                 {CPM_CLK_SMC1, CPM_BRG2, 1},
 441                 {CPM_CLK_SMC1, CPM_BRG3, 2},
 442                 {CPM_CLK_SMC1, CPM_BRG4, 3},
 443                 {CPM_CLK_SMC1, CPM_CLK1, 4},
 444                 {CPM_CLK_SMC1, CPM_CLK2, 5},
 445                 {CPM_CLK_SMC1, CPM_CLK3, 6},
 446                 {CPM_CLK_SMC1, CPM_CLK4, 7},
 447
 448                 {CPM_CLK_SMC2, CPM_BRG1, 0},
 449                 {CPM_CLK_SMC2, CPM_BRG2, 1},
 450                 {CPM_CLK_SMC2, CPM_BRG3, 2},
 451                 {CPM_CLK_SMC2, CPM_BRG4, 3},
 452                 {CPM_CLK_SMC2, CPM_CLK5, 4},
 453                 {CPM_CLK_SMC2, CPM_CLK6, 5},
 454                 {CPM_CLK_SMC2, CPM_CLK7, 6},
 455                 {CPM_CLK_SMC2, CPM_CLK8, 7},
 456         };
 457
 458         switch (target) {
 459         case CPM_CLK_SCC1:
 460                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 461                 shift = 0;
 462                 break;
 463
 464         case CPM_CLK_SCC2:
 465                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 466                 shift = 8;
 467                 break;
 468
 469         case CPM_CLK_SCC3:
 470                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 471                 shift = 16;
 472                 break;
 473
 474         case CPM_CLK_SCC4:
 475                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 476                 shift = 24;
 477                 break;
 478
 479         case CPM_CLK_SMC1:
 480                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 481                 shift = 12;
 482                 break;
 483
 484         case CPM_CLK_SMC2:
 485                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 486                 shift = 28;
 487                 break;
 488
 489         default:
 490                 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
 491                 return -EINVAL;
 492         }
 493
 494         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 495                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 496                         bits = clk_map[i][2];
 497                         break;
 498                 }
 499         }
 500
 501         if (i == ARRAY_SIZE(clk_map)) {
 502                 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
 503                 return -EINVAL;
 504         }
 505
 506         bits <<= shift;
 507         mask <<= shift;
 508
 509         if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
 510                 if (mode == CPM_CLK_RTX) {
 511                         bits |= bits << 3;
 512                         mask |= mask << 3;
 513                 } else if (mode == CPM_CLK_RX) {
 514                         bits <<= 3;
 515                         mask <<= 3;
 516                 }
 517         }
 518
 519         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 520
 521         return 0;
 522 }
 523
 524 /*
 525  * GPIO LIB API implementation
 526  */
 527 #ifdef CONFIG_8xx_GPIO
 528
 529 struct cpm1_gpio16_chip {
 530         struct of_mm_gpio_chip mm_gc;
 531         spinlock_t lock;
 532
 533         /* shadowed data register to clear/set bits safely */
 534         u16 cpdata;
 535
 536         /* IRQ associated with Pins when relevant */
 537         int irq[16];
 538 };
 539
 540 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
 541 {
 542         struct cpm1_gpio16_chip *cpm1_gc =
 543                 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
 544         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 545
 546         cpm1_gc->cpdata = in_be16(&iop->dat);
 547 }
 548
 549 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
 550 {
 551         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 552         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 553         u16 pin_mask;
 554
 555         pin_mask = 1 << (15 - gpio);
 556
 557         return !!(in_be16(&iop->dat) & pin_mask);
 558 }
 559
 560 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
 561         int value)
 562 {
 563         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 564         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 565
 566         if (value)
 567                 cpm1_gc->cpdata |= pin_mask;
 568         else
 569                 cpm1_gc->cpdata &= ~pin_mask;
 570
 571         out_be16(&iop->dat, cpm1_gc->cpdata);
 572 }
 573
 574 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
 575 {
 576         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 577         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 578         unsigned long flags;
 579         u16 pin_mask = 1 << (15 - gpio);
 580
 581         spin_lock_irqsave(&cpm1_gc->lock, flags);
 582
 583         __cpm1_gpio16_set(mm_gc, pin_mask, value);
 584
 585         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 586 }
 587
 588 static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
 589 {
 590         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 591         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 592
 593         return cpm1_gc->irq[gpio] ? : -ENXIO;
 594 }
 595
 596 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 597 {
 598         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 599         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 600         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 601         unsigned long flags;
 602         u16 pin_mask = 1 << (15 - gpio);
 603
 604         spin_lock_irqsave(&cpm1_gc->lock, flags);
 605
 606         setbits16(&iop->dir, pin_mask);
 607         __cpm1_gpio16_set(mm_gc, pin_mask, val);
 608
 609         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 610
 611         return 0;
 612 }
 613
 614 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
 615 {
 616         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 617         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 618         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 619         unsigned long flags;
 620         u16 pin_mask = 1 << (15 - gpio);
 621
 622         spin_lock_irqsave(&cpm1_gc->lock, flags);
 623
 624         clrbits16(&iop->dir, pin_mask);
 625
 626         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 627
 628         return 0;
 629 }
 630
 631 int cpm1_gpiochip_add16(struct device_node *np)
 632 {
 633         struct cpm1_gpio16_chip *cpm1_gc;
 634         struct of_mm_gpio_chip *mm_gc;
 635         struct gpio_chip *gc;
 636         u16 mask;
 637
 638         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
 639         if (!cpm1_gc)
 640                 return -ENOMEM;
 641
 642         spin_lock_init(&cpm1_gc->lock);
 643
 644         if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
 645                 int i, j;
 646
 647                 for (i = 0, j = 0; i < 16; i++)
 648                         if (mask & (1 << (15 - i)))
 649                                 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
 650         }
 651
 652         mm_gc = &cpm1_gc->mm_gc;
 653         gc = &mm_gc->gc;
 654
 655         mm_gc->save_regs = cpm1_gpio16_save_regs;
 656         gc->ngpio = 16;
 657         gc->direction_input = cpm1_gpio16_dir_in;
 658         gc->direction_output = cpm1_gpio16_dir_out;
 659         gc->get = cpm1_gpio16_get;
 660         gc->set = cpm1_gpio16_set;
 661         gc->to_irq = cpm1_gpio16_to_irq;
 662
 663         return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
 664 }
 665
 666 struct cpm1_gpio32_chip {
 667         struct of_mm_gpio_chip mm_gc;
 668         spinlock_t lock;
 669
 670         /* shadowed data register to clear/set bits safely */
 671         u32 cpdata;
 672 };
 673
 674 static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
 675 {
 676         struct cpm1_gpio32_chip *cpm1_gc =
 677                 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
 678         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 679
 680         cpm1_gc->cpdata = in_be32(&iop->dat);
 681 }
 682
 683 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
 684 {
 685         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 686         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 687         u32 pin_mask;
 688
 689         pin_mask = 1 << (31 - gpio);
 690
 691         return !!(in_be32(&iop->dat) & pin_mask);
 692 }
 693
 694 static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
 695         int value)
 696 {
 697         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 698         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 699
 700         if (value)
 701                 cpm1_gc->cpdata |= pin_mask;
 702         else
 703                 cpm1_gc->cpdata &= ~pin_mask;
 704
 705         out_be32(&iop->dat, cpm1_gc->cpdata);
 706 }
 707
 708 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
 709 {
 710         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 711         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 712         unsigned long flags;
 713         u32 pin_mask = 1 << (31 - gpio);
 714
 715         spin_lock_irqsave(&cpm1_gc->lock, flags);
 716
 717         __cpm1_gpio32_set(mm_gc, pin_mask, value);
 718
 719         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 720 }
 721
 722 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 723 {
 724         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 725         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 726         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 727         unsigned long flags;
 728         u32 pin_mask = 1 << (31 - gpio);
 729
 730         spin_lock_irqsave(&cpm1_gc->lock, flags);
 731
 732         setbits32(&iop->dir, pin_mask);
 733         __cpm1_gpio32_set(mm_gc, pin_mask, val);
 734
 735         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 736
 737         return 0;
 738 }
 739
 740 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
 741 {
 742         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 743         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 744         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 745         unsigned long flags;
 746         u32 pin_mask = 1 << (31 - gpio);
 747
 748         spin_lock_irqsave(&cpm1_gc->lock, flags);
 749
 750         clrbits32(&iop->dir, pin_mask);
 751
 752         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 753
 754         return 0;
 755 }
 756
 757 int cpm1_gpiochip_add32(struct device_node *np)
 758 {
 759         struct cpm1_gpio32_chip *cpm1_gc;
 760         struct of_mm_gpio_chip *mm_gc;
 761         struct gpio_chip *gc;
 762
 763         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
 764         if (!cpm1_gc)
 765                 return -ENOMEM;
 766
 767         spin_lock_init(&cpm1_gc->lock);
 768
 769         mm_gc = &cpm1_gc->mm_gc;
 770         gc = &mm_gc->gc;
 771
 772         mm_gc->save_regs = cpm1_gpio32_save_regs;
 773         gc->ngpio = 32;
 774         gc->direction_input = cpm1_gpio32_dir_in;
 775         gc->direction_output = cpm1_gpio32_dir_out;
 776         gc->get = cpm1_gpio32_get;
 777         gc->set = cpm1_gpio32_set;
 778
 779         return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
 780 }
 781
 782 static int cpm_init_par_io(void)
 783 {
 784         struct device_node *np;
 785
 786         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a")
 787                 cpm1_gpiochip_add16(np);
 788
 789         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b")
 790                 cpm1_gpiochip_add32(np);
 791
 792         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c")
 793                 cpm1_gpiochip_add16(np);
 794
 795         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d")
 796                 cpm1_gpiochip_add16(np);
 797
 798         /* Port E uses CPM2 layout */
 799         for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e")
 800                 cpm2_gpiochip_add32(np);
 801         return 0;
 802 }
 803 arch_initcall(cpm_init_par_io);
 804
 805 #endif /* CONFIG_8xx_GPIO */