arch/powerpc/platforms/pseries/iommu.c

   1 /*
   2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   3  *
   4  * Rewrite, cleanup:
   5  *
   6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
   8  *
   9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/types.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31 #include <linux/memblock.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/sched.h>        /* for show_stack */
  34 #include <linux/string.h>
  35 #include <linux/pci.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/crash_dump.h>
  38 #include <linux/memory.h>
  39 #include <linux/of.h>
  40 #include <asm/io.h>
  41 #include <asm/prom.h>
  42 #include <asm/rtas.h>
  43 #include <asm/iommu.h>
  44 #include <asm/pci-bridge.h>
  45 #include <asm/machdep.h>
  46 #include <asm/firmware.h>
  47 #include <asm/tce.h>
  48 #include <asm/ppc-pci.h>
  49 #include <asm/udbg.h>
  50 #include <asm/mmzone.h>
  51 #include <asm/plpar_wrappers.h>
  52
  53
  54 static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
  55                                       __be64 *startp, __be64 *endp)
  56 {
  57         u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
  58         unsigned long start, end, inc;
  59
  60         start = __pa(startp);
  61         end = __pa(endp);
  62         inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
  63
  64         /* If this is non-zero, change the format.  We shift the
  65          * address and or in the magic from the device tree. */
  66         if (tbl->it_busno) {
  67                 start <<= 12;
  68                 end <<= 12;
  69                 inc <<= 12;
  70                 start |= tbl->it_busno;
  71                 end |= tbl->it_busno;
  72         }
  73
  74         end |= inc - 1; /* round up end to be different than start */
  75
  76         mb(); /* Make sure TCEs in memory are written */
  77         while (start <= end) {
  78                 out_be64(invalidate, start);
  79                 start += inc;
  80         }
  81 }
  82
  83 static int tce_build_pSeries(struct iommu_table *tbl, long index,
  84                               long npages, unsigned long uaddr,
  85                               enum dma_data_direction direction,
  86                               struct dma_attrs *attrs)
  87 {
  88         u64 proto_tce;
  89         __be64 *tcep, *tces;
  90         u64 rpn;
  91
  92         proto_tce = TCE_PCI_READ; // Read allowed
  93
  94         if (direction != DMA_TO_DEVICE)
  95                 proto_tce |= TCE_PCI_WRITE;
  96
  97         tces = tcep = ((__be64 *)tbl->it_base) + index;
  98
  99         while (npages--) {
 100                 /* can't move this out since we might cross MEMBLOCK boundary */
 101                 rpn = __pa(uaddr) >> TCE_SHIFT;
 102                 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 103
 104                 uaddr += TCE_PAGE_SIZE;
 105                 tcep++;
 106         }
 107
 108         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
 109                 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
 110         return 0;
 111 }
 112
 113
 114 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
 115 {
 116         __be64 *tcep, *tces;
 117
 118         tces = tcep = ((__be64 *)tbl->it_base) + index;
 119
 120         while (npages--)
 121                 *(tcep++) = 0;
 122
 123         if (tbl->it_type & TCE_PCI_SWINV_FREE)
 124                 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
 125 }
 126
 127 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
 128 {
 129         __be64 *tcep;
 130
 131         tcep = ((__be64 *)tbl->it_base) + index;
 132
 133         return be64_to_cpu(*tcep);
 134 }
 135
 136 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
 137 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
 138
 139 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
 140                                 long npages, unsigned long uaddr,
 141                                 enum dma_data_direction direction,
 142                                 struct dma_attrs *attrs)
 143 {
 144         u64 rc = 0;
 145         u64 proto_tce, tce;
 146         u64 rpn;
 147         int ret = 0;
 148         long tcenum_start = tcenum, npages_start = npages;
 149
 150         rpn = __pa(uaddr) >> TCE_SHIFT;
 151         proto_tce = TCE_PCI_READ;
 152         if (direction != DMA_TO_DEVICE)
 153                 proto_tce |= TCE_PCI_WRITE;
 154
 155         while (npages--) {
 156                 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 157                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
 158
 159                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 160                         ret = (int)rc;
 161                         tce_free_pSeriesLP(tbl, tcenum_start,
 162                                            (npages_start - (npages + 1)));
 163                         break;
 164                 }
 165
 166                 if (rc && printk_ratelimit()) {
 167                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 168                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 169                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 170                         printk("\ttce val = 0x%llx\n", tce );
 171                         show_stack(current, (unsigned long *)__get_SP());
 172                 }
 173
 174                 tcenum++;
 175                 rpn++;
 176         }
 177         return ret;
 178 }
 179
 180 static DEFINE_PER_CPU(__be64 *, tce_page);
 181
 182 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 183                                      long npages, unsigned long uaddr,
 184                                      enum dma_data_direction direction,
 185                                      struct dma_attrs *attrs)
 186 {
 187         u64 rc = 0;
 188         u64 proto_tce;
 189         __be64 *tcep;
 190         u64 rpn;
 191         long l, limit;
 192         long tcenum_start = tcenum, npages_start = npages;
 193         int ret = 0;
 194         unsigned long flags;
 195
 196         if (npages == 1) {
 197                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 198                                            direction, attrs);
 199         }
 200
 201         local_irq_save(flags);  /* to protect tcep and the page behind it */
 202
 203         tcep = __get_cpu_var(tce_page);
 204
 205         /* This is safe to do since interrupts are off when we're called
 206          * from iommu_alloc{,_sg}()
 207          */
 208         if (!tcep) {
 209                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 210                 /* If allocation fails, fall back to the loop implementation */
 211                 if (!tcep) {
 212                         local_irq_restore(flags);
 213                         return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 214                                             direction, attrs);
 215                 }
 216                 __get_cpu_var(tce_page) = tcep;
 217         }
 218
 219         rpn = __pa(uaddr) >> TCE_SHIFT;
 220         proto_tce = TCE_PCI_READ;
 221         if (direction != DMA_TO_DEVICE)
 222                 proto_tce |= TCE_PCI_WRITE;
 223
 224         /* We can map max one pageful of TCEs at a time */
 225         do {
 226                 /*
 227                  * Set up the page with TCE data, looping through and setting
 228                  * the values.
 229                  */
 230                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
 231
 232                 for (l = 0; l < limit; l++) {
 233                         tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 234                         rpn++;
 235                 }
 236
 237                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 238                                             (u64)tcenum << 12,
 239                                             (u64)__pa(tcep),
 240                                             limit);
 241
 242                 npages -= limit;
 243                 tcenum += limit;
 244         } while (npages > 0 && !rc);
 245
 246         local_irq_restore(flags);
 247
 248         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 249                 ret = (int)rc;
 250                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
 251                                         (npages_start - (npages + limit)));
 252                 return ret;
 253         }
 254
 255         if (rc && printk_ratelimit()) {
 256                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 257                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 258                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 259                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
 260                 show_stack(current, (unsigned long *)__get_SP());
 261         }
 262         return ret;
 263 }
 264
 265 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 266 {
 267         u64 rc;
 268
 269         while (npages--) {
 270                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
 271
 272                 if (rc && printk_ratelimit()) {
 273                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 274                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 275                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 276                         show_stack(current, (unsigned long *)__get_SP());
 277                 }
 278
 279                 tcenum++;
 280         }
 281 }
 282
 283
 284 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 285 {
 286         u64 rc;
 287
 288         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
 289
 290         if (rc && printk_ratelimit()) {
 291                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 292                 printk("\trc      = %lld\n", rc);
 293                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 294                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 295                 show_stack(current, (unsigned long *)__get_SP());
 296         }
 297 }
 298
 299 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
 300 {
 301         u64 rc;
 302         unsigned long tce_ret;
 303
 304         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
 305
 306         if (rc && printk_ratelimit()) {
 307                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
 308                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 309                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 310                 show_stack(current, (unsigned long *)__get_SP());
 311         }
 312
 313         return tce_ret;
 314 }
 315
 316 /* this is compatible with cells for the device tree property */
 317 struct dynamic_dma_window_prop {
 318         __be32  liobn;          /* tce table number */
 319         __be64  dma_base;       /* address hi,lo */
 320         __be32  tce_shift;      /* ilog2(tce_page_size) */
 321         __be32  window_shift;   /* ilog2(tce_window_size) */
 322 };
 323
 324 struct direct_window {
 325         struct device_node *device;
 326         const struct dynamic_dma_window_prop *prop;
 327         struct list_head list;
 328 };
 329
 330 /* Dynamic DMA Window support */
 331 struct ddw_query_response {
 332         u32 windows_available;
 333         u32 largest_available_block;
 334         u32 page_size;
 335         u32 migration_capable;
 336 };
 337
 338 struct ddw_create_response {
 339         u32 liobn;
 340         u32 addr_hi;
 341         u32 addr_lo;
 342 };
 343
 344 static LIST_HEAD(direct_window_list);
 345 /* prevents races between memory on/offline and window creation */
 346 static DEFINE_SPINLOCK(direct_window_list_lock);
 347 /* protects initializing window twice for same device */
 348 static DEFINE_MUTEX(direct_window_init_mutex);
 349 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
 350
 351 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
 352                                         unsigned long num_pfn, const void *arg)
 353 {
 354         const struct dynamic_dma_window_prop *maprange = arg;
 355         int rc;
 356         u64 tce_size, num_tce, dma_offset, next;
 357         u32 tce_shift;
 358         long limit;
 359
 360         tce_shift = be32_to_cpu(maprange->tce_shift);
 361         tce_size = 1ULL << tce_shift;
 362         next = start_pfn << PAGE_SHIFT;
 363         num_tce = num_pfn << PAGE_SHIFT;
 364
 365         /* round back to the beginning of the tce page size */
 366         num_tce += next & (tce_size - 1);
 367         next &= ~(tce_size - 1);
 368
 369         /* covert to number of tces */
 370         num_tce |= tce_size - 1;
 371         num_tce >>= tce_shift;
 372
 373         do {
 374                 /*
 375                  * Set up the page with TCE data, looping through and setting
 376                  * the values.
 377                  */
 378                 limit = min_t(long, num_tce, 512);
 379                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 380
 381                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
 382                                              dma_offset,
 383                                              0, limit);
 384                 next += limit * tce_size;
 385                 num_tce -= limit;
 386         } while (num_tce > 0 && !rc);
 387
 388         return rc;
 389 }
 390
 391 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 392                                         unsigned long num_pfn, const void *arg)
 393 {
 394         const struct dynamic_dma_window_prop *maprange = arg;
 395         u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
 396         __be64 *tcep;
 397         u32 tce_shift;
 398         u64 rc = 0;
 399         long l, limit;
 400
 401         local_irq_disable();    /* to protect tcep and the page behind it */
 402         tcep = __get_cpu_var(tce_page);
 403
 404         if (!tcep) {
 405                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 406                 if (!tcep) {
 407                         local_irq_enable();
 408                         return -ENOMEM;
 409                 }
 410                 __get_cpu_var(tce_page) = tcep;
 411         }
 412
 413         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
 414
 415         liobn = (u64)be32_to_cpu(maprange->liobn);
 416         tce_shift = be32_to_cpu(maprange->tce_shift);
 417         tce_size = 1ULL << tce_shift;
 418         next = start_pfn << PAGE_SHIFT;
 419         num_tce = num_pfn << PAGE_SHIFT;
 420
 421         /* round back to the beginning of the tce page size */
 422         num_tce += next & (tce_size - 1);
 423         next &= ~(tce_size - 1);
 424
 425         /* covert to number of tces */
 426         num_tce |= tce_size - 1;
 427         num_tce >>= tce_shift;
 428
 429         /* We can map max one pageful of TCEs at a time */
 430         do {
 431                 /*
 432                  * Set up the page with TCE data, looping through and setting
 433                  * the values.
 434                  */
 435                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
 436                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 437
 438                 for (l = 0; l < limit; l++) {
 439                         tcep[l] = cpu_to_be64(proto_tce | next);
 440                         next += tce_size;
 441                 }
 442
 443                 rc = plpar_tce_put_indirect(liobn,
 444                                             dma_offset,
 445                                             (u64)__pa(tcep),
 446                                             limit);
 447
 448                 num_tce -= limit;
 449         } while (num_tce > 0 && !rc);
 450
 451         /* error cleanup: caller will clear whole range */
 452
 453         local_irq_enable();
 454         return rc;
 455 }
 456
 457 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
 458                 unsigned long num_pfn, void *arg)
 459 {
 460         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
 461 }
 462
 463
 464 #ifdef CONFIG_PCI
 465 static void iommu_table_setparms(struct pci_controller *phb,
 466                                  struct device_node *dn,
 467                                  struct iommu_table *tbl)
 468 {
 469         struct device_node *node;
 470         const unsigned long *basep, *sw_inval;
 471         const u32 *sizep;
 472
 473         node = phb->dn;
 474
 475         basep = of_get_property(node, "linux,tce-base", NULL);
 476         sizep = of_get_property(node, "linux,tce-size", NULL);
 477         if (basep == NULL || sizep == NULL) {
 478                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
 479                                 "missing tce entries !\n", dn->full_name);
 480                 return;
 481         }
 482
 483         tbl->it_base = (unsigned long)__va(*basep);
 484
 485         if (!is_kdump_kernel())
 486                 memset((void *)tbl->it_base, 0, *sizep);
 487
 488         tbl->it_busno = phb->bus->number;
 489         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 490
 491         /* Units of tce entries */
 492         tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
 493
 494         /* Test if we are going over 2GB of DMA space */
 495         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
 496                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 497                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 498         }
 499
 500         phb->dma_window_base_cur += phb->dma_window_size;
 501
 502         /* Set the tce table size - measured in entries */
 503         tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
 504
 505         tbl->it_index = 0;
 506         tbl->it_blocksize = 16;
 507         tbl->it_type = TCE_PCI;
 508
 509         sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
 510         if (sw_inval) {
 511                 /*
 512                  * This property contains information on how to
 513                  * invalidate the TCE entry.  The first property is
 514                  * the base MMIO address used to invalidate entries.
 515                  * The second property tells us the format of the TCE
 516                  * invalidate (whether it needs to be shifted) and
 517                  * some magic routing info to add to our invalidate
 518                  * command.
 519                  */
 520                 tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
 521                 tbl->it_busno = sw_inval[1]; /* overload this with magic */
 522                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 523         }
 524 }
 525
 526 /*
 527  * iommu_table_setparms_lpar
 528  *
 529  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 530  */
 531 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 532                                       struct device_node *dn,
 533                                       struct iommu_table *tbl,
 534                                       const __be32 *dma_window)
 535 {
 536         unsigned long offset, size;
 537
 538         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 539
 540         tbl->it_busno = phb->bus->number;
 541         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 542         tbl->it_base   = 0;
 543         tbl->it_blocksize  = 16;
 544         tbl->it_type = TCE_PCI;
 545         tbl->it_offset = offset >> tbl->it_page_shift;
 546         tbl->it_size = size >> tbl->it_page_shift;
 547 }
 548
 549 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 550 {
 551         struct device_node *dn;
 552         struct iommu_table *tbl;
 553         struct device_node *isa_dn, *isa_dn_orig;
 554         struct device_node *tmp;
 555         struct pci_dn *pci;
 556         int children;
 557
 558         dn = pci_bus_to_OF_node(bus);
 559
 560         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
 561
 562         if (bus->self) {
 563                 /* This is not a root bus, any setup will be done for the
 564                  * device-side of the bridge in iommu_dev_setup_pSeries().
 565                  */
 566                 return;
 567         }
 568         pci = PCI_DN(dn);
 569
 570         /* Check if the ISA bus on the system is under
 571          * this PHB.
 572          */
 573         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
 574
 575         while (isa_dn && isa_dn != dn)
 576                 isa_dn = isa_dn->parent;
 577
 578         if (isa_dn_orig)
 579                 of_node_put(isa_dn_orig);
 580
 581         /* Count number of direct PCI children of the PHB. */
 582         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
 583                 children++;
 584
 585         pr_debug("Children: %d\n", children);
 586
 587         /* Calculate amount of DMA window per slot. Each window must be
 588          * a power of two (due to pci_alloc_consistent requirements).
 589          *
 590          * Keep 256MB aside for PHBs with ISA.
 591          */
 592
 593         if (!isa_dn) {
 594                 /* No ISA/IDE - just set window size and return */
 595                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
 596
 597                 while (pci->phb->dma_window_size * children > 0x80000000ul)
 598                         pci->phb->dma_window_size >>= 1;
 599                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
 600                          pci->phb->dma_window_size);
 601                 pci->phb->dma_window_base_cur = 0;
 602
 603                 return;
 604         }
 605
 606         /* If we have ISA, then we probably have an IDE
 607          * controller too. Allocate a 128MB table but
 608          * skip the first 128MB to avoid stepping on ISA
 609          * space.
 610          */
 611         pci->phb->dma_window_size = 0x8000000ul;
 612         pci->phb->dma_window_base_cur = 0x8000000ul;
 613
 614         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
 615                            pci->phb->node);
 616
 617         iommu_table_setparms(pci->phb, dn, tbl);
 618         pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
 619         iommu_register_group(tbl, pci_domain_nr(bus), 0);
 620
 621         /* Divide the rest (1.75GB) among the children */
 622         pci->phb->dma_window_size = 0x80000000ul;
 623         while (pci->phb->dma_window_size * children > 0x70000000ul)
 624                 pci->phb->dma_window_size >>= 1;
 625
 626         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 627 }
 628
 629
 630 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
 631 {
 632         struct iommu_table *tbl;
 633         struct device_node *dn, *pdn;
 634         struct pci_dn *ppci;
 635         const __be32 *dma_window = NULL;
 636
 637         dn = pci_bus_to_OF_node(bus);
 638
 639         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
 640                  dn->full_name);
 641
 642         /* Find nearest ibm,dma-window, walking up the device tree */
 643         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
 644                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 645                 if (dma_window != NULL)
 646                         break;
 647         }
 648
 649         if (dma_window == NULL) {
 650                 pr_debug("  no ibm,dma-window property !\n");
 651                 return;
 652         }
 653
 654         ppci = PCI_DN(pdn);
 655
 656         pr_debug("  parent is %s, iommu_table: 0x%p\n",
 657                  pdn->full_name, ppci->iommu_table);
 658
 659         if (!ppci->iommu_table) {
 660                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
 661                                    ppci->phb->node);
 662                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
 663                 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
 664                 iommu_register_group(tbl, pci_domain_nr(bus), 0);
 665                 pr_debug("  created table: %p\n", ppci->iommu_table);
 666         }
 667 }
 668
 669
 670 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
 671 {
 672         struct device_node *dn;
 673         struct iommu_table *tbl;
 674
 675         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
 676
 677         dn = dev->dev.of_node;
 678
 679         /* If we're the direct child of a root bus, then we need to allocate
 680          * an iommu table ourselves. The bus setup code should have setup
 681          * the window sizes already.
 682          */
 683         if (!dev->bus->self) {
 684                 struct pci_controller *phb = PCI_DN(dn)->phb;
 685
 686                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
 687                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
 688                                    phb->node);
 689                 iommu_table_setparms(phb, dn, tbl);
 690                 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
 691                 iommu_register_group(tbl, pci_domain_nr(phb->bus), 0);
 692                 set_iommu_table_base_and_group(&dev->dev,
 693                                                PCI_DN(dn)->iommu_table);
 694                 return;
 695         }
 696
 697         /* If this device is further down the bus tree, search upwards until
 698          * an already allocated iommu table is found and use that.
 699          */
 700
 701         while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
 702                 dn = dn->parent;
 703
 704         if (dn && PCI_DN(dn))
 705                 set_iommu_table_base_and_group(&dev->dev,
 706                                                PCI_DN(dn)->iommu_table);
 707         else
 708                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
 709                        pci_name(dev));
 710 }
 711
 712 static int __read_mostly disable_ddw;
 713
 714 static int __init disable_ddw_setup(char *str)
 715 {
 716         disable_ddw = 1;
 717         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
 718
 719         return 0;
 720 }
 721
 722 early_param("disable_ddw", disable_ddw_setup);
 723
 724 static void remove_ddw(struct device_node *np, bool remove_prop)
 725 {
 726         struct dynamic_dma_window_prop *dwp;
 727         struct property *win64;
 728         u32 ddw_avail[3];
 729         u64 liobn;
 730         int ret = 0;
 731
 732         ret = of_property_read_u32_array(np, "ibm,ddw-applicable",
 733                                          &ddw_avail[0], 3);
 734
 735         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
 736         if (!win64)
 737                 return;
 738
 739         if (ret || win64->length < sizeof(*dwp))
 740                 goto delprop;
 741
 742         dwp = win64->value;
 743         liobn = (u64)be32_to_cpu(dwp->liobn);
 744
 745         /* clear the whole window, note the arg is in kernel pages */
 746         ret = tce_clearrange_multi_pSeriesLP(0,
 747                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
 748         if (ret)
 749                 pr_warning("%s failed to clear tces in window.\n",
 750                          np->full_name);
 751         else
 752                 pr_debug("%s successfully cleared tces in window.\n",
 753                          np->full_name);
 754
 755         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
 756         if (ret)
 757                 pr_warning("%s: failed to remove direct window: rtas returned "
 758                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 759                         np->full_name, ret, ddw_avail[2], liobn);
 760         else
 761                 pr_debug("%s: successfully removed direct window: rtas returned "
 762                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 763                         np->full_name, ret, ddw_avail[2], liobn);
 764
 765 delprop:
 766         if (remove_prop)
 767                 ret = of_remove_property(np, win64);
 768         if (ret)
 769                 pr_warning("%s: failed to remove direct window property: %d\n",
 770                         np->full_name, ret);
 771 }
 772
 773 static u64 find_existing_ddw(struct device_node *pdn)
 774 {
 775         struct direct_window *window;
 776         const struct dynamic_dma_window_prop *direct64;
 777         u64 dma_addr = 0;
 778
 779         spin_lock(&direct_window_list_lock);
 780         /* check if we already created a window and dupe that config if so */
 781         list_for_each_entry(window, &direct_window_list, list) {
 782                 if (window->device == pdn) {
 783                         direct64 = window->prop;
 784                         dma_addr = be64_to_cpu(direct64->dma_base);
 785                         break;
 786                 }
 787         }
 788         spin_unlock(&direct_window_list_lock);
 789
 790         return dma_addr;
 791 }
 792
 793 static int find_existing_ddw_windows(void)
 794 {
 795         int len;
 796         struct device_node *pdn;
 797         struct direct_window *window;
 798         const struct dynamic_dma_window_prop *direct64;
 799
 800         if (!firmware_has_feature(FW_FEATURE_LPAR))
 801                 return 0;
 802
 803         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
 804                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
 805                 if (!direct64)
 806                         continue;
 807
 808                 window = kzalloc(sizeof(*window), GFP_KERNEL);
 809                 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
 810                         kfree(window);
 811                         remove_ddw(pdn, true);
 812                         continue;
 813                 }
 814
 815                 window->device = pdn;
 816                 window->prop = direct64;
 817                 spin_lock(&direct_window_list_lock);
 818                 list_add(&window->list, &direct_window_list);
 819                 spin_unlock(&direct_window_list_lock);
 820         }
 821
 822         return 0;
 823 }
 824 machine_arch_initcall(pseries, find_existing_ddw_windows);
 825
 826 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 827                         struct ddw_query_response *query)
 828 {
 829         struct eeh_dev *edev;
 830         u32 cfg_addr;
 831         u64 buid;
 832         int ret;
 833
 834         /*
 835          * Get the config address and phb buid of the PE window.
 836          * Rely on eeh to retrieve this for us.
 837          * Retrieve them from the pci device, not the node with the
 838          * dma-window property
 839          */
 840         edev = pci_dev_to_eeh_dev(dev);
 841         cfg_addr = edev->config_addr;
 842         if (edev->pe_config_addr)
 843                 cfg_addr = edev->pe_config_addr;
 844         buid = edev->phb->buid;
 845
 846         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
 847                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
 848         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
 849                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
 850                 BUID_LO(buid), ret);
 851         return ret;
 852 }
 853
 854 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 855                         struct ddw_create_response *create, int page_shift,
 856                         int window_shift)
 857 {
 858         struct eeh_dev *edev;
 859         u32 cfg_addr;
 860         u64 buid;
 861         int ret;
 862
 863         /*
 864          * Get the config address and phb buid of the PE window.
 865          * Rely on eeh to retrieve this for us.
 866          * Retrieve them from the pci device, not the node with the
 867          * dma-window property
 868          */
 869         edev = pci_dev_to_eeh_dev(dev);
 870         cfg_addr = edev->config_addr;
 871         if (edev->pe_config_addr)
 872                 cfg_addr = edev->pe_config_addr;
 873         buid = edev->phb->buid;
 874
 875         do {
 876                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
 877                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create,
 878                                 cfg_addr, BUID_HI(buid), BUID_LO(buid),
 879                                 page_shift, window_shift);
 880         } while (rtas_busy_delay(ret));
 881         dev_info(&dev->dev,
 882                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
 883                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
 884                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
 885                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
 886
 887         return ret;
 888 }
 889
 890 struct failed_ddw_pdn {
 891         struct device_node *pdn;
 892         struct list_head list;
 893 };
 894
 895 static LIST_HEAD(failed_ddw_pdn_list);
 896
 897 /*
 898  * If the PE supports dynamic dma windows, and there is space for a table
 899  * that can map all pages in a linear offset, then setup such a table,
 900  * and record the dma-offset in the struct device.
 901  *
 902  * dev: the pci device we are checking
 903  * pdn: the parent pe node with the ibm,dma_window property
 904  * Future: also check if we can remap the base window for our base page size
 905  *
 906  * returns the dma offset for use by dma_set_mask
 907  */
 908 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
 909 {
 910         int len, ret;
 911         struct ddw_query_response query;
 912         struct ddw_create_response create;
 913         int page_shift;
 914         u64 dma_addr, max_addr;
 915         struct device_node *dn;
 916         u32 ddw_avail[3];
 917         struct direct_window *window;
 918         struct property *win64;
 919         struct dynamic_dma_window_prop *ddwprop;
 920         struct failed_ddw_pdn *fpdn;
 921
 922         mutex_lock(&direct_window_init_mutex);
 923
 924         dma_addr = find_existing_ddw(pdn);
 925         if (dma_addr != 0)
 926                 goto out_unlock;
 927
 928         /*
 929          * If we already went through this for a previous function of
 930          * the same device and failed, we don't want to muck with the
 931          * DMA window again, as it will race with in-flight operations
 932          * and can lead to EEHs. The above mutex protects access to the
 933          * list.
 934          */
 935         list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
 936                 if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
 937                         goto out_unlock;
 938         }
 939
 940         /*
 941          * the ibm,ddw-applicable property holds the tokens for:
 942          * ibm,query-pe-dma-window
 943          * ibm,create-pe-dma-window
 944          * ibm,remove-pe-dma-window
 945          * for the given node in that order.
 946          * the property is actually in the parent, not the PE
 947          */
 948         ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable",
 949                                          &ddw_avail[0], 3);
 950         if (ret)
 951                 goto out_failed;
 952
 953        /*
 954          * Query if there is a second window of size to map the
 955          * whole partition.  Query returns number of windows, largest
 956          * block assigned to PE (partition endpoint), and two bitmasks
 957          * of page sizes: supported and supported for migrate-dma.
 958          */
 959         dn = pci_device_to_OF_node(dev);
 960         ret = query_ddw(dev, ddw_avail, &query);
 961         if (ret != 0)
 962                 goto out_failed;
 963
 964         if (query.windows_available == 0) {
 965                 /*
 966                  * no additional windows are available for this device.
 967                  * We might be able to reallocate the existing window,
 968                  * trading in for a larger page size.
 969                  */
 970                 dev_dbg(&dev->dev, "no free dynamic windows");
 971                 goto out_failed;
 972         }
 973         if (query.page_size & 4) {
 974                 page_shift = 24; /* 16MB */
 975         } else if (query.page_size & 2) {
 976                 page_shift = 16; /* 64kB */
 977         } else if (query.page_size & 1) {
 978                 page_shift = 12; /* 4kB */
 979         } else {
 980                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
 981                           query.page_size);
 982                 goto out_failed;
 983         }
 984         /* verify the window * number of ptes will map the partition */
 985         /* check largest block * page size > max memory hotplug addr */
 986         max_addr = memory_hotplug_max();
 987         if (query.largest_available_block < (max_addr >> page_shift)) {
 988                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
 989                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
 990                           1ULL << page_shift);
 991                 goto out_failed;
 992         }
 993         len = order_base_2(max_addr);
 994         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
 995         if (!win64) {
 996                 dev_info(&dev->dev,
 997                         "couldn't allocate property for 64bit dma window\n");
 998                 goto out_failed;
 999         }
1000         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1001         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1002         win64->length = sizeof(*ddwprop);
1003         if (!win64->name || !win64->value) {
1004                 dev_info(&dev->dev,
1005                         "couldn't allocate property name and value\n");
1006                 goto out_free_prop;
1007         }
1008
1009         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1010         if (ret != 0)
1011                 goto out_free_prop;
1012
1013         ddwprop->liobn = cpu_to_be32(create.liobn);
1014         ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) |
1015                         create.addr_lo);
1016         ddwprop->tce_shift = cpu_to_be32(page_shift);
1017         ddwprop->window_shift = cpu_to_be32(len);
1018
1019         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1020                   create.liobn, dn->full_name);
1021
1022         window = kzalloc(sizeof(*window), GFP_KERNEL);
1023         if (!window)
1024                 goto out_clear_window;
1025
1026         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1027                         win64->value, tce_setrange_multi_pSeriesLP_walk);
1028         if (ret) {
1029                 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1030                          dn->full_name, ret);
1031                 goto out_free_window;
1032         }
1033
1034         ret = of_add_property(pdn, win64);
1035         if (ret) {
1036                 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1037                          pdn->full_name, ret);
1038                 goto out_free_window;
1039         }
1040
1041         window->device = pdn;
1042         window->prop = ddwprop;
1043         spin_lock(&direct_window_list_lock);
1044         list_add(&window->list, &direct_window_list);
1045         spin_unlock(&direct_window_list_lock);
1046
1047         dma_addr = be64_to_cpu(ddwprop->dma_base);
1048         goto out_unlock;
1049
1050 out_free_window:
1051         kfree(window);
1052
1053 out_clear_window:
1054         remove_ddw(pdn, true);
1055
1056 out_free_prop:
1057         kfree(win64->name);
1058         kfree(win64->value);
1059         kfree(win64);
1060
1061 out_failed:
1062
1063         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1064         if (!fpdn)
1065                 goto out_unlock;
1066         fpdn->pdn = pdn;
1067         list_add(&fpdn->list, &failed_ddw_pdn_list);
1068
1069 out_unlock:
1070         mutex_unlock(&direct_window_init_mutex);
1071         return dma_addr;
1072 }
1073
1074 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1075 {
1076         struct device_node *pdn, *dn;
1077         struct iommu_table *tbl;
1078         const __be32 *dma_window = NULL;
1079         struct pci_dn *pci;
1080
1081         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1082
1083         /* dev setup for LPAR is a little tricky, since the device tree might
1084          * contain the dma-window properties per-device and not necessarily
1085          * for the bus. So we need to search upwards in the tree until we
1086          * either hit a dma-window property, OR find a parent with a table
1087          * already allocated.
1088          */
1089         dn = pci_device_to_OF_node(dev);
1090         pr_debug("  node is %s\n", dn->full_name);
1091
1092         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1093              pdn = pdn->parent) {
1094                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1095                 if (dma_window)
1096                         break;
1097         }
1098
1099         if (!pdn || !PCI_DN(pdn)) {
1100                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1101                        "no DMA window found for pci dev=%s dn=%s\n",
1102                                  pci_name(dev), of_node_full_name(dn));
1103                 return;
1104         }
1105         pr_debug("  parent is %s\n", pdn->full_name);
1106
1107         pci = PCI_DN(pdn);
1108         if (!pci->iommu_table) {
1109                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
1110                                    pci->phb->node);
1111                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1112                 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
1113                 iommu_register_group(tbl, pci_domain_nr(pci->phb->bus), 0);
1114                 pr_debug("  created table: %p\n", pci->iommu_table);
1115         } else {
1116                 pr_debug("  found DMA window, table: %p\n", pci->iommu_table);
1117         }
1118
1119         set_iommu_table_base_and_group(&dev->dev, pci->iommu_table);
1120 }
1121
1122 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1123 {
1124         bool ddw_enabled = false;
1125         struct device_node *pdn, *dn;
1126         struct pci_dev *pdev;
1127         const __be32 *dma_window = NULL;
1128         u64 dma_offset;
1129
1130         if (!dev->dma_mask)
1131                 return -EIO;
1132
1133         if (!dev_is_pci(dev))
1134                 goto check_mask;
1135
1136         pdev = to_pci_dev(dev);
1137
1138         /* only attempt to use a new window if 64-bit DMA is requested */
1139         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1140                 dn = pci_device_to_OF_node(pdev);
1141                 dev_dbg(dev, "node is %s\n", dn->full_name);
1142
1143                 /*
1144                  * the device tree might contain the dma-window properties
1145                  * per-device and not necessarily for the bus. So we need to
1146                  * search upwards in the tree until we either hit a dma-window
1147                  * property, OR find a parent with a table already allocated.
1148                  */
1149                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1150                                 pdn = pdn->parent) {
1151                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1152                         if (dma_window)
1153                                 break;
1154                 }
1155                 if (pdn && PCI_DN(pdn)) {
1156                         dma_offset = enable_ddw(pdev, pdn);
1157                         if (dma_offset != 0) {
1158                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1159                                 set_dma_offset(dev, dma_offset);
1160                                 set_dma_ops(dev, &dma_direct_ops);
1161                                 ddw_enabled = true;
1162                         }
1163                 }
1164         }
1165
1166         /* fall back on iommu ops, restore table pointer with ops */
1167         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1168                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1169                 set_dma_ops(dev, &dma_iommu_ops);
1170                 pci_dma_dev_setup_pSeriesLP(pdev);
1171         }
1172
1173 check_mask:
1174         if (!dma_supported(dev, dma_mask))
1175                 return -EIO;
1176
1177         *dev->dma_mask = dma_mask;
1178         return 0;
1179 }
1180
1181 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1182 {
1183         if (!dev->dma_mask)
1184                 return 0;
1185
1186         if (!disable_ddw && dev_is_pci(dev)) {
1187                 struct pci_dev *pdev = to_pci_dev(dev);
1188                 struct device_node *dn;
1189
1190                 dn = pci_device_to_OF_node(pdev);
1191
1192                 /* search upwards for ibm,dma-window */
1193                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->iommu_table;
1194                                 dn = dn->parent)
1195                         if (of_get_property(dn, "ibm,dma-window", NULL))
1196                                 break;
1197                 /* if there is a ibm,ddw-applicable property require 64 bits */
1198                 if (dn && PCI_DN(dn) &&
1199                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1200                         return DMA_BIT_MASK(64);
1201         }
1202
1203         return dma_iommu_ops.get_required_mask(dev);
1204 }
1205
1206 #else  /* CONFIG_PCI */
1207 #define pci_dma_bus_setup_pSeries       NULL
1208 #define pci_dma_dev_setup_pSeries       NULL
1209 #define pci_dma_bus_setup_pSeriesLP     NULL
1210 #define pci_dma_dev_setup_pSeriesLP     NULL
1211 #define dma_set_mask_pSeriesLP          NULL
1212 #define dma_get_required_mask_pSeriesLP NULL
1213 #endif /* !CONFIG_PCI */
1214
1215 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1216                 void *data)
1217 {
1218         struct direct_window *window;
1219         struct memory_notify *arg = data;
1220         int ret = 0;
1221
1222         switch (action) {
1223         case MEM_GOING_ONLINE:
1224                 spin_lock(&direct_window_list_lock);
1225                 list_for_each_entry(window, &direct_window_list, list) {
1226                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1227                                         arg->nr_pages, window->prop);
1228                         /* XXX log error */
1229                 }
1230                 spin_unlock(&direct_window_list_lock);
1231                 break;
1232         case MEM_CANCEL_ONLINE:
1233         case MEM_OFFLINE:
1234                 spin_lock(&direct_window_list_lock);
1235                 list_for_each_entry(window, &direct_window_list, list) {
1236                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1237                                         arg->nr_pages, window->prop);
1238                         /* XXX log error */
1239                 }
1240                 spin_unlock(&direct_window_list_lock);
1241                 break;
1242         default:
1243                 break;
1244         }
1245         if (ret && action != MEM_CANCEL_ONLINE)
1246                 return NOTIFY_BAD;
1247
1248         return NOTIFY_OK;
1249 }
1250
1251 static struct notifier_block iommu_mem_nb = {
1252         .notifier_call = iommu_mem_notifier,
1253 };
1254
1255 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
1256 {
1257         int err = NOTIFY_OK;
1258         struct device_node *np = node;
1259         struct pci_dn *pci = PCI_DN(np);
1260         struct direct_window *window;
1261
1262         switch (action) {
1263         case OF_RECONFIG_DETACH_NODE:
1264                 /*
1265                  * Removing the property will invoke the reconfig
1266                  * notifier again, which causes dead-lock on the
1267                  * read-write semaphore of the notifier chain. So
1268                  * we have to remove the property when releasing
1269                  * the device node.
1270                  */
1271                 remove_ddw(np, false);
1272                 if (pci && pci->iommu_table)
1273                         iommu_free_table(pci->iommu_table, np->full_name);
1274
1275                 spin_lock(&direct_window_list_lock);
1276                 list_for_each_entry(window, &direct_window_list, list) {
1277                         if (window->device == np) {
1278                                 list_del(&window->list);
1279                                 kfree(window);
1280                                 break;
1281                         }
1282                 }
1283                 spin_unlock(&direct_window_list_lock);
1284                 break;
1285         default:
1286                 err = NOTIFY_DONE;
1287                 break;
1288         }
1289         return err;
1290 }
1291
1292 static struct notifier_block iommu_reconfig_nb = {
1293         .notifier_call = iommu_reconfig_notifier,
1294 };
1295
1296 /* These are called very early. */
1297 void iommu_init_early_pSeries(void)
1298 {
1299         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1300                 return;
1301
1302         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1303                 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
1304                         ppc_md.tce_build = tce_buildmulti_pSeriesLP;
1305                         ppc_md.tce_free  = tce_freemulti_pSeriesLP;
1306                 } else {
1307                         ppc_md.tce_build = tce_build_pSeriesLP;
1308                         ppc_md.tce_free  = tce_free_pSeriesLP;
1309                 }
1310                 ppc_md.tce_get   = tce_get_pSeriesLP;
1311                 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1312                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1313                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1314                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1315         } else {
1316                 ppc_md.tce_build = tce_build_pSeries;
1317                 ppc_md.tce_free  = tce_free_pSeries;
1318                 ppc_md.tce_get   = tce_get_pseries;
1319                 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
1320                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
1321         }
1322
1323
1324         of_reconfig_notifier_register(&iommu_reconfig_nb);
1325         register_memory_notifier(&iommu_mem_nb);
1326
1327         set_pci_dma_ops(&dma_iommu_ops);
1328 }
1329
1330 static int __init disable_multitce(char *str)
1331 {
1332         if (strcmp(str, "off") == 0 &&
1333             firmware_has_feature(FW_FEATURE_LPAR) &&
1334             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1335                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1336                 ppc_md.tce_build = tce_build_pSeriesLP;
1337                 ppc_md.tce_free  = tce_free_pSeriesLP;
1338                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1339         }
1340         return 1;
1341 }
1342
1343 __setup("multitce=", disable_multitce);